Voltage drop circuit and charging controller and method for voltage drop circuit

Abstract

The embodiment of the invention provides a voltage drop circuit and a charging controller and method for the voltage drop circuit, and the charging controller compares a reference voltage with a plurality of feedback voltages of a plurality of output voltages which are output to a plurality of voltage output ends by a pulse frequency modulation voltage drop module through a single inductor and a plurality of change-over switches. Each of the plurality of change-over switches is disposed between a single inductor and a corresponding voltage output terminal. Then, the charging controller determines the charging sequence of the plurality of voltage output ends according to the plurality of comparison result signals. And the control module is used for generating a plurality of switching signals for controlling the plurality of change-over switches and a starting signal for enabling the pulse wave frequency modulation voltage drop module to charge one of the plurality of voltage output ends according to the zero current detection signal of the single inductor and the charging sequence.

Description

Technical Field

[0001] The present invention relates to a buck circuit and a charging controller and method for the buck circuit, and particularly to a buck circuit of the Pulse Frequency Modulation (PFM) Single Inductor Multiple Output (SIMO) type and a charging controller and method for the buck circuit. Background Art

[0002] Conventional buck circuits usually have only one voltage output terminal (i.e., have a single power domain), and output a fixed output voltage at its voltage output terminal for use by a subsequent load. Conventional buck circuits usually configure a single inductor at its single voltage output terminal, and such buck circuits employ pulse frequency modulation, and thus are also referred to as single inductor single output (SISO) type buck circuits of pulse frequency modulation.

[0003] The single inductor single output type buck circuit of pulse frequency modulation can be used in the case where the subsequent load only requires a specific voltage. However, when the subsequent load is a microcontroller unit (MCU) or other circuit that requires multiple different specific voltages (i.e., the subsequent load demands a buck circuit of a multi-power domain), the single inductor single output type buck circuit of pulse frequency modulation cannot meet its requirements.

[0004] In view of this, there is a need in the industry for a pulse frequency modulation single inductor multiple output type buck circuit having multiple voltage output terminals to output different output voltages. However, some digital circuits as subsequent loads may operate at a relatively high speed and draw current at a fast rate. For example, the aforementioned microcontroller units with a relatively high operating speed, which results in the fact that the existing pulse frequency modulation single inductor multiple output type buck circuits cannot ensure that the output voltages of multiple voltage output terminals can be stably maintained within the range acceptable to the digital circuits. Summary of the Invention

[0005] It can be understood from the above description that the technical problem to be solved by the present invention is that the output voltages of multiple voltage output terminals of the existing pulse frequency modulation single inductor multiple output type buck circuit cannot be stably maintained within the range acceptable to the subsequent load due to the relatively high operating speed of the load.

[0006] To solve the above-mentioned conventional problems, an embodiment of the present invention provides a charging controller for a voltage drop circuit, which includes a comparison module and a single-inductor multi-output control circuit. The comparison module is used to compare a reference voltage with a plurality of feedback voltages of a plurality of output voltages output from a pulse frequency modulation voltage drop module to a plurality of voltage output terminals through a single inductor and a plurality of switching switches of a switching switch module, so as to generate a plurality of comparison result signals, wherein each of the plurality of switching switches is disposed between the single inductor and the corresponding voltage output terminal. The single-inductor multi-output control circuit is electrically connected to the comparison module, and is used to determine the charging sequence of the plurality of voltage output terminals according to the plurality of comparison result signals, and is used to generate a plurality of switching signals for controlling the plurality of switching switches and a start signal for enabling the pulse frequency modulation voltage drop module to charge one of the plurality of voltage output terminals according to the zero current detection signal of the single inductor and the charging sequence.

[0007] As described above, the present invention provides a charging controller and method that can perform charging control on the output voltages of a pulse frequency modulation single-inductor multi-output type voltage drop circuit. Therefore, the voltage drop circuit using this charging controller or method can stably maintain the output voltages of the plurality of voltage output terminals of the voltage drop circuit within an acceptable range of the backend load. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] To make the above and other objects, features, advantages and embodiments of the present invention more obvious and understandable, the description of the accompanying drawings is as follows:

[0009] Figure 1 is a circuit schematic diagram of the voltage drop circuit according to an embodiment of the present invention;

[0010] Figure 2 is a circuit schematic diagram of the pulse frequency modulation voltage drop unit of the voltage drop circuit according to an embodiment of the present invention;

[0011] Figure 3 is a circuit schematic diagram of the single-inductor multi-output control circuit of the charging controller of the voltage drop circuit according to an embodiment of the present invention;

[0012] Figure 4 is a partial flowchart of the charging method executed by the charging controller of the voltage drop circuit according to an embodiment of the present invention;

[0013] Figure 5 is another partial flowchart of the charging method executed by the charging controller of the voltage drop circuit according to an embodiment of the present invention;

[0014] Figure 6 is a signal waveform schematic diagram of the comparison result signal in the charging controller according to an embodiment of the present invention;

[0015] Figure 7It is another part of the flowchart of the charging method executed by the charging controller of the voltage drop circuit according to the embodiments of the present invention;

[0016] Figure 8 It is still another part of the flowchart of the charging method executed by the charging controller of the voltage drop circuit according to the embodiments of the present invention.

[0017] [Symbol Description]

[0018] 11: Pulse Frequency Modulation Voltage Drop Unit

[0019] 12: Single Inductor Multiple Output Control Circuit

[0020] 21: Fixed Peak Voltage Control Circuit

[0021] 22: Zero-Current Comparator

[0022] 23: Peak-Current Comparator

[0023] 31: Comparator Trigger Detection Circuit

[0024] 32: Sequencing Circuit

[0025] 33: Charge Path Control Circuit

[0026] CP1~CP4: Comparison Result Signals

[0027] CMP1~CMP4: Comparators

[0028] VFB1~VFB3, VFB: Feedback Voltages

[0029] VREF: Reference Voltage

[0030] ST: Start Signal

[0031] ZCD: Zero-Current Detection Signal

[0032] PCD: Peak-Current Detection Signal

[0033] SWON[2:0]: Switch Signals

[0034] SWS: Switching Switch Module

[0035] SW1~SW3: Switching Switches

[0036] PVDD: High Voltage

[0037] PVSS: Low Voltage

[0038] MP1: PMOS Power Transistor

[0039] MN1: NMOS Power Circuit Transistor

[0040] P1, N1: Drive signal

[0041] L: Inductance

[0042] GND: Ground voltage

[0043] C1 - C3: Load

[0044] VOUT1 - VOUT3, VSW: Output voltage

[0045] EN: Enable terminal

[0046] PDRV, NDRV: Drive stage

[0047] STC1 - STC3: Charge quantity indication signal

[0048] S501 - S801: Steps Detailed implementation manners

[0049] The voltage - drop circuit of the present invention is modified from the pulse - frequency - modulation single - inductor single - output type of voltage - drop circuit in the prior art. By additionally setting a comparison module and a single - inductor multi - output control circuit, and still maintaining the single - inductor manner, a pulse - frequency - modulation single - inductor multi - output type of voltage - drop circuit is realized. The comparison module and the single - inductor multi - output control circuit form the charge controller of the voltage - drop circuit, and this charge controller can stably keep the output voltages of multiple voltage output terminals of the voltage - drop circuit within the acceptable range of the backend load.

[0050] The following will, in conjunction with the drawings, elaborate on the possible implementation manners of the present invention. It should be noted that the following implementation details are not used to limit the scope of the patent application claimed by the present invention, but are only for the convenience of those with ordinary knowledge in the technical field to understand.

[0051] Please refer to Figure 1 , Figure 1 is the circuit schematic diagram of the voltage - drop circuit of the embodiment of the present invention. The voltage - drop circuit charge controller and the pulse - frequency - modulation voltage - drop module. The charge controller includes a comparison module and a single - inductor multi - output control circuit 12. In this embodiment, it is composed of multiple comparators CMP1 - CMP3, but the present invention is not limited thereto. The pulse - frequency - modulation voltage - drop module includes a single inductor L, a switching - switch module SWS, a pulse - frequency - modulation voltage - drop unit 11, and a power - switch circuit. In this embodiment, the switching - switch module SWS is composed of three switching switches SW1 - SW3, and the power - switch circuit is composed of a PMOS power transistor MP1 and an NMOS power - circuit transistor MN1, but the present invention is not limited thereto.

[0052] One end of each of a plurality of switching switches SW1 to SW3 is electrically connected to a first end of a single inductor L, the other end of each of the plurality of switching switches SW1 to SW3 is electrically connected to a corresponding voltage output terminal, and the control terminal of each of the plurality of switching switches SW1 to SW3 is electrically connected to a single inductor multi-output control circuit 12 to receive a corresponding switching signal SWON[2:0]. The pulse frequency modulation voltage drop unit 11 is electrically connected to the single inductor multi-output control circuit 12 for receiving a start signal ST and for outputting a zero current detection signal ZCD and drive signals P1, N1 when the current of the single inductor L is zero. Further, the plurality of switching switches SW1 to SW3 can be implemented by a plurality of PMOS low-power transistors, wherein the gate, source, and drain of each PMOS low-power transistor are respectively the control terminal, one end, and the other end of one of the switching switches SW1 to SW3.

[0053] The gate of the PMOS power transistor MP1 and the gate of the NMOS power circuit transistor MN1 are electrically connected to the pulse frequency modulation voltage drop unit 11 to respectively receive the drive signals P1, N1. The drain of the PMOS power transistor MP1 and the drain of the NMOS power circuit transistor MN1 are electrically connected to each other and are further electrically connected to a second end of the single inductor L. The source of the PMOS power transistor MP1 and the source of the NMOS power circuit transistor MN1 are respectively electrically connected to a high voltage PVDD and a low voltage PVSS. The high voltage PVDD and the low voltage PVSS are, for example, a supply voltage and a ground voltage, but the present invention is not limited thereto.

[0054] The voltage drop circuit is a pulse frequency modulation single inductor multi-output type voltage drop circuit, and a plurality of voltage output terminals respectively output output voltages VOUT1 to VOUT3 to the backend loads C1 to C3. Both ends of each of the backend loads C1 to C3 are respectively electrically connected between a corresponding voltage output terminal and a ground voltage GND, and the backend loads C1 to C3 can be capacitive impedances. The backend loads C1 to C3 may be different electronic components and use different output voltages VOUT1 to VOUT3 as operating voltages or supply voltages, or the backend loads C1 to C3 are a plurality of sub-circuits in a single electronic component that use different output voltages VOUT1 to VOUT3 as operating voltages or supply voltages. For example, the voltage drop circuit provides a plurality of different output voltages VOUT1 to VOUT3 to the same microcontroller unit. When the electronic components of the backend loads C1 to C3 operate faster or consume power faster, the output voltages VOUT1 to VOUT3 may drop and cannot be maintained within an acceptable range. Therefore, the charge controller must charge the voltage output terminals before the output voltages VOUT1 to VOUT3 drop out of the acceptable range.

[0055] The comparison module is used to compare the reference voltage VREF and the feedback voltages VFB1-VFB3 of the multiple output voltages VOUT1-VOUT3 output from the pulse frequency modulation voltage drop module to multiple voltage output terminals through a single inductor L and multiple switching switches SW1-SW3 of the switching switch module SWS, so as to generate multiple comparison result signals CP1-CP3. In Figure 1 In an embodiment, the multiple non-inverting input terminals of the multiple comparators CMP1-CMP3 receive the reference voltage VREF, and the multiple inverting input terminals of the multiple comparators CMP1-CMP3 receive the feedback voltages VFB1-VFB3 of the multiple output voltages VOUT1-VOUT3, and the multiple comparators CMP1-CMP3 respectively output the comparison result signals CP1-CP3.

[0056] It should be noted that, in other embodiments, the comparison module may only include a comparator, a multiplexer and a demultiplexer. The multiple input terminals received by the multiplexer receive the feedback voltages VFB1-VFB3, and the output terminal of the multiplexer switches and outputs one of the feedback voltages VFB1-VFB3 according to the switching frequency. The non-inverting input terminal of the comparator receives the reference voltage VREF, the inverting input terminal of the comparator is electrically connected to the output terminal of the multiplexer, the input terminal of the demultiplexer is electrically connected to the output terminal of the comparator, and the demultiplexer switches according to the switching frequency so that its multiple output terminals respectively output the multiple comparison result signals CP1-CP3. However, this way of implementing the comparison module must ensure that the switching time corresponding to the switching frequency is less than the charging time to avoid being unable to effectively prevent the output voltages VOUT1-VOUT3 from dropping out of the acceptable range.

[0057] In addition, in order to prevent a certain voltage output terminal from being charged for a long time and occupying the pulse frequency modulation voltage drop module, causing other voltage output terminals to be unable to be charged, the comparison module can be designed to reset the corresponding one of the comparison result signals CP1-CP3 with a high voltage level after one of the comparison result signals CP1-CP3 maintains a high voltage level for a period of time.

[0058] The single inductor multi-output control circuit 12 is electrically connected to the multiple comparators CMP1-CMP3 of the comparison module, and is used to determine the charging order of the multiple voltage output terminals according to the multiple comparison result signals CP1-CP3, and is used to generate multiple switch signals SWON[2:0] for controlling the multiple switching switches SW1-SW3 and a start signal ST for enabling the pulse frequency modulation voltage drop module to charge one of the multiple voltage output terminals according to the zero current detection signal ZCD of the single inductor L and the charging order. It should be noted that, Figure 1 The embodiment takes three output voltages VOUT1-VOUT3 as an example for illustration, but in other embodiments, the number of output voltages is two or more than four.

[0059] Please refer to Figure 1 and Figure 2 , Figure 2 is a circuit schematic diagram of the pulse frequency modulation voltage drop unit of the voltage drop circuit according to an embodiment of the present invention. The pulse frequency modulation voltage drop unit 11 has an enable terminal EN for receiving a start signal ST, and includes a comparator CMP4, a fixed peak voltage control circuit 21, driver stages PDRV, NDRV, a zero current comparator 22 and a peak current comparator 23. The comparator is used to compare a feedback voltage VFB with a reference voltage VREF to generate a comparison result signal CP4, where the feedback voltage VFB is the voltage on the first end of a single inductor L, that is, one of a plurality of feedback voltages VFB1 to VFB3.

[0060] The fixed peak voltage control circuit 21 is electrically connected to the comparator CMP4 and is used to generate drive signals input to the driver stages PDRV, NDRV according to a zero current detection signal ZCD and a peak current detection signal PCD of the single inductor L. The driver stages PDRV, NDRV are electrically connected to the fixed peak voltage control circuit 21 and are respectively used to generate drive signals P1, N1 according to the drive signals generated by the fixed peak voltage control circuit 21. The zero current comparator 22 and the peak current comparator 23 are electrically connected to the single inductor L and the fixed peak voltage control circuit 21, and are respectively used to detect the current flowing through the single inductor L to generate a zero current detection signal ZCD and a peak current detection signal PCD.

[0061] Please refer to Figure 1 and Figure 3 , Figure 3 is a circuit schematic diagram of the single inductor multi-output control circuit of the charging controller of the voltage drop circuit according to an embodiment of the present invention. The single inductor multi-output control circuit 12 includes a comparator trigger detection circuit 31, a sequencing circuit 32 and a charging path control circuit 33. The comparator trigger detection circuit 31 is used to generate a plurality of charging quantity indication signals STC1 to STC3 according to a plurality of comparison result signals CP1 to CP3, where the plurality of charging quantity indication signals STC1 to STC3 are used to indicate the number of voltage output terminals that need to be charged. For example, the charging quantity indication signals STC1 to STC3 respectively indicate that one, two and three voltage output terminals need to be charged. The sequencing circuit 32 is electrically connected to the comparator trigger detection circuit 31 and is used to determine the charging sequence according to the plurality of charging quantity indication signals STC1 to STC3 and the plurality of comparison result signals CP1 to CP3. The charging path control circuit 33 is electrically connected to the sequencing circuit 32 and is used to generate a plurality of switch signals SWON[2:0] according to the zero current detection signal ZCD and the charging sequence.

[0062] Please continue to refer to Figure 1, according to the above content, the above charging controller actually executes a charging control method for a voltage drop circuit, and this charging control method includes the following steps: comparing a reference voltage VREF and a plurality of feedback voltages VFB1 to VFB3 of a plurality of output voltages VOUT1 to VOUT3 output by a pulse frequency modulation voltage drop module to a plurality of voltage output terminals through a single inductor L and a plurality of switching switches SW1 to SW3 to generate a plurality of comparison result signals CP1 to CP3, wherein each of the plurality of switching switches SW1 to SW3 is disposed between the single inductor L and the corresponding voltage output terminal; and determining the charging order of the plurality of voltage output terminals according to the plurality of comparison result signals CP1 to CP3, and generating a plurality of switching signals SWON[2:0] for controlling the plurality of switching switches SW1 to SW3 and a start signal ST for enabling the pulse frequency modulation voltage drop module to charge one of the plurality of voltage output terminals according to the zero current detection signal ZCD of the single inductor L and the charging order.

[0063] Further, please refer to Figure 1 and Figure 4 , Figure 4 is a partial flowchart of the charging method executed by the charging controller of the voltage drop circuit according to an embodiment of the present invention. In step S401, the charging controller checks whether the comparison result signals CP1 to CP3 output by the comparators CMP1 to CMP3 are at a high voltage level or a low voltage level. In step S402, it is determined whether the inspection result is that all the comparison result signals CP1 to CP3 are at a high voltage level. If so, step S403 is executed; otherwise, step S405 is executed. In step S405, the charging controller determines to charge the three voltage output terminals. In step S403, it is determined whether the inspection result is that two of the comparison result signals CP1 to CP3 are at a high voltage level. If so, step S404 is executed; otherwise, step S406 is executed. In step S406, the charging controller determines to charge the two voltage output terminals corresponding to the two comparison result signals CP1 to CP3 that are at a high voltage level. In step S405, it is determined whether the inspection result is that only one of the comparison result signals CP1 to CP3 is at a high voltage level. If so, step S407 is executed; otherwise, step S401 is executed. In step S407, the charging controller determines to charge the voltage output terminal corresponding to the one comparison result signal CP1 to CP3 that is at a high voltage level.

[0064] Please refer to Figure 1 , Figure 5 and Figure 6 , Figure 5 is another partial flowchart of the charging method executed by the charging controller of the voltage drop circuit according to an embodiment of the present invention, and Figure 6It is a schematic diagram of the signal waveform of the comparison result signal in the charging controller according to an embodiment of the present invention. During a period of time, if the feedback voltage VFB3 is first less than the reference voltage VREF, then the feedback voltage VFB1 is less than the reference voltage VREF, and then the feedback voltage VFB2 is less than the reference voltage VREF, then as shown in Figure 6 , in the charging controller, the comparison result signal CP3 first changes from a low voltage level to a high voltage level, then the comparison result signal CP1 first changes from a low voltage level to a high voltage level, and then the comparison result signal CP2 first changes from a low voltage level to a high voltage level.

[0065] In this way, in Figure 5 step S501, the charging controller determines the charging order, and the determined charging order is to first charge the voltage output terminal of the output voltage VOUT3, then charge the voltage output terminal of the output voltage VOUT1, and then charge the voltage output terminal of the output voltage VOUT2. Simply put, the way the charging controller determines the charging order is to observe the priority of the comparison result signals CP1~CP3 changing from a low voltage level to a high voltage level during a period of time, and determine the charging order based on this priority of changing from a low voltage level to a high voltage level.

[0066] In steps S502~S504, the charging controller sequentially charges the voltage output terminals of the pulse frequency modulation voltage drop module of the voltage drop circuit with the first priority to the third priority, that is, sequentially charges the voltage output terminal of the output voltage VOUT3, the voltage output terminal of the output voltage VOUT1, and the voltage output terminal of the output voltage VOUT2. After step S504, the charging process is exited. Here, please note that as described above, in each of steps S502~S504, if a corresponding one of the output voltages VOUT1~VOUT3 of the voltage output terminal has been charged to a specific level, the current flowing through the single inductor L is zero, so the pulse frequency modulation voltage drop unit 11 will output a zero current detection signal ZCD to indicate that the voltage output terminal being charged has been charged and it is possible to proceed to the next charging step to charge the voltage output terminal of the next priority, or exit the charging process.

[0067] Please refer to Figure 1 and Figure 7 , Figure 7 It is another partial flowchart of the charging method executed by the charging controller of the voltage drop circuit according to an embodiment of the present invention. During a period of time, if the feedback voltage VFB1 is first less than the reference voltage VREF, then the feedback voltage VFB3 is less than the reference voltage VREF, and the feedback voltage VFB2 has never been less than the reference voltage VREF. In this way, in Figure 7In step S701, the charging controller determines the charging sequence, and the determined charging sequence is to first charge the voltage output terminal of output voltage VOUT1, and then charge the voltage output terminal of output voltage VOUT3.

[0068] In steps S702 and S703, the charging controller sequentially uses the pulse frequency modulation of the voltage drop circuit to charge the voltage output terminals from the first priority to the second priority, that is, sequentially charge the voltage output terminal of output voltage VOUT1 and the voltage output terminal of output voltage VOUT3. After step S703, the charging process is exited. Here, please note that as described above, in each of steps S702 and S703, if the output voltage of a corresponding one of the voltage output terminals VOUT1 and VOUT3 has been charged to a specific level, the current flowing through the single inductor L is zero, so the pulse frequency modulation voltage drop unit 11 will output a zero current detection signal ZCD to indicate that the voltage output terminal being charged has been charged and it is possible to proceed to the next charging step to charge the voltage output terminal of the next priority level, or exit the charging process.

[0069] Please refer to Figure 1 and Figure 8 , Figure 8 is another partial process schematic diagram of the charging method executed by the charging controller of the voltage drop circuit according to an embodiment of the present invention. During a period of time, if only the feedback voltage VFB1 is less than the reference voltage VREF, but the feedback voltages VFB2 and VFB3 are never less than the reference voltage VREF. In this way, in Figure 8 step S801, the charging controller determines the charging sequence, and the determined charging sequence is to first charge the voltage output terminal of output voltage VOUT1.

[0070] In step S802, the charging controller uses the pulse frequency modulation of the voltage drop circuit to charge the corresponding voltage output terminal, that is, charge the voltage output terminal of output voltage VOUT1. After step S802, the charging process is exited. Here, please note that as described above, in step S802, if the output voltage of the voltage output terminal VOUT1 has been charged to a specific level, the current flowing through the single inductor L is zero, so the pulse frequency modulation voltage drop unit 11 will output a zero current detection signal ZCD to indicate that the voltage output terminal being charged has been charged and it is possible to exit the charging process.

[0071] The present invention is disclosed herein only by way of preferred embodiments. However, those skilled in the art should understand that the above embodiments are only used to describe the present invention and are not intended to limit the scope of the patent rights claimed by the present invention. Any changes or substitutions that are equivalent or equivalent to the above embodiments should be construed as being covered by the spirit or scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the scope defined by the claims.

Claims

1. A charging controller for a voltage drop circuit, characterized in that The voltage drop circuit further includes a pulse frequency modulation voltage drop module, a single inductor, and a switching switch module. The pulse frequency modulation voltage drop module outputs a plurality of output voltages to a plurality of voltage output terminals through the single inductor and a plurality of switching switches of the switching switch module, and the charging controller includes: A comparison module for comparing a reference voltage and a plurality of feedback voltages of the plurality of output voltages to generate a plurality of comparison result signals, wherein each of the plurality of switching switches is disposed between the single inductor and the corresponding voltage output terminal; and A single inductor multi-output control circuit electrically connected to the comparison module for determining a charging sequence of the plurality of voltage output terminals according to the plurality of comparison result signals, and for generating a plurality of switching signals for controlling the plurality of switching switches and a start signal for enabling the pulse frequency modulation voltage drop module to charge one of the plurality of voltage output terminals according to a zero current detection signal of the single inductor and the charging sequence.

2. The charging controller according to claim 1, characterized in that, The plurality of voltage output terminals are respectively a first voltage output terminal, a second voltage output terminal, and a third voltage output terminal. The plurality of comparison result signals are respectively a first comparison result signal, a second comparison result signal, and a third comparison result signal generated after comparing a first feedback voltage of a first output voltage of the first voltage output terminal, a second feedback voltage of a second output voltage of the second voltage output terminal, and a third feedback voltage of a third output voltage of the third voltage output terminal with the reference voltage.

3. The charging controller according to claim 2, wherein, If the first feedback voltage is first less than the reference voltage, then the second feedback voltage is less than the reference voltage, and then the third feedback voltage is less than the reference voltage, the charging sequence is to charge the first voltage output terminal, the second voltage output terminal, and the third voltage output terminal in sequence; Wherein the plurality of switching signals generated by the single inductor multi-output control circuit first turn on a first switching switch corresponding to the first voltage output terminal so that the first voltage output terminal is charged. Then, when receiving the zero current detection signal of the single inductor, the plurality of switching signals generated by the single inductor multi-output control circuit turn off the first switching switch, and then turn on a second switching switch corresponding to the second voltage output terminal so that the second voltage output terminal is charged. Then, when receiving the zero current detection signal of the single inductor, the plurality of switching signals generated by the single inductor multi-output control circuit turn off the second switching switch, and then turn on a third switching switch corresponding to the third voltage output terminal so that the third voltage output terminal is charged. Then, when receiving the zero current detection signal of the single inductor, the plurality of switching signals generated by the single inductor multi-output control circuit turn off the third switching switch and the generated start signal disables the pulse frequency modulation voltage drop module from charging.

4. The charging controller according to claim 2, wherein If the first feedback voltage is first less than the reference voltage, and then the second feedback voltage is less than the reference voltage, the charging sequence is to charge the first voltage output terminal and the second voltage output terminal in sequence; Among them, the multiple switching signals generated by the single-inductor multi-output control circuit first turn on a first switching switch corresponding to the first voltage output terminal so that the first voltage output terminal is charged. After receiving the zero-current detection signal of the single inductor, the multiple switching signals generated by the single-inductor multi-output control circuit turn off the first switching switch, and then turn on a second switching switch corresponding to the second voltage output terminal so that the second voltage output terminal is charged. After receiving the zero-current detection signal of the single inductor, the multiple switching signals generated by the single-inductor multi-output control circuit turn off the second switching switch and the generated start signal disables the pulse frequency modulation voltage drop module for charging.

5. The charging controller according to claim 2, wherein If only the first feedback voltage is less than the reference voltage, the charging sequence is to charge only the first voltage output terminal and the second voltage output terminal; Among them, the multiple switching signals generated by the single-inductor multi-output control circuit first turn on a first switching switch corresponding to the first voltage output terminal so that the first voltage output terminal is charged. After receiving the zero-current detection signal of the single inductor, the multiple switching signals generated by the single-inductor multi-output control circuit turn off the first switching switch and the generated start signal disables the pulse frequency modulation voltage drop module for charging.

6. The charging controller according to claim 1, wherein The single-inductor multi-output control circuit includes: A comparator trigger detection circuit for generating a plurality of charging quantity indication signals according to the plurality of comparison result signals, wherein the plurality of charging quantity indication signals are used to indicate a quantity of the plurality of voltage output terminals that need to be charged; A sequence arrangement circuit electrically connected to the comparator trigger detection circuit for determining the charging sequence according to the plurality of charging quantity indication signals and the plurality of comparison result signals; and A charging path control circuit electrically connected to the sequence arrangement circuit for generating the plurality of switching signals according to the zero-current detection signal and the charging sequence.

7. The charging controller according to claim 1, wherein The comparison module includes a plurality of comparators, wherein a plurality of positive input terminals of the plurality of comparators receive the reference voltage, and a plurality of negative input terminals of the plurality of comparators receive the plurality of feedback voltages; alternatively, the comparison module includes a comparator, a multiplexer, and a demultiplexer, wherein a plurality of input terminals received by the multiplexer receive the plurality of feedback voltages, and an output terminal of the multiplexer outputs one of the plurality of feedback voltages according to a switching frequency, a positive input terminal of the comparator receives the reference voltage, a negative input terminal of the comparator is electrically connected to the output terminal of the multiplexer, an input terminal of the demultiplexer is electrically connected to the output terminal of the comparator, and the demultiplexer switches according to the switching frequency so that its plurality of output terminals respectively output the plurality of comparison result signals.

8. A voltage drop circuit, characterized in that, Comprising: The charging controller according to any one of claims 1 to 7; A pulse frequency modulation voltage drop module; A plurality of voltage output terminals; A single inductor; A switching switch module, comprising a plurality of switching switches, wherein one end of each of the plurality of switching switches is electrically connected to a first end of the single inductor, the other end of each of the plurality of switching switches is electrically connected to a corresponding one of the plurality of voltage output terminals, and a control end of each of the plurality of switching switches is electrically connected to the single inductor multi-output control circuit to receive the corresponding switch signal; And The pulse frequency modulation voltage drop module includes: A pulse frequency modulation voltage drop unit, electrically connected to the single inductor multi-output control circuit, for receiving the start signal, and for outputting the zero current detection signal, a first drive signal, and a second drive signal; and A power switch circuit, including a PMOS power transistor and an NMOS power circuit transistor, wherein a gate of the PMOS power transistor and a gate of the NMOS power circuit transistor are electrically connected to the pulse frequency modulation voltage drop unit to respectively receive the first drive signal and the second drive signal, a drain of the PMOS power transistor and a drain of the NMOS power circuit transistor are electrically connected to each other and are further electrically connected to a second end of the single inductor, and a source of the PMOS power transistor and a source of the NMOS power circuit transistor are respectively electrically connected to a first voltage and a second voltage.

9. The pressure drop circuit according to claim 8, wherein The pulse frequency modulation voltage drop unit has an enable terminal for receiving the start signal, and includes: A comparator, for comparing one of the plurality of feedback voltages with the reference voltage to generate another comparison result signal; A fixed peak voltage control circuit, electrically connected to the comparator, for generating a third drive signal according to the zero current detection signal and a peak current detection signal of the single inductor; A first drive stage and a second drive stage, electrically connected to the fixed peak voltage control circuit, for respectively generating the first drive signal and the second drive signal according to the third drive signal; A zero - current comparator and a peak - current comparator are electrically connected to the single inductor and the fixed - peak - voltage control circuit, and are respectively used to detect a current flowing through the single inductor to generate the zero - current detection signal and the peak - current detection signal.

10. A charging control method for a voltage drop circuit, characterized in that, Comprising: Comparing a reference voltage and multiple feedback voltages of multiple output voltages output by a pulse - frequency - modulation voltage - drop module to multiple voltage output terminals through a single inductor and multiple switching switches to generate multiple comparison result signals, wherein each of the multiple switching switches is disposed between the single inductor and the corresponding voltage output terminal; And Determining a charging sequence of the multiple voltage output terminals according to the multiple comparison result signals, and being used to generate multiple switching signals for controlling the multiple switching switches and a start signal for enabling the pulse - frequency - modulation voltage - drop module to charge one of the multiple voltage output terminals according to a zero - current detection signal of the single inductor and the charging sequence.

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