Amplifier with temperature dependent gain and temperature compensated bandwidth

Abstract

The invention relates to an amplifier with temperature dependent gain and temperature compensated bandwidth. An operational amplifier (OPAMP) is biased by a tail current that varies with temperature and process to compensate for variations in amplifier bandwidth. A proportional to absolute temperature (PTAT) current source generates a PTAT current, thereby producing a reference voltage. A reference voltage is converted into a reference current from which a tail current is derived using a voltage-to-current generator circuit of the differential amplifier circuit. A resistor coupled to the PTAT current source and the voltage-to-current generator circuit has a resistance value dependent on an operating temperature, wherein such resistor matches a resistor of a gain setting circuit for the OPAMP.

Description

Technical Field

[0001] The present invention relates to an amplifier circuit, and more particularly to an amplifier circuit having temperature-dependent gain and compensation bandwidth variation.

[0002] In particular, embodiments can be implemented in an amplification configuration including an operational amplifier, and even more specifically, in an amplification configuration including an operational amplifier having temperature-dependent gain. Background Art

[0003] Reference Figure 1 , shows a schematic circuit diagram for an amplifier circuit 10. The circuit 10 utilizes an operational amplifier (OPAMP) 12 having an inverting (-) input terminal, a non-inverting (+) input terminal, and an output terminal that generates an output voltage Vout. The input resistor R1 has a first terminal coupled to, preferably connected to, the inverting (-) input terminal and a second terminal coupled to receive an input signal Vin. The feedback resistor R2 has a first terminal coupled to, preferably connected to, the inverting (-) input terminal and a second terminal coupled to, preferably connected to, the output terminal. The non-inverting (+) input terminal is coupled to, preferably connected to, a power supply reference voltage node (e.g., ground).

[0004] By selecting the resistances of the resistors R1 and R2 of the gain-setting resistor network, the circuit 10 can be configured to exhibit a desired gain-temperature characteristic.

[0005] The resistor R1 has a first temperature coefficient whose temperature-dependent resistance is: where R10 is the nominal resistance at room temperature (e.g., 25 °C), ΔT is the change in temperature relative to room temperature, and is the thermal coefficient measured in 1 / °C.

[0006] The resistor R2 has a second temperature coefficient whose temperature-dependent resistance is: where R20 is the nominal resistance at room temperature (e.g., 25 °C), ΔT is the change in temperature relative to room temperature, and is the thermal coefficient measured in 1 / °C.

[0007] The ideal amplifier gain is given by: and is temperature-dependent.

[0008] The bandwidth (unity-gain product) of the amplifier circuit 10 is given by:

[0009]

[0010] Where: g m1 is the small-signal transconductance of the first (input) stage of OPAMP 12, C c is the compensation capacitor, and β is the amplification factor of the feedback network. In the context of a single-stage amplifier, the compensation capacitor C c is the load capacitor at the output node of the amplifier circuit. In the context of a multi-stage amplifier, the compensation capacitor C c is the compensation capacitor between the output nodes of each stage inside OPAMP 12, and the load capacitor C load is coupled to the output node of the amplifier circuit.

[0011] The amplifier bandwidth ω0 is accordingly temperature- and process-dependent (with a coefficient of ). The small-signal transconductance is also temperature-dependent.

[0012] Compensation of the amplifier circuit is required against temperature variations and process spread.

[0013] For example, the problem to be solved involves developing an amplifier with low bandwidth sensitivity to temperature and process variations that overcomes the drawbacks of the prior art. Summary of the Invention

[0014] By implementing an amplification scheme that overcomes the drawbacks of prior art solutions, where an operational amplifier (OPAMP), particularly the differential input stage of the amplifier, is biased with a tail current that varies with temperature and process to compensate for variations in the amplifier bandwidth. The amplification scheme includes: a proportional-to-absolute temperature (PTAT) current source to provide a PTAT current that generates a reference voltage; a voltage-to-current generator circuit that uses a differential amplifier circuit to convert the reference voltage into a reference current from which the tail current is obtained; and resistors coupled to the PTAT current source and the voltage-to-current generator circuit, the resistance values of these resistors depending on the operating temperature. These resistors are configured to match the resistors of the gain-setting circuit network for the OPAMP.

[0015] In an embodiment, an amplifier circuit includes: an operational amplifier having a first input terminal, a second input terminal, and an output terminal; an input resistor having a first resistor, the input resistor being coupled to the first input terminal; a feedback resistor having a second resistor, the feedback resistor being coupled between the output terminal and the first input terminal; wherein the operational amplifier includes a differential input circuit coupled to the first and second input terminals and biased by a bias current; and a bias current generator circuit. The bias current generator circuit includes: a proportional to absolute temperature (PTAT) current generator configured to generate a PTAT current; a first resistor having a resistance substantially equal to the sum of the first and second resistors; wherein the PTAT current is applied to the first resistor to generate a reference voltage; a voltage-to-current converter circuit configured to convert the reference voltage into a reference current, the reference current being generated according to a second resistor having a resistance substantially equal to the first resistor; and a mirror circuit configured to mirror the reference current to generate the bias current.

[0016] In an embodiment, a circuit includes: an amplifier circuit having a gain setting network formed by an input resistor and a feedback resistor; wherein the amplifier circuit includes a differential input circuit biased by a bias current tail; and a bias current generator circuit. The bias current generator circuit includes: a proportional to absolute temperature (PTAT) current generator coupled in series with a first resistor to generate a reference voltage; wherein the first resistor has a temperature-dependent resistance substantially equal to the sum of the temperature-dependent resistances of the input resistor and the feedback resistor; a voltage-to-current converter circuit configured to convert the reference voltage into a reference current applied across a second resistor; wherein the second resistor has a temperature-dependent resistance substantially equal to the temperature-dependent resistance of the input resistor; and a mirror circuit configured to mirror the reference current to generate the bias current.

[0017] In an embodiment, a circuit includes: an operational amplifier (OPAMP) having a gain setting network formed by an input resistor having a first resistor R1 and a feedback resistor having a second resistor R2; wherein the OPAMP has a bandwidth that is set according to the transconductance of the input stage of the OPAMP multiplied by a first factor equal to ; wherein the transconductance depends on a tail current configured to bias the input stage of the OPAMP; and a bias current generator circuit configured to generate the tail current according to a second factor substantially equal to ;

[0018] Second factor Set by the first resistor of the bias current generator circuit and by the second resistor of the bias current generator circuit, the first resistor having a third resistor R3 substantially equal to the sum of the first resistor R1 and the second resistor R2, and the second resistor having a fourth resistor R4 substantially equal to the first resistor R1. Description of the Drawings

[0019] To understand the present invention, embodiments thereof will now be described by way of non-limiting example only with reference to the accompanying drawings, in which:

[0020] Figure 1 is a schematic circuit diagram for an amplifier circuit;

[0021] Figure 2 is a schematic circuit diagram for an amplifier circuit with bandwidth compensation;

[0022] Figure 3 is a diagram Figure 2 showing the circuit details of the amplifier circuit with bandwidth compensation shown in ; and

[0023] Figure 4 is a diagram Figure 2 showing the circuit details of the amplifier circuit with bandwidth compensation shown in. Detailed Description

[0024] Referring to Figure 2 , a schematic circuit diagram for an amplifier circuit 110 is shown. The amplifier circuit is configured to compensate for variations in the amplifier bandwidth while exhibiting a temperature-dependent gain. Circuit 110 utilizes an operational amplifier (OPAMP) 112 having an inverting (-) input terminal, a non-inverting (+) input terminal, and an output terminal that generates an output voltage Vout. Input resistor R1 has a first terminal coupled to, preferably connected to, the inverting (-) input terminal and a second terminal coupled to receive an input signal Vin. Feedback resistor R2 has a first terminal coupled to, preferably connected to, the inverting (-) input terminal and a second terminal coupled to, preferably connected to, the output terminal. The non-inverting (+) input terminal is coupled to, preferably connected to, a supply reference voltage node (e.g., ground).

[0025] By selecting the resistances of resistors R1 and R2 for the gain-setting resistor network, circuit 110 can be configured to exhibit a desired gain-temperature characteristic.

[0026] Resistor R1 has a first temperature coefficient whose temperature-dependent resistance is: where R10 is the nominal resistance at room temperature (e.g., 25 °C), ΔT is the change in temperature relative to room temperature, and The thermal coefficient is measured in units of 1 / °C.

[0027] Resistor R2 has a second temperature coefficient Its temperature-dependent resistance is: where R20 is the nominal resistance at room temperature (e.g., 25 °C), ΔT is the change in temperature relative to room temperature, and The thermal coefficient is measured in units of 1 / °C.

[0028] The ideal amplifier gain is given by: And is temperature-dependent.

[0029] To compensate for the change in the amplifier bandwidth due to temperature, OPAMP 112 is biased with a bias current Ibias that depends on temperature and process variables. More specifically, the bias current Ibias is applied as the tail current of the differential input stage of the OPAMP and is generated based on a resistance that matches (i.e., is substantially equal, preferably equal) the resistance of the gain-setting resistor network of the OPAMP.

[0030] Additionally referring to Figure 3 , the differential input stage 114 of OPAMP 112 includes a differential pair of input transistors 116a and 116b, shown here only as an example as n-channel MOSFET devices. The first conduction terminal (here the drain) of each transistor 116a, 116b is coupled to a load circuit (formed by a p-channel MOSFET current mirror circuit 122 coupled to the voltage supply node Vdd) and is further coupled in a multi-stage embodiment to one or more additional amplification stages A (e.g., as shown in Figure 4 by reference numeral 124). The second conduction terminal (here the source) is coupled to, preferably connected to, a common node 118. The control terminal (here the gate) of input transistor 116a forms the inverting (-) input of OPAMP 112, and the control terminal (here the gate) of input transistor 116b forms the non-inverting (+) input of OPAMP 112. The tail transistor 120 applies the bias (tail) current Ibias to the common node 118. The tail transistor 120 has a first conduction terminal (here the drain) coupled to, preferably connected to, the common node 118 and a second conduction terminal (here the source) coupled to, preferably connected to, the supply reference voltage node (ground). The control terminal (here the gate) of the tail transistor 120 is controlled (as will be discussed in further detail below) to sink the bias current Ibias from the common node 118.

[0031] The bias current Ibias is generated by a bias current generator circuit 130. The bias current generator circuit 130 includes a current source 132 powered by a voltage supply node Vdd and configured to generate a proportional to absolute temperature (PTAT) reference current Iptat. The PTAT current generator circuit is well known to those skilled in the art. A resistor R3 is serially coupled, preferably connected, to the current source 132 at an intermediate node 134.

[0032] In this configuration, the resistor R3 has a resistance substantially equal to, preferably equal to, the sum of the resistances of the resistors R1 and R2 used to set the gain of the amplifier circuit 110: R3 = R1 + R2. Thus, like the resistances of the resistors R1 and R2, the resistance of the resistor R3 is temperature-dependent. The resistor R3 can be implemented, for example, by a series connection circuit of a resistor that matches the resistor R1 (having a temperature-dependent resistance ) and a resistor that matches the resistor R2 (having a temperature-dependent resistance ).

[0033] The application of the current Iptat across the resistor R3 generates a reference voltage Vref at the intermediate node 134: Vref = Iptat * R3 = Iptat(R1 + R2). The reference voltage Vref is applied to the inverting (-) input terminal of a differential amplifier circuit 140. In an embodiment, the differential amplifier circuit 140 includes an operational amplifier (OPAMP). The output terminal of the differential amplifier circuit 140 is coupled to, preferably connected to, the control terminal (here the gate) of an output transistor 142. The transistor 142 includes a p-channel MOSFET, the first conduction terminal (here the source) of which is coupled to, preferably connected to, the voltage supply node Vdd, and the second conduction terminal (here the drain) of which is coupled to, preferably connected to, an intermediate node 144. The intermediate node 144 is coupled to, preferably connected to, the non-inverting (+) input terminal of the differential amplifier circuit 140 in a feedback manner. A resistor R4 has a first terminal coupled to, preferably connected to, the intermediate node 144 and a second terminal coupled to, preferably connected to, a supply reference voltage node (ground).

[0034] The resistance of the resistor R4 is substantially equal to, preferably equal to, the resistance of the resistor R1 used in the gain setting network of the amplifier circuit 110. The resistor R4 can be implemented, for example, by a resistor circuit that matches the resistor R1 (having a temperature-dependent resistance ).

[0035] Differential amplifier circuit 140, transistor 142, and resistor R4 form a voltage-to-current converter circuit configured to convert a reference voltage Vref applied to the inverting (-) input terminal into a reference current Iref flowing through the series connection of transistor 142 and resistor R4, where:

[0036] The output terminal of differential amplifier circuit 140 is also coupled to, preferably connected to, the control terminal (here the gate) of mirror transistor 150. Transistor 150 includes a p-channel MOSFET, whose first conduction terminal (here the source) is coupled to, preferably connected to, the voltage supply node Vdd, and whose second conduction terminal (here the drain) is coupled to, preferably connected to, intermediate node 152. Transistor 150 mirrors the current Iref flowing through transistor 142 to generate a mirrored current Iref'. In an embodiment: Iref = Iref′, where transistors 142 and 150 have the same size (e.g., are matching replicas of each other). In an alternative embodiment, the current Iref' can be scaled relative to the current Iref by sizing transistor 150 to be larger or smaller than transistor 142.

[0037] The mirrored current Iref' flowing through transistor 150 is mirrored by a current mirror circuit formed by transistor 154 and tail transistor 120 with a mirror ratio of 1:k (where k is less than, greater than, or equal to 1, and non-zero) to apply a bias current Ibias to common node 118, where: Ibias = k * Iref′. The input transistor 154 of the current mirror circuit includes an n-channel MOSFET having a first conduction terminal (here the drain) coupled to, preferably connected to, intermediate node 152 and a second conduction terminal (here the source) coupled to, preferably connected to, the supply reference voltage node (ground). The control terminal (here the gate) of transistor 154 is coupled to, preferably connected to, the drain at intermediate node 152. The 1:k mirror ratio can be achieved, for example, by sizing tail transistor 120, which serves as the output transistor of the current mirror circuit, to be k times larger or smaller than input transistor 154 (where k is less than, greater than, or equal to 1, and non-zero).

[0038] Assuming that the differential pair of transistors 116a, 116b is biased in the subthreshold region, the transconductance of the input stage of OPAMP 112 is given by:

[0039]

[0040] Therefore, the bandwidth (unity-gain product) of amplifier circuit 110 is given by:

[0041]

[0042] where: η is a technology-related parameter; g m1 is the small-signal transconductance of the first stage (input stage) of OPAMP 112, C c is the compensation capacitor, and β is the amplification factor of the feedback network. In the context of a single-stage amplifier, as Figure 3 shown in c the compensation capacitor C Figure 4 is the load capacitor at the output node of the amplifier. In the context of a multi-stage amplifier, as c shown in load the compensation capacitor C

[0043] Therefore, the current Iptat is used to generate the tail bias current Ibias of the input stage (differential pair with transistors 116a, 116b) of OPAMP 112, compensating for the temperature dependence of the amplifier bandwidth introduced by the gain-setting resistors R1 and R2. In addition, the PTAT behavior of the thermal voltage is also compensated. Therefore, the bandwidth of the amplifier circuit 110 is independent of temperature, while the amplifier gain remains temperature-dependent.

[0044] It will be noted that appropriate design and layout guidelines should be employed in order to correctly match the behavior of the resistors R3 and R4 in the bias current generator circuit 130 with the resistors R1 and R2 that control the gain setting of the amplifier circuit 110. Generating the tail bias current Ibias with a circuit 130 using the same type of resistors (R3, R4) as those used in the amplifier gain-setting circuit ensures temperature and process spread compensation.

[0045] Therefore, the (temperature-dependent) resistance of resistor R3 is substantially equal to, preferably equal to, the sum of the (temperature-dependent) resistances of resistors R1 and R2. In addition, the (temperature-dependent) resistance of resistor R4 is substantially equal to, preferably equal to, the (temperature-dependent) resistance of resistor R1.

[0046] Similarly, it will be noted that appropriate design and layout guidelines should be employed in order to correctly match the behavior of transistors 142, 150 and transistors 120, 154 in the current mirror circuit used to generate the tail bias current Ibias from the reference current Iref. In addition, further circuit precautions can be taken to ensure correct (accurate) current mirroring. Such circuit precautions can include, for example, using a cascode current mirror circuit (as known to those skilled in the art).

[0047] The solution proposed in this paper for generating the tail bias current Ibias allows reducing the impact of temperature variations and process spread on the bandwidth of the amplifier circuit 110. In particular, the temperature stability requirement is removed from the design of the OPAMP 112 itself and transferred to the PTAT current generator 132.

[0048] Any residual temperature drift of the amplifier circuit 110 can be attributed to: the temperature drift of the compensation capacitor C c ; and the defect caused by the definition of the subthreshold transconductance g m .

[0049] Regarding the voltage-to-current converter circuit formed by the differential amplifier circuit 140, the transistor 142, and the resistor R4, it should be noted that the compensation of the Iref current generator feedback loop is easily achieved using dominant pole compensation.

[0050] The solution presented in this paper offers multiple advantages, including: the combination of the normal operation of an amplifier circuit with temperature-dependent gain and the temperature and process spread insensitivity of the improved amplifier bandwidth; by using the tail bias current Ibias solution, overdesign of the amplifier bandwidth is avoided; the generation of the tail bias current Ibias utilizes a voltage-to-current converter circuit (formed by the differential amplifier circuit 140, the transistor 142, and the resistor R4), which has a moderate circuit complexity to achieve the design goal of providing an amplifier bandwidth with temperature and process spread insensitivity.

[0051] Although Figure 3 and Figure 4 the circuit implementations shown in utilize the differential pair of the input transistors 116a, 116b and the tail current transistor 120 of the n-channel MOSFET type, it will be understood that the input transistors 116a, 116b and the tail current transistor 120 can alternatively be of the p-channel MOSFET type (the current mirror load circuit is formed by n-channel MOSFETs). In the case of the p-channel MOSFET implementation, as an example, the current mirror circuit function performed by the transistors 150 and 154 can be omitted. Then, the control (here the gate) terminal of the p-channel tail current transistor can be coupled to, preferably connected to, the output terminal of the differential amplifier 140 (by selectively adjusting the relative dimensions of the transistors, using a suitable 1:k scaling implementation, where k is less than, greater than, or equal to 1, and non-zero).

[0052] As used herein, the phrases "substantially the same" or "substantially equal" should be understood to mean the same or equal within the manufacturing tolerances of the process or within a margin of + / - 10%, preferably less than + / - 5%.

[0053] Although the present invention has been illustrated and described in detail in the drawings and the foregoing description, such illustrations and descriptions are to be considered illustrative or exemplary and not restrictive; the present invention is not limited to the disclosed embodiments. Other variations of the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed invention, from a study of the drawings, the disclosure, and the appended claims.

Claims

1. An amplifier circuit, comprising: An operational amplifier having a first input terminal, a second input terminal, and an output terminal; An input resistor having a first resistance and coupled to the first input terminal; A feedback resistor having a second resistance and coupled between the output terminal and the first input terminal; Wherein the operational amplifier includes a differential input circuit coupled to the first input terminal and the second input terminal and biased by a bias current; and A bias current generator circuit, comprising: A proportional-to-absolute-temperature (PTAT) current generator configured to generate a PTAT current; A first resistor having a resistance substantially equal to the sum of the first resistance and the second resistance; Wherein the PTAT current is applied to the first resistor to generate a reference voltage; A voltage-to-current converter circuit configured to convert the reference voltage into a reference current generated according to a second resistor having a resistance substantially equal to the first resistance; and A mirror circuit configured to mirror the reference current to generate the bias current.

2. The amplifier circuit according to claim 1, wherein The mirror ratio of the reference current to the bias current is 1:k, where k is less than, greater than, or equal to 1, and non-zero.

3. The amplifier circuit according to claim 1, wherein, The voltage-to-current converter circuit includes: A differential amplifier having a first input terminal, a second input terminal, and an output terminal; Wherein the first input terminal is coupled to receive the reference voltage; An output transistor having a control terminal coupled to the output terminal of the differential amplifier; A feedback connection between the conduction terminal of the output transistor and the second input terminal of the differential amplifier; and Wherein the second resistor is coupled between the conduction terminal of the output transistor and a supply reference node, and the reference current flows through the second resistor.

4. A circuit, comprising: An amplifier circuit having a gain setting network formed by an input resistor and a feedback resistor; Wherein the amplifier circuit includes a differential input circuit biased by a bias current tail; and A bias current generator circuit, comprising: A proportional-to-absolute-temperature (PTAT) current generator coupled in series with a first resistor to generate a reference voltage; Wherein the first resistor has a temperature-dependent resistance substantially equal to the sum of the temperature-dependent resistances of the input resistor and the feedback resistor; A voltage-to-current converter circuit configured to convert the reference voltage into a reference current applied across a second resistor; Wherein the second resistor has a temperature-dependent resistance substantially equal to the temperature-dependent resistance of the input resistor; and A mirror circuit configured to mirror the reference current to generate the bias current.

5. The circuit according to claim 4, wherein, The mirror ratio of the reference current to the bias current is 1:k, where k is less than, greater than, or equal to 1, and non-zero.

6. The circuit according to claim 4, wherein, The voltage-to-current converter circuit includes: A differential amplifier coupled to receive the reference voltage; An output transistor having a control terminal coupled to the output terminal of the differential amplifier; A feedback connection between a conduction terminal of the output transistor and an input terminal of the differential amplifier; and wherein the second resistor is coupled between the conduction terminal of the output transistor and a supply reference node, and the reference current flows through the second resistor.

7. A circuit comprising: An operational amplifier OPAMP having a gain setting network formed by an input resistor having a first resistor R1 and a feedback resistor having a second resistor R2; wherein, the OPAMP has a bandwidth that is set according to the transconductance of the input stage of the OPAMP multiplied by a first factor equal to ; wherein the transconductance depends on a tail current configured to bias an input stage of the OPAMP; and A bias current generator circuit configured to generate the tail current based on a second factor substantially equal to .

8. The circuit according to claim 7, wherein, The second factor is set by a first resistor of the bias current generator circuit and by a second resistor of the bias current generator circuit, the first resistor having a third resistor R3 that is substantially equal to the sum of a first resistor R1 and a second resistor R2, and the second resistor having a fourth resistor R4 that is substantially equal to the first resistor R1.

9. The circuit according to claim 7, wherein The bias current generator circuit comprises: A proportional-to-absolute temperature PTAT current generator coupled in series with a first resistor to generate a reference voltage; wherein the first resistor has a third resistor R3 substantially equal to the sum of the first resistor R1 and the second resistor R2; A voltage-to-current converter circuit configured to convert the reference voltage into a reference current applied across a second resistor; wherein the second resistor has a fourth resistor R4 substantially equal to the first resistor R1; and A mirror circuit configured to mirror the reference current to generate the tail current.

10. The circuit according to claim 9, wherein, The mirror ratio of the reference current to the tail current is 1:k, where k is less than, greater than, or equal to 1, and non-zero.

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