Voltage conversion rate calibration circuit and method for decimal N frequency division-sampling phase-locked loop

Abstract

The invention provides a voltage conversion rate calibration circuit and method for a decimal N frequency division-sampling phase-locked loop, and the circuit comprises a voltage rate conversion state machine, and also comprises a sampling phase discriminator, an oscillator, a sampling clock generation circuit, and a digital time converter which are used in the sampling phase-locked loop. Wherein the sampling phase discriminator comprises a ramp generator and a sampling circuit, and the voltage conversion rate calibration state machine controls the output voltage conversion rate of the ramp generator. According to the decimal N frequency division-sampling phase-locked loop circuit and the voltage conversion rate calibration circuit and method thereof provided by the invention, the problems that the design and other costs of hardware are increased, the calibration accuracy is reduced and the like in the existing calibration technology of the voltage conversion rate of a sampling phase discriminator applied to a sampling phase-locked loop can be solved.

Description

Technical Field

[0001] The present invention relates to the technical field of voltage conversion rate calibration, and more specifically, to a voltage conversion rate calibration circuit and method for a fractional-N frequency division-sampling phase-locked loop circuit. Background Art

[0002] Traditional voltage conversion rate calibration techniques are mainly applied in driving circuits or analog amplifiers. Such techniques detect the transition time of the rising edge or falling edge of the output signal during the voltage transition from low to high or from high to low. For example, during the transition period, the output is detected as high level while the output remains low level at other times. Subsequently, a counter and / or other circuits can be used to generate a control signal to adjust the resistance / capacitance value, transistor size, etc., and ultimately achieve the calibration of the voltage conversion rate of the output signal.

[0003] For the sampling phase detector in the sampling phase-locked loop, the voltage conversion rate of its clock signal after passing through the ramp generator and the clock frequency determine the gain of the sampling phase detector. Therefore, the change in the voltage conversion rate of the clock signal with the process corner will affect the loop bandwidth size under different process corners. To ensure a small change in the loop bandwidth, it is necessary to calibrate the voltage conversion rate of the clock signal. However, directly adopting the above traditional voltage conversion rate calibration technique requires additional design of a detection circuit, which will increase the hardware design and other costs.

[0004] The existing calibration technique for the voltage conversion rate of the sampling phase detector applied in the sampling phase-locked loop generates a replicated differential sampling output signal by replicating the sampling phase detector circuit, and passes the sampling output signal through circuits such as peak detection and a comparator to obtain the transition time detection result. Finally, a counter, etc., is used to obtain the corresponding control signal for the voltage conversion rate, and based on this control signal, the voltage conversion rate of the sampling phase detector in the sampling phase-locked loop is calibrated (for example, [US7288958B2]).

[0005] Compared with directly applying the traditional voltage conversion rate calibration technique, although the existing technique (for example, [US7288958B2]) can reduce the design cost of the detection circuit part by using a replicated sampling phase detector, it still needs to design additional circuits such as a peak detection circuit, a comparator, and a counter. Moreover, the deviation of the peak detection circuit based on analog design will affect the detection result of the voltage conversion rate and is not conducive to iterative design under different processes. It can be seen that the existing technique still has disadvantages such as increasing the hardware design and other costs, and reducing the calibration accuracy.

[0006] Based on the above technical problems, there is an urgent need for a solution that does not require additional hardware design and can effectively ensure the calibration accuracy. Summary of the Invention

[0007] In view of the above problems, the object of the present invention is to provide a voltage conversion rate calibration circuit and method for a fractional-N frequency division-sampling phase-locked loop circuit, so as to solve the problems of the existing calibration technology for the voltage conversion rate of the sampling phase detector applied in the sampling phase-locked loop, such as increasing the design and other costs of the hardware and reducing the calibration accuracy.

[0008] The present invention provides a voltage conversion rate calibration circuit for a fractional-N frequency division-sampling phase-locked loop, including a fractional-N frequency division-sampling phase-locked loop circuit and a voltage conversion rate calibration state machine. The fractional-N frequency division-sampling phase-locked loop circuit includes a sampling phase detector, an oscillator, a sampling clock generation circuit, and a digital time converter; wherein, The oscillator is used to generate an oscillation clock signal; The reference clock signal is sequentially processed by the digital time converter and the sampling clock generation circuit to form a sampling clock signal; The sampling phase detector is used to process the loop feedback clock signal converted from the oscillation clock signal and the sampling clock signal, and generate a phase detection output signal; The voltage conversion rate calibration state machine is used to control the output voltage conversion rate of the sampling phase detector.

[0009] In addition, a preferred solution is that the fractional-N frequency division-sampling phase-locked loop circuit further includes a multi-mode frequency divider; and, The multi-mode frequency divider is used to process the oscillation clock signal and output the loop feedback clock signal.

[0010] In addition, a preferred solution is that the fractional-N frequency division-sampling phase-locked loop circuit further includes a modulator; and, The fractional frequency division of the fractional-N frequency division-sampling phase-locked loop circuit is realized by controlling the multi-mode frequency divider through the output of the frequency control word after passing through the modulator.

[0011] In addition, a preferred solution is that the sampling phase detector includes a ramp generator and a sampling circuit; wherein, The input signal of the ramp generator includes the loop feedback clock signal, the input signal of the sampling circuit includes the sampling clock signal, and the output signal of the ramp generator is sampled by the sampling circuit to form the phase detection output signal; and, The voltage conversion rate calibration state machine is used to control the output voltage conversion rate of the ramp generator.

[0012] In addition, a preferred solution is that a loop filter is provided between the output end of the sampling phase detector and the oscillator; wherein, The phase detection output signal is used to control the frequency and phase of the oscillator after being processed by the loop filter; and, When the fractional-N frequency division-sampling phase-locked loop circuit is closed-loop, the frequency and phase of the oscillator track the reference clock signal.

[0013] In addition, preferably, the oscillator is configured with an automatic frequency calibration module; The digital time converter is configured with a range calibration module and a gain calibration module.

[0014] In addition, preferably, a sampling voltage monitoring circuit is connected to the output end of the sampling phase detector.

[0015] On the other hand, the present invention also provides a voltage conversion rate calibration method for a fractional-N frequency division-sampling phase-locked loop, which is implemented based on the aforementioned voltage conversion rate calibration circuit of the fractional-N frequency division-sampling phase-locked loop. The calibration method includes: S110: Automatically calibrate the frequency of the oscillator through the automatic frequency calibration module; S120: Calibrate the range of the digital time converter through the range calibration module; S130: Calibrate the voltage conversion rate of the sampling phase detector based on the voltage conversion rate calibration state machine.

[0016] In addition, preferably, the range calibration module includes a replicated digital time converter and a digital time converter range calibration state machine; and, the calibrating the range of the digital time converter through the range calibration module includes: Simultaneously input the same reference clock signal into the digital time converter and the replicated digital time converter respectively; wherein, the input codewords of the digital time converter and the replicated digital time converter are the maximum converter code and the minimum converter code respectively; Compare the phase of the output signal of the digital time converter and the output signal of the replicated digital time converter after a set delay through the sampling phase detector; Generate a range control codeword for the digital time converter by the digital time converter range calibration state machine based on the phase comparison result; Calibrate the range of the digital time converter through the range control codeword.

[0017] In addition, preferably, the calibrating the voltage conversion rate of the sampling phase detector based on the voltage conversion rate calibration state machine includes: Simultaneously input the same reference clock signal into the digital time converter and the replicated digital time converter respectively; Use the output signal of the replication digital time converter as the input signal of the ramp generator in the sampling phase detector, and use the sampling clock signal formed after processing the output signal of the digital time converter by the sampling clock generation circuit as the input signal of the sampling circuit in the sampling phase detector; Use the output signal of the sampling voltage monitoring circuit as the input signal of the voltage conversion rate calibration state machine; Perform voltage conversion rate calibration on the sampling phase detector based on the output signal of the voltage conversion rate calibration state machine.

[0018] Compared with the prior art, the voltage conversion rate calibration circuit and method of the fractional-N frequency division-sampling phase-locked loop circuit provided by the present invention can detect the voltage conversion rate by using the existing hardware resources of the fractional-N frequency division-sampling phase-locked loop circuit; in the detection of its voltage conversion rate, no additional design and other costs are generated, and through the cooperation of other calibration modules or circuits (such as the automatic frequency calibration module, the range calibration module and the gain calibration module configured with the digital time converter, the sampling voltage monitoring circuit, etc.) and a reasonable calibration process, the accuracy of calibration can be effectively guaranteed.

[0019] To achieve the above and related purposes, one or more aspects of the present invention include features that will be described in detail later and specifically pointed out in the claims. The following description and the accompanying drawings detail certain exemplary aspects of the present invention. However, these aspects indicate only some of the various ways in which the principles of the present invention can be used. In addition, the present invention is intended to cover all these aspects and their equivalents. Description of the Drawings

[0020] By referring to the following description in conjunction with the drawings and the content of the claims, and with a more comprehensive understanding of the present invention, other objects and results of the present invention will become more apparent and easier to understand. In the drawings: Figure 1 It is a schematic diagram of a fractional-N frequency division-sampling phase-locked loop circuit provided by an embodiment of the present invention; Figure 2 It is a schematic diagram of a voltage conversion rate calibration circuit of a fractional-N frequency division-sampling phase-locked loop provided by an embodiment of the present invention; Figure 3 It is a flowchart of a voltage conversion rate calibration method of a fractional-N frequency division-sampling phase-locked loop provided by an embodiment of the present invention; Figure 4 It is a schematic diagram of the range calibration of a digital time converter provided by an embodiment of the present invention; Figure 5 It is a schematic diagram of a voltage conversion rate calibration method of a fractional-N frequency division-sampling phase-locked loop provided by an embodiment of the present invention; Figure 6 A comparison diagram of each signal in the voltage conversion rate calibration method of the fractional-N frequency division-sampling phase-locked loop provided by the embodiment of the present invention.

[0021] In all the drawings, the same reference numerals indicate similar or corresponding features or functions. Detailed implementation manners

[0022] In the following description, for the purpose of illustration, in order to provide a comprehensive understanding of one or more embodiments, many specific details are set forth. However, it is obvious that these embodiments can also be implemented without these specific details. In other instances, well-known structures and devices are shown in block diagram form for the purpose of facilitating the description of one or more embodiments.

[0023] It should be noted that the diagrams provided in this embodiment only illustrate the basic concept of the present invention schematically. Therefore, only the components related to the present invention are shown in the diagrams, rather than being drawn according to the number, shape, and size of the components in actual implementation. The type, quantity, and ratio of each component in actual implementation can be arbitrarily changed, and the component layout type may also be more complex.

[0024] The principle of the voltage conversion rate calibration circuit of the fractional-N frequency division-sampling phase-locked loop circuit provided by the present invention will be introduced in detail below with reference to the accompanying drawings. Figure 1 The principle of a fractional-N frequency division-sampling phase-locked loop circuit provided by the embodiment of the present invention is shown. Figure 2 The principle of a voltage conversion rate calibration circuit of a fractional-N frequency division-sampling phase-locked loop provided by the embodiment of the present invention is shown. Figure 3 The flow of a voltage conversion rate calibration method of a fractional-N frequency division-sampling phase-locked loop provided by the embodiment of the present invention is shown. Figure 4 The digital time converter range calibration principle provided by the embodiment of the present invention is shown. Figure 5 The principle of a voltage conversion rate calibration method of a fractional-N frequency division-sampling phase-locked loop provided by the embodiment of the present invention is shown. Figure 6 The comparison relationship of each signal in the voltage conversion rate calibration method of the fractional-N frequency division-sampling phase-locked loop provided by the embodiment of the present invention is shown.

[0025] Combined Figure 1 With Figure 2 It can be seen that the voltage conversion rate calibration circuit of the fractional-N frequency division-sampling phase-locked loop circuit provided by the present invention includes a fractional-N frequency division-sampling phase-locked loop circuit and a voltage conversion rate calibration state machine. Among them, the fractional-N frequency division-sampling phase-locked loop circuit includes a sampling phase detector, an oscillator, a sampling clock generation circuit, and a digital time converter; among them, The oscillator is used to generate an oscillating clock signal (DCLK). The reference clock signal (REF_CLK) is processed by the digital time converter and the sampling clock generation circuit in sequence to form a two-phase sampling clock signal (including PH1 and PH2). The sampling phase detector is used to process the loop feedback clock signal (FB_CLK) converted from the oscillating clock signal and the sampling clock signal, and generate a phase detection output signal. The voltage conversion rate calibration state machine is used to control the output voltage conversion rate of the sampling phase detector.

[0026] Further, to achieve the formation of the loop feedback clock signal, the fractional-N frequency division-sampling phase-locked loop circuit further includes a multi-mode frequency divider, which is used to process the oscillating clock signal and output the loop feedback clock signal (FB_CLK).

[0027] In a specific embodiment of the present invention, the sampling phase detector may include a ramp generator and a sampling circuit (a switched-capacitor sampling circuit); wherein, the ramp generation of the ramp generator mainly results from the resistor in the charging path, and the voltage conversion rate can be monotonically changed by changing the resistance value of the resistor.

[0028] Specifically, the input signal of the ramp generator includes the loop feedback clock signal after the DCLK output from the oscillator passes through the multi-mode frequency divider, the input signal of the sampling circuit includes the sampling clock signal (the clock signal after the reference clock signal passes through the digital time converter and the sampling clock generation circuit), the output signal of the ramp generator is sampled by the sampling circuit to form the phase detection output signal; the voltage conversion rate calibration state machine is used to control the output voltage conversion rate of the ramp generator.

[0029] Further, a loop filter is provided between the output end of the sampling phase detector and the oscillator; wherein, the phase detection output signal is processed by the loop filter to control the frequency and phase of the oscillator; and when the fractional-N frequency division-sampling phase-locked loop circuit is closed-loop, the frequency and phase of the oscillator track the reference clock signal.

[0030] Further, the fractional-N frequency division-sampling phase-locked loop circuit provided by the present invention further includes a modulator (such as a ΔΣ modulator), and the fractional frequency division of the fractional-N frequency division-sampling phase-locked loop circuit is realized by controlling the multi-mode frequency divider through the output of the frequency control word FCW after passing through the modulator. In addition, to minimize the influence of the quantization noise of FCW after passing through the ΔΣ modulator on the phase noise and fractional spurs, phase compensation can be performed through a digital time converter. And to achieve a better compensation effect, the digital time converter usually needs to be provided with a range and gain calibration module.

[0031] Specifically, the digital time converter is configured with a range calibration module and a gain calibration module. By setting the range calibration module and the gain calibration module, it can be ensured that the digital time converter can complete phase compensation more ideally to offset the influence of quantization noise on phase noise or fractional spurs as much as possible.

[0032] More specifically, the oscillator is configured with an automatic frequency calibration module. The automatic frequency calibration module can ensure that when the phase-locked loop operates in an open-loop mode, the self-oscillation frequency of the oscillator is close to the target operating frequency when the loop is closed.

[0033] In addition, the fractional-N frequency division-sampling phase-locked loop circuit provided by the present invention also connects a working state monitoring circuit (such as a sampling voltage monitoring circuit) to the output end of the sampling phase detector. The working state monitoring circuit can monitor in real time whether the sampling voltage exceeds the range from VL to VH.

[0034] It should be noted that by setting the components in the fractional-N frequency division-sampling phase-locked loop circuit provided by the present invention, on the basis of the above two existing calibration modules, the clock frequency of DCLK can be obtained more accurately first, and then the range calibration of the digital time converter is completed by using DCLK, and a fine digital time conversion accuracy t is obtained. dtc,res Under these conditions, the present invention can complete the voltage conversion rate calibration of the sampling phase detector by using the existing hardware resources of the fractional-N frequency division-sampling phase-locked loop circuit.

[0035] It should be noted that from Figure 2 it can be seen that the voltage conversion rate calibration circuit of a fractional-N frequency division-sampling phase-locked loop provided by the present invention has no complex additional hardware design cost, especially the additional analog circuit design; the additional circuit is only the voltage conversion rate calibration state machine of the control circuit; that is to say, only a simple voltage conversion rate calibration state machine, combined with the existing calibration circuit of the fractional-N frequency division-sampling phase-locked loop circuit, can complete the process as Figure 3 shown, so as to realize the calibration of the voltage conversion rate.

[0036] To further illustrate the working principle of the voltage conversion rate calibration circuit of a fractional-N frequency division-sampling phase-locked loop provided by the present invention, the present invention also provides a voltage conversion rate calibration method for a fractional-N frequency division-sampling phase-locked loop, which is implemented based on the foregoing voltage conversion rate calibration circuit of the fractional-N frequency division-sampling phase-locked loop. As Figure 3 shown, the calibration method includes: S110: Automatically calibrate the oscillator through the automatic frequency calibration module; S120: Perform range calibration on the digital time converter through the range calibration module; S130: Calibrate the voltage conversion rate of the sampling phase detector based on the voltage conversion rate calibration state machine.

[0037] In the present invention, after completing the automatic frequency calibration of the oscillator and the range calibration of the digital time converter according to the Figure 3 process, the output of the digital-to-time analog converter is copied to replace the output of the multi-mode frequency divider as the input of the sampling phase detector, and the calibration of the voltage conversion rate in the sampling phase detector is started.

[0038] Specifically, as Figure 4 shown, to achieve the range calibration of the digital time converter, the range calibration module may include a copy digital time converter and a digital time converter range calibration state machine; and further, the range calibration of the digital time converter by the range calibration module includes: Simultaneously input the same reference clock signal into the digital time converter and the copy digital time converter respectively; wherein, the input codewords of the digital time converter and the copy digital time converter are the maximum converter code and the minimum converter code respectively; Compare the phase of the output signal of the digital time converter and the output signal of the copy digital time converter after a set delay through the sampling phase detector; Generate the range control codeword of the digital time converter based on the phase comparison result through the digital time converter range calibration state machine; Calibrate the range of the digital time converter through the range control codeword.

[0039] More specifically, to achieve the calibration of the voltage conversion rate of the sampling phase detector, the calibration of the voltage conversion rate of the sampling phase detector based on the voltage conversion rate calibration state machine further includes: Simultaneously input the same reference clock signal into the digital time converter and the copy digital time converter respectively; Use the output signal of the copy digital time converter as the input signal of the ramp generator in the sampling phase detector, and use the sampling clock signal formed by processing the output signal of the digital time converter through the sampling clock generation circuit as the input signal of the sampling circuit in the sampling phase detector; Use the output signal of the sampling voltage monitoring circuit as the input signal of the voltage conversion rate calibration state machine; Calibrate the voltage conversion rate of the sampling phase detector based on the output signal of the voltage conversion rate calibration state machine.

[0040] Furthermore, Figure 5 shown is the main circuit connection involved in the voltage conversion rate calibration of the present invention, asFigure 5 As shown, the inputs of the digital time converter and the replicated digital time converter are both the same reference clock. The output DTCRo of the replicated digital time converter serves as the input to the ramp generator in the sampling phase detector. In the sampling phase detector, the sampling clock is the clock signal PH1 / PH2 obtained by passing the reference clock REF_CLK through the digital time converter and the sampling clock generation circuit. The output IN_BOUND of the sampling voltage monitoring circuit is the input to the voltage conversion rate calibration state machine. The voltage conversion rate calibration state machine generates an output SR_CODE to control the resistance value in the ramp generator to achieve voltage conversion rate calibration. Among them, the codeword of the replicated digital time converter is fixed at 0, and when the codeword of the digital time converter scans from 0, the output voltage VSAMP of the sampling phase detector changes from high to low. In the sampling voltage detection circuit, VSAMP is the signal actually sampled from Y1.

[0041] Figure 6 The following shows the comparison relationship of the main signals in the voltage conversion rate calibration, as Figure 6 shown. By scanning the input codeword of the digital time converter, an offset of the sampling edge of the sampling clock is generated. In this way, at different sampling times, the sampling phase detector will sample different voltage values on the rising edge of the output Y1 of DTCRo after passing through the ramp generator. When the sampling voltage VSAMP is between VH and VL, IN_BOUND is at a high level, otherwise it is at a low level. During the process of scanning the codeword, the voltage conversion rate calibration state machine will record the codeword length corresponding to IN_BOUND = 1 as D DTCr , and using the calibrated digital time conversion accuracy t dtc,res , the voltage conversion rate SR can be obtained as:

[0042] Based on the detected voltage conversion rate and the monotonic change relationship between the resistance and the voltage conversion rate, the voltage conversion rate calibration codeword SR_CODE can be correspondingly adjusted to change the resistance, so as to obtain the required voltage conversion rate and complete the calibration.

[0043] As described above by way of example with reference to the accompanying drawings, the voltage conversion rate calibration circuit and method of the fractional-N frequency division-sampling phase-locked loop circuit according to the present invention are described. However, those skilled in the art should understand that various improvements can be made to the above-mentioned voltage conversion rate calibration circuit and method of the fractional-N frequency division-sampling phase-locked loop circuit of the present invention without departing from the content of the present invention. Therefore, the protection scope of the present invention should be determined by the content of the appended claims.

Claims

1. A voltage conversion rate calibration circuit for a fractional N - frequency - division sampling phase - locked loop, characterized in that, Comprising a fractional-N frequency division-sampling phase-locked loop circuit and a voltage conversion rate calibration state machine, the fractional-N frequency division-sampling phase-locked loop circuit includes a sampling phase detector, an oscillator, a sampling clock generation circuit, and a digital time converter; wherein, The oscillator is used to generate an oscillation clock signal; The reference clock signal is sequentially processed by the digital time converter and the sampling clock generation circuit to form a sampling clock signal; The sampling phase detector is used to process the loop feedback clock signal converted from the oscillation clock signal and the sampling clock signal, and generate a phase detection output signal; The voltage conversion rate calibration state machine is used to control the output voltage conversion rate of the sampling phase detector.

2. The voltage conversion rate calibration circuit of the fractional-N frequency division-sampling phase-locked loop according to claim 1, wherein, The fractional-N frequency division-sampling phase-locked loop circuit further includes a multi-mode frequency divider; and, The multi-mode frequency divider is used to process the oscillation clock signal and output the loop feedback clock signal.

3. The voltage conversion rate calibration circuit of the fractional-N frequency division-sampling phase-locked loop according to claim 2, wherein, The fractional-N frequency division-sampling phase-locked loop circuit further includes a modulator; and, The fractional division of the fractional-N frequency division-sampling phase-locked loop circuit controls the multi-mode frequency divider through the output of the frequency control word after passing through the modulator.

4. The voltage conversion rate calibration circuit of the fractional-N frequency division-sampling phase-locked loop according to claim 3, wherein, The sampling phase detector includes a ramp generator and a sampling circuit; wherein, The input signal of the ramp generator includes the loop feedback clock signal, the input signal of the sampling circuit includes the sampling clock signal, and the output signal of the ramp generator is sampled by the sampling circuit to form the phase detection output signal; and, The voltage conversion rate calibration state machine is used to control the output voltage conversion rate of the ramp generator.

5. The voltage conversion rate calibration circuit of the fractional-N frequency division-sampling phase-locked loop according to claim 4, wherein, A loop filter is provided between the output end of the sampling phase detector and the oscillator; wherein, The phase detection output signal is processed by the loop filter to control the frequency and phase of the oscillator; and, When the fractional-N frequency division-sampling phase-locked loop circuit is closed-loop, the frequency and phase of the oscillator track the reference clock signal.

6. The voltage conversion rate calibration circuit of the fractional-N frequency division-sampling phase-locked loop according to claim 5, wherein, The oscillator is configured with an automatic frequency calibration module; The digital time converter is configured with a range calibration module and a gain calibration module.

7. The voltage conversion rate calibration circuit of the fractional-N frequency division-sampling phase-locked loop according to claim 6, wherein, A sampling voltage monitoring circuit is connected to the output end of the sampling phase detector.

8. A voltage conversion rate calibration method for a fractional N-divide-sampling phase-locked loop, characterized in that, Based on the voltage conversion rate calibration circuit of the fractional-N frequency division-sampling phase-locked loop described in claim 7, the calibration method includes: S110: Automatically calibrate the frequency of the oscillator through the automatic frequency calibration module; S120: Calibrate the digital time converter through the range calibration module; S130: Calibrate the voltage conversion rate of the sampling phase detector based on the voltage conversion rate calibration state machine.

9. The voltage conversion rate calibration method of the fractional N-frequency division-sampling phase-locked loop according to claim 8, characterized in that, The range calibration module includes a replicated digital time converter and a digital time converter range calibration state machine; and, calibrating the digital time converter through the range calibration module includes: Simultaneously input the same reference clock signal into the digital time converter and the replicated digital time converter respectively; wherein, the input codewords of the digital time converter and the replicated digital time converter are the maximum converter code and the minimum converter code respectively; Perform phase comparison on the output signal of the digital time converter and the output signal of the replicated digital time converter after a set delay through the sampling phase detector; Generate the range control codeword of the digital time converter based on the phase comparison result through the digital time converter range calibration state machine; Calibrate the range of the digital time converter through the range control codeword.

10. The voltage conversion rate calibration method of the fractional N-divide-sampling phase-locked loop according to claim 9, characterized in that Calibrating the voltage conversion rate of the sampling phase detector based on the voltage conversion rate calibration state machine includes: Simultaneously input the same reference clock signal into the digital time converter and the replicated digital time converter respectively; Use the output signal of the replicated digital time converter as the input signal of the ramp generator in the sampling phase detector, and use the sampling clock signal formed after processing the output signal of the digital time converter by the sampling clock generation circuit as the input signal of the sampling circuit in the sampling phase detector; Use the output signal of the sampling voltage monitoring circuit as the input signal of the voltage conversion rate calibration state machine; Calibrate the voltage conversion rate of the sampling phase detector based on the output signal of the voltage conversion rate calibration state machine.

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