High-speed time domain interleaving analog-to-digital conversion system based on radio frequency sampling front-end technology

Abstract

The invention discloses a high-speed time domain interleaving analog-to-digital conversion system based on a radio frequency sampling front-end technology. The high-speed time domain interleaving analog-to-digital conversion system comprises a clock generation circuit based on a time sequence starting circuit, a signal buffer circuit based on a body-driven auxiliary turnover source follower and a single-channel ADC circuit based on a gain multiplexing CDRA. According to the time domain interleaving analog-to-digital conversion system, a framework from a voltage domain to a time domain and then to the voltage domain is adopted for signal quantization on the whole, and the time sequence starting circuit ensures that the clock generation circuit can generate a complete and correct-sequence sampling clock for the multi-channel time domain interleaving system in a PVT fluctuation environment; according to the signal buffer circuit based on the body-driven auxiliary turnover source follower, smaller output impedance, better kick-back resistance and higher buffer linearity can be realized; based on the gain multiplexing type CDRA circuit, the robustness and the common mode stability of the inter-stage residual amplifier circuit in the PVT fluctuation environment are effectively improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of high-speed hybrid-domain multi-channel interleaved analog-to-digital converters, and particularly relates to a high-speed time-domain interleaved analog-to-digital conversion system based on radio frequency sampling front-end technology. Background Art

[0002] With the development of the information age, the continuous emergence of technologies such as 5G communication technology and the Internet of Things, high-data-rate communication systems have gradually become the focus of development and research. High-speed medium-high-precision ADC (analog to digital converter) is a key interface connecting external physical signals and chip digital processing, and is an essential component in wireless communication devices such as mobile phones, satellite communications, and radars. Currently, the main architecture of high-speed medium-high-precision analog-to-digital converter systems is still the multi-channel time-domain interleaved type. As shown in Figure 1 it mainly includes three important functional modules: a sampling clock generation module, a broadband high-linearity radio frequency sampling network front-end, and a single-channel ADC.

[0003] The traditional timing start circuit is composed of a series of clock-controlled D flip-flops. In a low-frequency application environment, this D flip-flop chain architecture has the best stability under PVT (Process Voltage Temperature, process / power supply voltage / temperature fluctuations). However, in ultra-high-frequency (e.g., >100 GHz) time-domain interleaved system applications, this architecture is restricted by the limited storage and conduction speed of the D flip-flop itself. Even a timing start circuit constructed with TSPC-type high-speed D flip-flop units may face the problem of incorrect channel opening order due to insufficient time margin under PVT fluctuations, and cannot achieve a completely ideal opening effect. This will lead to disorder or even loss of the order of code values output between channels, greatly increasing the difficulty of subsequent calibration work.

[0004] The performance of the sampling network front-end largely restricts and determines the signal processing ability of the entire ADC system, and thus becomes a key concern area for analog design engineers. As shown in Figure 2 it is a signal buffer circuit based on a traditional flip-type source follower. This architecture reduces the drain current I of the main buffer transistor by moving the bias current source from the source terminal of the main buffer transistor to the drain terminal. Figure 2 d ​Input signal dependence. In addition, additional loop gain is provided to obtain the ideal unity gain, and the output impedance of the buffer is minimized to drive small loads. This architecture has lower buffer distortion and larger buffer bandwidth compared to the early single-transistor source follower, and is currently a more concerned input signal buffer circuit architecture. However, the Class A-based operating mode results in a relatively large static power consumption overhead for this architecture. Moreover, the obvious channel modulation effect and low supply voltage under the development of advanced processes seriously deteriorate the linearity and swing performance of the output signal of the traditional buffer architecture. In addition, the non-linear voltage-variable capacitance effect at the input and output nodes of the main buffer transistor becomes an important factor restricting the optimization of linearity.

[0005] As the core component of a time-interleaved system, for a single-channel ADC, the trade-off among speed, accuracy, and power consumption is the basis for system performance optimization. Currently, the architecture concept of "two-step" amplification greatly alleviates the design pressure of concentrating the improvement of slewing and bandwidth performance on a single operational amplifier, but inevitably brings accompanying problems such as relative offset and complex structure. In recent years, "digital" new-type operational amplifiers based on inverter circuits (such as ring operational amplifiers, CDRAs) provide the possibility for developing inter-stage operational amplifiers that are compatible with the development trend of processes and have higher comprehensive performance. Refer to Figure 5 as shown Figure 5 is a traditional CDRA circuit, which has good stability and bandwidth performance, but the optimization concept based on sacrificing the open-loop gain limits the amplification accuracy of this type of operational amplifier. Summary of the Invention

[0006] In order to solve the above problems existing in the prior art, the present invention provides a high-speed time-interleaved analog-to-digital conversion system based on radio frequency sampling front-end technology. The technical problems to be solved by the present invention are realized through the following technical solutions:

[0007] The present invention provides a high-speed time-interleaved analog-to-digital conversion system based on radio frequency sampling front-end technology, including: a clock generation circuit, a signal buffer circuit, and a multi-channel ADC circuit, wherein,

[0008] The clock generation circuit uses a timing start circuit to achieve two-stage frequency division to generate a complete and correctly ordered multi-channel sampling clock;

[0009] The signal buffer circuit includes a first-stage signal buffer circuit and a second-stage signal buffer circuit based on a body-driven assisted flip-type source follower. The first-stage signal buffer circuit is used to perform a first buffer on the input radio frequency signal to obtain a first-buffered signal. The second-stage signal buffer circuit uses a VTC circuit to perform a time-domain buffer on the first-buffered signal to obtain a second-buffered signal, and uses a sample-and-hold switch circuit to sample the second-buffered signal according to the multi-channel sampling clock to obtain a sampled signal;

[0010] The multi-channel ADC circuit includes multiple single-channel hybrid-domain ADC circuits connected in parallel. Each single-channel hybrid-domain ADC circuit is used to quantize the input sampling signal and output a digital code. The single-channel hybrid-domain ADC circuit includes a front-stage sub-ADC based on time-domain quantization, an inter-stage residual amplifier circuit based on a gain-multiplexed CDRA circuit, and a rear-stage sub-ADC based on voltage-domain quantization, which are connected in sequence.

[0011] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0012] The high-speed time-interleaved analog-to-digital conversion system based on the radio frequency sampling front-end technology of the present invention includes a clock generation circuit based on a timing start circuit, a signal buffer circuit based on a body-driven assisted flip-type source follower, and a single-channel ADC circuit based on a gain-multiplexed CDRA. In order to relieve the ultra-large load driving pressure faced by the front-end analog signal buffer circuit in the multi-channel time-interleaved ADC system to the greatest extent and maximize the working speed of the single-channel ADC, the overall time-interleaved analog-to-digital conversion system adopts an architecture of "voltage domain to time domain and then to voltage domain (V+T+V)" for signal quantization. The timing start circuit can achieve the effect of providing a stable PWRD driving signal to the second-stage clock frequency division and digital logic combination circuit, ensuring that the clock generation circuit can generate a complete and correctly sequenced sampling clock for the multi-channel time-interleaved system in a PVT fluctuation environment; the signal buffer circuit based on the body-driven assisted flip-type source follower can achieve a smaller output impedance, better anti-kickback ability, and higher buffer linearity; the gain-multiplexed CDRA circuit effectively improves the robustness and common-mode stability of the inter-stage residual operation in a PVT fluctuation environment.

[0013] The above description is only an overview of the technical solution of the present invention. In order to be able to understand the technical means of the present invention more clearly, it can be implemented according to the content of the specification. And in order to make the above and other purposes, features, and advantages of the present invention more obvious and understandable, the following specifically gives preferred embodiments and, in conjunction with the drawings, details are described as follows. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 is a unilateral architecture diagram of the TI-ADC system;

[0015] Figure 2 is a signal buffer circuit based on a traditional flip-type source follower;

[0016] Figure 3 is a signal buffer circuit based on a body-driven assisted flip-type source follower provided by an embodiment of the present invention;

[0017] Figure 4is the clock generation circuit based on the timing start circuit provided by the embodiments of the present invention;

[0018] Figure 5 is the traditional CDRA circuit;

[0019] Figure 6 is the gain multiplexing type CDRA circuit provided by the embodiments of the present invention.

[0020] Figure 7 is a schematic diagram of the high-speed time-interleaved analog-to-digital conversion system based on the radio frequency sampling front-end technology provided by the embodiments of the present invention. Detailed implementation manners

[0021] In order to further elaborate on the technical means and effects adopted by the present invention to achieve the intended invention purpose, the following combines the accompanying drawings and specific implementation manners to detail a high-speed time-interleaved analog-to-digital conversion system based on the radio frequency sampling front-end technology proposed according to the present invention.

[0022] The foregoing and other technical contents, features and effects of the present invention can be clearly presented in the following detailed description in conjunction with the accompanying drawings. Through the description of the specific implementation manners, a more in-depth and specific understanding of the technical means and effects adopted by the present invention to achieve the intended purpose can be obtained. However, the accompanying drawings are only for reference and illustration, and are not used to limit the technical solution of the present invention.

[0023] First, the meanings of the symbols in the accompanying drawings are explained. AVDD / AGND and VDD / GND both represent the corresponding power supply voltage and ground voltage in the circuit; Input signal represents the off-chip input signal of the single-sided architecture of the high-speed time-interleaved analog-to-digital conversion system based on the radio frequency sampling front-end technology; CLK HF represents the off-chip high-frequency signal of the clock generation circuit; C L collectively represents the load capacitance driven by each output terminal in each circuit; VB2 represents the bias voltage of the signal buffer circuit based on the traditional flip-type source follower; V IN and V IP collectively represent each differential input port of each circuit, V ON and V OPUniformly represents the differential output ports of each circuit, Vref represents the on-chip reference voltage of the signal buffer circuit based on the body-driven assisted flip-source follower, and PWRD1 / 2 respectively represent the start signal and reset signal of the timing start circuit; CLK1_CHj (j = 1, 2... 8) represents the primary clock signal generated by the clock generation circuit, CLK2_CHk (k = 1, 2... 64) represents the sampling clock generated by the clock generation circuit, and CLK2_PWDi (i = 1, 2... 8) represents the secondary clock timing start signal output by the timing start circuit; Sub-ADCOutput represents the output signal of the pre-stage sub-ADC circuit of the single-channel ADC circuit; φ A1 / 2 / E respectively represent the clock control signals for the open-loop connection mode and the closed-loop connection mode in the fast amplification stage of the inter-stage residual amplifier circuit, CK cmp1 / 2 respectively represent the asynchronous adaptive regulation clock module for the inter-stage residual amplifier circuit and the comparator control clock of the DC CMFB circuit; R and C respectively represent the corresponding resistor and capacitor elements in each circuit, and their specific functional differences will be described in detail in the following content and will not be specifically classified here; CLK_CMP represents the clock signal for controlling the comparator circuit.

[0024] It should be noted that for the convenience of description, Figure 1 、 Figure 2 、 Figure 5 and Figure 6 only show the schematic diagrams of the single-sided circuits of their corresponding circuits. In the actual circuit, these circuits adopt a differential architecture to suppress various common-mode non-ideal effects and eliminate even harmonics; in addition, the nodes with the same labels in each circuit diagram are connected together, which will not be elaborated here.

[0025] The embodiment of the present invention provides a high-speed time-interleaved analog-to-digital conversion system based on radio frequency sampling front-end technology. Please refer to Figure 7 , Figure 7 is the schematic diagram of the high-speed time-interleaved analog-to-digital conversion system based on radio frequency sampling front-end technology provided by the embodiment of the present invention. As shown in Figure 7As shown in the figure, the high-speed time-interleaved analog-to-digital conversion system based on radio frequency sampling front-end technology in this embodiment includes: a clock generation circuit, a signal buffer circuit, and a multi-channel ADC circuit. Among them, the clock generation circuit uses a timing start circuit to achieve two-stage frequency division to generate a complete and correctly sequenced multi-channel sampling clock; the signal buffer circuit includes a first-stage signal buffer circuit and a second-stage signal buffer circuit based on a body-driven assisted flip-type source follower. The first-stage signal buffer circuit is used to perform a first buffer on the input radio frequency signal to obtain a first-buffered signal. The second-stage signal buffer circuit uses a VTC circuit to perform a time-domain buffer on the first-buffered signal to obtain a second-buffered signal, and uses a sample-and-hold switch circuit to sample the second-buffered signal according to the multi-channel sampling clock to obtain a sampled signal; the multi-channel ADC circuit includes multiple parallel single-channel hybrid-domain ADC circuits. Each single-channel hybrid-domain ADC circuit is used to quantize the input sampled signal and output a digital code. The single-channel hybrid-domain ADC circuit includes a pre-stage sub-ADC based on time-domain quantization, an inter-stage residual amplifier circuit based on a gain-multiplexed CDRA circuit, and a post-stage sub-ADC based on voltage-domain quantization connected in sequence.

[0026] The high-speed time-interleaved analog-to-digital conversion system based on radio frequency sampling front-end technology of the present invention includes a clock generation circuit based on a timing start circuit, a signal buffer circuit based on a body-driven assisted flip-type source follower, and a single-channel ADC circuit based on a gain-multiplexed CDRA. In order to relieve the extremely large load driving pressure faced by the front-end analog signal buffer circuit in the multi-channel time-interleaved ADC system to the greatest extent and maximize the working speed of the single-channel ADC, the overall time-interleaved analog-to-digital conversion system adopts an architecture of "voltage domain to time domain and then to voltage domain (V+T+V)" for signal quantization. The timing start circuit can achieve the effect of providing a stable PWRD driving signal for the second-stage clock frequency division and digital logic combination circuit, ensuring that the clock generation circuit can generate a complete and correctly sequenced sampling clock for the multi-channel time-interleaved system in a PVT fluctuation environment; the signal buffer circuit based on a body-driven assisted flip-type source follower can achieve a smaller output impedance, better anti-kickback ability, and higher buffer linearity; the gain-multiplexed CDRA circuit effectively improves the robustness and common-mode stability of the inter-stage residual amplifier when working in a PVT fluctuation environment.

[0027] Furthermore, the specific structure of the high-speed time-interleaved analog-to-digital conversion system based on radio frequency sampling front-end technology in this embodiment will be described in detail with reference to the accompanying drawings.

[0028] Please refer to Figure 4 , Figure 4 which is the clock generation circuit based on a timing start circuit provided by the embodiment of the present invention. As shown in Figure 4As shown in the figure, the clock generation circuit of this embodiment includes: a CML amplifier circuit, a CML2CMOS circuit, a frequency division circuit based on D flip-flops, a digital combinational logic circuit, and a timing start circuit. Among them, the input end of the CML amplifier circuit inputs high-frequency differential signals with the same amplitude but opposite phases, which are used to amplify the high-frequency differential signals to obtain differential amplified signals; the input end of the CML2CMOS circuit is connected to the output end of the CML amplifier circuit, and is used to filter the differential amplified signals and reset the common-mode voltage to generate differential square-wave signals; the input end of the frequency division circuit based on D flip-flops is connected to the output end of the CML2CMOS circuit, and is used to perform a first-level frequency division on the square-wave signals to generate first-level clock signals; the input end of the timing start circuit is connected to the output end of the frequency division circuit based on D flip-flops, and is used to generate a second-level clock timing start signal according to a pair of clock signals with opposite phases in the first-level clock signals; the input end of the digital combinational logic circuit is connected to the output end of the frequency division circuit based on D flip-flops, and is used to perform a second-level frequency division on the first-level clock signals to obtain second-level clock signals, and combine the second-level clock timing start signals to perform corresponding digital logic operations on the first-level clock signals and the second-level clock signals to generate complete and correctly sequenced multi-channel sampling clocks.

[0029] Specifically, the CML amplifier circuit is composed of a basic five-transistor differential amplifier, whose input ends are respectively connected to off-chip high-frequency differential signals with the same amplitude but opposite phases, and the output ends are respectively connected to the subsequent CML2CMOS circuit. The function of the CML amplifier circuit is to amplify the high-frequency signals with a smaller swing in the previous stage, facilitating further signal processing by the subsequent circuit.

[0030] The CML2CMOS circuit includes a high-pass filter circuit, a common-mode reset circuit, and a square-wave generation and driving circuit based on an inverter chain. Among them, the high-pass filter circuit is composed of large-capacitance capacitor devices and large-resistance resistor devices, and is used to filter out the original common-mode voltage of the input signal; the common-mode reset circuit is composed of inverters connected end to end with the help of cross-connected resistors, and the differential input signals can be biased at the required common-mode voltage level by adjusting the size of the inverters; the square-wave generation and driving circuit based on the inverter chain is composed of cross-connected inverters and a series inverter driving chain. The CML2CMOS circuit is mainly used to process the high-frequency sine differential signals in the previous stage into high-frequency differential square-wave signals with steep edges, that is, two-phase high-frequency square-wave signals.

[0031] The frequency division circuit based on D flip-flops consists of a C with its reverse output port connected to its input port 2MOS type D flip-flop and its combination are used to generate the quarter-frequency and eighth-frequency effects of the two-phase high-frequency square wave signal for the output of the previous stage, that is, the first-stage frequency division. The digital combinational logic circuit is composed of basic logic gates such as NAND gates and XOR gates connected to each other according to the required digital logic. Its input end is connected to the frequency division circuit based on D flip-flop of the previous stage to realize the second-stage frequency division and the generation of multi-channel sampling clocks. As Figure 7 shown, taking the "8x8" type 64-channel bifurcated tree clock architecture as an example in the figure, the clock result generated at the output end is used as the sampling clock for 64 single-channel mixed-domain ADC circuits.

[0032] The timing start circuit includes two timing start sub-circuits. The timing start sub-circuit includes a D flip-flop, a delay chain circuit formed by connecting multiple delay circuits in series, and multiple inverters. Among them, the D flip-flop is a TSPC type D flip-flop. The Q end of the D flip-flop is connected to the input end of the first delay circuit in the delay chain circuit; the Q end of the D flip-flop and the output end of each delay circuit are respectively connected to the input end of an inverter; the reset end of the D flip-flop inputs an external reset signal; the D end of the D flip-flop in the first timing start sub-circuit inputs an external working signal, and the Q end is connected to the D end of the D flip-flop in the second timing start sub-circuit; a pair of clock signals with opposite phases in the first-stage clock signal are respectively input to the clock ends of the D flip-flops in the two timing start sub-circuits; the output signals of all inverters are used as the second-stage clock timing start signals.

[0033] Exemplarily, for the sampling clock of 64 channels, the delay chain circuit selects a serial chain architecture in which 2 D flip-flops each drive 3 delay units. The output Q end of the first D flip-flop is connected to the input D port of the second D flip-flop, and the two D flip-flops respectively use CLK1_CH5 and CLK1_CH1 with opposite phases in the first-stage clock signal as the trigger clocks, which gives the reset process of the D flip-flop a sufficient time margin of 1 / 2 times the CLK1 period. Only CLK2_PWD1 and CLK2_PWD5 are respectively generated by the output of the D flip-flop, and the remaining second-stage clock timing start signals are all provided by the output of the delay chain based on inverters. Since the delay of the inverter is small and controllable, the adoption of this architecture allows the start clock to have a large range of delay fluctuations, solving the problem of incorrect channel opening sequence due to insufficient time margin faced by the traditional timing start circuit composed of only D flip-flops in the PVT fluctuation environment. At the same time, it relaxes the high design requirements for the working speed of D flip-flops in the traditional timing start circuit in the high-frequency application environment, ensuring that the clock generation circuit can generate complete and correctly sequenced sampling clock cycles for the multi-channel time-domain interleaved system in the PVT fluctuation environment.

[0034] The timing startup circuit designed in the embodiment of the present invention for the clock generation circuit can achieve the effect of providing a stable PWRD drive signal for the secondary clock frequency division and digital logic combination circuit, ensuring that the clock generation circuit can generate a complete and correctly sequenced sampling clock cycle for the multi-channel time-domain interleaved system in a PVT fluctuation environment. This is due to the concept of reasonably selecting a corresponding number of D flip-flops and a combination of delay units based on an inverter chain to form the timing startup circuit, solving the problem of incorrect channel opening sequence caused by insufficient time margin faced by the traditional timing startup circuit composed only of D flip-flops in a PVT fluctuation environment. At the same time, it relaxes the high requirements for the operating speed of D flip-flops in the traditional timing startup circuit in a high-frequency application environment, alleviating the design pressure of the D flip-flop circuit.

[0035] The first-stage signal buffer circuit of this embodiment is a signal buffer circuit based on a body-driven assisted flip-type source follower, including a core circuit, a bias circuit, a Class AB enhancement circuit, an auxiliary circuit, and a common-mode feedback circuit. Among them, the core circuit uses a set of mirror-symmetrical single-sided buffer circuits to achieve the first buffering of the radio frequency signal to generate a first buffered signal; the bias circuit is used to provide a bias voltage for the core circuit; the Class AB enhancement circuit is used to inject additional current into the core circuit to increase the slew rate and small-signal buffer bandwidth of the core circuit; the auxiliary circuit is used to charge the output node of the core circuit to avoid odd-order harmonics introduced by the non-linear capacitance of the core circuit; the common-mode feedback circuit is used to stabilize the static bias of the core circuit.

[0036] Specifically, please refer to Figure 3 , Figure 3 is the signal buffer circuit based on a body-driven assisted flip-type source follower provided by the embodiment of the present invention. As Figure 3 shown, the core circuit includes: transistor M MN1 , transistor M MN2 , transistor M MN3 , transistor M MN4 , transistor M MP1 , transistor M MP2 , transistor M MP3 , transistor M MP4 , transistor M MP5 , transistor M MP6 , transistor M MP7 , transistor M MP8 , transistor MN1, transistor MN2, transistor MN3, transistor MN4, transistor MN5, transistor MN6, transistor MN7, transistor MN8, transistor MP1, transistor MP2, transistor MP3, transistor MP4, capacitor C C1 , capacitor C C2 , capacitor CJ1 , capacitor C J2 , capacitor C B1 , capacitor C B2 , resistor R B1 , resistor R B2 , resistor R B3 and resistor R B4 .

[0037] Among them, the source electrodes of transistor M MP3 , transistor M MP4 , transistor M MP7 and transistor M MP8 are all connected to the power supply voltage; the drain electrode of transistor M MP7 is connected to the source electrode of transistor M MP5 , and the gate electrodes are respectively connected to the gate electrode and the drain electrode of transistor M MP5 ; the drain electrode of transistor M MP3 is connected to the source electrode of transistor M MP1 , and the gate electrodes are respectively connected to the gate electrodes of transistor M MP7 and transistor M MP1 ; the drain electrode of transistor M MP4 is connected to the source electrode of transistor M MP2 , and the gate electrodes are respectively connected to the gate electrodes of transistor M MP8 and transistor M MP2 ; the drain electrode of transistor M MP8 is connected to the source electrode of transistor M MP6 , and the gate electrodes are respectively connected to the gate electrode and the drain electrode of transistor M MP6 . The source electrode of transistor M MN3 is connected to the drain electrode of transistor M MN1 , the drain electrode is connected to the drain electrode of transistor M MP5 , and the gate electrodes are respectively connected to the gate electrodes of transistor M MN1 and transistor M MN2 ; the source electrode of transistor M MN4 is connected to the drain electrode of transistor M MN2 , the drain electrode is connected to the drain electrode of transistor M MP6 , and the gate electrode is connected to the gate electrode of transistor M MN2 ; the source electrodes of transistor M MN1 and transistor M MN2 are both connected to the ground voltage.

[0038] The source electrode of transistor MP1 is connected to the drain electrode of transistor M MP1 , the drain electrode is connected to the source electrode of transistor MP3, and the gate electrode is connected to the gate electrode of transistor MP2; the drain electrode of transistor MP3 is connected to the drain electrode of transistor MN7, and the gate electrode is connected to the gate electrode of transistor MP4; the source electrode of transistor MP2 is connected to transistor M MP2The drain of which is connected to the source of transistor MP4; the drain of transistor MP4 is connected to the drain of transistor MN8; the gate of transistor MN7 is connected to the gate of transistor MN8, and the sources of transistor MN7 and transistor MN8 are both connected to the ground voltage; the source of transistor MN3 is connected to the drain of transistor MN1, and the drain is connected to transistor M MP1 The drain of which, and the gate is connected to capacitor C B1 The first terminal of capacitor C B1 The second terminal of which is connected to the gate of transistor MN1; the source of transistor MN1 is connected to the drain of transistor MN5, and the gate serves as one of the differential inputs of the RF signal; the gate of transistor MN5 is connected to resistor R B3 The first terminal of resistor R B3 The second terminal of which is connected to resistor R B4 The first terminal; the source of transistor MN4 is connected to the drain of transistor MN2, and the drain is connected to transistor M MP2 The drain of which, and the gate is connected to capacitor C B2 The first terminal of capacitor C B2 The second terminal of which is connected to the gate of transistor MN2; the source of transistor MN2 is connected to the drain of transistor MN6, and the gate serves as the other differential input of the RF signal; the gate of transistor MN6 is connected to resistor R B4 The second terminal; the sources of transistor MN5 and transistor MN6 are both connected to the ground voltage.

[0039] Resistor R B1 The first terminal of which is connected to resistor R B2 The second terminal, and the second terminal is connected to the gate of transistor MN3; resistor R B2 The first terminal is connected to the gate of transistor MN4; capacitor C J1 Is connected between the drain of transistor MN7 and the gate of transistor MN5; capacitor C J2 Is connected between the drain of transistor MN8 and the gate of transistor MN6; capacitor C C1 Is connected between the drain of transistor MP3 and the ground voltage; capacitor C C2 Is connected between the drain of transistor MP4 and the ground voltage; the drain of transistor MN5 serves as one of the differential outputs of the primary buffer signal, and the drain of transistor MN6 serves as the other differential output of the primary buffer signal.

[0040] In this embodiment, the core circuit includes a group of mirror-symmetrical single-sided buffer circuits. A group of mirror-symmetrical single-sided buffer circuits includes two single-sided circuits with exactly the same circuit structure and mirror-symmetrical positions. The input ends of this group of mirror-symmetrical single-sided buffer circuits are respectively connected to the output signals of the previous-stage circuit of the system to sense and receive the input voltage, and its output ends are connected to the subsequent-stage load circuit to output the replicated and buffered input signals to the subsequent-stage circuit for subsequent processing. The purpose of adopting the differential architecture is to eliminate even harmonics and reduce common-mode noise.

[0041] In this embodiment, the single-sided circuits with exactly the same circuit structure and mirror-symmetrical positions are composed of a main buffer transistor, a stacked auxiliary transistor, a group of pseudo-cascode current mirrors, a group of voltage bootstrap networks, a current feedback loop, a decoupling capacitor, a bias resistor, and a zero-point cancellation capacitor. Introducing a stacked auxiliary transistor can achieve the synchronization of the drain-source voltage of the main transistor pair during operation, thereby reducing the influence of the channel modulation effect and the non-linear distortion caused by the change of the non-linear capacitance C ds The change of. Further improving the linearity of the buffered signal. One of the voltage bootstrap networks is composed of a resistor for providing a bias voltage to the stacked auxiliary transistor and a capacitor for realizing the signal bootstrap function in parallel. The resistor is used to provide a suitable static bias to ensure the normal operation of the circuit in any case, and the capacitor realizes the bootstrap of the input signal to the gate of the stacked auxiliary transistor. By adopting a reasonable value of the capacitor and resistor, the reception and processing of the input signal within the required frequency band can be realized. The current feedback loop is composed of two series-connected PMOS transistors, an NMOS transistor for providing a bias current to it, and an NMOS pull-down transistor connected to the source of the main buffer transistor. The substrates of all NMOS and PMOS transistors in the loop are respectively connected to their own sources, which is beneficial to reducing the harmonic distortion caused by the non-linear change of the source-substrate voltage V SB And the body effect, thereby improving the linearity performance of the buffer. A group of pseudo-cascode current mirrors is composed of two PMOS transistors with their gates connected and their current replication branches. The essence of the pseudo-cascode current mirror is to increase the equivalent L by connecting transistors in series, so as to suppress the problem of serious mismatch of the current mirror caused by the channel modulation effect in advanced processes. This technology can achieve more accurate current mirror matching without additional power consumption and margin, so it provides a more stable static DC bias for the main buffer transistor to reduce the fluctuation of V GS Voltage. It is worth mentioning that in advanced processes, transistors with different threshold selections are usually provided. The threshold voltages of the two series-connected transistors in the pseudo-cascode current mirror can be reasonably selected to achieve the effect of a true cascode current mirror without bringing additional margin overhead; due to the addition of the decoupling capacitor C Ji(i＝1,2)Together with an additional bias resistor, a feed-forward zero is introduced into the signal path. Therefore, a zero-canceling capacitor Cc is added in the design of the present invention to construct a pole to cancel this zero, and the best linearity effect can be achieved by reasonably designing the capacitance value of Cc.

[0042] As Figure 3 shown, the bias circuit includes: transistor M B1 , transistor M B2 , transistor M B3 , transistor M B4 , transistor M B5 , transistor M B6 , transistor M B7 , transistor M B8 , transistor M B9 , transistor M B10 , transistor M B11 , transistor M B12 , transistor M B13 , transistor M B14 , transistor M B15 , transistor M B16 , the first amplifier and resistor R0.

[0043] Among them, the sources of transistor M B2 , transistor M B4 , transistor M B6 and transistor M B8 are all connected to the power supply voltage; the drain of transistor M B2 is connected to the source of transistor M B1 , and the gates are respectively connected to the gate and drain of transistor M B1 ; the drain of transistor M B4 is connected to the source of transistor M B3 , and the gates are respectively connected to the gate of transistor M B2 and the gate of transistor M B3 ; the drain of transistor M B6 is connected to the source of transistor M B5 , and the gates are respectively connected to the gate of transistor M B4 and the gate of transistor M B5 ; the drain of transistor M B8 is connected to the source of transistor M B7 , and the gates are respectively connected to the gate of transistor M B6 and the gate of transistor M B7 .

[0044] The source of transistor M B9 is connected to the drain of transistor M B10 , the drain is connected to the drain of transistor M B3 , and the gate is respectively connected to its drain and transistor MB10 gate; transistor M B10 The gate of which is connected to transistor M MN3 gate; transistor M B11 The source of which is connected to transistor M B5 drain, and the drain is connected to transistor M B12 source, gate are respectively connected to its drain and the gate of transistor MP1; transistor M B12 drain is connected to transistor M B13 drain, gate are respectively connected to its drain and the gate of transistor MP3; transistor M B13 gate is connected to its drain; transistor M B14 source is connected to transistor M B15 drain, and the drain is connected to transistor M B7 drain, gate are respectively connected to its drain and resistor R B1 the first end; transistor M B15 gate are respectively connected to its drain and resistor R B3 the second end; transistor M B16 source is respectively connected to the negative input terminal of the first amplifier and the first end of resistor R0, drain is connected to transistor M B1 drain, gate is connected to the output terminal of the first amplifier, the positive input terminal of the first amplifier is connected to an off-chip reference voltage; the second end of resistor R0, transistor M B10 source, transistor M B13 source of and transistor M B15 source of are all connected to the ground voltage.

[0045] In this embodiment, the bias circuit is composed of a traditional current mirror bias architecture and an operational amplifier for implementing the voltage clamping function, that is, the first amplifier. Among them, the output terminal of the operational amplifier for implementing the voltage clamping function is connected to the off-chip reference voltage V BG , and this operational amplifier generally adopts a traditional op-amp architecture with high gain and low bandwidth. Based on the "virtual short" property of the closed-loop op-amp, V BG is accurately replicated to the negative input terminal of the op-amp and acts together with the bias resistor R0 to define the magnitude of the bias current. Based on the overall power consumption expectation of the system, the bias current is set to 5 mA in this embodiment.

[0046] As Figure 3 shown, the Class AB enhancement circuit includes: transistor M AB1 , transistor M AB2 , transistor M AB3 and transistor M AB4 . Among them, the source of transistor M AB1 is connected to the drain of transistor MN5, and the drain is connected to transistor M AB3The source of the [transistor] is connected to the gate of the transistor MN1; the transistor M AB3 The drain of the [transistor] is connected to the power supply voltage, and the gate is connected to the gate of the transistor MN3; the transistor M AB2 The source of the [transistor] is connected to the drain of the transistor MN6, and the drain is connected to the transistor M AB4 The source of the [transistor], and the gate is connected to the gate of the transistor MN2; the transistor M AB4 The drain of the [transistor] is connected to the power supply voltage, and the gate is connected to the gate of the transistor MN4.

[0047] In this embodiment, the Class AB enhancement circuit consists of a group of Class AB auxiliary transistors. Each group of auxiliary transistors is composed of two NMOS transistors with dimensions scaled in proportion to the main buffer transistor connected in series. The Class AB driving method is adopted to increase the slew rate and reduce the static bias consumption of the entire circuit. Since the operation mode of Class AB can significantly increase the current, the size of this auxiliary branch can be scaled down proportionally (in this embodiment, the ratio to the main transistor is 1:2), so that the introduced additional parasitic capacitance is controllable.

[0048] As Figure 3 shown, the auxiliary circuit includes: the transistor M MN5 , the transistor M MN6 , the transistor M MN7 , the transistor M MN8 , the transistor M AUX1 and the transistor M AUX2 . Among them, the drains of the transistors M AUX1 and the transistor M AUX2 are both connected to the power supply voltage; the sources of the transistors M AUX1 are respectively connected to their substrates, the drain of the transistor M MN7 , the substrate of the transistor M AB1 and the substrate of the transistor MN1; the gate of the transistor M AUX1 is connected to the gate of the transistor MN1; the sources of the transistors M AUX2 are respectively connected to their substrates, the drain of the transistor M MN8 , the substrate of the transistor M AB2 and the substrate of the transistor MN2; the gate of the transistor M AUX2 is connected to the gate of the transistor MN2; the source of the transistor M MN7 is connected to the drain of the transistor M MN5 , and the gate is connected to the gates of the transistors M MN5 and the transistor M MN1 ; the source of the transistor M MN8 is connected to the drain of the transistor M MN6 , and the gate is respectively connected to the gates of the transistors M MN5 and the transistor M MN6 ; the transistor M MN5and transistor M MN6 The sources of both are connected to the ground voltage.

[0049] In this embodiment, the auxiliary circuit is composed of a group of smaller-sized NMOS transistors and a bias current source based on a pseudo-cascode current mirror. Its output terminal is connected to the substrate of the main buffer transistor, the substrate of the Class AB auxiliary transistor, and its own substrate terminal. Since the body-well capacitance of M AB1-4 directly connected to the buffer output node is a non-linear voltage-variable capacitance, charging this node with the auxiliary circuit can effectively avoid the odd harmonics related to the input signal frequency introduced by the non-linear capacitance, achieving better SFDR performance.

[0050] In this embodiment, coupling capacitors C J1 and C J2 and additional bias resistors R B3 and R B4 decouple the direct connection between the gate nodes of transistors MN5 and MN6 and the drain nodes of transistors MN7 and MN8. In this way, the output signal range can be expanded, and the voltage consumption requirement can be reduced from one V GS to an overdrive voltage V ov . This technology is extremely effective in advanced processes where the power supply voltage is reduced proportionally but the transistor threshold voltage changes little. However, there is a problem with this architecture: the common-mode voltage at the drains of transistors MN7 and MN8 may fluctuate significantly due to the upper and lower voltage mismatches, resulting in the loop losing its function. Therefore, a common-mode feedback mechanism is also needed to stabilize the voltage at this point.

[0051] As Figure 3 shown, the common-mode feedback circuit includes: resistor R1, resistor R B5 , resistor R B6 , capacitor C1, capacitor C2, and a second amplifier. Among them, the first end of resistor R B5 is connected to the drain of transistor MN7, and the second end is connected to the first end of resistor R B6 . The second end of resistor R B6 is connected to the drain of transistor MN8; the first end of capacitor C2 is connected to the ground voltage, and the second end is connected to the second end of resistor R B5 ; the first end of resistor R1 is connected to the on-chip reference voltage, and the second end is respectively connected to the first end of capacitor C1 and the negative input terminal of the second amplifier. The positive input terminal of the second amplifier is connected to the first end of resistor R B6 ; the second end of capacitor C1 is connected to the gate of transistor MN7, and the output terminal of the second amplifier is connected to the gate of transistor MN8.

[0052] In this embodiment, a common-mode feedback circuit based on an active integrator is adopted. The common-mode feedback circuit is composed of a low-pass filter circuit for extracting the common-mode voltage and an active filter for providing the feedback voltage. The low-pass filter circuit for extracting the common-mode voltage is composed of a pair of large resistors and a large capacitor grounded. The active filter for providing the feedback voltage is formed by connecting an operational amplifier and a low-pass filter network composed of a resistor and a capacitor. Its input terminal is connected to the reference voltage V ref are connected to each other. The working process of this common-mode feedback circuit is similar to that of the traditional common-mode feedback circuit, and will not be elaborated here.

[0053] The signal buffer circuit designed in the embodiment of the present invention based on the body-driven assisted flip-type source follower can achieve a smaller output impedance, better anti-kickback ability and higher buffer linearity. This is because an additional cascode transistor is introduced into the current feedback loop, which suppresses the current fluctuation caused by the channel modulation effect of the bias current source while increasing the loop gain. In addition, the method of driving the gate and substrate of the main buffer transistor simultaneously with the pre-stage input signal V in and adding an auxiliary stage circuit with controllable additional overhead to drive the substrate node of the Class AB auxiliary transistor effectively increases the equivalent g m of the main buffer transistor, and releases the voltage-variable parasitic loading of the non-linear substrate well capacitors of the main buffer transistor and the Class AB auxiliary transistor on the output end, greatly suppressing the odd harmonics in the signal buffering process of the Buffer circuit. In addition, the signal buffer circuit designed in the embodiment of the present invention has a larger output signal swing, a larger slew rate and a smaller static bias consumption, which is due to the adoption of the Class AB operation mode and the decoupling effect of the coupling capacitor on the gates of the directly connected transistors MN5 and MN6 and the drains of the transistors MN7 and MN8.

[0054] In this embodiment, the second-stage signal buffer circuit includes: a sample-and-hold switch circuit, a VTC circuit, and a trace driving circuit. Among them, the sample-and-hold switch circuit is composed of a traditional gate voltage bootstrap switch circuit, whose input terminal is connected to the output terminal of the previous-stage signal buffer circuit, and whose output terminal is connected to the input terminal of the VTC circuit. The VTC circuit adopts a traditional discharge-type VTC architecture. By using the VTC circuit to replace the traditional second-stage signal buffer circuit based on the source follower architecture, the capacitive load pressure on the first-stage signal buffer circuit can be greatly reduced. Changing the traditional "voltage domain buffer" to a "time domain buffer" can effectively improve the overall working speed of the front-end sampling network. In addition, the essence of the time-domain signal is the delay difference of digital signals. As long as the driving circuit based on the inverter chain can achieve a good edge slope retention effect during the conduction process, the distortion introduced by the time-domain signal during the conduction process to the subsequent circuit is more controllable than that of the voltage-domain signal. The trace driving circuit is composed of a driving chain formed by cascading inverters, whose input terminal is connected to the output terminal of the previous-stage signal buffer circuit, and the output terminal is connected to the input terminals of each single-channel hybrid-domain ADC circuit.

[0055] In this embodiment, the previous-stage sub-ADC based on time-domain quantization is composed of a traditional TVC circuit, a traditional TCD circuit, a traditional flash-type TDC circuit, and a CDAC array based on split-capacitor logic. The input terminal of the traditional TVC circuit is connected to the output terminal of its corresponding trace driving circuit, and its output terminal is connected to the CDAC array based on split-capacitor logic. The input terminal of the traditional TCD circuit is connected to the output terminal of its corresponding trace driving circuit, and its output terminal is connected to the input terminal of the traditional flash-type TDC circuit. The output result of the traditional flash-type TDC circuit is the digital code value of time-domain quantization, which acts on the CDAC array based on split-capacitor logic. The subsequent-stage sub-ADC based on voltage-domain quantization adopts a traditional ADC architecture based on SAR logic, which will not be elaborated here.

[0056] The inter-stage residual amplifier circuit of this embodiment is based on a gain-multiplexing CDRA circuit. Please refer to Figure 6 , Figure 6 is the gain-multiplexing CDRA circuit provided by the embodiment of the present invention. As shown in Figure 6 , this inter-stage residual amplifier circuit includes a core circuit based on cascaded inverters, an asynchronous adaptive regulation clock circuit, and a composite CMFB circuit. Among them, the core circuit based on cascaded inverters includes: a first-stage equivalent inverter circuit, a second-stage equivalent inverter circuit, a traditional inverter circuit, a feedback capacitor C F , a related voltage shift capacitor C LS , a capacitor C S1 , a capacitor C S2and a switch circuit, wherein, the first-stage equivalent inverter circuit, the second-stage equivalent inverter circuit and the conventional inverter circuit are connected in series in sequence; a feedback capacitor C F is connected between the input end of the first-stage equivalent inverter circuit and the second end of the related voltage-level shifting capacitor C LS ; the first end of the related voltage-level shifting capacitor C LS is connected to the output end of the conventional inverter circuit; a capacitor C S1 is connected between the input end of the first-stage equivalent inverter circuit and the ground terminal; a capacitor C S2 is connected between the second end of the related voltage-level shifting capacitor C LS and the ground terminal; the switch circuit is used to control the two-phase working stages of the inter-stage residual amplifier circuit.

[0057] In this embodiment, the core circuit based on cascaded inverters is composed of two-stage equivalent inverter circuits, one-stage conventional inverter circuit, a feedback capacitor C F , a related voltage-level shifting capacitor C LS and each switch circuit related to the amplifier working stage. Wherein, the equivalent inverter circuit is composed of a conventional inverter circuit and a series connection of 1 / g m stage inverters connected end to end, and the sizes of the two are in an N-fold ratio. The source electrodes of the PMOS transistor and the NMOS transistor in the conventional inverter circuit are respectively connected to a single MOS switch. This group of single MOS switches is used to reduce the power consumption of the residual amplifier. The switches are closed during amplification. At this time, each stage is equivalent to the operation of a conventional inverter. After the amplification process ends, the switches are disconnected to avoid additional static power consumption of the circuit. In order to minimize the additional voltage loss introduced by the single MOS switch as much as possible, this group of switches should be selected as large as possible without significantly introducing the pressure of capacitive load.

[0058] The asynchronous adaptive regulation clock circuit is connected to the core circuit based on cascaded inverters, and is used to extract the output voltage of the conventional inverter circuit, and generate an adaptive regulation clock for controlling the inter-stage residual amplifier circuit in the coarse amplification working stage and the fine amplification working stage according to the extracted voltage.

[0059] In this embodiment, the asynchronous adaptive regulation clock circuit is composed of a comparator for judging the node polarity, a clock-controlled charge pump based on XOR gate logic and a voltage-controlled delay circuit. The clock-controlled charge pump based on XOR gate logic is composed of a delay unit, an inverter and an XOR gate connected in corresponding digital logic to form a control clock for switching the charge and discharge path of the charge pump and a conventional charge pump circuit based on a current mirror. The voltage-controlled delay circuit is jointly composed of multiple-stage cascaded voltage-controlled inverters and a simple digital combinational logic circuit, and finally outputs an adaptive regulation clock for controlling the coarse amplification and fine amplification working stages of the inter-stage residual amplifier.

[0060] To reduce the time overhead and further improve the speed of the inter-stage residual operational amplifier, the gain-multiplexed CDRA operates in the coarse amplification φ A1 phase. The first two stages are connected in an open-loop operating mode. Since the main pole of the CDRA is the output pole and the poles provided by the first two inverters are high-frequency poles, it naturally has high-speed performance. The open-loop operating mode can achieve an almost rail-to-rail amplification effect and a higher upper limit of voltage gain, thus alleviating the need for a large-value C LS capacitor in the traditional CDRA to reduce the pressure of the charge sharing effect, further improving the speed of the coarse amplification operation, avoiding the trade-off between the equivalent open-loop gain and the amplification speed caused by using the traditional CDRA, and effectively achieving the performance requirements of large swing and high slew rate. In the fine amplification φ A2 phase, the third inverter is turned on and connected to the first two inverters to jointly achieve a closed-loop operating mode. At this time, the grounded end of the capacitor C LS is connected to the output of the third inverter, that is, the V RA terminal, to achieve the effect of related level shifting. The principle of this process is similar to that of the traditional related level shifting and will not be elaborated here. The access of the third inverter also increases the equivalent open-loop gain in the fine amplification phase, effectively achieving a high-linearity fine amplification process. It should be noted that φ AE remains closed throughout the entire amplification process of the operational amplifier.

[0061] Near the end of the amplification process, the voltage levels at the V X node and the V RA node should ideally approach the common-mode voltage V CMO . However, in an environment affected by non-ideal effects such as PVT and power supply voltage fluctuations, it is unreasonable to allocate a constant time period to the coarse amplification phase and the fine amplification phase, which will result in a large gap between the actual amplification result and the ideal result. For example, when the coarse amplification time is too short, V RA should be higher than the common-mode voltage V CMO at the end of the amplification phase, otherwise vice versa. At this time, an asynchronous adaptive control clock circuit is used to perform simple digital logic operations on the comparator result and control the on / off of the charge pump up / down branches to charge / discharge the capacitor C S3 , finally generating a corresponding elevated / lowered adjustment voltage. This adjustment voltage acts on the gate of the PMOS transistor in the voltage-controlled delay circuit, which can change the length of the generated delay time. As Figure 6 shown, the amplification clock φ A and its delayed variant clock undergo corresponding logical operations to generate a new coarse amplification φ A1 / fine amplification φ A2a clock, so that the adjusted actual amplification result is closer to the ideal amplification result. Selecting the V RA node as the reference point for polarity judgment can avoid damaging the input virtual ground V X , thus ensuring that the asynchronous adaptive control clock circuit does not change the final output result of the operational amplifier during operation.

[0062] The composite CMFB circuit includes: an AC CMFB circuit and a DC CMFB circuit. Among them, the AC CMFB circuit is used to extract the common-mode voltage V CMO based on the output of the core circuit of the cascaded inverter, and generate a feedback signal for the second-stage equivalent inverter circuit according to the common-mode voltage V CMO ; the DC CMFB circuit is used to generate a feedback signal for the first-stage equivalent inverter circuit according to the common-mode voltage V CMO .

[0063] In this embodiment, the composite CMFB circuit is used to ensure the common-mode stability of the circuit during operation. The DC CMFB circuit is composed of an auxiliary inverter unit that provides a flip reference voltage V trip , a comparator and an integrator. The positive and negative input ports of the comparator are respectively connected to the common-mode voltage V CMO of the differential output terminal of the core circuit of the cascaded inverter and the output of the auxiliary inverter unit. The output terminal of the comparator is connected to the input terminal of the integrator, and the output terminal of the integrator is connected to the input terminal of the core circuit of the cascaded inverter. By comparing the common-mode voltage V CMO of the feedback output node and the flip point V trip of the auxiliary inverter unit, the comparison result is used to drive the integrator to output the corresponding common-mode adjustment voltage, thereby stabilizing the common-mode voltage of the amplifier. Since the circuit has a relatively low requirement for the working speed of the DC CMFB, a traditional comparator and a simple capacitive integrator can be used to achieve an ideal function. The AC CMFB circuit is composed of two large resistors for extracting the common-mode voltage, an additional two-stage inverter, and a C STB capacitor for controlling the position of the main pole to ensure the stability of the feedback loop. Its input terminals are respectively connected to the differential output terminals V ON and V OP of the core circuit of the cascaded inverter.They are connected, and their output terminals are respectively connected to the differential output terminals VFp and VFn of the second-stage equivalent inverter of the core circuit based on cascaded inverters. The whole composed of two additional stages of inverters and the third-stage inverter of the core circuit based on cascaded inverters together constitutes a negative feedback loop for implementing common-mode correction. This composite CMFB essentially suppresses the common-mode fluctuations caused by high-frequency and low-frequency non-ideal factor interferences through a "fast" path (AC CMFB) and a "slow" path (DC CMFB) respectively, and well realizes the common-mode stability of the overall inter-stage operational amplifier circuit.

[0064] The gain-multiplexing CDRA circuit of the embodiment of the present invention utilizes the architecture feature of the traditional CDRA circuit itself, which is composed of three stages of "equivalent inverters", combines the two-step amplification principle and multiplexes the open-loop gain provided by the three-stage inverters, and realizes the effect of completing the two-step amplification of coarse / fine in the same operational amplifier, effectively reducing the design complexity and eliminating the relative offset problem inevitably introduced in the traditional two-step amplification architecture due to the separate use of two amplifiers. When the gain-multiplexing CDRA circuit operates in the coarse amplification stage, its first two stages are connected in an open-loop operation mode. Since the main pole of the CDRA circuit is the output pole and the poles provided by the first two stages of inverters are high-frequency poles, it naturally has high-speed performance. The open-loop operation mode can achieve an almost rail-to-rail amplification effect and a higher upper limit of voltage gain, thus alleviating the pressure of using a large-capacitance C LS capacitor to reduce the charge sharing effect, significantly shortening the time of coarse amplification, further improving the speed of coarse amplification operation, avoiding the trade-off problem between the equivalent open-loop gain and the amplification speed caused by using the traditional CDRA circuit, and effectively realizing the performance requirements of large swing and high slew rate. In the fine amplification stage, the third-stage inverter is turned on and connected to the first two stages of inverters to jointly realize a closed-loop operation mode, improving the open-loop gain in the fine amplification stage and effectively realizing the performance requirements of high linearity. The novel gain-multiplexing CDRA circuit retains the high-bandwidth performance achievable by the traditional CDRA architecture and makes up for the open-loop gain loss caused by the introduction of g m stage, realizing the excellent performance of high-speed and high-linearity amplification of the inter-stage residual operational amplifier, which helps to improve the overall working speed of the single-channel ADC circuit.

[0065] Secondly, through the designed auxiliary circuits applied to the gain-multiplexed CDRA circuit, namely, the asynchronous adaptive regulation clock module based on a comparator, a charge pump, and a digital logic circuit, and the composite CMFB circuit based on a comparator, an integrator, and an inverting amplifier, the robustness and common-mode stability of the inter-stage residual op-amp operating in the PVT fluctuation environment are effectively improved. The design concept of this auxiliary architecture is not only applicable to the design of the present invention, but also can be extended to any inter-stage residual op-amp with a similar structure, such as a ring amplifier. Moreover, the composite CMFB circuit adopted in the design of the present invention can be extended to almost any type of inter-stage residual op-amp.

[0066] It should be noted that in this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprising", "including" or any other variant are intended to cover non-exclusive inclusion, so that an article or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed. Without more limitations, an element defined by the statement "including an..." does not exclude the existence of additional identical elements in the article or device including the element. Terms such as "connected" or "coupled" do not necessarily refer to physical or mechanical connections, but may include electrical connections, whether direct or indirect. The orientation or positional relationship indicated by "up", "down", "left", "right", etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus cannot be construed as a limitation of the present invention.

[0067] In the description of this specification, the description with reference to terms such as "one embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features or characteristics described can be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art can combine and combine the different embodiments or examples described in this specification.

[0068] The above content is a further detailed description of the present invention in combination with specific preferred embodiments. It cannot be determined that the specific implementation of the present invention is only limited to these descriptions. For those of ordinary skill in the technical field to which the present invention pertains, without departing from the concept of the present invention, several simple deductions or substitutions can be made, and all should be regarded as belonging to the protection scope of the present invention.

Claims

1. A high-speed time-interleaved analog-to-digital conversion system based on RF sampling front-end technology, characterized in that, Including: a clock generation circuit, a signal buffer circuit, and a multi-channel ADC circuit, wherein the clock generation circuit uses a timing start circuit to achieve two-stage frequency division to generate a complete and correctly sequenced multi-channel sampling clock; the signal buffer circuit includes a first-stage signal buffer circuit and a second-stage signal buffer circuit based on a body-driven assisted flip-type source follower. The first-stage signal buffer circuit is used to perform a first buffer on the input radio frequency signal to obtain a first-buffered signal. The second-stage signal buffer circuit uses a VTC circuit to perform a time-domain buffer on the first-buffered signal to obtain a second-buffered signal, and uses a sample-and-hold switch circuit to sample the second-buffered signal according to the multi-channel sampling clock to obtain a sampled signal; the multi-channel ADC circuit includes a plurality of parallel single-channel hybrid-domain ADC circuits. Each single-channel hybrid-domain ADC circuit is used to quantize the input sampled signal and output a digital code. The single-channel hybrid-domain ADC circuit includes a pre-stage sub-ADC based on time-domain quantization, an inter-stage residual amplifier circuit based on a gain-multiplexed CDRA circuit, and a post-stage sub-ADC based on voltage-domain quantization connected in sequence.

2. The high-speed time-interleaved analog-to-digital conversion system based on radio frequency sampling front-end technology according to claim 1, wherein The clock generation circuit includes: a CML amplifier circuit, a CML2CMOS circuit, a frequency division circuit based on a D flip-flop, a digital combinatorial logic circuit, and the timing start circuit; wherein the input end of the CML amplifier circuit inputs high-frequency differential signals with the same amplitude but opposite phases, and is used to amplify the high-frequency differential signals to obtain differential amplified signals; the input end of the CML2CMOS circuit is connected to the output end of the CML amplifier circuit, and is used to filter the differential amplified signals and reset the common-mode voltage to generate differential square-wave signals; the input end of the frequency division circuit based on a D flip-flop is connected to the output end of the CML2CMOS circuit, and is used to perform a first-stage frequency division on the square-wave signals to generate first-stage clock signals; the input end of the timing start circuit is connected to the output end of the frequency division circuit based on a D flip-flop, and is used to generate a second-stage clock timing start signal according to a pair of clock signals with opposite phases in the first-stage clock signals; the input end of the digital combinatorial logic circuit is connected to the output end of the frequency division circuit based on a D flip-flop, and is used to perform a second-stage frequency division on the first-stage clock signals to obtain second-stage clock signals, and perform corresponding digital logic operations on the first-stage clock signals and the second-stage clock signals in combination with the second-stage clock timing start signal to generate a complete and correctly sequenced multi-channel sampling clock.

3. The high-speed time-interleaved analog-to-digital conversion system based on radio frequency sampling front-end technology according to claim 2, characterized in that The timing start circuit includes two timing start sub-circuits. The timing start sub-circuit includes a D flip-flop, a delay chain circuit formed by connecting a plurality of delay circuits in series, and a plurality of inverters, wherein the D flip-flop is a TSPC type D flip-flop. The Q end of the D flip-flop is connected to the input end of the first delay circuit in the delay chain circuit; the Q end of the D flip-flop and the output end of each delay circuit are respectively connected to the input end of an inverter; the reset end of the D flip-flop inputs an external reset signal; The D terminal of the D flip-flop in the first timing promoter circuit inputs an external working signal, and the Q terminal is connected to the D terminal of the D flip-flop in the second timing promoter circuit; A pair of clock signals with opposite phases in the primary clock signal are correspondingly input to the clock terminals of the D flip-flops in the two timing promoter circuits; The output signals of all inverters serve as the secondary clock timing start signal.

4. The high-speed time-interleaved analog-to-digital conversion system based on radio frequency sampling front-end technology according to claim 1, characterized in that The first-stage signal buffer circuit includes a core circuit, a bias circuit, a Class AB enhancement circuit, an auxiliary circuit, and a common-mode feedback circuit, where The core circuit uses a group of mirror-symmetric single-sided buffer circuits to achieve the primary buffering of the radio frequency signal to generate the primary buffer signal; The bias circuit is used to provide a bias voltage for the core circuit; The Class AB enhancement circuit is used to inject additional current into the core circuit to increase the slew rate and small-signal buffer bandwidth of the core circuit; The auxiliary circuit is used to charge the output node of the core circuit to avoid odd-order harmonics introduced by the nonlinear capacitance of the core circuit; The common-mode feedback circuit is used to stabilize the static bias of the core circuit.

5. The high-speed time-interleaved analog-to-digital conversion system based on radio frequency sampling front-end technology according to claim 4, characterized in that The core circuit includes: transistor M MN1 、transistor M MN2 、transistor M MN3 、transistor M MN4 、transistor M MP1 、transistor M MP2 、transistor M MP3 、transistor M MP4 、transistor M MP5 、transistor M MP6 、transistor M MP7 、transistor M MP8 、transistors MN1, MN2, MN3, MN4, MN5, MN6, MN7, MN8, MP1, MP2, MP3, MP4, capacitor C C1 、capacitor C C2 、capacitor C J1 、capacitor C J2 、capacitor C B1 、capacitor C B2 、resistor R B1 、resistor R B2 、resistor R B3 and resistor R B4 , where The transistor M MP3 、 the transistor M MP4 、 the transistor M MP7 and the transistor M MP8 have their source electrodes connected to a power supply voltage; The drain of the transistor M MP7 is connected to the source of the transistor M MP5 , and the gates are respectively connected to the gate and drain of the transistor M MP5 ; the drain of the transistor M MP3 is connected to the source of the transistor M MP1 , and the gates are respectively connected to the gate of the transistor M MP7 and the transistor M MP1 ; the drain of the transistor M MP4 is connected to the source of the transistor M MP2 , and the gates are respectively connected to the gate of the transistor M MP8 and the transistor M MP2 ; the drain of the transistor M MP8 is connected to the source of the transistor M MP6 , and the gates are respectively connected to the gate and drain of the transistor M MP6 ; The source of the transistor M MN3 is connected to the drain of the transistor M MN1 and the drain is connected to the drain of the transistor M MP5 while the gates are respectively connected to the gates of the transistor M MN1 and the transistor M MN2 ; the source of the transistor M MN4 is connected to the drain of the transistor M MN2 and the drain is connected to the drain of the transistor M MP6 while the gate is connected to the gate of the transistor M MN2 ; the sources of the transistor M MN1 and the transistor M MN2 are both connected to the ground voltage; The source of the transistor MP1 is connected to the drain of the transistor M MP1 and the drain is connected to the source of the transistor MP3, and the gate is connected to the gate of the transistor MP2; the drain of the transistor MP3 is connected to the drain of the transistor MN7, and the gate is connected to the gate of the transistor MP4; The source of the transistor MP2 is connected to the drain of the transistor M MP2 ; the drain is connected to the source of the transistor MP4; the drain of the transistor MP4 is connected to the drain of the transistor MN8; the gate of the transistor MN7 is connected to the gate of the transistor MN8, and the sources of the transistor MN7 and the transistor MN8 are both connected to the ground voltage; The source of the transistor MN3 is connected to the drain of the transistor MN1, and the drain is connected to the drain of the transistor M MP1 , and the gate is connected to the first end of the capacitor C B1 ; the second end of the capacitor C B1 is connected to the gate of the transistor MN1; the source of the transistor MN1 is connected to the drain of the transistor MN5, and the gate serves as one of the differential input terminals of the radio frequency signal; the gate of the transistor MN5 is connected to the first end of the resistor R B3 , and the second end of the resistor R B3 is connected to the first end of the resistor R B4 . The source of the transistor MN4 is connected to the drain of the transistor MN2, and the drain is connected to the drain of the transistor M MP2 ; the gate is connected to the first end of the capacitor C B2 ; the second end of the capacitor C B2 is connected to the gate of the transistor MN2; the source of the transistor MN2 is connected to the drain of the transistor MN6, and the gate serves as the other differential input terminal of the radio frequency signal; the gate of the transistor MN6 is connected to the second end of the resistor R B4 ; the sources of the transistor MN5 and the transistor MN6 are both connected to the ground voltage; The resistor R B1 has its first end connected to the second end of the resistor R B2 and its second end connected to the gate of the transistor MN3; the first end of the resistor R B2 is connected to the gate of the transistor MN4; The capacitor C J1 is connected between the drain of the transistor MN7 and the gate of the transistor MN5; the capacitor C J2 is connected between the drain of the transistor MN8 and the gate of the transistor MN6; the capacitor C C1 is connected between the drain of the transistor MP3 and the ground voltage; the capacitor C C2 is connected between the drain of the transistor MP4 and the ground voltage; The drain of the transistor MN5 serves as one differential output terminal of the primary buffer signal, and the drain of the transistor MN6 serves as the other differential output terminal of the primary buffer signal.

6. The high-speed time-interleaved analog-to-digital conversion system based on radio frequency sampling front-end technology according to claim 5, wherein The bias circuit includes: transistor M B1 , transistor M B2 , transistor M B3 , transistor M B4 , transistor M B5 , transistor M B6 , transistor M B7 , transistor M B8 , transistor M B9 , transistor M B10 , transistor M B11 , transistor M B12 , transistor M B13 , transistor M B14 , transistor M B15 , transistor M B16 , a first amplifier and a resistor R0, where The transistor M B2 、 the transistor M B4 、 the transistor M B6 and the transistor M B8 have their source electrodes connected to the power supply voltage; The drain of the transistor M B2 is connected to the source of the transistor M B1 , and the gates are respectively connected to the gate and the drain of the transistor M B1 ; the drain of the transistor M B4 is connected to the source of the transistor M B3 , and the gates are respectively connected to the gate of the transistor M B2 and the gate of the transistor M B3 ; the drain of the transistor M B6 is connected to the source of the transistor M B5 , and the gates are respectively connected to the gate of the transistor M B4 and the gate of the transistor M B5 ; the drain of the transistor M B8 is connected to the source of the transistor M B7 , and the gates are respectively connected to the gate of the transistor M B6 and the gate of the transistor M B7 ; The source of the transistor M B9 is connected to the drain of the transistor M B10 and the drain is connected to the drain of the transistor M B3 while the gates are respectively connected to its drain and the gate of the transistor M B10 ; the gate of the transistor M B10 is connected to the gate of the transistor M MN3 ; The transistor M B11 has its source connected to the drain of the transistor M B5 and its drain connected to the source of the transistor M B12 . Its gate is respectively connected to its drain and the gate of the transistor MP1; the transistor M B12 has its drain connected to the drain of the transistor M B13 and its gate is respectively connected to its drain and the gate of the transistor MP3; the transistor M B13 has its gate connected to its drain; The source electrode of the transistor M B14 is connected to the drain electrode of the transistor M B15 whose drain electrode is connected to the drain electrode of the transistor M B7 and whose gate electrode is respectively connected to its drain electrode and the first end of the resistor R B1 ; the gate electrode of the transistor M B15 is respectively connected to its drain electrode and the second end of the resistor R B3 ; The transistor M B16 has its source connected to the negative input terminal of the first amplifier and the first terminal of the resistor R0 respectively, and its drain connected to the drain of the transistor M B1 ; its gate is connected to the output terminal of the first amplifier, and the positive input terminal of the first amplifier is connected to an off-chip reference voltage. The second terminal of the resistor R0, the source of the transistor M B10 The source of the transistor M B13 The source of the transistor M B15 The source of the transistor M is all connected to the ground voltage.

7. The high-speed time-interleaved analog-to-digital conversion system based on radio frequency sampling front-end technology according to claim 5, characterized in that, The Class AB enhancement circuit includes: transistor M AB1 , transistor M AB2 , transistor M AB3 and transistor M AB4 , where The source of the transistor M AB1 is connected to the drain of the transistor MN5, and the drain is connected to the source of the transistor M AB3 ; the gate is connected to the gate of the transistor MN1; the transistor M AB3 's drain is connected to the power supply voltage, and the gate is connected to the gate of the transistor MN3; The source of the transistor M AB2 is connected to the drain of the transistor MN6, and the drain is connected to the source of the transistor M AB4 ; the gate is connected to the gate of the transistor MN2. The drain of the transistor M AB4 is connected to the power supply voltage, and the gate is connected to the gate of the transistor MN4.

8. The high-speed time-interleaved analog-to-digital conversion system based on radio frequency sampling front-end technology according to claim 7, characterized in that The auxiliary circuit includes: transistor M MN5 , transistor M MN6 , transistor M MN7 , transistor M MN8 , transistor M AUX1 , and transistor M AUX2 , where The transistor M AUX1 and the transistor M AUX2 have their drains connected to the power supply voltage; The source of the transistor M AUX1 is respectively connected to its substrate, the drain of the transistor M MN7 , the substrate of the transistor M AB1 , and the substrate of the transistor MN1; the gate of the transistor M AUX1 is connected to the gate of the transistor MN1; The transistor M AUX2 has its source connected to its substrate, the drain of the transistor M MN8 , the substrate of the transistor M AB2 , and the substrate of the transistor MN2; the gate of the transistor M AUX2 is connected to the gate of the transistor MN2; The source of the transistor M MN7 is connected to the drain of the transistor M MN5 and the gate is connected to the transistor M MN5 and the transistor M MN1 ; the source of the transistor M MN8 is connected to the drain of the transistor M MN6 and the gates are respectively connected to the transistor M MN5 and the transistor M MN6 ; The transistor M MN5 and the transistor M MN6 have their source electrodes connected to the ground voltage.

9. The high-speed time-interleaved analog-to-digital conversion system based on radio frequency sampling front-end technology according to claim 5, wherein The common-mode feedback circuit includes: resistor R1, resistor R B5 , resistor R B6 , capacitor C1, capacitor C2, and a second amplifier, wherein The resistor R B5 has its first end connected to the drain of the transistor MN7 and its second end connected to the first end of the resistor R B6 ; the second end of the resistor R B6 is connected to the drain of the transistor MN8; The first end of the capacitor C2 is connected to the ground voltage, and the second end is connected to the second end of the resistor R B5 ; The first end of the resistor R1 is connected to the internal reference voltage of the chip, and the second end is respectively connected to the first end of the capacitor C1 and the negative input end of the second amplifier. The positive input end of the second amplifier is connected to the first end of the resistor R B6 ; the second end of the capacitor C1 is connected to the gate of the transistor MN7, and the output end of the second amplifier is connected to the gate of the transistor MN8.

10. The high-speed time-interleaved analog-to-digital conversion system based on radio frequency sampling front-end technology according to claim 1, characterized in that, The inter-stage residual amplifier circuit includes a core circuit based on cascaded inverters, an asynchronous adaptive regulation clock circuit, and a composite CMFB circuit, where The core circuit based on the cascaded inverter includes: a first-stage equivalent inverter circuit, a second-stage equivalent inverter circuit, a conventional inverter circuit, a feedback capacitor C F , a related level-shifting capacitor C LS , a capacitor C S1 , a capacitor C S2 , and a switch circuit. Among them, the first-stage equivalent inverter circuit, the second-stage equivalent inverter circuit, and the conventional inverter circuit are connected in series in sequence; the feedback capacitor C F is connected between the input end of the first-stage equivalent inverter circuit and the second end of the related level-shifting capacitor C LS ; the first end of the related level-shifting capacitor C LS is connected to the output end of the conventional inverter circuit; the capacitor C S1 is connected between the input end of the first-stage equivalent inverter circuit and the ground end; the capacitor C S2 is connected between the second end of the related level-shifting capacitor C LS and the ground end; the switch circuit is used to control the two-phase working stage of the inter-stage residual amplifier circuit; The asynchronous adaptive regulation clock circuit is connected to the core circuit based on cascaded inverters, and is used to extract the voltage at the output terminal of the traditional inverter circuit, and generate an adaptive regulation clock for controlling the inter-stage residual amplifier circuit in the coarse amplification working stage and the fine amplification working stage according to the extracted voltage; The composite CMFB circuit includes: an AC CMFB circuit and a DC CMFB circuit. Among them, the AC CMFB circuit is used to extract the common-mode voltage V according to the output of the core circuit based on cascaded inverters CMO , and generate a feedback signal for the second-stage equivalent inverter circuit according to the common-mode voltage V CMO ; the DC CMFB circuit is used to generate a feedback signal for the first-stage equivalent inverter circuit according to the common-mode voltage V CMO .

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