Semiconductor structure, manufacturing method thereof and electronic equipment

Abstract

The invention relates to a semiconductor structure, a manufacturing method thereof and electronic equipment. The semiconductor structure comprises a substrate; a word line vertically disposed on the substrate; the at least one semiconductor channel is arranged at intervals in the direction perpendicular to the substrate, each semiconductor channel surrounds and covers part of the circumferential surface of the word line, and each semiconductor channel comprises a first end and a second end which are oppositely arranged in the first direction parallel to the substrate; the at least one oxide insulation part is arranged at intervals in the direction perpendicular to the substrate, the at least one oxide insulation part and the at least one semiconductor channel are arranged in a one-to-one correspondence mode, each oxide insulation part covers the peripheral face, except the first end and the second end, of the corresponding semiconductor channel, and the oxide insulation parts have a good electric isolation effect; the material performance and the energy level structure of the oxide insulation part are not easy to form a charge potential well, so that the semiconductor channel has good conductivity, and adverse effects on the semiconductor structure are avoided.

Description

Technical Field

[0001] The present disclosure relates to the field of integrated circuit technologies, and in particular, to a semiconductor structure, a manufacturing method thereof, and an electronic device. Background Art

[0002] At present, silicon nitride is often used as an electrical isolation material to fill between semiconductor devices in semiconductor memories. However, due to the material properties and energy level structure of silicon nitride itself, it is easy to form charge potential wells, thereby capturing charges, which may affect the conductivity of semiconductor devices and ultimately have an adverse impact on the performance of semiconductor memories. Summary of the Invention

[0003] Based on this, the present disclosure provides a semiconductor structure, a manufacturing method thereof, and an electronic device.

[0004] To achieve the above object, in a first aspect, the present disclosure provides a semiconductor structure, including:

[0005] A substrate;

[0006] A word line, vertically disposed on the substrate;

[0007] At least one semiconductor channel, spaced along a direction perpendicular to the substrate, each semiconductor channel surrounding and covering a part of the circumferential surface of the word line, and along a first direction parallel to the substrate, each semiconductor channel includes a first end and a second end disposed opposite to each other;

[0008] At least one oxide insulating portion, spaced along a direction perpendicular to the substrate, at least one oxide insulating portion and at least one semiconductor channel are arranged in one-to-one correspondence, and each oxide insulating portion covers the circumferential surface of the corresponding semiconductor channel except the first end and the second end.

[0009] Optionally, the length of the semiconductor channel in the first direction is less than the length of the semiconductor channel in a second direction, the second direction is parallel to the substrate, and the first direction and the second direction intersect.

[0010] Optionally, each oxide insulating portion includes a first portion and a second portion disposed opposite to each other on both sides of the semiconductor channel along the second direction.

[0011] Optionally, an oxide insulating layer is formed between adjacent semiconductor channels along the second direction, and the oxide insulating layer is respectively connected to the oxide insulating portions corresponding to the adjacent semiconductor channels, the second direction is parallel to the substrate, and the first direction and the second direction intersect.

[0012] Optionally, the semiconductor structure further includes:

[0013] A capacitor is disposed on one side of the semiconductor channel along the first direction. The capacitor includes a first electrode, a dielectric layer, and a second electrode. The second electrode is vertically disposed on the substrate. The first electrode is disposed on the outer periphery of the second electrode. The first electrode is in contact connection with the first end. The dielectric layer is disposed between the first electrode and the second electrode;

[0014] A bit line is disposed on the side of the semiconductor channel away from the capacitor along the first direction. The bit line extends along a second direction. The bit line is in contact connection with the second end.

[0015] Optionally, the semiconductor structure further includes an oxide layer and a nitride layer. The oxide layer and the nitride layer are alternately disposed on the substrate. The semiconductor channel, the capacitor, and the bit line are disposed in the nitride layer. The semiconductor channel is separated from the nitride layer by the oxide insulating portion;

[0016] Along a direction perpendicular to the substrate, the oxide layer covers the word line located between adjacent semiconductor channels.

[0017] In a second aspect, the present disclosure provides an electronic device including the semiconductor structure described in the first aspect.

[0018] In a third aspect, the present disclosure provides a manufacturing method of a semiconductor structure, including the following steps:

[0019] Provide a substrate, and alternately form an oxide layer and a nitride layer on the substrate to form a stacked structure;

[0020] Form a channel hole, the channel hole being perpendicular to the substrate and penetrating through the stacked structure;

[0021] Remove a part of the nitride layer around the channel hole;

[0022] Form an oxide insulating portion at the position where the nitride layer is removed;

[0023] Form a semiconductor layer and a word line in the channel hole in sequence. The semiconductor layer covers the oxide insulating portion and the hole wall of the channel hole. The word line covers the inner wall of the semiconductor layer and fills the channel hole;

[0024] Etch and remove the semiconductor layer covered by the oxide layer. The remaining semiconductor layer forms at least one semiconductor channel. Each semiconductor channel includes a first end and a second end disposed opposite to each other along a first direction. The peripheral surface of the semiconductor channel except the first end and the second end is covered by the oxide insulating portion.

[0025] Optionally, removing a portion of the nitride layer around the channel hole includes:

[0026] Etching the nitride layer exposed by the channel hole to form a first groove and a second groove disposed opposite to each other on both sides of the channel hole along a second direction, the first direction and the second direction being parallel to the substrate, and the first direction and the second direction intersecting;

[0027] The oxide insulating portion includes a first portion formed in the first groove and a second portion formed in the second groove, and the oxide insulating portion exposes the hole wall of the channel hole between the first groove and the second groove.

[0028] Optionally, after forming the first groove and the second groove disposed opposite to each other on both sides of the channel hole along the second direction, the size of the channel hole in the nitride layer in the first direction is smaller than the size of the channel hole in the second direction.

[0029] Optionally, forming an oxide insulating portion at the position where the nitride layer is removed includes:

[0030] Forming an oxide insulating layer that covers the side walls of the first groove, the side walls of the second groove, and the exposed hole wall of the channel hole;

[0031] Forming a protective layer that covers the oxide insulating layer;

[0032] Etching and removing the protective layer covering the hole wall of the channel hole;

[0033] Using the remaining protective layer as a mask to etch the oxide insulating layer, etching and removing the oxide insulating layer covering the hole wall of the channel hole, and the oxide insulating layer in the first groove and the second groove is formed as the oxide insulating portion.

[0034] Optionally, after forming the channel hole, it includes:

[0035] Etching the oxide layer exposed by the channel hole to remove a portion of the oxide layer and form a third groove, and along a direction parallel to the substrate, the third groove extends away from the channel hole;

[0036] Forming a first dielectric layer that fills the channel hole and the third groove.

[0037] Optionally, removing a portion of the nitride layer around the channel hole includes:

[0038] Along a second direction, first through-holes are respectively formed on both sides of the channel hole, and the first through-holes and the channel hole are arranged at intervals, and the first through-holes vertically penetrate the stacked structure;

[0039] Based on the first through-holes, part of the nitride layer is etched away to expose the first dielectric layer covered by the nitride layer.

[0040] Optionally, an oxide insulating portion is formed at the position where the nitride layer is removed, including:

[0041] An oxide insulating layer is deposited, and the oxide insulating layer covers the exposed surface of the first dielectric layer and fills the position where the nitride layer is removed and the first through-holes to form the oxide insulating portion.

[0042] Optionally, before a semiconductor layer and a word line are sequentially formed in the channel hole, the first dielectric layer in the channel hole is removed, and the first dielectric layer in the third groove is retained.

[0043] Optionally, etching away the semiconductor layer covered by the oxide layer includes:

[0044] A second through-hole perpendicular to the substrate is formed, and the second through-hole is disposed close to the channel hole, and the second through-hole exposes the first dielectric layer in the third groove;

[0045] Etch away the first dielectric layer in the third groove and etch the semiconductor layer covered by the first dielectric layer in the third groove.

[0046] Optionally, the manufacturing method further includes:

[0047] A capacitor hole is formed, the capacitor and the channel hole are arranged at intervals along the first direction, and the capacitor hole vertically penetrates the stacked structure along a direction perpendicular to the substrate;

[0048] Based on the capacitor hole, part of the nitride layer is etched away until the channel hole is reached to form a fourth groove;

[0049] A first electrode is formed in the fourth groove, and the first electrode is in contact connection with the first end of the semiconductor channel;

[0050] A dielectric layer covering the first electrode and a second electrode covering the dielectric layer and filling the capacitor hole are sequentially formed in the capacitor hole.

[0051] Optionally, the manufacturing method further includes:

[0052] Along the first direction, a first etching groove is formed on a side of the channel hole away from the capacitor. The first etching groove and the channel hole are arranged at intervals, and the first etching groove extends along a second direction.

[0053] Based on the first etching groove, a part of the nitride layer is etched away until reaching the channel hole, forming a bit line groove along the second direction.

[0054] A bit line is formed in the bit line groove. The bit line extends along the second direction and is in contact connection with the second end of the semiconductor channel.

[0055] In the semiconductor structure, manufacturing method, and electronic device of the present disclosure, except for the first end and the second end, the semiconductor channel is covered by an oxide insulating portion. The oxide insulating portion has a good electrical isolation effect, and the material properties and energy level structure of the oxide insulating portion are not likely to form a charge potential well, ensuring that the semiconductor channel has good electrical conductivity and avoiding adverse effects on the semiconductor structure. Description of the Drawings

[0056] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present disclosure. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0057] Figure 1 It is a schematic structural diagram of a semiconductor structure provided in an embodiment.

[0058] Figure 2 It is Figure 1 a cross-sectional view perpendicular to the substrate along the A - A line in

[0059] Figure 3 It is Figure 1 a cross-sectional view parallel to the substrate along the B - B line in

[0060] Figure 4 It is Figure 1 a cross-sectional view parallel to the substrate along the C - C line in

[0061] Figure 5 It is a schematic structural diagram of a semiconductor structure provided in another embodiment.

[0062] Figure 6 It is Figure 5 a cross-sectional view parallel to the substrate along the B - B line in

[0063] Figure 7 It is Figure 5 a cross-sectional view parallel to the substrate along the C - C line in

[0064] Figure 8 Process flow diagram of a method for fabricating a semiconductor structure provided in one embodiment.

[0065] Figure 9 Process flow diagram of a method for fabricating a semiconductor structure provided in another embodiment.

[0066] Figure 10 Schematic diagram after forming a capacitor and bit lines in one embodiment.

[0067] Figure 11 Schematic diagram of a channel hole provided in one embodiment.

[0068] Figure 12 Schematic diagram after forming a first groove and a second groove in one embodiment.

[0069] Figure 13 Schematic diagram of a channel hole after forming a first groove and a second groove in one embodiment.

[0070] Figure 14 Schematic diagram after forming an oxide insulating layer and a protective layer in one embodiment.

[0071] Figure 15 Schematic diagram after forming a protective layer on the hole wall of a removed channel hole in one embodiment.

[0072] Figure 16 Schematic diagram after forming an oxide insulating portion in one embodiment.

[0073] Figure 17 Schematic diagram of an oxide insulating portion formed in one embodiment.

[0074] Figure 18 Parallel cross-sectional view parallel to the substrate along the B-B line in Figure 5 after forming a capacitor hole and a channel hole in one embodiment.

[0075] Figure 19 Parallel cross-sectional view parallel to the substrate along the C-C line in Figure 5 after forming a capacitor hole and a channel hole in one embodiment.

[0076] Figure 20 Parallel cross-sectional view parallel to the substrate along the C-C line in Figure 5 after forming a third groove in one embodiment.

[0077] Figure 21 Parallel cross-sectional view parallel to the substrate along the B-B line in Figure 5 after forming a first dielectric layer in one embodiment.

[0078] Figure 22A cross-sectional view parallel to the substrate along the C-C line after forming the first dielectric layer in an embodiment. Figure 5 in the

[0079] Figure 23 A cross-sectional view parallel to the substrate along the B-B line after forming the capacitor and bit line in an embodiment. Figure 5 in the

[0080] Figure 24 A cross-sectional view parallel to the substrate along the B-B line after forming the first via hole in an embodiment. Figure 5 in the

[0081] Figure 25 A cross-sectional view parallel to the substrate along the B-B line after removing the nitride layer around the channel trench in an embodiment. Figure 5 in the

[0082] Figure 26 A cross-sectional view parallel to the substrate along the B-B line after forming the oxide insulating portion in an embodiment. Figure 5 in the

[0083] Figure 27 A cross-sectional view parallel to the substrate along the C-C line after forming the oxide insulating portion in an embodiment. Figure 5 in the

[0084] Figure 28 A cross-sectional view parallel to the substrate along the B-B line after removing the first dielectric layer in the channel hole in an embodiment. Figure 5 in the

[0085] Figure 29 A cross-sectional view parallel to the substrate along the C-C line after removing the first dielectric layer in the channel hole in an embodiment. Figure 5 in the

[0086] Figure 30 A cross-sectional view parallel to the substrate along the B-B line after forming the semiconductor layer and word line in an embodiment. Figure 5 in the

[0087] Figure 31 A cross-sectional view parallel to the substrate along the C-C line after forming the semiconductor layer and word line in an embodiment. Figure 5 in the

[0088] Figure 32 A cross-sectional view parallel to the substrate along the B-B line after forming the second via hole in an embodiment. Figure 5 in the

[0089] Figure 33 A cross-sectional view parallel to the substrate along the B-B line after removing the first dielectric layer and the semiconductor layer parallel to the substrate connected thereto in the third groove in an embodiment.Figure 5 Cross-sectional view of line B-B in Description of the Drawings:

[0091] 1. Initial structure; 10. Substrate; 121. Protective layer; 122. First dielectric layer; 20. Word line; 21. Gate dielectric layer; 22. Diffusion barrier layer; 30. Semiconductor channel; 30a. Semiconductor layer; 31. First end; 32. Second end; 40. Oxide insulating portion; 40a. Oxide insulating layer; 41. First part; 42. Second part; 50. Capacitor; 51. First electrode; 52. Dielectric layer; 53. Second electrode; 531. First sub-electrode; 532. Second sub-electrode; 70. Bit line; 80. Stacked structure; 81. Oxide layer; 82. Nitride layer; 91. Channel hole; 911. First groove; 912. Second groove; 913. Third groove; 92. Capacitance hole; 101. First through hole; 102. Second through hole;

[0092] D1. First direction; D2. Second direction. Detailed Description of the Invention

[0093] To facilitate the understanding of the present disclosure, the present disclosure will be described more comprehensively hereinafter with reference to the relevant drawings. Preferred embodiments of the present disclosure are shown in the drawings. However, the present disclosure may be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided to make the disclosure of the present disclosure more thorough and comprehensive.

[0094] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the technical field to which this disclosure belongs. The terms used in the description of the present disclosure herein are for the purpose of describing specific embodiments only and are not intended to limit the present disclosure.

[0095] Currently, for semiconductor memories, especially 3D memory structures based on Channel All Around (CAA) transistors, such as Dynamic Random Access Memory (DRAM) and NAND Flash Memory (NAND), the memory cells in the memory cell layer are electrically isolated by silicon nitride. Limited by its own material properties and energy level structure, silicon nitride is prone to form charge potential wells, thereby capturing charges. Silicon nitride is in direct contact with the channel of the transistor. The capture of charges by silicon nitride will affect the conductivity of the channel and the performance of the transistor, having an adverse effect on the semiconductor memory.

[0096] According to an exemplary embodiment, the present embodiment provides a semiconductor structure, referring to Figures 1 - 4 as shown, or referring to Figures 5 - 7As shown, the semiconductor structure includes a substrate 10, a word line 20, at least one semiconductor channel 30, and at least one oxide insulating portion 40. The word line 20 is vertically disposed on the substrate 10; at least one semiconductor channel 30 is spaced along a direction perpendicular to the substrate 10, and each semiconductor channel 30 surrounds and covers a partial peripheral surface of the word line 20. Along a first direction D1 parallel to the substrate 10, each semiconductor channel 30 includes a first end 31 and a second end 32 that are oppositely disposed; at least one oxide insulating portion 40 is spaced along a direction perpendicular to the substrate 10, and at least one oxide insulating portion 40 and at least one semiconductor channel 30 are disposed in one-to-one correspondence. Each oxide insulating portion 40 covers the peripheral surface of its corresponding semiconductor channel 30 except for the first end 31 and the second end 32.

[0097] The first end 31 of the semiconductor channel 30 is a source contact end or a drain contact end, the second end 32 of the semiconductor channel 30 is a drain contact end or a source contact end, the peripheral surface of the semiconductor channel 30 except for the first end 31 and the second end 32 is covered by the oxide insulating portion 40. The oxide insulating portion 40 has a good electrical isolation effect, and the material properties and energy level structure of the oxide insulating portion 40 are not likely to form a charge potential well, which can ensure that the semiconductor channel 30 has good electrical conductivity and avoid adverse effects on the semiconductor structure.

[0098] In some embodiments, referring to Figures 1 - 4 as shown, or referring to Figures 5 - 7 as shown, the semiconductor structure further includes a gate dielectric layer 21. The gate dielectric layer 21 covers the outer peripheral surface of the word line 20, and the gate dielectric layer 21 is disposed between the word line 20 and the semiconductor channel 30.

[0099] The semiconductor structure further includes a diffusion barrier layer 22. The diffusion barrier layer 22 is disposed between the word line 20 and the gate dielectric layer 21, and the diffusion barrier layer 22 covers the outer peripheral surface of the word line 20 and is in direct contact with the word line 20. The diffusion barrier layer 22 is used to prevent the elements in the word line 20 from diffusing into other device structures, avoiding the deterioration of electrical performance caused by the pollution of other device structures.

[0100] In some embodiments, referring to Figures 1 - 4 as shown, the length of the semiconductor channel 30 in the first direction D1 is less than the length of the semiconductor channel 30 in the second direction D2. The second direction D2 is parallel to the substrate 10, and the first direction D1 and the second direction D2 intersect. Exemplarily, the first direction D1 and the second direction D2 are perpendicular. Thus, the length of the semiconductor channel 30 is increased, which can improve the short-channel effect and is beneficial to improving the performance of the transistor in the semiconductor structure.

[0101] In some embodiments, referring to Figures 1 - 4As shown, each oxide insulating portion 40 includes a first portion 41 and a second portion 42 that are oppositely disposed on both sides of the semiconductor channel 30 along the second direction D2. Among them, the first portion 41 and the second portion 42 are symmetrically disposed along the midline of the semiconductor channel 30 in the first direction D1. Thus, the size of the oxide insulating portion 40 is small, and the setting of the oxide insulating portion 40 does not limit the size and setting density of the semiconductor channel 30. The size of the oxide insulating portion 40 can be miniaturized according to the semiconductor channel 30, adapting to the development of the semiconductor structure towards miniaturization and high density.

[0102] In some embodiments, referring to Figures 5 - 7 As shown, along the second direction D2, an oxide insulating layer is formed between adjacent semiconductor channels 30, and the oxide insulating layer is respectively connected to the oxide insulating portions 40 corresponding to the adjacent semiconductor channels 30. That is, a plurality of oxide insulating portions 40 are sequentially connected to form an oxide insulating layer 40a. The second direction D2 is parallel to the substrate 10, and the first direction D1 and the second direction D2 intersect. Thus, the structural size of the oxide insulating portion 40 is larger, and the oxide insulating layer 40a can provide a better electrical isolation effect for the semiconductor channels 30 arranged along the second direction D2. When the transistors formed by the semiconductor channels 30 are in the working state to form charge potential wells, it is beneficial to improve the reliability of the semiconductor structure.

[0103] Referring to Figures 5 - 7 As shown, in the embodiment where a plurality of oxide insulating portions 40 are sequentially connected to form an oxide insulating layer 40a, the length of the semiconductor channel 30 in the first direction D1 is equal to the length of the semiconductor channel 30 in the second direction D2 (the equality in this disclosure is approximately equal). The semiconductor channel 30 is closer to an ideal perfect circle, which can avoid charge accumulation at the corners of the semiconductor channel 30 and affect the electrical performance of the semiconductor structure.

[0104] In some embodiments, referring to Figures 1 - 4 As shown, or referring to Figures 5 - 7 As shown, the semiconductor structure further includes a capacitor 50 disposed on one side of the semiconductor channel 30 along the first direction D1. The capacitor 50 includes a first electrode 51, a dielectric layer 52, and a second electrode 53. The second electrode 53 is perpendicularly disposed on the substrate 10, the first electrode 51 is disposed on the outer periphery of the second electrode 53, the first electrode 51 is in contact connection with the first end 31, and the dielectric layer 52 is disposed between the first electrode 51 and the second electrode 52.

[0105] In some embodiments, the second electrode 53 includes a first sub - electrode 531 covering the dielectric layer 52, and a second sub - electrode 532 covering the inner wall of the first sub - electrode 531 and filling the accommodation space enclosed by the first sub - electrode 531. In this way, the volume ratio of the second electrode 52 of the capacitor 50 is increased, the storage capacity of the capacitor 50 is increased, and the storage ability of the semiconductor structure is improved.

[0106] In some embodiments, referring to Figures 1 - 4 as shown, or referring to Figures 5 - 7 as shown, the semiconductor structure further includes a bit line 70. The bit line 70 is disposed on the side of the semiconductor channel 30 away from the capacitor 50 along the first direction D1, the bit line 70 extends along the second direction D2, and the bit line 70 is in contact connection with the second end 32.

[0107] In some embodiments, referring to Figures 1 - 4 as shown, or referring to Figures 5 - 7 as shown, the semiconductor structure further includes an oxide layer 81 and a nitride layer 82. The oxide layer 81 and the nitride layer 82 are alternately disposed on the substrate 10. The semiconductor channel 30, the capacitor 50, and the bit line 70 are disposed in the nitride layer, and the semiconductor channel 30 is separated from the nitride layer 81 by an oxide insulating portion 40.

[0108] Along the direction perpendicular to the substrate 10, the oxide layer 81 covers the outer peripheral wall of the word line 20 located between adjacent semiconductor channels 30.

[0109] The semiconductor structure of this embodiment can be a Dynamic Random Access Memory (DRAM). However, the semiconductor structure of this embodiment can also be a Static Random - Access Memory (SRAM), a flash EPROM, a Ferroelectric Random - Access Memory (FRAM), a Magnetic Random - Access Memory (MRAM), a Phase change Random - Access Memory (PRAM), etc.

[0110] According to an exemplary embodiment, this embodiment provides an electronic device. The electronic device in this embodiment includes the semiconductor structure in the above - mentioned embodiment.

[0111] Exemplarily, the electronic device can be: a storage device, a smart phone, a computer, a computer, an artificial intelligence device, a wearable device, or a mobile power supply, etc. The storage device can include the memory in a computer, etc., which is not limited here.

[0112] Figure 8 A flowchart showing a method for fabricating a semiconductor structure according to some embodiments of the present disclosure Figures 10 - 17 is a schematic diagram of various stages of a method for fabricating a semiconductor structure. Below, in combination with Figures 10 - 17 and with reference to Figures 1 - 4 a method for fabricating a semiconductor structure of some embodiments will be introduced. As Figure 8 shown, a method for fabricating a semiconductor structure of some embodiments includes the following steps:

[0113] Step S110: Provide a substrate, and alternately form an oxide layer and a nitride layer on the substrate to form a stacked structure.

[0114] Step S120: Form a channel hole that is perpendicular to the substrate and penetrates the stacked structure.

[0115] Step S130: Remove a part of the nitride layer around the channel hole.

[0116] Step S140: Form an oxide insulating portion at the position where the nitride layer is removed.

[0117] Step S150: Sequentially form a semiconductor layer and a word line in the channel hole. The semiconductor layer covers the oxide insulating portion and the hole wall of the channel hole, and the word line covers the inner wall of the semiconductor layer and fills the channel hole.

[0118] Step S160: Etch and remove the semiconductor layer covered by the oxide layer, and the remaining semiconductor layer forms at least one semiconductor channel. Each semiconductor channel includes a first end and a second end that are oppositely arranged in a first direction. The peripheral surface of the semiconductor channel except for the first end and the second end is covered by the oxide insulating portion.

[0119] In step S110, referring to Figure 10 shown, the substrate 10 may be a semiconductor substrate. The material of the semiconductor substrate may include silicon (Si), silicon germanium (SiGe), silicon germanium carbide (SiGeC), silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), indium phosphide (InP), or other III / V semiconductor materials or II / VI semiconductor materials. Alternatively, for example, the semiconductor substrate may be a layered substrate including, such as Si / SiGe, Si / SiC, silicon on insulator (SOI), or silicon germanium on insulator. The substrate 10 may be a single-layer structure or a multi-layer structure.

[0120] The stacked structure 80 includes an oxide layer 81 and a nitride layer 82 that are alternately disposed on the substrate 10. The oxide layer 81 may include silicon oxide, and the nitride layer 82 may include silicon nitride or silicon oxynitride.

[0121] In step S120, referring to Figure 10As shown, a dry process can be used to pattern the stacked structure 80. Part of the stacked structure 80 is etched away to form a channel hole 91 that vertically penetrates the stacked structure 80 along the third direction D3. The sidewalls of the channel hole 91 expose part of the oxide layer 81 and part of the nitride layer 82.

[0122] It can be understood that between step S120 and step S130, processes for forming other devices can be performed. The other devices can be semiconductor devices and / or metal devices. Among them, the semiconductor devices can include at least one of a metal-oxide-semiconductor field-effect transistor, a bipolar junction transistor, a resistor, an inductor, a diode, and an optical device. The nitride layers 82 located on both sides of the channel hole 91 along the first direction D1 are removed and replaced with other material film layers.

[0123] For example, in some embodiments, between step S120 and step S130, processes for forming the capacitor 50 and the bit line 70 are performed. The steps of forming the capacitor 50 and the bit line 70 will be described in detail in subsequent embodiments. Refer to Figure 10 As shown, along the first direction D1, the capacitor 50 is disposed on one side of the channel hole 91, and the bit line 70 is formed on the side of the channel hole 91 away from the capacitor 50.

[0124] In some embodiments of the present disclosure, step S130 removes part of the nitride layer 82 around the channel hole 91, including:

[0125] Step S131a: Etch the nitride layer exposed by the channel hole to form a relatively disposed first groove and a second groove on both sides of the channel hole along the second direction. The first direction and the second direction are parallel to the substrate, and the first direction and the second direction intersect.

[0126] As Figure 12 、 Figure 13 shown, referring to Figure 10 、 Figure 11 , based on the channel hole 91, etch the nitride layer 82 exposed by the channel hole 91 to form a first groove 911 and a second groove 912 on the sidewalls of the channel hole 91. The first groove 911 and the second groove 912 are independently disposed. Along the circumferential direction of the channel hole 91, the first groove 911 and the second groove 912 are separated by other material film layers.

[0127] Among them, the etching process has a high etching ratio for the oxide layer 81, and the etching rate of the etching process for the oxide layer 81 is close to zero to ensure that the first groove 911 and the second groove 912 are formed in the nitride layer 82.

[0128] Exemplarily, the etching process is an isotropic etching process. The nitride layer 82 exposed in the channel hole 91 is etched away, and first and second grooves 911 and 912 are formed on the sidewalls of the channel hole 91 and disposed opposite to each other along the second direction D2. The first groove 911 and the second groove 912 extend away from the channel groove 91 along the second direction D2 respectively.

[0129] As Figure 7 , Figure 8 shown, after the first and second grooves 911 and 912 disposed opposite to each other are formed on both sides of the channel hole 91 along the second direction D2, the size of the channel hole 91 in the nitride layer 82 in the first direction D1 is smaller than the size of the channel hole 91 in the second direction D2. The first direction D1 and the second direction D2 are parallel to the substrate 10, and the first direction D1 and the second direction D2 intersect.

[0130] Exemplarily, the first direction D1 and the second direction D2 are perpendicular.

[0131] In some embodiments of the present disclosure, the oxide insulating portion 40 formed in step S140 includes a first portion 41 disposed in the first groove 911 and a second portion 42 disposed in the second groove 912. The oxide insulating portion 40 exposes the hole wall of the channel hole 91 between the first groove 911 and the second groove 912.

[0132] In some embodiments of the present disclosure, forming the oxide insulating portion in step S140 includes steps S141 - S144:

[0133] Step S141: Form an oxide insulating layer, which covers the groove walls of the first groove, the groove walls of the second groove, and the exposed hole walls of the channel hole.

[0134] As Figure 14 shown, referring to Figure 12 , an oxide insulating layer 40a can be formed by chemical vapor deposition (CVD) or atomic layer deposition (ALD). The oxide insulating layer 40a covers the hole walls of the first groove 911, the hole walls of the second groove 912, and the exposed hole walls of the channel hole 91. The material of the oxide insulating layer 40a can include at least one of silicon oxide, aluminum oxide, magnesium oxide, or zirconium oxide.

[0135] During the process of depositing the oxide insulating layer 40a, the thickness of the oxide insulating layer 40a is controlled by controlling the deposition duration and deposition parameters, so that the thickness of the oxide insulating layer 40a is sufficient to cover the sidewalls of the first groove 911 and the sidewalls of the second groove 912, and the oxide insulating layer 40a does not fill the first groove 911 and the second groove 912. Thus, after the oxide insulating layer 40a is formed, the oxide insulating layer 40a in the first groove 911 and the oxide insulating layer 40a in the second groove 912 are still recessed relative to the oxide insulating layer 40a covering other regions in the channel hole 91.

[0136] Step S142: Form a protective layer that covers the oxide insulating layer.

[0137] As Figure 14 shown, referring to Figure 12 , a protective layer 121 is deposited by a deposition process to cover the oxide insulating layer 40a. Since the oxide insulating layer 40a in the first groove 911 and the oxide insulating layer 40a in the second groove 912 are recessed, the protective layer 121 in the first groove 911 and the protective layer 121 in the second groove 912 are recessed relative to the protective layer 121 covering other regions in the channel hole 91.

[0138] Exemplarily, the material of the protective layer 121 may include at least one of single-crystalline silicon and polycrystalline silicon.

[0139] Step S143: Etch and remove the protective layer covering the sidewalls of the channel hole.

[0140] As Figure 15 shown, referring to Figure 14 , a wet process may be used to etch the protective layer 121, etch and remove the protective layer 121 covering the sidewalls of the channel hole 91, expose the oxide insulating layer 40a covering the sidewalls of the channel hole 91, and retain the protective layer 121 in the first groove 911 and the protective layer 121 in the second groove 912.

[0141] Step S144: Use the remaining protective layer as a mask to etch the oxide insulating layer, etch and remove the oxide insulating layer covering the sidewalls of the channel hole, and the oxide insulating layer in the first groove and the second groove is formed into an oxide insulating portion.

[0142] As Figure 16 , Figure 17 shown, referring to Figure 12 , Figure 13 , Figure 14, using the remaining protective layer 121 as a mask to protect the oxide insulating layer 40a in the first groove 911 and the oxide insulating layer 40a in the second groove 912, injecting an etching solution into the channel hole 91, and wet-etching to remove the oxide insulating layer 40a exposed by the protective layer 121, that is, etching to remove the oxide insulating layer 40a covering the hole wall of the channel hole 91. The oxide insulating layer 40a in the first groove 911 forms the first part 41 of the oxide insulating portion 40, and the oxide insulating layer 40a in the second groove 912 forms the second part 42 of the oxide insulating portion 40.

[0143] It can be understood that after forming the oxide insulating portion 40, the protective layer 121 covering the oxide insulating portion 40 is etched and removed by a wet process to expose the oxide insulating portion 40, so that the subsequent formed semiconductor channel 30 can be in direct contact and connection with the oxide insulating portion 40.

[0144] In step S150, a semiconductor layer 30a can be deposited and formed by any one of chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or sputtering (refer to Figure 31 ), and the semiconductor layer 30a covers the oxide insulating portion 40 and the hole wall of the channel hole 91.

[0145] The material of the semiconductor layer 30a can include metal oxides. The material of the metal oxide can be indium gallium zinc oxide (IGZO). When the metal oxide material is IGZO, the leakage current of the transistor 11 is small (the leakage current is less than or equal to 10-15A), thereby ensuring the low refresh rate of the dynamic memory. It should be noted that the material of the metal oxide can also be ITO, IWO, ZnOx, InOx, In2O3, InWO, SnO2, TiOx, InSnOx, ZnxOyNz, MgxZnyOz, InxZnyOz, InxGayZnzOa, ZrxInyZnzOa, HfxInyZnzOa, SnxInyZnzOa, AlxSnyInzZnaOd, SixInyZnzOa, ZnxSnyOz, AlxZnySnzOa, GaxZnySnzOa, ZrxZnySnzOa, InGaSiO, IAZO, IGO, IZO (indium-zinc-oxide), IZOx and other materials, as long as the leakage current of the transistor can meet the requirements, and it can be adjusted according to the actual situation.

[0146] Then, a gate dielectric layer 21 is deposited and formed by any of the above deposition processes (refer to Figure 31 ), the gate dielectric layer 21 covers the inner wall of the semiconductor layer 30a, and the material of the gate dielectric layer 21 may include at least one of hafnium silicate oxynitride (HfSiON), zirconium silicate oxynitride (ZrSiON), and strontium silicate oxynitride (SrSiON).

[0147] Then, a diffusion barrier layer 22 is deposited and formed by any of the above deposition processes, the diffusion barrier layer 22 covers the gate dielectric layer 21, and the material of the diffusion barrier layer 22 may include titanium nitride or tantalum nitride.

[0148] Next, a word line 20 is deposited and formed by any of the above deposition processes (refer to Figure 31 ), the word line 20 covers the diffusion barrier layer 22 and fills the channel hole 91. The material of the word line 20 may include tungsten or a tungsten compound, titanium or a titanium compound. Exemplarily, the material of the word line 20 includes tungsten.

[0149] The diffusion barrier layer 22 is used to prevent the elements in the word line 20 from diffusing into other device structures and causing pollution to other device structures, so as to avoid the deterioration of electrical performance caused by the pollution of other device structures.

[0150] In some embodiments, after the oxide insulating portion 40 is formed, there are still unfilled spaces in the first groove 911 and the second groove 812. The semiconductor layer may also fill the unfilled spaces in the first groove 911 and the second groove 912.

[0151] In step S150, refer to Figures 1 - 4 、 Figure 31 , an etch is performed on the stacked structure 80 to form a through hole (not shown in the figure) that vertically penetrates the stacked structure 80 along the third direction D3, and sidewalls of the through hole expose a part of the oxide layer 81 and a part of the nitride layer 82.

[0152] The exposed oxide layer 81 in the through hole is etched away in a direction parallel to the substrate 10 until the semiconductor layer covered by the oxide layer 81 is exposed.

[0153] Next, refer to Figures 1 - 4 、 Figure 31 , the semiconductor layer 30a connected to the oxide layer 81 and the semiconductor layer 30a connected to it in the circumferential direction are etched away, and the semiconductor layer 30a is cut along a direction perpendicular to the substrate 10 to form a plurality of semiconductor channels 30 arranged at intervals along the third direction D3.

[0154] Each semiconductor channel 30 includes a first end 31 and a second end 32 oppositely disposed along a first direction D1. The region of the semiconductor channel 30 other than the first end 31 and the second end 32 is covered by an oxide insulating portion 40.

[0155] In some embodiments, the first end 31 and the second end 32 of the semiconductor channel 30 are respectively used to contact and connect to the source or the drain of the transistor, thereby forming a transistor in the semiconductor structure.

[0156] In the manufacturing method of the semiconductor structure according to some embodiments of the present disclosure, by forming the oxide insulating portion 40, the outer peripheral surface of the semiconductor channel 30 other than the first end 31 and the second end 32 is covered by the oxide insulating portion 40, preventing the semiconductor channel 30 from contacting the nitride layer 82, avoiding the material of the nitride layer 82 from capturing charges and affecting the electrical transport ability of the semiconductor channel 30, and avoiding affecting the performance of the transistor, thereby improving the electrical performance of the semiconductor structure.

[0157] In some embodiments of the present disclosure, the first end 31 of the semiconductor channel 30 is in contact connection with the first electrode 51 of the capacitor 50; the second end 32 of the semiconductor channel 30 is in contact connection with the bit line 70. While forming the channel hole in step S120, step S1200 is also executed:

[0158] Step S1200: Form a capacitor hole. The capacitor hole and the channel hole are spaced along the first direction, and the capacitor hole penetrates the stacked structure in a direction perpendicular to the substrate.

[0159] In some embodiments of the present disclosure, with reference to Figure 18 、 Figure 19 As shown, after forming the channel hole 91 in step S120 and the capacitor hole 93 in step S1200, before removing a part of the nitride layer 82 around the channel hole 91 in step S130, the following steps are also executed:

[0160] Step S100: Fill a first dielectric layer in the channel hole.

[0161] Exemplarily, the material of the first dielectric layer 122 includes polysilicon.

[0162] In some embodiments, with reference to Figure 21 , while filling the first dielectric layer 122 in the channel hole 91, the first dielectric layer 122 is also filled in the channel hole 92.

[0163] Step S101: Along the first direction, form a first etching groove on the side of the channel hole away from the capacitor. The first etching groove and the channel hole are spaced apart, and the first etching groove extends along a second direction.

[0164] The graphical stack structure 80 forms a first etching groove (not shown in the figure) that vertically penetrates the stack structure 80 along the third direction D3. Along the first direction D1, the first etching groove is disposed on a side of the channel hole 91 away from the capacitor hole 92, and the first etching groove and the channel hole 91 are spaced apart.

[0165] Step S102: Based on the first etching groove, etch and remove a part of the nitride layer until reaching the channel hole to form a bit line groove along the second direction.

[0166] Referring to Figures 1 - 4 、 Figure 10 , etch the nitride layer 82 exposed by the first etching groove until the first dielectric layer 122 located in the channel hole 91 is exposed, and then stop etching. A bit line groove (not shown in the figure) is formed on a side of the channel hole 91 away from the capacitor hole 92. The bit line groove extends along the second direction D2 and is spaced apart along the third direction D3 perpendicular to the substrate 10.

[0167] Step S103: Form a bit line in the bit line groove. The bit line extends along the second direction and is in contact connection with the second end of the semiconductor channel.

[0168] Referring to Figures 1 - 4 、 Figure 10 , deposit a conductive material to fill the bit line groove, and form a bit line 70 in the bit line groove. The bit line 70 extends along the second direction D2 and is spaced apart along the direction perpendicular to the substrate 10. Exemplarily, the material of the bit line 70 can be selected from metal materials such as cobalt (Co), titanium (Ti), tungsten (W), tantalum (Ta), titanium nitride (TiN), tantalum titanium (TaTi), tungsten nitride (WN), etc.

[0169] The bit line 70 covers a part of the first dielectric layer 122 in the channel hole 91 on a side away from the capacitor hole 92 (referring to Figure 3 、 Figure 4 、 Figure 19 ). In this way, the bit line 70 is in contact connection with the second end 32 of the semiconductor channel 30 formed subsequently in the channel hole 91.

[0170] After forming the bit line 70, etch and remove the conductive material in the first etching groove to disconnect the multiple bit lines 70 along the direction perpendicular to the substrate 10.

[0171] Fill the first etching groove with an insulating material, which can include filled silicon oxide or silicon nitride. This avoids the electrical conduction short circuit of adjacent bit lines 70 in the semiconductor structure and improves the reliability of the performance of the semiconductor structure.

[0172] Step S104: Based on the capacitor hole, etch and remove a part of the nitride layer until reaching the channel hole to form a fourth groove.

[0173] First, referring to Figure 3 、Figure 4 , Figure 19 , Figure 21 , etch and remove the first dielectric layer 122 in the capacitor hole 92 to expose the capacitor hole 92, and the sidewalls of the capacitor hole 92 expose a part of the oxide layer 81 and a part of the nitride layer 82.

[0174] Then, use a wet etching process to etch the nitride layer 82 exposed in the capacitor hole 92, and stop etching after exposing the first dielectric layer 122 in the channel hole 91, and form a fourth groove (not shown in the figure) on the sidewall of the capacitor hole 92. The radial dimension of the fourth groove is larger than the radial dimension of the capacitor hole 92.

[0175] Step S105: Form a first electrode in the fourth groove, and the first electrode is in contact connection with the first end of the semiconductor channel.

[0176] Refer to Figure 3 , Figure 4 , the first electrode 51 can fill the fourth groove or the first electrode 51 can only cover the groove wall of the fourth groove. The first electrode 51 covers the first dielectric layer 122 exposed on the side of the channel hole 91 close to the capacitor hole 92, so that the first electrode 51 is in contact connection with the first end 31 of the semiconductor channel 30 formed in the channel hole 91 subsequently.

[0177] The material of the first electrode 51 can include high melting point metals, such as at least one of cobalt (Co), titanium (Ti), nickel (Ni), tungsten (W), and / or molybdenum (Mo); alternatively, the material of the first electrode 51 can also include metal nitrides, such as titanium nitride, titanium silicon nitride, titanium aluminum nitride, tantalum nitride, tantalum silicon nitride, tantalum aluminum nitride, and / or tungsten nitride.

[0178] Step S106: Sequentially form a dielectric layer covering the first electrode and a second electrode covering the dielectric layer and filling the capacitor hole in the capacitor hole.

[0179] Refer to Figure 3 , Figure 4 , deposit and form a dielectric layer 52 by atomic layer deposition process. The dielectric layer 52 covers the first electrode 51 and the exposed sidewalls of the capacitor hole 92. The material of the dielectric layer 52 can include at least one of strontium titanate (SrTiO3), aluminum oxide (Al2O3), zirconium oxide (ZrO), or hafnium oxide (HfO2).

[0180] Refer to Figure 3 , Figure 4 , a second electrode 53 can be deposited and formed by chemical vapor deposition process or atomic layer deposition process. The second electrode 53 covers the dielectric layer 52 and fills the capacitor hole 92 and the unfilled area of the fourth groove.

[0181] In some embodiments, forming the second electrode 53 includes first forming a first sub-electrode 531 of the second electrode 53. The first sub-electrode 531 of the second electrode 53 covers the dielectric layer 52, and then forming a second sub-electrode 532 of the second electrode 53, which covers the first sub-electrode 531 of the second electrode 53 and fills the capacitor via 92, improving the proportion of the second electrode 53 of the capacitor 50, enhancing the storage capacity of the capacitor 50, and thus improving the storage performance of the semiconductor structure.

[0182] In some embodiments, after forming the bit line 70 and the capacitor 50, a wet etching process is used to etch and remove the first dielectric layer 122 in the channel hole 91, exposing the channel hole 91.

[0183] Refer to Figure 10 、 Figure 11 As shown, along the first direction D1, one side of the channel hole 91 exposes a part of the first electrode 51 of the capacitor 50, and the other side of the channel hole 91 exposes a part of the bit line 70. Then, steps S130 - S160 are performed based on the structure after forming the capacitor 50, the bit line 70, and removing the first dielectric layer 122 in the channel hole 91.

[0184] Thus, in the semiconductor structure formed in some embodiments of the present disclosure, the first end 31 of the semiconductor channel 30 is in contact connection with the first electrode 51 of the capacitor 50. A part of the first electrode 51 of the capacitor 50 serves as the source or drain of the transistor. The second end 32 of the semiconductor channel 30 is in contact connection with the bit line 70. A part of the structure of the bit line 70 serves as the drain or source of the transistor. The word line 20 covered by the semiconductor channel 30 serves as the gate of the transistor. The source, drain, gate, and the semiconductor channel 30 together form a transistor. The region of the semiconductor channel 30 of the transistor other than the first end 31 and the second end 32 is covered by the oxide insulating portion 40, preventing the semiconductor channel 30 from contacting the nitride layer 82, avoiding the material of the nitride layer 82 capturing charges and affecting the electrical transmission ability of the semiconductor channel 30, and avoiding affecting the performance of the transistor, thereby improving the electrical performance of the semiconductor structure.

[0185] The transistor and the capacitor connected thereto form a storage cell. In the manufacturing method of the semiconductor structure of this embodiment, the storage cells arranged in the same layer are separated by the oxide insulating portion, and the storage cells in different layers are separated by the oxide layer, further improving the electrical isolation effect of the storage cells in the semiconductor structure.

[0186] Some exemplary embodiments of the present disclosure provide a method for manufacturing a semiconductor structure, as Figure 9 shown, including the following steps:

[0187] Step S210: Provide a substrate, and alternately form an oxide layer and a nitride layer on the substrate to form a stacked structure.

[0188] The steps of providing the substrate 10 in step S210 and step S110 in the above embodiments and forming the stacked structure 80 are the same, and will not be described again.

[0189] Step S220: Form a channel hole, which is perpendicular to the substrate and penetrates the stacked structure.

[0190] The stacked structure 80 can be patterned, and the stacked structure 80 is etched to form a channel hole 91 that penetrates the stacked structure 80 along the third direction D3.

[0191] In some embodiments, as Figure 18 、 Figure 19 shown, referring to Figures 5 - 7 , while forming the channel hole 91 in step S220, step S2200 is executed: forming a capacitor hole 92, the capacitor hole 92 and the channel hole 91 are arranged at intervals along the first direction D1, and the capacitor hole 92 penetrates the stacked structure 80 along a direction perpendicular to the substrate 10.

[0192] Step S230: Etch the oxide layer exposed by the channel hole to form a third groove, and along a direction parallel to the substrate, the third groove extends away from the channel hole.

[0193] As Figure 20 shown, referring to Figure 19 , an etching process with a high etching selectivity for the nitride layer 82 is selected to etch the oxide layer 81 exposed by the channel hole 91, remove a part of the oxide layer 81 around the channel hole 91, and form a third groove 913 connected to the channel hole 91. The third groove 913 extends away from the channel hole 91 along a direction parallel to the substrate 10.

[0194] It can be understood that during the process of etching the oxide layer 81, by controlling the etching time and process parameters, the size of the third groove 913 is controlled to ensure that the third groove 913 and the capacitor hole 92 are separated by the oxide layer 81 remaining after etching, so as to avoid affecting the execution of subsequent manufacturing steps.

[0195] Step S240: Form a first dielectric layer, and the first dielectric layer fills the channel hole and the third groove.

[0196] As Figure 21 、 Figure 22 shown, referring to Figure 18 、 Figure 20 , the first dielectric layer 122 can be deposited, and the first dielectric layer 122 fills the channel hole 91 and the third groove. Exemplarily, the material of the first dielectric layer 122 includes polysilicon.

[0197] In some embodiments, the first dielectric layer 122 also fills the capacitor hole 92.

[0198] In some embodiments, the process of forming the capacitor 50 and the bit line 70 is performed between step S240 and step S250. The steps of forming the capacitor 50 and the bit line 70 are as described above and will not be elaborated here. Refer to Figure 23 As shown, along the first direction D1, the capacitor 50 is disposed on one side of the channel hole 91, and the bit line 70 is formed on the side of the channel hole 91 away from the capacitor 50.

[0199] Step S250: Remove a part of the nitride layer around the channel hole.

[0200] In some embodiments of the present disclosure, removing a part of the nitride layer around the channel hole includes:

[0201] Step S251: Along the second direction, first through-holes are respectively formed on both sides of the channel hole, and the first through-holes and the channel hole are spaced apart, and the first through-holes vertically penetrate the stacked structure.

[0202] As Figure 24 shown, refer to Figure 23 , perform patterning etching on the stacked structure 80 according to the arrangement of the channel holes 91 to form first through-holes 101 that penetrate the stacked structure 80 in a direction perpendicular to the substrate 10 (refer to Figure 5 ).

[0203] Step S252: Etch and remove a part of the nitride layer based on the first through-hole to expose the first dielectric layer covered by the nitride layer.

[0204] As Figure 25 shown, refer to Figure 24 , etch the nitride layer 82 based on the first through-hole 101 to remove the nitride layer 82 around the channel hole 91 until the first dielectric layer 122 covered by the nitride layer 82 in the channel hole 91 is exposed.

[0205] Exemplarily, a wet process can be used to etch the nitride layer 82.

[0206] Step S260: Form an oxide insulating portion at the position where the nitride layer is removed.

[0207] As Figure 26 shown, Figure 27 shown, refer to Figure 25 , deposit an oxide insulating layer 40a, and the oxide insulating layer 40a covers the exposed surface of the first dielectric layer 122 and fills the position where the nitride layer 82 is removed and the first through-hole 101.

[0208] Step S270: Remove the first dielectric layer in the channel hole and retain the first dielectric layer in the third groove.

[0209] As Figure 28 shown, Figure 29 shown, refer toFigure 26 As shown Figure 27 , an anisotropic etching process is used to etch the first dielectric layer 122 in the channel hole 91 along a third direction D3 perpendicular to the substrate 10 (refer to Figure 5 ). The etching rate of the etching process along the third direction D3 is much greater than the etching rate along the direction parallel to the substrate 10, so as to etch and remove the first dielectric layer 122 in the channel hole 91, while retaining the first dielectric layer 122 in the third groove 913.

[0210] Exemplarily, the first dielectric layer 122 in the channel hole 91 can be removed by plasma etching.

[0211] Step S280: A semiconductor layer and a word line are sequentially formed in the channel hole. The semiconductor layer covers the oxide insulating portion and the hole wall of the channel hole, and the word line covers the inner wall of the semiconductor layer and fills the channel hole.

[0212] As Figure 30 shown Figure 31 shown, refer to Figure 28 shown Figure 29 , the semiconductor layer 30a covers the device structures disposed on both sides of the channel groove 91 along the first direction D1, the oxide insulating portion 40, and the first dielectric layer 122 in the third groove 913 (refer to Figure 20 ). Exemplarily, the material of the semiconductor layer 30a includes indium gallium zinc oxide.

[0213] The word line 20 covers the semiconductor layer and fills the unfilled area of the channel groove 91. Exemplarily, the material of the word line 20 includes tungsten metal.

[0214] In some embodiments, as Figure 30 , Figure 31 shown, before forming the word line 20, a gate dielectric layer 21 and a diffusion barrier layer 22 are sequentially formed. The gate dielectric layer 21 covers the semiconductor layer 30a, the word line 20 is separated from the semiconductor layer 30a by the gate dielectric layer 21, and the diffusion barrier layer 22 covers the gate dielectric layer 21.

[0215] The diffusion barrier layer 22 is disposed between the gate dielectric layer 21 and the word line 20, and is used to block the diffusion of elements in the word line 20 into other device structures, avoiding the risk of short - circuit between device structures, and improving the electrical performance and reliability of the semiconductor structure.

[0216] Step S290: Etch and remove the semiconductor layer covered by the oxide layer, and the remaining semiconductor layer forms at least one semiconductor channel. Each semiconductor channel includes a first end and a second end disposed opposite to each other along the first direction. The peripheral surface of the semiconductor channel except the first end and the second end is covered by the oxide insulating portion.

[0217] In some embodiments, etching to remove the semiconductor layer covered by the oxide layer includes:

[0218] Step S291: Form a second through-hole perpendicular to the substrate and close to the channel hole, and the second through-hole exposes the first dielectric layer in the third groove.

[0219] As Figure 32 shown, referring to Figure 31 , after patterning to form the word line 20, remove a part of the nitride layer 82 and the oxide layer 81 around the channel hole 91; or, remove a part of the oxide insulating portion 40 and a part of the oxide layer 81 around the channel hole 91 to form a second through-hole 102 perpendicular to the substrate 10 (refer to Figure 5 ).

[0220] Along the direction parallel to the substrate 10 (refer to Figure 5 ), the second through-hole 102 exposes a part of the first dielectric layer 122 covering the semiconductor layer 30a, and the second through-hole 102 and the semiconductor layer 30a in the channel hole 91 are arranged separately to avoid damaging the semiconductor layer 102 during the formation of the second through-hole 102 and ensure the structural integrity of the formed semiconductor structure.

[0221] Step S292: Etch and remove the first dielectric layer in the third groove, and etch the semiconductor layer covered by the first dielectric layer in the third groove.

[0222] As Figure 33 shown, referring to Figure 32 , etch the first dielectric layer 122 exposed by the second through-hole 102 to completely etch and remove the first dielectric layer 122 in the third trench 913 (refer to Figure 19 ), exposing the semiconductor layer 30a covered by the first dielectric layer 122 in the third trench 913. Then, completely etch and remove the semiconductor layer 30a covered by the first dielectric layer 122. Referring to Figures 5 - 7 shown, the remaining semiconductor layer 30a forms semiconductor channels 30 arranged at intervals along the third direction D3 (refer to Figure 5 ), and the peripheral surface of the semiconductor channels 30 except for the first end 31 and the second end 32 is covered by the oxide insulating layer portion 40, and the oxide insulating portions 40 arranged along the second direction D2 are sequentially connected to form an oxide insulating layer 40a.

[0223] In some embodiments, referring to Figures 5 - 7As shown, after the semiconductor channel 30 is formed, an insulating material is deposited to fill the second through hole 201 and the area where the first dielectric layer 122 and the semiconductor layer 30a are removed. Exemplarily, the insulating material includes silicon oxide, so that the memory cells arranged in the same layer are separated by the oxide, and the memory cells in different layers are also separated by the oxide, further improving the electrical isolation effect of the memory cells in the semiconductor structure, avoiding the insulating material from capturing charges and affecting the electrical transmission ability of the semiconductor channel 30 and having an adverse effect on the semiconductor structure, thereby improving the electrical performance and reliability of the semiconductor structure.

[0224] In some embodiments of the present disclosure, after step S240 and before step S250, the process of forming the capacitor 50 and the bit line 70 is performed. The steps of forming the capacitor 50 and the bit line 70 include:

[0225] Step S201: Along the first direction, a first etching groove is formed on the side of the channel hole away from the capacitor. The first etching groove and the channel hole are arranged at intervals, and the first etching groove extends along the second direction.

[0226] Step S202: Based on the first etching groove, a part of the nitride layer is etched away until the channel hole is reached, and a bit line groove extending along the second direction is formed.

[0227] Step S203: A bit line is formed in the bit line groove. The bit line extends along the second direction and is in contact connection with the second end of the semiconductor channel.

[0228] Step S204: Based on the capacitor hole, a part of the nitride layer is etched away until the channel hole is reached, and a fourth groove is formed.

[0229] Step S205: A first electrode is formed in the fourth groove. The first electrode is in contact connection with the first end of the semiconductor channel.

[0230] Step S206: A dielectric layer covering the first electrode and a second electrode covering the dielectric layer and filling the capacitor hole are sequentially formed in the capacitor hole.

[0231] The implementation manners of steps S201 - S203 are the same as those of steps S101 - S106 in the above embodiments, and will not be elaborated here. Refer to Figures 5 - 7 As shown, in the semiconductor structure formed in some embodiments of the present disclosure, the first end 31 of the semiconductor channel 30 is in contact connection with the first electrode 51 of the capacitor 50, the second end 32 of the semiconductor channel 30 is in contact connection with the bit line 70, and the peripheral surface of the semiconductor channel 30 except for the first end 31 and the second end 32 is covered by the oxide insulating portion 40.

[0232] The method for manufacturing a semiconductor structure according to some embodiments of the present disclosure forms first vias on both sides of a channel hole along a second direction, and based on the first vias, a nitride layer covering a first dielectric layer in the channel hole is removed from the outside of the channel hole. The process of removing the nitride layer does not damage the shape of the channel hole. Thus, the shape of the channel hole is closer to a perfect circle, and the orthographic projection of the semiconductor channel formed in the channel hole on the substrate is closer to a perfect circle. The semiconductor channel has almost no obvious corners or has gentle corners, which can avoid charge accumulation at the corners of the semiconductor channel and affect the electrical performance of the semiconductor structure.

[0233] The technical features of the above-described embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features of the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope described in this specification.

[0234] The above-described embodiments merely represent several implementation manners of the present disclosure. The description is relatively specific and detailed, but it should not be construed as a limitation on the scope of the patent application. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present disclosure, several modifications and improvements can still be made, and these all belong to the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure patent shall be subject to the appended claims.

Claims

1. A semiconductor structure, characterized in that, Comprising: A substrate; Word lines, vertically disposed on the substrate; At least one semiconductor channel, spaced along a direction perpendicular to the substrate, each semiconductor channel surrounding and covering a partial circumferential surface of the word line, along a first direction parallel to the substrate, each semiconductor channel including a first end and a second end disposed opposite to each other; At least one oxide insulating portion, spaced along a direction perpendicular to the substrate, at least one of the oxide insulating portions and at least one of the semiconductor channels being disposed in a one-to-one correspondence, each oxide insulating portion covering a circumferential surface of its corresponding semiconductor channel except for the first end and the second end.

2. The semiconductor structure according to claim 1, wherein The length of the semiconductor channel in the first direction is less than the length of the semiconductor channel in a second direction, the second direction being parallel to the substrate, and the first direction and the second direction intersect.

3. The semiconductor structure according to claim 2, wherein Each of the oxide insulating portions includes a first portion and a second portion disposed opposite to each other on both sides of the semiconductor channel along the second direction.

4. The semiconductor structure according to claim 1, wherein Along the second direction, an oxide insulating layer is formed between adjacent semiconductor channels, and the oxide insulating layer is respectively connected to the oxide insulating portions corresponding to the adjacent semiconductor channels, the second direction being parallel to the substrate, and the first direction and the second direction intersect.

5. The semiconductor structure according to claim 1, wherein The semiconductor structure further comprises: A capacitor, disposed on one side of the semiconductor channel along the first direction, the capacitor including a first electrode, a dielectric layer, and a second electrode, the second electrode being vertically disposed on the substrate, the first electrode being disposed on the outer periphery of the second electrode, the first electrode being in contact connection with the first end, and the dielectric layer being disposed between the first electrode and the second electrode; A bit line, disposed on the side of the semiconductor channel away from the capacitor along the first direction, the bit line extending along the second direction, and the bit line being in contact connection with the second end.

6. The semiconductor structure according to claim 5, wherein, The semiconductor structure further comprises an oxide layer and a nitride layer, the oxide layer and the nitride layer being alternately disposed on the substrate, the semiconductor channel, the capacitor, and the bit line being disposed in the nitride layer, and the semiconductor channel being separated from the nitride layer by the oxide insulating portion; Along a direction perpendicular to the substrate, the oxide layer covers the word line located between adjacent semiconductor channels.

7. An electronic device, characterized in that, Comprising the semiconductor structure according to any one of claims 1-6.

8. A method for fabricating a semiconductor structure, characterized in that, Comprising the following steps: Providing a substrate, alternately forming an oxide layer and a nitride layer on the substrate to form a stacked structure; Forming a channel hole, the channel hole being perpendicular to the substrate and penetrating through the stacked structure; Removing a part of the nitride layer around the channel hole; Forming an oxide insulating portion at the position where the nitride layer is removed; Sequentially forming a semiconductor layer and a word line in the channel hole, the semiconductor layer covering the oxide insulating portion and the inner wall of the channel hole, and the word line covering the inner wall of the semiconductor layer and filling the channel hole; Etch away the semiconductor layer covered by the oxide layer, and the remaining semiconductor layer forms at least one semiconductor channel. Each semiconductor channel includes a first end and a second end oppositely arranged in a first direction, and the peripheral surface of the semiconductor channel except the first end and the second end is covered by the oxide insulating portion.

9. The method for manufacturing a semiconductor structure according to claim 8, wherein, Remove a part of the nitride layer around the channel hole, including: Etch the nitride layer exposed by the channel hole, and form a relatively arranged first groove and a second groove on both sides of the channel hole along a second direction. The first direction and the second direction are parallel to the substrate, and the first direction intersects with the second direction. The oxide insulating portion includes a first part formed in the first groove and a second part formed in the second groove, and the oxide insulating portion exposes the hole wall of the channel hole between the first groove and the second groove.

10. The manufacturing method of the semiconductor structure according to claim 9, wherein, After forming a relatively arranged first groove and a second groove on both sides of the channel hole along the second direction, the size of the channel hole in the nitride layer in the first direction is smaller than the size of the channel hole in the second direction.

11. The method for fabricating a semiconductor structure according to claim 10, wherein Form an oxide insulating portion at the position where the nitride layer is removed, including: Form an oxide insulating layer, and the oxide insulating layer covers the groove walls of the first groove, the groove walls of the second groove, and the exposed hole wall of the channel hole. Form a protective layer, and the protective layer covers the oxide insulating layer. Etch away the protective layer covering the hole wall of the channel hole. Etch the oxide insulating layer using the remaining protective layer as a mask, and etch away the oxide insulating layer covering the hole wall of the channel hole. The oxide insulating layer in the first groove and the second groove is formed as the oxide insulating portion.

12. The method for manufacturing a semiconductor structure according to claim 8, wherein, After forming the channel hole, including: Etch the oxide layer exposed by the channel hole, remove a part of the oxide layer, and form a third groove. Along the direction parallel to the substrate, the third groove extends away from the channel hole. Form a first dielectric layer, and the first dielectric layer fills the channel hole and the third groove.

13. The manufacturing method of the semiconductor structure according to claim 12, wherein, Remove a part of the nitride layer around the channel hole, including: Along the second direction, form first through holes on both sides of the channel hole respectively, and the first through holes and the channel hole are spaced apart. The first through holes vertically penetrate the stacked structure. Based on the first through holes, etch away a part of the nitride layer to expose the first dielectric layer covered by the nitride layer.

14. The method for manufacturing a semiconductor structure according to claim 13, wherein, Form an oxide insulating portion at the position where the nitride layer is removed, including: Deposit an oxide insulating layer, and the oxide insulating layer covers the exposed surface of the first dielectric layer and fills the position where the nitride layer is removed and the first through holes to form the oxide insulating portion.

15. The method for manufacturing a semiconductor structure according to claim 14, wherein, Before sequentially forming a semiconductor layer and a word line in the channel hole, remove the first dielectric layer in the channel hole and retain the first dielectric layer in the third groove.

16. The method for fabricating a semiconductor structure according to claim 15, wherein Etch away the semiconductor layer covered by the oxide layer, including: A second through hole perpendicular to the substrate is formed, and the second through hole is disposed close to the channel hole, and the first dielectric layer in the third groove is exposed by the second through hole; The first dielectric layer in the third groove is etched away, and the semiconductor layer covered by the first dielectric layer in the third groove is etched.

17. The method for fabricating a semiconductor structure according to claim 9 or 12, wherein The manufacturing method further includes: A capacitor hole is formed, the capacitor and the channel hole are spaced along the first direction, and the capacitor hole penetrates the stacked structure in a direction perpendicular to the substrate; Based on the capacitor hole, a part of the nitride layer is etched away until the channel hole is reached to form a fourth groove; A first electrode is formed in the fourth groove, and the first electrode is in contact connection with the first end of the semiconductor channel; A dielectric layer covering the first electrode and a second electrode covering the dielectric layer and filling the capacitor hole are sequentially formed in the capacitor hole.

18. The method for fabricating a semiconductor structure according to claim 17, wherein, The manufacturing method further includes: A first etching groove is formed on one side of the channel hole away from the capacitor along the first direction, the first etching groove and the channel hole are spaced apart, and the first etching groove extends in the second direction; Based on the first etching groove, a part of the nitride layer is etched away until the channel hole is reached to form a bit line groove in the second direction; A bit line is formed in the bit line groove, the bit line extends in the second direction and the bit line is in contact connection with the second end of the semiconductor channel.

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