Semiconductor device and preparation method thereof, and memory system
By setting spacers between adjacent gate lines of DRAM and transferring the word line decoder into the core area, the problem of excessive volume in three-dimensional integrated DRAM is solved, further compression and process simplification of semiconductor devices are achieved.
Patent Information
- Application Number
- CN202410041740.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-01-10
- Publication Date
- 2025-07-11
AI Technical Summary
In three-dimensional integrated DRAM, how to reduce the volume of the memory cell is an urgent problem.
By providing a first spacer between two adjacent gate lines in the adjacent first core area and the second core area, the first spacer is connected to the first gate line and the second gate line respectively, the number of spacers between the gate lines of the adjacent first core area and the second core area is reduced, and the word line decoder is transferred from the connection area to the core area.
The spacer occupancy area is reduced, which is conducive to further compression of the semiconductor device volume, reduces the difficulty of process wiring, and simplifies the production process.
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Figure CN120302634A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the technical field of semiconductor devices, and particularly to a semiconductor device, a manufacturing method thereof, and a memory system. Background Art
[0002] Transistors in semiconductor structures are widely used as switching devices or driving devices in integrated circuits. For example, a memory cell of a Dynamic Random Access Memory (DRAM) may include a transistor and a capacitor structure, and data writing or reading of the capacitor structure is controlled by the transistor.
[0003] However, in a three-dimensional integrated DRAM, a transistor and a capacitor structure form a memory cell. In the manufacturing process, how to reduce the volume of the DRAM is an urgent problem to be solved currently. Summary of the Invention
[0004] In view of this, this application provides a semiconductor device, a manufacturing method thereof, and a memory system that can solve the above technical problems.
[0005] To solve the above problems, the technical solutions provided in this application are as follows:
[0006] This application provides a semiconductor device, including a first semiconductor structure; the first semiconductor structure includes a first core region, a second core region, and a first connection region located between the first core region and the second core region; the first semiconductor structure further includes:
[0007] A first gate line group, located in the first core region and including a first gate line extending along a first direction;
[0008] A second gate line group, located in the second core region and including a second gate line extending along the first direction; and
[0009] A first spacer, located in the first connection region;
[0010] Wherein, the first spacer is respectively connected to the first gate line and the second gate line, and the first gate line and the second gate line are spaced apart by the first spacer.
[0011] In some embodiments, the first gate line group further includes a third gate line located on one side of the first gate line, and the second gate line group further includes a fourth gate line located on one side of the second gate line;
[0012] The third gate line is connected to the fourth gate line.
[0013] In some embodiments, the first semiconductor structure further includes a first lead contact, and the third gate line and the fourth gate line are respectively connected to the first lead contact.
[0014] In some embodiments, the first lead contact is located in the first connection area and is adjacent to the first spacer.
[0015] In some embodiments, a part of the first lead contacts is located within the first spacer, and another part of the first lead contacts is located outside the first spacer.
[0016] In some embodiments, the first semiconductor structure further includes a second spacer, the second spacer is located in the first core area and away from the first spacer, the first gate line and the third gate line in the first gate line group are respectively connected to the second spacer, and the first gate line and the third gate line are spaced apart by the second spacer.
[0017] In some embodiments, the third gate line and the fourth gate line extend along the first direction respectively;
[0018] The first gate line and the third gate line are spaced apart along a second direction perpendicular to the first direction, and the second gate line and the fourth gate line are spaced apart along the second direction;
[0019] Multiple first gate line groups and multiple second gate line groups are spaced apart along the second direction respectively.
[0020] In some embodiments, two third gate lines or two first gate lines of two adjacent first gate line groups in the second direction are adjacent to each other;
[0021] Two fourth gate lines or two second gate lines of two adjacent second gate line groups in the second direction are adjacent to each other.
[0022] In some embodiments, two adjacent second gate lines of two second gate line groups and two adjacent first gate lines of two first gate line groups are respectively connected to the same first spacer.
[0023] In some embodiments, two adjacent third gate lines are connected to the same second spacer.
[0024] In some embodiments, the third gate line of the first gate line group is adjacent to the first gate line of another first gate line group adjacent to the first gate line group;
[0025] The fourth gate line of the second gate line group is adjacent to the second gate line of another second gate line group adjacent to the second gate line group.
[0026] In some embodiments, the second gate line of a second gate line group and the first gate line of a first gate line group are spaced apart by a first spacer.
[0027] In some embodiments, the first gate line and the third gate line in a first gate line group are spaced apart by a second spacer.
[0028] In some embodiments, the first semiconductor structure further includes a second connection region located on a side of the first core region away from the first connection region;
[0029] The first semiconductor structure further includes a second lead contact located in the second connection region, and the second lead contact is disposed adjacent to the second spacer;
[0030] One end of the first gate line away from the first spacer is connected to the second lead contact.
[0031] In some embodiments, the first semiconductor structure further includes a semiconductor pillar group located in the first core region and the second core region. Each semiconductor pillar group includes a plurality of semiconductor pillars arranged along a first direction; the first gate line group is located between two adjacent semiconductor pillar groups in the first core region, and the second gate line group is located between two adjacent semiconductor pillar groups in the second core region.
[0032] In some embodiments, there are at least two semiconductor pillar groups between two adjacent first gate line groups in a second direction and / or between two adjacent second gate line groups in the second direction;
[0033] The first semiconductor structure further includes a shielding layer, and the shielding layer extends along the first direction and is located between two adjacent semiconductor pillar groups.
[0034] In some embodiments, there is a first spacer and a first lead contact between two adjacent first gate line groups in the first direction; and / or when the number of second core regions is multiple, there is a first spacer and a first lead contact between two adjacent second gate line groups in the first direction.
[0035] In some embodiments, the semiconductor device further includes a second semiconductor structure, and the second semiconductor structure includes a word line decoder corresponding to the first core region and / or the second core region;
[0036] The second semiconductor structure is bonded and connected to the first semiconductor structure in a third direction perpendicular to the first direction, and the first lead contact is connected to the word line decoder.
[0037] In some embodiments, one first lead contact is connected to one word line decoder.
[0038] The present application also provides a method for manufacturing a semiconductor device, including:
[0039] Providing a semiconductor structure including a first core region, a second core region and a first connection region, the semiconductor structure including a plurality of initial semiconductor pillars spaced apart along a first direction;
[0040] Form a plurality of first trenches extending in a first direction and distributed in a second direction perpendicular to the first direction on a semiconductor structure, and the first trenches divide an initial semiconductor column into a plurality of semiconductor columns;
[0041] Form a gate layer in the first trenches; and
[0042] Form a first spacer in a first connection region, and the first spacer divides a part of the gate layer into a first gate line and a second gate line to obtain a first semiconductor structure; wherein, the first gate line and the second gate line are located on the same straight line, the first spacer is respectively connected to the first gate line and the second gate line, and the first gate line and the second gate line are spaced apart by the first spacer.
[0043] In some embodiments, in the process of forming a first spacer in a first connection region and dividing a part of the gate layer into a first gate line and a second gate line to obtain a first semiconductor structure, it further includes:
[0044] Form a second spacer at a position in a first core region and away from the first spacer, and the second spacer divides another part of the gate layer into a third gate line and a fourth gate line; the third gate line is located on one side of the first gate line, the fourth gate line is located on one side of the second gate line, the first gate line and the third gate line are respectively connected to the second spacer, and the first gate line and the third gate line are spaced apart by the second spacer.
[0045] In some embodiments, after the steps of forming a first spacer in a first connection region and forming a second spacer in a first core region, it further includes:
[0046] Form a first lead contact at a position in the first connection region and adjacent to the first spacer, and connect the third gate line and the fourth gate line to the first lead contact respectively.
[0047] In some embodiments, the first gate line and the third gate line constitute a first gate line group, and the second gate line and the fourth gate line constitute a second gate line group;
[0048] In the process of forming a first lead contact at a position in the first connection region and adjacent to the first spacer, it further includes:
[0049] Form a second lead contact at a position at one end of the first gate line group away from the first spacer and adjacent to the second spacer, and connect one end of the first gate line away from the first spacer to the second lead contact.
[0050] In some embodiments, in the process of forming a plurality of first trenches extending in a first direction and distributed in a second direction perpendicular to the first direction on a semiconductor structure, it further includes:
[0051] Form a plurality of second trenches extending in a first direction and distributed in a second direction on a semiconductor structure, with one second trench located between two adjacent first trenches; the second trenches and the first trenches together divide an initial semiconductor column into a plurality of semiconductor columns;
[0052] During the process of forming a gate layer in the first trench, it further includes:
[0053] Form a shielding layer in the second trench.
[0054] In some embodiments, two adjacent second gate lines of two second gate line groups and two adjacent first gate lines of two first gate line groups are respectively connected to the same first spacer;
[0055] Two adjacent third gate lines arranged adjacent to each other are connected to the same second spacer.
[0056] In some embodiments, a second gate line of a second gate line group and a first gate line of a first gate line group are spaced apart by a first spacer;
[0057] A first gate line and a third gate line within a first gate line group are spaced apart by a second spacer;
[0058] Two adjacent first gate line groups in the second direction correspond to two first spacers and two second spacers.
[0059] In some embodiments, after the step of forming a first spacer in a first connection region, the first spacer divides the gate layer into a first gate line and a second gate line to obtain a first semiconductor structure, it further includes:
[0060] Bond and connect a second semiconductor structure including a word line decoder corresponding to the first core region and / or the second core region to the first semiconductor structure in a third direction perpendicular to the first direction, and a first lead contact is connected to the word line decoder.
[0061] This application also provides a memory system, including: at least one semiconductor device as described above; and a controller coupled to the semiconductor device and configured to control the semiconductor structure.
[0062] For the semiconductor device, its manufacturing method, and the memory system provided in some embodiments of this application, two adjacent first gate lines and second gate lines located in adjacent first core regions and second core regions are spaced apart by a first spacer, and the first spacer is respectively connected to the first gate line and the second gate line, so that the number of spacers between the gate lines of the adjacent first core region and the second core region is reduced, thereby reducing the occupied area of the spacers and facilitating further compression of the volume of the semiconductor device. Description of the Drawings
[0063] To more clearly illustrate the technical solutions in some embodiments of the present application, the following will briefly introduce the accompanying drawings required for the description of the embodiments. Obviously, the accompanying drawings in the following description are only some embodiments of the present application. For those skilled in the art, without creative efforts, other accompanying drawings can be obtained based on these drawings.
[0064] Figure 1 Schematic diagrams of a first semiconductor structure and a second semiconductor structure of a semiconductor device provided in some embodiments of the present application.
[0065] Figure 2 Process flow chart of a manufacturing method of a semiconductor device provided in some embodiments of the present application.
[0066] Figure 3 Top view of a semiconductor structure provided in some embodiments of the present application.
[0067] Figure 4 Is Figure 3 Cross-sectional view along III-III shown.
[0068] Figure 5 Is at Figure 3 Top view after forming a first groove and a second groove (with a mask) on the semiconductor structure shown.
[0069] Figure 6 Is to remove Figure 5 Top view after removing the mask shown.
[0070] Figure 7 Is Figure 2 Process flow chart of step S2 in the process flow chart shown.
[0071] Figure 8 Top view of a first semiconductor structure provided in some embodiments of the present application.
[0072] Figure 9 Is Figure 8 Partial enlarged view of the first semiconductor structure shown.
[0073] Figure 10 Top view of a first semiconductor structure provided in some other embodiments of the present application.
[0074] Figure 11 Is Figure 10 Partial enlarged view of the first semiconductor structure shown.
[0075] Figure 12 Module schematic diagram of a semiconductor device provided in some embodiments of the present application.
[0076] Figure 13 For Figure 12 the arrangement schematic diagram of the word line driver and bit line amplifier of the second semiconductor structure of the semiconductor device shown.
[0077] Figure 14 The module schematic diagram of the memory system provided by some embodiments of the present application. Specific embodiments
[0078] Next, the technical solutions in some embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in some embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative efforts fall within the protection scope of the present application.
[0079] In the description of the present application, it should be understood that the orientation or positional relationship indicated by terms such as "upper", "lower", etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus cannot be understood as a limitation to the present application. In addition, the terms "first" and "second" are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more features. In the description of the present application, "a plurality" means two or more, unless otherwise specifically defined.
[0080] In the description of the present application, it should be understood that the term "layer" refers to a part of a material including a region having a thickness. The layer can extend over the entire structure below or above, or can have a range smaller than the range of the structure below or above. In addition, the layer can be a region of a homogeneous or heterogeneous continuous structure with a thickness smaller than the thickness of the continuous structure. The layer can extend horizontally, vertically, and / or along an inclined surface. The layer can include multiple sub-layers. For example, an interconnect layer can include one or more conductor and contact sub-layers (wherein interconnect lines and / or via contacts are formed), and one or more dielectric sub-layers.
[0081] The present application may repeat reference numerals and / or reference letters in different embodiments. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or arrangements discussed.
[0082] Some embodiments of the present application provide a semiconductor device 4000, which is at least part of a DRAM memory and includes a semiconductor structure 1200 and a peripheral circuit 1300. The semiconductor structure 1200 includes a gate line group 1001 having at least one gate line and a plurality of connection contacts 1002. The semiconductor structure 1200 includes a plurality of core regions 1003 and a plurality of connection regions 1004 located on at least one side of the core regions 1003. The gate line group 1001 is located within the core regions 1003, and the connection contacts 1002 are located within the connection regions 1004. Both ends of a gate line group 1001 each have a connection contact 1002 connected to the gate line group 1001, and there are two connection contacts 1002 between two adjacent core regions 1003. The peripheral circuit 1300 includes a word line driver (WLD) 1301 and a bit line sense amplifier (BLSA) 1302. The word line driver 1301 is opposite to the connection region 1004 of the semiconductor structure 1200, and the bit line sense amplifier 1302 is opposite to the core region 1003 of the semiconductor structure 1200. The word line driver 1301 is connected to the connection contact 1002 of the semiconductor structure 1200( Figure 1 The dashed line between the connection contact 1002 and the word line driver 1301 in the figure indicates their connection).
[0083] For the semiconductor device as described above, since the word line driver 1301 is opposite to the connection region 1004 of the semiconductor structure 1200, there are two connection contacts 1002 arranged at intervals between two adjacent core regions 1003 of the semiconductor device. The two connection contacts 1002 occupy a large area, which is not conducive to further reducing the volume of the semiconductor device.
[0084] To address the technical problem that the volume of the semiconductor device cannot be further reduced, in the present application, two adjacent first gate lines and second gate lines respectively located in an adjacent first core region and second core region are spaced apart by a first spacer. The first spacer is respectively connected to the first gate line and the second gate line, so that the number of spacers between the gate lines of the adjacent first core region and second core region is reduced, thereby reducing the occupied area of the spacers and being conducive to further reducing the volume of the semiconductor device.
[0085] Next, in combination with Figures 2 to 13 , the specific manufacturing method of the semiconductor device, the specific structure of the semiconductor device, and the memory system will be specifically described.
[0086] Please refer to Figures 2 to 13 , the present application provides a manufacturing method of a semiconductor device, including:[[]]
[0087] Step S1: Please refer toFigures 2 to 4 An initial semiconductor structure 110 is provided, including a first core region 101, a second core region 102, and a first connection region 103. The initial semiconductor structure 110 includes a plurality of initial semiconductor pillars 10 that are spaced apart along a first direction X and extend along a second direction Y perpendicular to the first direction X.
[0088] Among them, the number of the first core regions 101 is 1 or 2, the number of the second core regions 102 is at least one, and the number of the first connection regions 103 is at least 1. The second core region 102 is located on one side of the first core region 101, and the first connection region 103 is located between the first core region 101 and the second core region 102.
[0089] In this embodiment, the number of the first core regions 101 is 2, the number of the second core regions 102 is 2, and the number of the first connection regions 103 is 2. The second core region 102 is located between the two first core regions 101, and the first connection region 103 is located between the first core region 101 and the second core region 102.
[0090] In some other embodiments, when the number of the second core regions 102 is multiple, the first connection region 103 is also located between two adjacent second core regions 102.
[0091] In some embodiments, the initial semiconductor structure 110 further includes a second connection region 111 located on a side of the first core region 101 away from the first connection region.
[0092] Among them, the initial semiconductor pillar 10 also extends along a third direction Z that is perpendicular to the first direction X and intersects the second direction Y.
[0093] In some embodiments, step S1 includes: First, providing a semiconductor substrate 104; Second, forming a plurality of spaced grooves 105 on the semiconductor substrate 104 that are spaced apart along the first direction X and extend along the second direction Y and the third direction Z, so as to divide the semiconductor substrate 104 into a plurality of initial semiconductor pillars 10, and two adjacent initial semiconductor pillars 10 are spaced apart by one spaced groove 105; Third, filling a dielectric layer 106 in the spaced groove 105 to obtain the initial semiconductor structure 110.
[0094] Among them, the material of the semiconductor substrate 104 includes at least one of single crystal silicon (Si), single crystal germanium (Ge), and silicon germanium (GeSi), etc. In this embodiment, the material of the semiconductor substrate 104 is single crystal silicon (Si).
[0095] In some embodiments, a spacer groove 105 is formed by disposing a mask template with a preset pattern (not shown in the figure) on the surface of the semiconductor substrate 104 and assisting processes such as dry or wet etching. There is also a hard-mask layer 107 between the mask template and the semiconductor substrate 104. After removing the mask template, a part of the hard-mask layer 107 remains at one end of the initial semiconductor pillar 10. In subsequent steps, the hard-mask layer 107 is also removed.
[0096] In some embodiments, the spacer groove 105 is a groove or a through groove. In this embodiment, the spacer groove 105 does not penetrate the semiconductor substrate 104. At this time, the initial semiconductor structure 110 includes, in addition to the initial semiconductor pillar 10, a connecting portion 108. A plurality of initial semiconductor pillars 10 are disposed on the connecting portion, and one end of each of the plurality of initial semiconductor pillars 10 is connected to the connecting portion 108. In other embodiments, when the spacer groove 105 is a through groove, the initial semiconductor structure 110 does not include a connecting portion.
[0097] In some embodiments, a first oxide layer 109 is further formed at one end of the initial semiconductor pillar 10. The first oxide layer 107 is located between the initial semiconductor pillar 10 and the hard-mask layer 107. Among them, the first oxide layer 107 is formed due to the oxidation of the surface of the semiconductor substrate 104 used.
[0098] In other embodiments, there may be no first oxide layer 109 at one end of the initial semiconductor pillar 10. The material of the first oxide layer 109 includes silicon oxide and the like.
[0099] Step S2: Please refer to Figure 2 , Figure 5 and Figure 6 , and a plurality of first trenches 20 extending along a first direction X and distributed along a second direction Y perpendicular to the first direction X are formed on the initial semiconductor structure 110. The first trenches 20 divide the initial semiconductor pillar 10 into a plurality of semiconductor pillars 30.
[0100] In some embodiments, step S2 further includes: forming a plurality of second trenches 203 extending along the first direction X and distributed along the second direction Y perpendicular to the first direction X on the initial semiconductor structure 110. The second trenches 203 are spaced apart from and alternately arranged with the first trenches 20.
[0101] In some embodiments, the depth of the first trench 20 in the third direction Z is greater than the depth of the second trench 203 in the third direction Z, and the size of the first trench 20 in the first direction X is greater than the size of the second trench 203 in the first direction X.
[0102] Please refer to Figures 5 to 8 , in some embodiments, the steps of forming the first trench 20 and the second trench 203 include:
[0103] Step S21: Refer to Figure 5 and Figure 7 , form a plurality of first grooves 201 arranged at intervals and extending along the first direction X and a plurality of second grooves 202 arranged at intervals and extending along the first direction X on the initial semiconductor structure 110. The first grooves 201 and the second grooves 202 are arranged at intervals and alternately.
[0104] Step S22: Refer to Figures 5 to 7 , divide the second groove 202 into a plurality of second trenches 203. Two adjacent second trenches 203 are arranged at intervals. The second trenches 203 correspond to the first core region 101 and the second core region 102 one by one.
[0105] Step S23, refer to Figure 7 and Figure 8 , fill sacrificial materials in the first grooves 201 and the second trenches 203. Then, remove the sacrificial materials in the first grooves 201, and expand the depth of the first grooves 201 in the third direction Z and the size in the first direction X through processes such as wet etching or dry etching to obtain the first trenches 20. Finally, remove the sacrificial materials in the second trenches 203.
[0106] In step S21, the first grooves 201 and the second grooves 202 are formed by double patterning technology.
[0107] In some embodiments, the depth of the first grooves 201 and the second grooves 202 in the third direction Z and the size in the first direction are the same.
[0108] In step S22, a partition groove 204 can be formed at the position where the second groove 202 is to be partitioned through a special mask plate, and an insulating dielectric material is filled in the partition groove 204 to divide the second groove 202 into a plurality of second trenches 203. The partition groove 204 is arranged corresponding to the first connection region 103 and the second connection region 111.
[0109] Among them, the special mask plate 205 is applicable to positive photoresist or negative photoresist. The positive photoresist copies the same pattern as on the mask plate onto the silicon wafer, and the negative photoresist copies the pattern opposite to that on the mask plate onto the silicon wafer. In this embodiment, the special mask plate 205 is applicable to negative photoresist.
[0110] In step S23, before the step of filling sacrificial materials in the first grooves 201 and the second trenches 203, it further includes the step of forming a second oxide layer (not shown in the figure) on the inner walls of the first grooves 201 and the second grooves 202 to repair the damage on the surface of the semiconductor pillar 30. The material of the second oxide layer can include silicon oxide, etc.
[0111] Step S3: Refer to Figure 2 and Figure 6 and Figure 8 , and form a gate layer 40 in the first trench 20.
[0112] Among them, the gate layer 40 extends along the first direction X and the third direction Z, and corresponds to the first core region 101, the first connection region 103, the second core region 102, and the second connection region 111.
[0113] Step S3 further includes: filling a shielding material in the second trench 203 to form a shielding layer 50, the shielding layer 50 extends along the first direction X and the third direction Z, and corresponds to the first core region 101 and the second core region 102.
[0114] In some embodiments, a gate insulating layer 401 is further formed on a side of the gate layer 40 away from the inner wall of the first trench 20, the gate layer 40 surrounds the gate insulating layer 401, and the gate layer 40 and the gate insulating layer 401 together fill the first trench 20.
[0115] In other embodiments, the gate layer 40 fills the first trench 20, and the gate insulating layer 401 does not exist.
[0116] In some embodiments, the constituent material of the gate layer 40 includes a conductive material, for example, single crystal silicon, polycrystalline silicon, doped single crystal silicon, doped polycrystalline silicon, tungsten, copper, aluminum, platinum, titanium, or ruthenium, etc. The constituent material of the shielding layer 50 includes at least one of, but not limited to, metals such as W, Co, Cu, Al, and silicides.
[0117] Step S4: Refer to Figure 2 and Figure 8 and Figure 9 , and form a first spacer 61 in the first connection region 103, the first spacer 61 divides a part of the gate layer 40 into a first gate line 41 and a second gate line 42; among them, the first gate line 41 and the second gate line 42 are on the same straight line, the first spacer 61 is respectively connected to the first gate line 41 and the second gate line 42, and the first gate line 41 and the second gate line 42 are spaced apart by the first spacer 61.
[0118] In some embodiments, step S4 further includes: forming a second spacer 62 at a position in the first core region 101 and away from the first spacer 61, the second spacer 62 divides another part of the gate layer 40 into a third gate line 43 and a fourth gate line 44; the third gate line 43 is on one side of the first gate line 41, the fourth gate line 44 is on one side of the second gate line 42, the first gate line 41 and the third gate line 43 are respectively connected to the second spacer 62, and the first gate line 41 and the third gate line 43 are spaced apart by the second spacer 62.
[0119] Step S5: Please refer back to Figure 2 and Figure 8 and Figure 9 , at a position within the first connection region 103 and adjacent to the first spacer 61, form a first lead contact 71, and connect the third gate line 43 and the fourth gate line 44 to the first lead contact 71 respectively, to obtain the first semiconductor structure 100.
[0120] Among them, the first gate line 41 and the third gate line 43 constitute a first gate line group 410, and the second gate line 42 and the fourth gate line 44 constitute a second gate line group 420.
[0121] Please refer to Figure 8 and Figure 9 , in some embodiments, two adjacent second gate lines 42 of the two second gate line groups 420 and two adjacent first gate lines 41 of the two first gate line groups 410 are respectively connected to the same first spacer 61, and two adjacent third gate lines 43 are connected to the same second spacer 62.
[0122] Please refer to Figure 10 and Figure 11 , in some embodiments, the second gate line 42 of a second gate line group 420 and the first gate line 41 of a first gate line group 410 are spaced apart by a first spacer 61, and the first gate line 41 and the third gate line 43 within a first gate line group 410 are spaced apart by a second spacer 62. That is, two adjacent first gate line groups 410 in the second direction Y correspond to two first spacers 61 and two second spacers 62.
[0123] Please refer to Figures 8 to 11 , in some embodiments, the size of the first lead contact 71 and the second lead contact 72 in the second direction Y is slightly larger than the size of the first trench 20 in the second direction Y.
[0124] Please refer to Figures 8 to 11 , in some embodiments, there is a first spacer 61 and a first lead contact 71 between the first gate line group 410 and the second gate line group 420 adjacent in the first direction X.
[0125] In some embodiments, when the number of the second core regions 102 is multiple, there is a first spacer 61 and a first lead contact 71 between two adjacent second gate line groups 420 in the first direction X respectively.
[0126] In some embodiments, step S5 further includes: forming a second lead contact 72 at a position adjacent to the second spacer 62 and away from the first spacer 61 at one end of the first gate line group 410, and connecting one end of the first gate line 41 away from the first spacer 61 to the second lead contact 72.
[0127] Step S6: Refer to Figure 2 and Figure 12 , bond and connect the second semiconductor structure 200 including the word line decoder 81 with the first semiconductor structure 100 or 300 in the third direction Z, connect the first lead contact 71 with the word line decoder 81, to obtain the semiconductor device 1000 or 2000.
[0128] In step S6, the second lead contact 72 is also connected to the word line decoder 81.
[0129] The second semiconductor structure 200 further includes a bit line sense amplifier 82 corresponding to the first core region 101 and / or the second core region 102. The word line decoder 81 and the bit line sense amplifier 82 are arranged at intervals, and the bit line sense amplifier 82 is connected to a bit line (not shown in the figure).
[0130] Refer to Figure 8 , Figure 9 and Figure 12 , this application further provides a semiconductor device 1000, and the semiconductor device 1000 is at least a part of a DRAM memory. The semiconductor device 1000 includes a first semiconductor structure 100, and the first semiconductor structure 100 includes a first core region 101, a second core region 102 and a first connection region 103 located between the first core region 101 and the second core region 102. The first semiconductor structure 100 further includes a first gate line group 410, a second gate line group 420 and a first spacer 61. The first gate line group 410 is located in the first core region 101 and includes a first gate line 41 extending along the first direction X. The second gate line group 420 is located in the second core region 102 and includes a second gate line 42 extending along the first direction X. The first spacer 61 is located in the first connection region 103. Wherein, the first spacer 61 is respectively connected to the first gate line 41 and the second gate line 42, and the first gate line 41 and the second gate line 42 are spaced apart by the first spacer 61.
[0131] In some embodiments, the first gate line group 410 further includes a third gate line 43 on one side of the first gate line 41, the second gate line group 420 further includes a fourth gate line 44 on one side of the second gate line 42, and the third gate line 43 is connected to the fourth gate line 44.
[0132] In some embodiments, the constituent materials of the first gate line 41, the second gate line 42, the third gate line 43, and the fourth gate line 44 include conductive materials, such as single-crystalline silicon, polycrystalline silicon, doped single-crystalline silicon, doped polycrystalline silicon, tungsten, copper, aluminum, platinum, titanium, or ruthenium.
[0133] In some embodiments, the first semiconductor structure 100 further includes a first lead contact 71, and the third gate line 43 and the fourth gate line 44 are respectively connected to the first lead contact 71.
[0134] In some embodiments, the first lead contact 71 is located within the first connection region 103 and is disposed adjacent to the first spacer 61.
[0135] In some embodiments, a part of the first lead contact 71 is located within the first spacer 61, and another part of the first lead contact 71 is located outside the first spacer 61. That is, the first spacer 61 has a recess 711, and the first lead contact 71 is located within the recess 711 of the first spacer 61.
[0136] In some embodiments, the first semiconductor structure 100 further includes a second spacer 62. The second spacer 62 is located within the first core region 101 and is away from the first spacer 61. The first gate line 41 and the third gate line 43 within the first gate line group 410 are respectively connected to the second spacer 62, and the first gate line 41 and the third gate line 43 are spaced apart by the second spacer 62.
[0137] In some embodiments, the third gate line 43 and the fourth gate line 44 respectively extend along a first direction X. The first gate line 41 and the third gate line 43 are spaced apart along a second direction Y perpendicular to the first direction X. The second gate line 42 and the fourth gate line 44 are spaced apart along the second direction Y. The plurality of first gate line groups 410 and the plurality of second gate line groups 420 are respectively spaced apart along the second direction Y.
[0138] Please refer to Figure 8 and Figure 9 , in some embodiments, two third gate lines 43 or two first gate lines 41 of two adjacent first gate line groups 410 in the second direction are adjacent to each other. Two fourth gate lines 44 or two second gate lines 42 of two adjacent second gate line groups 420 in the second direction are adjacent to each other. In some other embodiments, the third gate line 43 of a first gate line group 410 is adjacent to the first gate line 41 of another first gate line group 410 adjacent to the first gate line group 410. The fourth gate line 44 of the second gate line group 420 is adjacent to the second gate line 42 of another second gate line group 420 adjacent to the second gate line group 420.
[0139] Please refer to Figure 8 andFigure 9 In some embodiments, two adjacent second gate lines 42 of the two second gate line groups 420 and two adjacent first gate lines 41 of the two first gate line groups 410 are respectively connected to the same first spacer 61, and two adjacent third gate lines 43 arranged adjacent to each other are connected to the same second spacer 62.
[0140] In some embodiments, the first semiconductor structure 100 further includes a second connection region 111 on a side of the first core region 101 away from the first connection region 103. The first semiconductor structure 100 further includes a second lead contact 72 located in the second connection region 111. The second lead contact 72 is arranged adjacent to the second spacer 62, and one end of the first gate line 41 away from the first spacer 61 is connected to the second lead contact 72.
[0141] In some embodiments, the first semiconductor structure 100 further includes a semiconductor pillar group 130 located in the first core region 101 and the second core region 102. Each semiconductor pillar group 130 includes a plurality of semiconductor pillars 30 arranged along the first direction X. The first gate line group 410 is located between two adjacent semiconductor pillar groups 130 in the first core region 101, and the second gate line group 420 is located between two adjacent semiconductor pillar groups 130 in the second core region 102.
[0142] In some embodiments, there are at least two semiconductor pillar groups 130 between two adjacent first gate line groups 410 in the second direction Y and / or between two adjacent second gate line groups 420 in the second direction Y.
[0143] In some embodiments, the first semiconductor structure 100 further includes a shielding layer 50. The shielding layer 50 extends along the first direction X and the third direction Z and is located between two adjacent semiconductor pillar groups 130.
[0144] In some embodiments, the constituent materials of the shielding layer 50 include but are not limited to at least one of metals such as W, Co, Cu, Al, and silicides.
[0145] In some embodiments, there is a first spacer 61 and a first lead contact 71 between the first gate line group 410 and the second gate line group 420 adjacent to each other in the first direction X.
[0146] In some embodiments, when the number of the second core regions 102 is multiple, there is a first spacer 61 and a first lead contact 71 between two adjacent second gate line groups 420 in the first direction X.
[0147] In some embodiments, the first spacers 61 and the second spacers 62 at both ends of the same first gate line group 410 are respectively located on both sides of the first gate line group 410 in the second direction Y. The first spacers 61 at both ends of the same second gate line group 420 are respectively located on both sides of the second gate line group 420 in the second direction Y.
[0148] Please refer to Figure 12 and Figure 13 , in some embodiments, the semiconductor device 1000 further includes a second semiconductor structure 200. The second semiconductor structure 200 includes a word line decoder 81 corresponding to the first core region 101 and / or the second core region 102. The second semiconductor structure 200 is bonded and connected to the first semiconductor structure 100 in the third direction Z. The first lead contact 71 is connected to the word line decoder 81.
[0149] In some embodiments, one first lead contact 71 is connected to one word line decoder 81. One second lead contact 72 is also connected to one word line decoder 81.
[0150] The second semiconductor structure 200 includes a bit line sense amplifier 82 corresponding to the first core region 101 and / or the second core region 102. The word line decoder 81 and the bit line sense amplifier 82 are spaced apart. The bit line sense amplifier 82 is connected to a bit line (not shown in the figure).
[0151] Please refer to Figures 10 to 13 , this application also provides a semiconductor device 2000. The structure of the semiconductor device 2000 is basically the same as that of the semiconductor device 1000, except that the first semiconductor structures are not completely the same. The semiconductor device 2000 includes a first semiconductor structure 300. The structure of the first semiconductor structure 300 is similar to that of the first semiconductor structure 100. The difference between the two is only that: the second gate line 42 of one second gate line group 420 of the first semiconductor structure 300 is spaced apart from the first gate line 41 of each first gate line group 410 by a first spacer 61, and the first gate line 41 in one first gate line group 410 is spaced apart from the third gate line 43 by a second spacer 62. That is, two first spacers 61 and two second spacers 62 correspond to two adjacent first gate line groups 410 in the second direction Y.
[0152] Please refer to Figure 14 , this application also provides a memory system 1100. The memory system 1100 includes one or more semiconductor devices 1000 or 2000 as described above and a controller 3000. The controller 3000 is connected to the semiconductor device 1000 or 2000. The controller 3000 is configured to control the semiconductor device 1000 or 2000.
[0153] The memory system 1100 can be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a memory therein. The controller can be configured to control the operations of the semiconductor devices, such as read, erase, and program operations.
[0154] In some embodiments, the controller is designed to operate in a low duty cycle environment, such as a Secure Digital (SD) card, a Compact Flash (CF) card, a Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal calculators, digital cameras, mobile phones, etc.
[0155] In some embodiments, the controller is designed to operate in a high duty cycle environment, a Solid State Disk (SSD) or an Embedded Multi Media Card (eMMC), where the SSD or eMMC serves as a data storage for mobile devices such as smart phones, tablet computers, laptop computers, etc., as well as enterprise storage arrays.
[0156] In some embodiments of the present application, the semiconductor device, its manufacturing method, and the memory system provided separate the adjacent first gate line and the second gate line located in the adjacent first core area and the second core area by a first spacer. The first spacer is respectively connected to the first gate line and the second gate line, so that the number of spacers between the gate lines of the adjacent first core area and the second core area is reduced, thereby reducing the occupied area of the spacers and facilitating further compression of the volume of the semiconductor device. Additionally, by moving the word line decoder from the connection area to the core area, the occupied area of the spacers can be further reduced, which is beneficial to further compression of the volume of the semiconductor device.
[0157] In addition, the third gate line of the adjacent first gate line group and the fourth gate line of the second gate line group or the fourth gate lines of two adjacent second gate line groups are connected through a first lead contact and connected to the word line decoder by the first lead contact, without being respectively led out through corresponding lead wires, reducing the process routing difficulty of the semiconductor device.
[0158] In addition, splitting the gate layer formed in the same first trench into multiple gate lines simplifies the manufacturing process.
[0159] In addition, by partitioning the same second groove into a plurality of second grooves that are spaced apart and respectively correspond to the first core region and the second core region, and then filling the second grooves with a shielding layer, the first spacer and the second spacer can be avoided, providing space for the arrangement of the first spacer and the second spacer.
[0160] In summary, although the present application has been disclosed above with preferred embodiments, the above preferred embodiments are not intended to limit the present application. Those of ordinary skill in the art can make various modifications and refinements without departing from the spirit and scope of the present application. Therefore, the protection scope of the present application is subject to the scope defined by the claims.
Claims
1. A semiconductor device, comprising a first semiconductor structure; the first semiconductor structure includes a first core region, a second core region, and a first connection region located between the first core region and the second core region; characterized in that, The first semiconductor structure further includes: A first gate line group, located within the first core region and including a first gate line extending in a first direction; A second gate line group, located within the second core region and including a second gate line extending in the first direction; and A first spacer, located within the first connection region; Wherein, the first spacer is respectively connected to the first gate line and the second gate line, and the first gate line and the second gate line are spaced apart by the first spacer.
2. The semiconductor device according to claim 1, wherein, The first gate line group further includes a third gate line on one side of the first gate line, and the second gate line group further includes a fourth gate line on one side of the second gate line; The third gate line is connected to the fourth gate line.
3. The semiconductor device according to claim 2, wherein The first semiconductor structure further includes a first lead contact, and the third gate line and the fourth gate line are respectively connected to the first lead contact.
4. The semiconductor device according to claim 3, wherein, The first lead contact is located within the first connection region and is disposed adjacent to the first spacer.
5. The semiconductor device according to claim 4, characterized in that, A part of the first lead contact is located within the first spacer, and another part of the first lead contact is located outside the first spacer.
6. The semiconductor device according to claim 2, wherein, The first semiconductor structure further includes a second spacer, the second spacer is located within the first core region and is away from the first spacer, the first gate line and the third gate line within the first gate line group are respectively connected to the second spacer, and the first gate line and the third gate line are spaced apart by the second spacer.
7. The semiconductor device according to claim 6, wherein, The third gate line and the fourth gate line respectively extend along the first direction; The first gate line and the third gate line are spaced apart along a second direction perpendicular to the first direction, and the second gate line and the fourth gate line are spaced apart along the second direction; Multiple first gate line groups and multiple second gate line groups are respectively spaced apart along the second direction.
8. The semiconductor device according to claim 7, wherein, Two third gate lines or two first gate lines of two adjacent first gate line groups in the second direction are adjacent to each other; Two fourth gate lines or two second gate lines of two adjacent second gate line groups in the second direction are adjacent to each other.
9. The semiconductor device according to claim 8, wherein, Two adjacent second gate lines of two second gate line groups and two adjacent first gate lines of two first gate line groups are respectively connected to the same first spacer.
10. The semiconductor device according to claim 9, characterized in that, Two adjacent third gate lines are connected to the same second spacer.
11. The semiconductor device according to claim 6, wherein, The third gate line of the first gate line group is adjacent to the first gate line of another first gate line group adjacent to the first gate line group; The fourth gate line of the second gate line group is adjacent to the second gate line of another second gate line group adjacent to the second gate line group.
12. The semiconductor device according to claim 11, wherein The second gate line of one second gate line group and the first gate line of one first gate line group are spaced apart by one first spacer.
13. The semiconductor device according to claim 11, wherein, The first gate line and the third gate line within one first gate line group are spaced apart by one second spacer.
14. The semiconductor device according to claim 6, wherein The first semiconductor structure further includes a second connection region located on a side of the first core region away from the first connection region; The first semiconductor structure further includes a second lead contact located in the second connection region, and the second lead contact is disposed adjacent to the second spacer; One end of the first gate line away from the first spacer is connected to the second lead contact.
15. The semiconductor device according to claim 3, wherein, The first semiconductor structure further includes a semiconductor pillar group located in the first core region and the second core region. Each semiconductor pillar group includes a plurality of semiconductor pillars arranged along the first direction; the first gate line group is located between two adjacent semiconductor pillar groups in the first core region, and the second gate line group is located between two adjacent semiconductor pillar groups in the second core region.
16. The semiconductor device according to claim 15, characterized in that, There are at least two semiconductor pillar groups between two adjacent first gate line groups in the second direction and / or between two adjacent second gate line groups in the second direction; The first semiconductor structure further includes a shielding layer, and the shielding layer extends along the first direction and is located between two adjacent semiconductor pillar groups.
17. The semiconductor device according to any one of claims 2-16, characterized in that, There is one first spacer and one first lead contact between the first gate line group and the second gate line group adjacent to each other in the first direction; and / or when the number of the second core regions is multiple, there is one first spacer and one first lead contact between two adjacent second gate line groups in the first direction.
18. The semiconductor device according to any one of claims 1 to 16, characterized in that, The semiconductor device further includes a second semiconductor structure, and the second semiconductor structure includes a word line decoder corresponding to the first core region and / or the second core region; The second semiconductor structure is bonded and connected to the first semiconductor structure in a third direction perpendicular to the first direction, and the first lead contact is connected to the word line decoder.
19. The semiconductor device according to claim 18, wherein, One first lead contact is connected to one word line decoder.
20. A method for manufacturing a semiconductor device, characterized in that, Including: Providing a semiconductor structure including a first core region, a second core region and a first connection region, the semiconductor structure including a plurality of initial semiconductor pillars spaced apart along a first direction; Forming a plurality of first trenches extending along the first direction and distributed along a second direction perpendicular to the first direction on the semiconductor structure, and the first trenches divide the initial semiconductor pillars into a plurality of semiconductor pillars; Forming a gate layer in the first trenches; And Forming a first spacer in the first connection region, and the first spacer divides a part of the gate layer into a first gate line and a second gate line to obtain a first semiconductor structure; wherein, the first gate line and the second gate line are located on the same straight line, the first spacer is respectively connected to the first gate line and the second gate line, and the first gate line and the second gate line are spaced apart by the first spacer.
21. The method for manufacturing a semiconductor device according to claim 20, wherein, In the process of forming a first spacer in the first connection region, and the first spacer divides a part of the gate layer into a first gate line and a second gate line to obtain a first semiconductor structure, it further includes: A second spacer is formed at a position within the first core region and away from the first spacer. The second spacer divides another portion of the gate layer into a third gate line and a fourth gate line. The third gate line is located on one side of the first gate line, and the fourth gate line is located on one side of the second gate line. The first gate line and the third gate line are respectively connected to the second spacer, and the first gate line and the third gate line are spaced apart by the second spacer.
22. The manufacturing method of the semiconductor device according to claim 21, wherein, After the steps of forming the first spacer in the first connection region and forming the second spacer in the first core region, it further includes: A first lead contact is formed at a position within the first connection region and adjacent to the first spacer, and the third gate line and the fourth gate line are respectively connected to the first lead contact.
23. The method for manufacturing a semiconductor device according to claim 22, characterized in that, The first gate line and the third gate line constitute a first gate line group, and the second gate line and the fourth gate line constitute a second gate line group; During the process of forming the first lead contact at a position within the first connection region and adjacent to the first spacer, it further includes: A second lead contact is formed at a position at one end of the first gate line group away from the first spacer and adjacent to the second spacer, and one end of the first gate line away from the first spacer is connected to the second lead contact.
24. The method for manufacturing a semiconductor device according to claim 20, wherein, During the process of forming a plurality of first trenches extending in the first direction and distributed in a second direction perpendicular to the first direction on the semiconductor structure, it further includes: A plurality of second trenches extending in the first direction and distributed in the second direction are formed on the semiconductor structure. One second trench is located between two adjacent first trenches. The second trenches and the first trenches together divide the initial semiconductor pillar into a plurality of semiconductor pillars; During the process of forming the gate layer in the first trenches, it further includes: A shielding layer is formed in the second trenches.
25. The method for manufacturing a semiconductor device according to claim 23, wherein, Two adjacent second gate lines of the two second gate line groups and two adjacent first gate lines of the two first gate line groups are respectively connected to the same first spacer; Two adjacent third gate lines are connected to the same second spacer.
26. The method for manufacturing a semiconductor device according to claim 23, wherein, The second gate line of one second gate line group and the first gate line of one first gate line group are spaced apart by one first spacer; The first gate line and the third gate line within one first gate line group are spaced apart by one second spacer; Two first gate line groups adjacent in the second direction correspond to two first spacers and two second spacers.
27. The method for manufacturing a semiconductor device according to any one of claims 20-26, characterized in that, After the step of forming the first spacer in the first connection region, where the first spacer divides the gate layer into a first gate line and a second gate line to obtain a first semiconductor structure, it further includes: A second semiconductor structure including a word line decoder correspondingly arranged with the first core region and / or the second core region is bonded and connected to the first semiconductor structure in a third direction perpendicular to the first direction, and the first lead contact is connected to the word line decoder.
28. A memory system, characterized in that, It includes: At least a semiconductor device as described in any one of claims 1 to 19; and a controller, coupled to the semiconductor device and configured to control the semiconductor structure.