Semiconductor device and forming method thereof

Abstract

The invention provides a semiconductor device and a forming method thereof. The semiconductor device comprises a substrate, an isolation structure, a word line structure, a first dielectric column, a second dielectric column, a first conductive layer and a second conductive layer. The substrate has an active region and a dummy region adjacent to the active region. The isolation structure is located in the dummy region and disposed in the substrate. The word line structure is located in the active region and arranged in the substrate. The first dielectric pillar is disposed on the isolation structure and the word line structure. The second dielectric pillar is disposed on the isolation structure. The first conductive layer is located in the active region and disposed on the substrate. The second conductive layer is disposed on the first conductive layer and the second dielectric pillar. Wherein a bottom surface of the second conductive layer in the dummy region is lower than a top surface of the first dielectric pillar in the dummy region.

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a method of forming the same, and more particularly to a semiconductor device as a memory device and a method of forming the same. Background Art

[0002] The miniaturization of semiconductors can increase device density and improve performance. However, it may cause problems such as unnecessary conduction, leakage current and / or short circuit between adjacent devices or reduced reliability. Summary of the Invention

[0003] In view of the above problems, the present application avoids the problem of leakage current by forming a second dielectric pillar in the isolation structure. For example, by forming a second dielectric pillar on the isolation structure and in the dummy region, the second conductive layer disposed on the second dielectric pillar is prevented from generating leakage current in the dummy region. Therefore, the present application can avoid leakage current between adjacent devices and / or improve the reliability of the semiconductor device.

[0004] In some embodiments, a semiconductor device is provided, which includes a substrate, an isolation structure, a word line structure, a first dielectric pillar, a second dielectric pillar, a first conductive layer, and a second conductive layer. The substrate has an active region and a dummy region adjacent to the active region. The isolation structure is located in the dummy region and disposed in the substrate. The word line structure is located in the active region and disposed in the substrate. The first dielectric pillar is disposed on the isolation structure and the word line structure. The second dielectric pillar is disposed on the isolation structure. The first conductive layer is located in the active region and disposed on the substrate. The second conductive layer is disposed on the first conductive layer and the second dielectric pillar. Wherein, the bottom surface of the second conductive layer in the dummy region is lower than the top surface of the first dielectric pillar in the dummy region.

[0005] In some embodiments, a method of forming a semiconductor device is provided. The forming method includes providing a substrate having an active region and a dummy region adjacent to the active region. Forming an isolation structure in the dummy region and in the substrate. Forming a word line structure in the active region and in the substrate. Forming a first dielectric pillar on the isolation structure and the word line structure. Forming a second dielectric pillar on the isolation structure, wherein the top surface of the second dielectric pillar is lower than the top surface of the first dielectric pillar. Forming a first conductive layer in the active region and on the substrate. Forming a second conductive layer on the first conductive layer and the second dielectric pillar. Brief Description of the Drawings

[0006] Figures 1 to 11 Schematic cross-sectional views showing the formation of a semiconductor device at various stages according to some embodiments of the present invention.

[0007] Figure 12 Schematic cross-sectional view showing a semiconductor device according to some embodiments of the present invention.

[0008]

Symbol Explanation

[0009] 1, 2: Semiconductor device

[0010] 100: Substrate

[0011] 101: First dielectric layer

[0012] 102: Second dielectric layer

[0013] 103: Dielectric filler

[0014] 104: First liner

[0015] 105: First word line conductive layer

[0016] 106: Second liner

[0017] 107: Second word line conductive layer

[0018] 108: Third dielectric layer

[0019] 109: Fourth dielectric layer

[0020] 110: First transistor conductive layer

[0021] 111: Second transistor conductive layer

[0022] 112: Fifth dielectric layer

[0023] 113: First spacer

[0024] 114: Second spacer

[0025] 115: Planarization layer

[0026] 202: Contact

[0027] 204: Capping layer

[0028] 206: First dielectric pillar

[0029] 206T, 208T, 310T, 400T: Top surface

[0030] 206S, 310S, 320S: Side surface

[0031] 208: Second dielectric pillar

[0032] 310: First photoresist layer

[0033] 320: Second photoresist layer

[0034] 400: First conductive layer

[0035] 500: Second conductive layer

[0036] 500B: Bottom surface

[0037] AA: Active area

[0038] D1: First direction

[0039] D2: Second direction

[0040] DA:Dummy area

[0041] H1: First height

[0042] H2: Second height

[0043] ISO: Isolation structure

[0044] PA: Peripheral area

[0045] TS: Transistor structure

[0046] WLS: Word line structure

[0047] WLS’: Bypass word line structure Detailed implementation manners

[0048] In the present application, each direction is not limited to a rectangular coordinate system, such as the X-axis, Y-axis, and Z-axis, and can be interpreted in a broader sense. For example, the X-axis, Y-axis, and Z-axis may be perpendicular to each other, but this is not a limitation. For the sake of illustration, hereinafter, the X-axis direction is the first direction D1 (width direction), and the Z-axis direction is the second direction D2 (height / depth direction). In some embodiments, the second direction D2 may be the normal direction of the substrate. In some embodiments, the cross-sectional schematic diagrams described herein are cross-sectional schematic diagrams of the XZ plane.

[0049] Refer to Figure 1 , which is a cross-sectional schematic diagram showing the formation of a semiconductor device at various stages according to some embodiments of the present invention. Among them, the cross-sectional schematic diagrams described herein are cross-sectional schematic diagrams obtained by extracting along a direction parallel to the extension direction of the bit line and not overlapping with the bit line. In some embodiments, a substrate 100 may be provided. The substrate 100 may include a silicon wafer, a bulk semiconductor, or a semiconductor-on-insulation (SOI) substrate. Other types of the substrate 100 are, for example, a multi-layer substrate or a graded substrate.

[0050] The substrate 100 may have an active region AA, a dummy region DA, and a peripheral region PA. The active region AA may be adjacent to the dummy region DA, and the dummy region DA may be between the active region AA and the peripheral region PA. Memory cells of the semiconductor device may be disposed in a storage region, the storage region may include the active region AA and the dummy region DA, and the storage region may be adjacent to the peripheral region PA. Memory cells located in the active region AA may perform a storage function, and memory cells located in the dummy region DA may not perform a storage function. In addition, peripheral circuits for controlling the memory cells may be disposed in the peripheral region PA.

[0051] A plurality of trenches (not shown) may be formed in the substrate 100, and isolation material may be formed in the trenches to form an isolation structure ISO in the dummy region DA and provide electrical isolation. The isolation structure ISO may be a single-layer or multi-layer structure. For example, the multi-layer isolation structure ISO may include a first dielectric layer 101, a second dielectric layer 102, and / or a dielectric filler 103 made of materials such as oxides, nitrides, oxynitrides, etc. For example, the first dielectric layer 101 may include silicon oxide, the second dielectric layer 102 may include silicon nitride, and the dielectric filler 103 may include spin on glass (SOG) oxide.

[0052] A word line structure WLS may be formed in the active region AA. The top surface of the word line structure WLS may be lower than the top surface of the substrate 100, so the word line structure WLS may be a buried word line structure. A group of word lines may include a pair of word line structures WLS and passing word line structures WLS' disposed on both sides of the pair of word line structures WLS. The word line structure WLS and the passing word line structure WLS' may include a first dielectric layer 101, a second dielectric layer 102, a first liner 104, a first word line conductive layer 105, a second liner 106, a second word line conductive layer 107, and a third dielectric layer 108.

[0053] In some embodiments, the first liner 104, the first word line conductive layer 105, the second liner 106, and / or the second word line conductive layer 107 may include polysilicon; amorphous silicon; metals such as tungsten, copper, silver, gold, cobalt; metal nitrides such as tungsten nitride, titanium nitride; conductive metal oxides; other suitable materials; analogs thereof or combinations thereof, but the present application is not limited thereto. The material of the third dielectric layer 108 may be the same as or different from the material of the first dielectric layer 101. For example, the first liner 104 may include titanium nitride, the first word line conductive layer 105 may include polysilicon, the second liner 106 may include titanium nitride, the second word line conductive layer 107 may include tungsten, and the third dielectric layer 108 may include silicon oxide.

[0054] Furthermore, a contact 202 can be formed on the word line structure WLS, and the contact 202 is electrically connected to a subsequently formed first conductive layer. The contact 202 can be disposed between a pair of word line structures WLS and can be disposed on the upper portion of the word line structure WLS. The contact 202 can serve as a gate contact (GC) of a memory cell of the semiconductor device, and thus the contact 202 can be used to electrically connect to a gate electrode of a transistor structure in the peripheral area PA of the semiconductor device.

[0055] In some embodiments, a transistor structure TS can be formed in the peripheral area PA and on the substrate 100. The transistor structure TS can include a fourth dielectric layer 109, a first transistor conductive layer 110, a second transistor conductive layer 111, a fifth dielectric layer 112, a first spacer 113, and a second spacer 114.

[0056] In some embodiments, the materials of the fourth dielectric layer 109, the fifth dielectric layer 112, the first spacer 113, and / or the second spacer 114 can be the same as or different from the material of the first dielectric layer 101. The materials of the first transistor conductive layer 110 and / or the second transistor conductive layer 111 can be the same as or different from the material of the first word line conductive layer 105. For example, the fourth dielectric layer 109 can include silicon oxide, the first transistor conductive layer 110 can include polysilicon, the second transistor conductive layer 111 can include tungsten, the fifth dielectric layer 112 can include silicon nitride, the first spacer 113 can include silicon nitride, and the second spacer 114 can include silicon oxide.

[0057] In some embodiments, a planarization layer 115 is formed on the transistor structure TS to cover the side surfaces of the transistor structure TS. In some embodiments, a covering layer 204 is formed on the planarization layer 115 to cover the top surface of the transistor structure TS and the top surface of the planarization layer 115. The materials of the planarization layer 115 and / or the covering layer 204 can be the same as or different from the material of the first dielectric layer 101. For example, the planarization layer 115 can include spin-on glass oxide, and the covering layer 204 can include silicon nitride.

[0058] In some embodiments, the first dielectric pillar 206 and the second dielectric pillar 208 may be respectively formed in the active region AA and the dummy region DA, and are respectively formed on the word line structure WLS, the bypass word line structure WLS', and the isolation structure ISO. The second dielectric pillar 208 and the first dielectric pillar 206 may be staggered in the first direction D1. The materials of the first dielectric pillar 206 and the second dielectric pillar 208 may be the same as or different from the material of the first dielectric layer 101. For example, the first dielectric pillar 206 may include a nitride such as silicon nitride, and the second dielectric pillar 208 may include an oxide such as spin-on glass oxide. In some embodiments, in the second direction D2, the second dielectric pillar 208 may have a first height H1. The first height H1 may be greater than or equal to 0 and less than or equal to 250 nm. For example, the first height H1 may be 50 nm, 100 nm, 150 nm, 200 nm, 250 nm, or any value or range of values between the foregoing values, but the present application is not limited thereto.

[0059] Referring Figure 2 , in some embodiments, the second dielectric pillar 208 is etched back so that the top surface 208T of the second dielectric pillar 208 is lower than the top surface 206T of the first dielectric pillar 206. The etch back may be a partial wet etching process. In the second direction D2, the etched-back second dielectric pillar 208 has a second height H2, and the second height H2 is 20% to 75% of the first height H1. For example, the ratio of the second height H2 to the first height H1 (second height H2 / first height H1) may be 0.2, 0.3, 0.4, 0.5, 0.6, 0.7, 0.75, or any value or range of values between the foregoing values, but the present application is not limited thereto.

[0060] In some embodiments, the depth of the etch-back process may be 25% to 80% of the first height H1. For example, the depth of the etch-back process may be 25%, 30%, 40%, 50%, 60%, 70%, 80% of the first height H1, or any value between the foregoing values or any range of values composed of any values, but the present application is not limited thereto. In some embodiments, the depth of the etch-back process may be 20 nm to 80 nm. For example, the depth of the etch-back process may be 20 nm, 30 nm, 40 nm, 50 nm, 60 nm, 70 nm, 80 nm, or any value between the foregoing values or any range of values composed of any values, but the present application is not limited thereto. Perform the etch-back process to form a recess (not shown) on the second dielectric pillar 208. Since the depth of the etch-back process performed is substantially the same as the thickness of the first photoresist layer subsequently formed in the recess, the thickness of the first photoresist layer in the recess can be adjusted by controlling the depth of the etch-back process. For example, when the depth of the etch-back process may be 20 nm, the thickness of the first photoresist layer in the recess may be 20 nm. Therefore, the over-etching of the subsequent wet etching process can be blocked by the first photoresist layer in the recess. Then, the second dielectric pillar 208 can be patterned to adjust the setting position of the second dielectric pillar 208.

[0061] Referring to Figures 3 to 7 , patterning the second dielectric pillar 208 may include forming and covering a photoresist layer on the second dielectric pillar 208 in the dummy region DA. Then, by using the photoresist layer as an etch mask to perform a wet etching process, the second dielectric pillar 208 in the active region AA is removed. Then, the photoresist layer is removed. The photoresist layer may include two photoresist layers with different viscosities.

[0062] Specifically, as Figure 3 shown, a first photoresist layer 310 is formed on the active region AA, the dummy region DA, and the peripheral region PA, and is formed on the first dielectric pillar 206 and the second dielectric pillar 208. The first photoresist layer 310 may include an oxide, a nitride, a nitroxide, a carbon-based material. For example, the first photoresist layer 310 may include spin on carbon (SOC) or a carbon-based material with a viscosity lower than that of spin on carbon to completely fill the recess (not shown) on the second dielectric pillar 208. Accordingly, the reliability of filling the recess with the first photoresist layer 310 can be improved by using a low-viscosity carbon-based material.

[0063] As Figure 4As shown, a second photoresist layer 320 is formed on the first photoresist layer 310, and the second photoresist layer 320 exposes the top surface 310T of the first photoresist layer 310 in the active region AA. In some embodiments, the viscosity of the first photoresist layer 310 is less than that of the second photoresist layer 320, so that the first photoresist layer 310 can more easily fill the recesses (not shown) completely, while the second photoresist layer 320 with a higher viscosity can better form a mask. In some embodiments, the material and formation method of the second photoresist layer 320 may be the same as or different from those of the first photoresist layer 310.

[0064] As Figure 5 shown, by using the first photoresist layer 310 as an etching mask to perform an etching process, the first photoresist layer 310 in the active region AA is removed, so that the side surface 310S of the first photoresist layer 310 is aligned with the side surface 320S of the second photoresist layer 320. The side surface 310S of the first photoresist layer 310 and the side surface 320S of the second photoresist layer 320 can be aligned with the side surface 206S of the first dielectric pillar 206 located in the dummy region DA and closest to the active region AA.

[0065] As shown in Figure 6 By using the first photoresist layer 310 and the second photoresist layer 320 together as an etching mask to perform a wet etching process, the second dielectric pillar 208 in the active region AA is removed. Since the first photoresist layer 310 is disposed below the second photoresist layer 320 in the dummy region DA, over-etching during the wet etching process can be avoided due to the edge warping or gaps of the second photoresist layer 320 with a high viscosity. For example, in the case where the second photoresist layer 320 is directly formed on the second dielectric pillar 208, the etchant used in the wet etching process may penetrate from the bottom of the second photoresist layer 320 or the junction between the second photoresist layer 320 and other devices. Therefore, forming the first photoresist layer 310 with a low viscosity first and then the second photoresist layer 320 with a high viscosity can effectively block the etchant from over-etching in the dummy region DA. Thus, leakage current between adjacent devices is avoided and / or the reliability of the semiconductor device is improved.

[0066] As Figure 7 shown, the photoresist layer can be further removed by a removal process such as an ashing process.

[0067] Referring to Figure 8 , a part of the word line structure WLS and a part of the bypass word line structure WLS' are removed to expose the top surface of the substrate 100. For example, a part of the first dielectric layer 101 of the word line structure WLS and the bypass word line structure WLS' can be removed.

[0068] Referring toFigure 9 and Figure 10 , a first conductive layer 400 is formed in the active region AA and on the exposed top surface of the substrate 100, and the first conductive layer 400 is electrically connected to the contact 202.

[0069] Specifically, the material of the first conductive layer 400 is deposited on the substrate 100, the first dielectric pillar 206, and the second dielectric pillar 208. The material and formation method of the first conductive layer 400 may be the same as or different from those of the first word line conductive layer 105.

[0070] As Figure 10 shown, the material of the first conductive layer 400 is etched back so that the top surface 400T of the first conductive layer 400 is lower than the top surface 206T of the first dielectric pillar 206. For example, in the second direction D2, the height of the first conductive layer 400 may be between 50 nm and 150 nm. The top surface 400T of the first conductive layer 400 in the active region AA may be substantially flush with the top surface 208T of the second dielectric pillar 208 in the dummy region DA. The first conductive layer 400 in the dummy region DA may be substantially completely removed.

[0071] Referring to Figure 11 , a second conductive layer 500 is formed on the first conductive layer 400, the first dielectric pillar 206, the second dielectric pillar 208, and the cover layer 204 to obtain the semiconductor device 1. The bottom surface 500B of the second conductive layer 500 in the dummy region DA may be lower than the top surface 206T of the first dielectric pillar 206 in the dummy region DA. The bottom surface 500B of the second conductive layer 500 in the dummy region DA may be substantially flush with the bottom surface 500B of the second conductive layer 500 in the active region AA. At the junction of the active region AA and the dummy region DA, the first dielectric pillar 206 may be interposed between the first conductive layer 400 and the second dielectric pillar 208. In the dummy region DA, the second conductive layer 500 is in direct contact with the second dielectric pillar 208. Accordingly, since the second dielectric pillar 208 is disposed below the second conductive layer 500, unnecessary conduction, leakage current, and / or short circuit between the second conductive layer 500 and the device below it can be avoided.

[0072] Referring to Figure 12 , which is a cross-sectional schematic diagram of a semiconductor device 2 according to some embodiments of the present invention. In some embodiments, similar to Figure 10 , after the etching process, the first conductive layer 400 in the dummy region DA is retained. So that the top surface 400T of the first conductive layer 400 in the active region AA may be substantially flush with the top surface 400T of the first conductive layer 400 in the dummy region DA. The top surface 400T of the first conductive layer 400 in the active region AA may be higher than the top surface 208T of the second dielectric pillar 208 in the dummy region DA. Then, similar to Figure 11, a second conductive layer 500 can be formed on the first conductive layer 400 and the second dielectric pillar 208, thereby obtaining the semiconductor device 2 (such as Figure 12 as shown). In the dummy region DA, the first conductive layer 400 can be interposed between the second conductive layer 500 and the second dielectric pillar 208. In the dummy region DA, the first conductive layer 400 can be in direct contact with the second conductive layer 500, and the first conductive layer 400 can be in direct contact with the second dielectric pillar 208. Accordingly, even if the first conductive layer 400 is in direct contact with the second conductive layer 500, since the second dielectric pillar 208 is disposed below the second conductive layer 500 and the first conductive layer 400, unnecessary conduction, leakage current, and / or short circuit between the first conductive layer 400 and the devices therebelow can be avoided.

[0073] In some embodiments, further processes can be performed on the semiconductor device 1 and / or 2 to form a memory device. For example, landing pads can be formed on the semiconductor device 1 and / or 2, and then storage contacts (SCs) (also referred to as capacitor contacts) can be formed on the landing pads.

[0074] In summary, the semiconductor device of the present application includes a second dielectric pillar on the isolation structure, so that unnecessary conduction, leakage current, and / or short circuit between adjacent devices can be avoided, and / or the reliability of the semiconductor device can be improved. Furthermore, the method for forming the semiconductor device of the present application can form the second dielectric pillar in the dummy region by making the top surface of the second dielectric pillar lower than the top surface of the first dielectric pillar and patterning the second dielectric pillar. Thereby, the process complexity and cost can be reduced (for example, in the case where the second dielectric pillar is not provided in the dummy region, photoresists of different sizes need to be repeatedly provided to test the damage range after performing the wet etching process), leakage current between adjacent devices can be avoided, and / or the reliability of the semiconductor device can be improved. In addition, the method for forming the semiconductor device of the present application can include using photoresist layers with different viscosities to avoid over-etching in the etching process.

[0075] The above outlines several embodiments so that those of ordinary skill in the art to which the present application pertains can better understand the viewpoints of the embodiments of the present application. Those skilled in the art should understand that they can design or modify other processes and structures based on the embodiments of the present application to achieve the same purposes and / or advantages as those introduced herein. Those skilled in the art should also understand that such equivalent processes and structures do not depart from the spirit and scope of the present application, and they can make various changes, substitutions, and replacements without departing from the spirit and scope of the present application.

Claims

1. A semiconductor device, characterized in that, Comprising: A substrate having an active region and a dummy region adjacent to the active region; An isolation structure located in the dummy region and disposed within the substrate; A word line structure located in the active region and disposed within the substrate; A first dielectric pillar disposed on the isolation structure and the word line structure; A second dielectric pillar disposed on the isolation structure; A first conductive layer located in the active region and disposed on the substrate; And A second conductive layer disposed on the first conductive layer and the second dielectric pillar; Wherein a bottom surface of the second conductive layer in the dummy region is lower than a top surface of the first dielectric pillar in the dummy region.

2. The semiconductor device according to claim 1, wherein The first dielectric pillar is between the first conductive layer and the second dielectric pillar.

3. The semiconductor device according to claim 1, wherein In the dummy region, the second conductive layer contacts the second dielectric pillar.

4. The semiconductor device according to claim 1, characterized in that, In the dummy region, the first conductive layer is between the second conductive layer and the second dielectric pillar.

5. The semiconductor device according to claim 1, wherein, The bottom surface of the second conductive layer in the dummy region is flush with the bottom surface of the second conductive layer in the active region.

6. A method for forming a semiconductor device, characterized in that, Comprising: Providing a substrate having an active region and a dummy region adjacent to the active region; Forming an isolation structure in the dummy region and within the substrate; Forming a word line structure in the active region and within the substrate; Forming a first dielectric pillar on the isolation structure and the word line structure; Forming a second dielectric pillar on the isolation structure, wherein a top surface of the second dielectric pillar is lower than a top surface of the first dielectric pillar; Forming a first conductive layer in the active region and on the substrate; and Forming a second conductive layer on the first conductive layer and the second dielectric pillar.

7. The forming method according to claim 6, characterized in that, Forming the second dielectric pillar on the isolation structure further includes: Forming the second dielectric pillar in the active region and the dummy region and on the isolation structure and the word line structure; Etching back the second dielectric pillar to make a top surface of the second dielectric pillar lower than the top surface of the first dielectric pillar; and Patterning the second dielectric pillar.

8. The forming method according to claim 7, wherein: Forming the second dielectric pillar in the active region and the dummy region such that the second dielectric pillar has a first height, and Etching back the second dielectric pillar such that the etched second dielectric pillar has a second height, and the second height is 20% to 75% of the first height.

9. The forming method according to claim 7, characterized in that, Forming the second dielectric pillar in the active region and the dummy region such that the second dielectric pillar is arranged in an interleaved manner with the first dielectric pillar.

10. The forming method according to claim 7, characterized in that, Patterning the second dielectric pillar further includes: Forming a photoresist layer on the second dielectric pillar located in the dummy region such that the photoresist layer covers the second dielectric pillar located in the dummy region; Removing the second dielectric pillar located in the active region; and Removing the photoresist layer.

11. The forming method according to claim 10, wherein, A side surface of the photoresist layer is aligned with a side surface of the first dielectric pillar located in the dummy region.

12. The forming method according to claim 10, wherein Forming the photoresist layer on the second dielectric pillar located in the dummy region further includes: Form a first photoresist layer on the first dielectric pillar and the second dielectric pillar; Form a second photoresist layer on the first photoresist layer, and the second photoresist layer exposes the top surface of the first photoresist layer; and Remove the first photoresist layer in the active region, wherein the viscosity of the first photoresist layer is less than the viscosity of the second photoresist layer.

13. The forming method according to claim 6, characterized in that, Forming the first conductive layer in the active region further includes: Depositing the material of the first conductive layer on the substrate, the first dielectric pillar and the second dielectric pillar; Etching back the material of the first conductive layer so that the top surface of the first conductive layer is lower than the top surface of the first dielectric pillar.

14. The forming method according to claim 13, wherein Etching back the material of the first conductive layer so that the top surface of the first conductive layer in the active region is flush with the top surface of the second dielectric pillar in the dummy region or the top surface of the first conductive layer in the dummy region.

Images