Semiconductor device and manufacturing method thereof

Abstract

An active region strip-shaped column comprises a middle dielectric column and semiconductor material columns located on the two sides of the middle dielectric column in a self-alignment mode, the top surface of the middle dielectric column is flush with the top surfaces of the semiconductor material columns, and the bottom surface of the middle dielectric column is located below the top surface of an isolation oxide layer. And the semiconductor material columns on the top surface of the isolation oxide layer and on the two sides of the middle dielectric column are respectively used as a first side active region and a second side active region. And symmetrical first and second side gate structures respectively cover the side surfaces of the first and second side active regions and are respectively used for controlling the on-off of the first and second side channels. The first side surface active region and the second side surface active region are isolated from each other through the middle dielectric cylinder, so that crosstalk between the first side surface channel and the second side surface channel is prevented. The invention further discloses a manufacturing method of the semiconductor device. According to the invention, side surface channels can be formed on the two side surfaces of the convex active region, and crosstalk of the two side surface channels can be prevented.

Description

Technical Field

[0001] The present invention relates to a semiconductor device, and particularly to a manufacturing method of a semiconductor device. Background Art

[0002] When the active region is a columnar structure protruding from the semiconductor substrate, channels can also be formed on the side surfaces of the active region. Therefore, under the condition of the same device width, the width of the channel region can be increased. The applicant's NORD flash memory structure has a channel region controlled by three split gate structures located between two source-drain regions. Combining with the columnar active region, a gate structure of the NORD flash memory is formed on the side surface of the active region, and multi-bit storage can be achieved on one active region.

[0003] As Figure 1 shown, it is the layout of a conventional semiconductor device; Figure 2A is the schematic cross-sectional structure along the Figure 1 AA line in Figure 2B is the schematic cross-sectional structure along the Figure 1 AA line in Figure 2C is the schematic cross-sectional structure along the Figure 1 CC line in Figure 2D is the schematic cross-sectional structure along the Figure 1 DD line in Figure 2E is the schematic cross-sectional structure corresponding to the XY plane along Figure 1 ; the columnar active region 101 is formed by patterning and etching a semiconductor substrate 101a such as a silicon substrate. Shallow trench isolation 102 is formed at the bottom of the trenches between the active regions 101.

[0004] Combined with Figure 2E shown, the semiconductor device is formed on the active region 101, including: a first source-drain region 106a, a second source-drain region 106b, a first gate structure including a stacked structure of a first floating gate 103a and a first control gate 104a, a second gate structure including a word line gate 105, and a third gate structure including a stacked structure of a second floating gate 103b and a second control gate 104b.

[0005] The process structures of the first source-drain region 106a and the second source-drain region 106b are the same, only the connected electrodes are different. Figure 2A In

[0006] By Figure 2BAs shown, the top surface of the active region 101 has a mask layer 111, and the active region 101 is defined through the mask layer 111. It can be seen that the top surface of the word line gate 105 is flush with the top surface of the mask layer 111. The word line gates 105 on both sides of the active region 101 are connected to different word lines. Figure 1 Two word line gates 105 are shown in [Figure reference]. The one on the left is connected to the odd-numbered word lines WL0_odd of the first row, and the one on the right is connected to the even-numbered word lines WL0_even of the first row.

[0007] The process structures of the first floating gate 103a and the second floating gate 103b are the same, only their positions are different. One is located on the source region side and the other is located on the drain region side; Figure 2C In [Figure reference], both the first floating gate 103a and the second floating gate 103b are represented by the floating gate 103. One floating gate 103 corresponds to one storage bit. Figure 1 In [Figure reference], the four floating gates 103 in the middle active region 101 are also represented by FG1, FG2, FG3, and FG4 respectively, for separating 4 storage bits. The floating gates 103 corresponding to the active regions 101 on the left and right sides are also represented by FG.

[0008] The process structures of the first control gate 104a and the second control gate 104b are the same, only their positions are different. One is located on the source region side and the other is located on the drain region side; Figure 2C In [Figure reference], both the first control gate 104a and the second control gate 104b are represented by the control gate 104. Figure 2C As can be seen from [Figure reference], the control gates 104 on both sides of the active region 101 are connected together at the top of the active region 101. Back to Figure 1 As shown in [Figure reference], the control gates 104 in the same row are connected together to form a control gate row. Figure 1 Two control gate rows are shown in [Figure reference], represented by CGL and CGR respectively.

[0009] Figure 1 In [Figure reference], it shows that the source-drain region 106 at the bottom of the semiconductor device formed in the middle active region 101 is connected to the drain, and the drain is also represented by Drain. At the same time, the source-drain region 106 at the bottom of the semiconductor device of the active region 101 on the right side is also connected to the drain, and the two drains share, as shown by Drain(share) in Figure 1 ; the source-drain region 106 at the top of the semiconductor device of the middle active region 101 is connected to the source, and the source is also represented by Source; the source-drain region 106 at the top of the semiconductor device of the active region 101 on the right side is connected to the inhibit potential Inhibit, and the potentials of Drain, Source, and Inhibit are applied through the corresponding bit lines.

[0010] Figure 1The arrow line 110 in Figure 1 represents the channel current when reading the selected bit corresponding to the dashed box 109, i.e., FG2. As the width of the active region 101 decreases, Summary of the Invention

[0011] The technical problem to be solved by the present invention is to provide a semiconductor device that can form side channels on both sides of a convex active region and can prevent crosstalk between the side channels on both sides of the active region. For this purpose, the present invention also provides a manufacturing method of a semiconductor device.

[0012] To solve the above technical problem, the semiconductor device provided by the present invention includes: an active region bar column protruding above the top surface of a semiconductor substrate.

[0013] Isolation oxide layers are formed on both sides of the active region bar column.

[0014] The active region bar column includes an intermediate dielectric column and semiconductor material columns self-aligned on both sides of the intermediate dielectric column. The top surface of the intermediate dielectric column is flush with the top surfaces of the semiconductor material columns, and the bottom surface of the intermediate dielectric column is located below the top surface of the isolation oxide layer.

[0015] Above the top surface of the isolation oxide layer, the semiconductor material column at the first side of the intermediate dielectric column serves as a first side active region, and the semiconductor material column at the second side of the intermediate dielectric column serves as a second side active region.

[0016] A first side gate structure covers the side of the first side active region and is used to control the on / off of a first side channel at the side of the first side active region.

[0017] A second side gate structure covers the side of the second side active region and is used to control the on / off of a second side channel at the side of the second side active region.

[0018] The intermediate dielectric column isolates the first side active region and the second side active region from each other and thus prevents crosstalk between the first side channel and the second side channel.

[0019] A further improvement is that the bottom surface of the intermediate dielectric column is located above the bottom surface of the active region bar column; the semiconductor material columns on both sides of the intermediate dielectric column are combined together below the bottom surface of the intermediate dielectric column.

[0020] A further improvement is that, along the length direction of the first side channel, a first source-drain region and a second source-drain region are respectively formed in the active region strip columns on both sides of the first side gate structure.

[0021] The first side gate structure and the second side gate structure are symmetrically arranged on both sides of the active region strip column.

[0022] The first source-drain region and the second source-drain region are also located on both sides of the side of the second side gate structure along the length direction of the first side channel.

[0023] A further improvement is that an embedded epitaxial layer is formed in the first source-drain region and the second source-drain region.

[0024] A further improvement is that the semiconductor device is a flash memory cell of a split-gate flash memory.

[0025] The first side gate structure includes:

[0026] The first gate structure, the second gate structure, and the third gate structure on the side of the first side active region are arranged in sequence in the direction from the first source-drain region to the second source-drain region.

[0027] The first gate structure includes a first floating gate and a first control gate stacked in sequence. There is a first floating gate dielectric layer between the first floating gate and the side of the first side active region, and a first inter-gate dielectric layer between the first control gate and the first floating gate.

[0028] The second gate structure includes a word line gate, and there is a first word line gate dielectric layer between the word line gate and the side of the first side active region.

[0029] The third gate structure includes a second floating gate and a second control gate stacked in sequence. There is a second floating gate dielectric layer between the second floating gate and the side of the first side active region, and a second inter-gate dielectric layer between the second control gate and the second floating gate.

[0030] The second side gate structure also includes the first gate structure, the second gate structure, and the third gate structure arranged on the second side active region. The first gate structure, the second gate structure, and the third gate structure of the second side gate structure and the first gate structure, the second gate structure, and the third gate structure of the first side gate structure are symmetric about the center line along the length direction of the active region strip column.

[0031] A further improvement is that the first control gates on both sides of the active region strip column also extend to the top of the active region strip column and are connected together.

[0032] The second control gates on both sides of the active region strip columns also extend to the top of the active region strip columns and are connected together.

[0033] A further improvement is that the flash memory cells of the split-gate flash memory are arranged in an array structure.

[0034] The row structure of the array structure includes:

[0035] The flash memory cells in the same row are aligned and arranged, the first control gates of the flash memory cells in the same row are connected together, and the second control gates of the flash memory cells in the same row are connected together.

[0036] The word line gates located between two active region strip columns in the same row are connected together, the word line gates at odd positions in the same row are all connected to the odd-numbered word lines, and the word line gates at even positions in the same row are all connected to the even-numbered word lines.

[0037] The column structure of the array structure includes:

[0038] The flash memory cells in the same column are aligned and arranged, the first source-drain regions of the flash memory cells in the same column are connected to the first bit line, and the second source-drain regions of the flash memory cells in the same column are connected to the second bit line.

[0039] The first source-drain regions of the flash memory cells share with the first source-drain regions of adjacent flash memory cells, and the second source-drain regions of the flash memory cells share with the second source-drain regions of adjacent flash memory cells.

[0040] Two adjacent column structures have two independent first bit lines and share one second bit line or have two independent second bit lines and share one first bit line.

[0041] A further improvement is that the material of the intermediate dielectric column includes an oxide layer or silicon nitride.

[0042] To solve the above technical problems, the manufacturing method of the semiconductor device provided by the present invention includes the following steps:

[0043] Step 1: Form a first opening in a first mask layer formed on a semiconductor substrate, and the first opening exposes the formation region of the active region strip columns.

[0044] Step 2: Form a first inner sidewall on the inner side surface of the first opening, and the first inner sidewall encloses a second opening.

[0045] Step 3: Etch the semiconductor substrate to form a first trench at the bottom of the second opening.

[0046] Step Four: Fill the first trench with a dielectric layer to form an intermediate dielectric pillar and fill the second opening with a dielectric layer to form a second filling layer. The second mask layer is composed of the first inner sidewall and the second filling layer.

[0047] Step Five: Remove the first mask layer and retain the second mask layer.

[0048] Step Seven: Etch the semiconductor substrate to form a second trench outside the area covered by the second mask layer and form an active region strip pillar in the area covered by the second mask layer.

[0049] The active region strip pillar includes the intermediate dielectric pillar and semiconductor material pillars composed of the semiconductor substrate that are self-aligned on both sides of the intermediate dielectric pillar. The top surfaces of the intermediate dielectric pillar and the semiconductor material pillars are flush.

[0050] Step Eight: Form an isolation oxide layer in the bottom region of the second trench.

[0051] The bottom surface of the intermediate dielectric pillar is located below the top surface of the isolation oxide layer.

[0052] Above the top surface of the isolation oxide layer, the semiconductor material pillar at the first side of the intermediate dielectric pillar serves as the first side active region, and the semiconductor material pillar at the second side of the intermediate dielectric pillar serves as the second side active region.

[0053] Step Nine: Form a first side gate structure and a second side gate structure.

[0054] The first side gate structure covers the side of the first side active region and is used to control the on / off of the first side channel at the side of the first side active region.

[0055] The second side gate structure covers the side of the second side active region and is used to control the on / off of the second side channel at the side of the second side active region.

[0056] The intermediate dielectric pillar isolates the first side active region and the second side active region from each other and thus prevents crosstalk between the first side channel and the second side channel.

[0057] A further improvement is that the bottom surface of the intermediate dielectric pillar is located above the bottom surface of the active region strip pillar; the semiconductor material pillars on both sides of the intermediate dielectric pillar are merged together below the bottom surface of the intermediate dielectric pillar.

[0058] A further improvement is that in step ten, along the length direction of the first side channel, a first source-drain region and a second source-drain region are respectively formed in the active region strip columns on both sides of the side of the first side gate structure.

[0059] The first side gate structure and the second side gate structure are symmetrically arranged on both sides of the active region strip column.

[0060] The first source-drain region and the second source-drain region are also located on both sides of the side of the second side gate structure along the length direction of the first side channel.

[0061] A further improvement is that when forming the first source-drain region and the second source-drain region, an embedded epitaxial layer is further formed in the first source-drain region and the second source-drain region.

[0062] A further improvement is that the semiconductor device is a flash memory cell of a split-gate flash memory.

[0063] The first side gate structure includes:

[0064] The first gate structure, the second gate structure, and the third gate structure on the side of the first side active region are arranged in sequence in the direction from the first source-drain region to the second source-drain region.

[0065] The first gate structure includes a first floating gate and a first control gate stacked in sequence. There is a first floating gate dielectric layer between the first floating gate and the side of the first side active region, and a first inter-gate dielectric layer between the first control gate and the first floating gate.

[0066] The second gate structure includes a word line gate, and there is a first word line gate dielectric layer between the word line gate and the side of the first side active region.

[0067] The third gate structure includes a second floating gate and a second control gate stacked in sequence. There is a second floating gate dielectric layer between the second floating gate and the side of the first side active region, and a second inter-gate dielectric layer between the second control gate and the second floating gate.

[0068] The second side gate structure also includes the first gate structure, the second gate structure, and the third gate structure arranged on the second side active region. The first gate structure, the second gate structure, and the third gate structure of the second side gate structure and the first gate structure, the second gate structure, and the third gate structure of the first side gate structure are symmetric about the center line along the length direction of the active region strip column.

[0069] A further improvement is that the first control gates on both sides of the active region strip columns further extend to the top of the active region strip columns and are connected together.

[0070] The second control gates on both sides of the active region strip columns further extend to the top of the active region strip columns and are connected together.

[0071] A further improvement is that the flash memory cells of the split-gate flash memory are arranged in an array structure.

[0072] The row structure of the array structure includes:

[0073] The flash memory cells in the same row are aligned and arranged, the first control gates of the flash memory cells in the same row are connected together, and the second control gates of the flash memory cells in the same row are connected together.

[0074] The word line gates located between two active region strip columns in the same row are connected together, the word line gates at odd positions in the same row are all connected to the odd bit lines, and the word line gates at even positions in the same row are all connected to the even bit lines.

[0075] The column structure of the array structure includes:

[0076] The flash memory cells in the same column are aligned and arranged, the first source / drain regions of the flash memory cells in the same column are connected to the first bit line, and the second source / drain regions of the flash memory cells in the same column are connected to the second bit line.

[0077] The first source / drain regions of the flash memory cells share with the first source / drain regions of adjacent flash memory cells, and the second source / drain regions of the flash memory cells share with the second source / drain regions of adjacent flash memory cells.

[0078] Two adjacent column structures have two independent first bit lines and share one second bit line or have two independent second bit lines and share one first bit line.

[0079] A further improvement is that the material of the intermediate dielectric column includes an oxide layer or silicon nitride.

[0080] A further improvement is that the material of the first inner sidewall includes silicon nitride.

[0081] Step four includes the following sub-steps:

[0082] Oxidize the semiconductor substrate exposed on the inner surface of the first trench to form a first oxide layer.

[0083] Form a second silicon nitride layer to completely fill the first trench and the second opening; stack the first oxide layer and the second silicon nitride layer filled in the first trench to form the intermediate dielectric column, and use the second silicon nitride layer filled in the second opening as the second filling layer and form the second mask layer.

[0084] A further improvement is that step one includes the following sub-steps:

[0085] Step 11: Form a dummy mask layer.

[0086] Perform patterned etching on the dummy mask layer to form a first dummy mask strip, the first dummy mask strip covering the formation region of the active region strip column, and removing the dummy mask layer outside the formation region of the active region strip column.

[0087] Step 12: Form the first mask layer to completely fill the spaced region between the first dummy mask strips.

[0088] Step 13: Remove the first dummy mask strip and form the first opening in the removed region of the first dummy mask strip.

[0089] A further improvement is that the material of the dummy mask layer is silicon nitride.

[0090] The material of the first mask layer is polysilicon.

[0091] Before step 12, it further includes: forming a second oxide layer on the surface of the semiconductor substrate outside the first dummy mask strip.

[0092] In subsequent step five, the second oxide layer serves as an etching stop layer.

[0093] A further improvement is that in step 12, polysilicon deposition is used to form the first mask layer and the CMP process is used to make the top surface of the first mask layer flush with the top surface of the first dummy mask strip.

[0094] After step 12 is completed and before step 13, it further includes:

[0095] Perform back etching on the first mask layer to make the top surface of the first mask layer lower than the top surface of the first dummy mask strip.

[0096] Form a third oxide layer on the top surface of the first mask layer.

[0097] A further improvement is that in step nine, after forming the first side gate structure and the second side gate structure, the second mask layer remains on top of the active region strip column, the top surface of the word line gate is flush with the top surface of the second mask layer, and the first control gate further extends above the top surface of the second mask layer on top of the active region strip column.

[0098] The present invention makes a special arrangement for the process structure of the active region strip column protruding above the top surface of the semiconductor substrate. Different from the prior art where the active region strip column is directly formed by patterning and etching the material of the semiconductor substrate, an intermediate dielectric column is provided in the middle region of the active region strip column of the present invention, and the intermediate dielectric column separates the semiconductor material columns on both sides. In this way, the crosstalk path of the side channels formed on the sides of the semiconductor material columns on both sides will be cut off, thereby preventing crosstalk between the side channels on both sides of the active region strip column.

[0099] Since the top surface of the intermediate dielectric column of the present invention is flush with the top surfaces of the semiconductor material columns on both sides, even if top channels are formed on the top surfaces of the semiconductor metamaterial columns on both sides, the top channels can serve as the conduction channels during the normal operation of the semiconductor device or the conduction channels formed by coupling when the gate voltage of the semiconductor device is too large. The intermediate dielectric column can also cut off the top channels on both sides, thereby ensuring that no crosstalk occurs between the side channels on both sides of the active region strip column.

[0100] The intermediate dielectric column and the semiconductor material column of the present invention can be realized by a self-alignment process. Only by using a photomask for defining the active region strip column once and combining self-alignment processes such as the inner sidewalls formed by self-alignment and the corresponding etching and dielectric layer deposition processes can the intermediate dielectric column and the semiconductor material column be obtained. Therefore, the present invention does not increase the lithography level and has the characteristic of low process cost.

[0101] The semiconductor device of the present invention is particularly suitable for use as the cell structure of a flash memory, i.e., a flash memory cell. In the present invention, since the two side channels of the active region strip column do not crosstalk, storage bits can be symmetrically arranged on both sides of the active region strip column to achieve multi-bit storage, and the storage bits do not interfere with each other.

[0102] The flash memory cell structure of the present invention can further adopt the NORD structure. In this way, a set of gate structures of the NORD structure can be formed on each side of the active region strip column, that is, the second gate structure composed of word line gates and the first and third gate structures symmetrically arranged on both sides of the second gate structure and composed of a floating gate and a control gate stacked. The NORD structure can achieve the storage of 2-bit data. In this way, 4-bit data storage can be achieved on two sides of the active region strip column between a set of source-drain regions, that is, the first source-drain region and the second source-drain region. The channel between the first source-drain region and the second source-drain region is controlled by three gate structures. Therefore, it is equivalent to 3 transistors (T). So, the present invention can implement a 0.75T flash memory cell and can improve the crosstalk between the side channels of the 0.75T flash memory, thereby improving the performance of the flash memory.

[0103] In the present invention, after eliminating the crosstalk of the side channels, it is beneficial to reduce the width of the active region strip column. That is to say, the reduction of the width of the active region strip column is not limited by the crosstalk of the side channels. At the same time, the length and width of the side channels are not limited by the width of the active region strip column. Therefore, after the width of the active region strip column is reduced, the length and width of the side channels can be unaffected, and the conductivity of the device is not affected. In the application of flash memory, it will not affect the current window when the stored bit in the flash memory is "1", that is, when it is turned on, during the miniaturization process.

[0104] In addition, in the present invention, the intermediate dielectric column is located inside the active region strip column and will not affect other structures of the device. Therefore, after being applied to flash memory, the operation mode of the flash memory will not be affected. After forming the active region strip column, the subsequent manufacturing process will not be affected either. BRIEF DESCRIPTION OF THE DRAWINGS

[0105] The present invention will be further described in detail below with reference to the drawings and specific embodiments:

[0106] Figure 1 is the layout of an existing semiconductor device;

[0107] Figure 2A is along Figure 1 the cross-sectional structure schematic diagram of the AA line in

[0108] Figure 2B is along Figure 1 the cross-sectional structure schematic diagram of the AA line in

[0109] Figure 2C is along Figure 1 the cross-sectional structure schematic diagram of the CC line in

[0110] Figure 2D is along Figure 1 the cross-sectional structure schematic diagram of the DD line in

[0111] Figure 2E is alongFigure 1 Schematic cross-sectional structure diagram corresponding to the XY plane;

[0112] Figure 3A is the layout of the semiconductor device according to an embodiment of the present invention;

[0113] Figure 3B is the current schematic diagram during programming of the semiconductor device according to an embodiment of the present invention;

[0114] Figure 3C is the current schematic diagram during reading of the semiconductor device according to an embodiment of the present invention;

[0115] Figure 3D is the current schematic diagram during erasing of the semiconductor device according to an embodiment of the present invention;

[0116] Figure 4A is along Figure 3A Schematic cross-sectional structure diagram along line AA in;

[0117] Figure 4B is along Figure 3A Schematic cross-sectional structure diagram along line BB in;

[0118] Figure 4C is along Figure 3A Schematic cross-sectional structure diagram along line CC in;

[0119] Figure 4D is along Figure 3A Schematic cross-sectional structure diagram along line DD in;

[0120] Figure 4E is along Figure 3A Schematic cross-sectional structure diagram along line EE in;

[0121] Figure 4F is along Figure 3A Schematic cross-sectional structure diagram along line FF in;

[0122] Figure 4G is along Figure 3A Schematic cross-sectional structure diagram along line GG in;

[0123] Figure 4H is along Figure 3A Schematic cross-sectional structure diagram corresponding to the XY plane;

[0124] Figure 5 is Figure 3A corresponding simulation diagram;

[0125] Figure 6A is Figure 4A corresponding simulation diagram;

[0126] Figure 6B is Figure 4BThe corresponding simulation diagram;

[0127] Figure 6C is Figure 4C The corresponding simulation diagram;

[0128] Figure 6D is Figure 4D The corresponding simulation diagram;

[0129] Figure 6E is Figure 4E The corresponding simulation diagram;

[0130] Figure 6F is Figure 4F The corresponding simulation diagram;

[0131] Figure 6G is Figure 4G The corresponding simulation diagram;

[0132] Figure 6H It is a schematic diagram of preventing crosstalk of the side channel current inside the active region bar column in the semiconductor device of the embodiment of the present invention;

[0133] Figure 6I It is a schematic diagram of preventing crosstalk of the side channel current on the top surface of the active region bar column in the semiconductor device of the embodiment of the present invention;

[0134] Figure 7 It is the layout below the first via layer of the array structure of the semiconductor device of the embodiment of the present invention;

[0135] Figure 8A is Figure 7 The layout with the first metal layer added on the basis of;

[0136] Figure 8B is Figure 8A The layout with the second metal layer added on the basis of;

[0137] Figure 8C is Figure 8B The layout with the third metal layer added on the basis of;

[0138] Figure 9A - Figure 9L It is a schematic diagram of the device structure in each step of the manufacturing method of the semiconductor device of the embodiment of the present invention. Detailed implementation manners

[0139] Such as Figure 1 shown, it is the layout of the existing semiconductor device; Figure 2A is the cross-sectional structure schematic diagram along the Figure 1 AA line in; Figure 2B is the cross-sectional structure schematic diagram along the Figure 1 AA line in; Figure 2C is the cross-sectional structure schematic diagram along the Figure 1Schematic cross-sectional structure diagram of the CC line; Figure 2D is along Figure 1 Schematic cross-sectional structure diagram of the DD line; Figure 2E is along Figure 1 Schematic cross-sectional structure diagram corresponding to the XY plane; In an embodiment of the present invention, the semiconductor device includes: an active region bar column 201 protruding above the top surface of the semiconductor substrate 201'.

[0140] Isolation oxide layers 202 are formed on both sides of the active region bar column 201. In some examples, the isolation oxide layers 202 are formed by a shallow trench isolation process and are shallow trench oxide layers.

[0141] The active region bar column 201 includes an intermediate dielectric column 201b and semiconductor material columns 201a self-aligned on both sides of the intermediate dielectric column 201b. The top surface of the intermediate dielectric column 201b is flush with the top surface of the semiconductor material columns 201a, and the bottom surface of the intermediate dielectric column 201b is located below the top surface of the isolation oxide layer 202.

[0142] Above the top surface of the isolation oxide layer 202, the semiconductor material column 201a at the first side of the intermediate dielectric column 201b serves as a first side active region, and the semiconductor material column 201a at the second side of the intermediate dielectric column 201b serves as a second side active region.

[0143] The first side gate structure covers the side of the first side active region and is used to control the on / off of the first side channel at the side of the first side active region.

[0144] The second side gate structure covers the side of the second side active region and is used to control the on / off of the second side channel at the side of the second side active region.

[0145] The intermediate dielectric column 201b isolates the first side active region and the second side active region from each other and thus prevents crosstalk between the first side channel and the second side channel.

[0146] In an embodiment of the present invention, the bottom surface of the intermediate dielectric column 201b is located above the bottom surface of the active region bar column 201; the semiconductor material columns 201a on both sides of the intermediate dielectric column 201b are merged together below the bottom surface of the intermediate dielectric column 201b. That is, the bottom surface of the intermediate dielectric column 201b only needs to be lower than the top surface of the isolation oxide layer 202, which is sufficient to prevent crosstalk between the two side channels.

[0147] In some embodiments, the material of the intermediate dielectric column 201b includes an oxide layer or silicon nitride.

[0148] In an embodiment of the present invention, along the length direction of the first side channel, a first source-drain region 206a and a second source-drain region 206b are respectively formed in the active region bar-shaped columns 201 on both sides of the side of the first side gate structure. The first source-drain region 206a and the second source-drain region 206b are completely symmetric structures, and hereinafter, the first source-drain region 206a and the second source-drain region 206b will also be uniformly referred to as the source-drain region 206. Which of the first source-drain region 206a and the second source-drain region 206b serves as the source region and which serves as the drain region completely depends on the voltage applied during subsequent operation. The source-drain region 206 corresponding to the source voltage serves as the first source-drain region 206a, and the source-drain region 206 corresponding to the drain voltage serves as the second source-drain region 206b.

[0149] The first side gate structure and the second side gate structure are symmetrically arranged on both sides of the active region bar-shaped column 201.

[0150] The first source-drain region 206a and the second source-drain region 206b are also located on both sides of the side of the second side gate structure along the length direction of the first side channel.

[0151] An embedded epitaxial layer is formed in the first source-drain region 206a and the second source-drain region 206b. For the structure of the embedded epitaxial layer, please refer to Figure 4A as shown.

[0152] Figure 3A In, the dashed box 301 corresponds to the unit structure of the semiconductor device. In the dashed box 301, the two source-drain regions 206 are respectively marked with 206a and 206b, that is, the first source-drain region 206a and the second source-drain region 206b respectively. In Figure 3A As shown in the X direction, the first side gate structure and the second side gate structure are respectively located on the left and right sides of the active region bar-shaped column 201.

[0153] In an embodiment of the present invention, the semiconductor device is a flash memory cell of a split-gate flash memory, and the dashed box 301 is one such flash memory cell. Now, in combination with Figure 3A the structure in the dashed box 301 in, the gate structure of the embodiment of the present invention is further described as follows:

[0154] The first side gate structure includes:

[0155] The first gate structure 304a, the second gate structure 304b, and the third gate structure 304c on the side of the first side active region are arranged in sequence in the direction from the first source-drain region 206a to the second source-drain region 206b. The markings of the first gate structure 304a, the second gate structure 304b, and the third gate structure 304c are shown in Figure 4H . The Figure 4H X direction and Y direction in Figure 3A are the same as the X direction and Y direction in Figure 4H , only the viewing angles are different.

[0156] The first gate structure 304a includes a first floating gate 203a and a first control gate 204a stacked in sequence. A first floating gate dielectric layer is interposed between the first floating gate 203a and the side of the first side active region. A first inter-gate dielectric layer 303 is interposed between the first control gate 204a and the first floating gate 203a. The first inter-gate dielectric layer 303 is shown in Figure 4C .

[0157] The second gate structure 304b includes a word line gate 205. A first word line gate dielectric layer is interposed between the word line gate 205 and the side of the first side active region.

[0158] The third gate structure 304c includes a second floating gate 203b and a second control gate 204b stacked in sequence. A second floating gate dielectric layer is interposed between the second floating gate 203b and the side of the first side active region. A second inter-gate dielectric layer is interposed between the second control gate 204b and the second floating gate 203b.

[0159] In the embodiment of the present invention, since the first floating gate 203a and the second floating gate 203b are symmetric, when shown separately in the cross-section, both are represented by the floating gate 203. For example, in Figure 4C , the floating gate 203 represents either the first floating gate 203a or the second floating gate 203b.

[0160] Similarly, in Figure 4C , the control gate 204 also represents either the first control gate 204a or the second control gate 204b.

[0161] The second side gate structure also includes the first gate structure 304a, the second gate structure 304b, and the third gate structure 304c disposed on the second side active region. The first gate structure 304a, the second gate structure 304b, and the third gate structure 304c of the second side gate structure and the first gate structure 304a, the second gate structure 304b, and the third gate structure 304c of the first side gate structure are symmetric about the center line in the length direction of the active region strip column 201.

[0162] In an embodiment of the present invention, the first control gates 204a on both sides of the active region strip column 201 further extend to the top of the active region strip column 201 and are connected together.

[0163] The second control gates 204b on both sides of the active region strip column 201 further extend to the top of the active region strip column 201 and are connected together.

[0164] As Figure 4C shown, the control gates 204 on the same row are connected together. Figure 3A In the top view structure of, in order to show each floating gate 203, only a partial region of the control gate 204 is shown. Actually, the control gate 204 will form a strip structure in the top view. Figure 4C In, a second mask layer 302 is further formed on the top of the active region strip column 201, and the active region strip column 201 is defined by the second mask layer 302.

[0165] As Figure 4B shown, the top surface of the word line gate 205 is flush with the top surface of the second mask layer 302, that is, the word line gate 205 does not extend above the top surface of the active region strip column 201, so a conduction channel will not be formed on the top surface of the active region strip column 201.

[0166] As Figure 3B shown, it is a current schematic diagram during programming of a semiconductor device according to an embodiment of the present invention; Figure 3B In, the four floating gates 203 corresponding to the middle active region strip column 201 are further marked as FG1, FG2, FG3, and FG4, and the four floating gates 203 can store 4-bit data; the left and right control gates 205 are respectively marked as WL0-odd and WL0-even, and the upper and lower rows of control gates 204 are respectively marked as CGL and CGR.

[0167] Among them, the constituent structure of the first side gate structure includes: CGL, FG1, WL0-odd, FG2, and CGR. The constituent structure of the second side gate structure includes: CGL, FG3, WL0-even, FG4, and CGR.

[0168] In the first side gate structure, FG1 and CGL are superimposed to form the first gate structure 304a, WL0-odd serves as the second gate structure 304b, and FG2 and CGR are superimposed to form the third gate structure 304c;

[0169] In the second side gate structure, FG3 and CGL are superimposed to form the first gate structure 304a, WL0-even serves as the second gate structure 304b, and FG4 and CGR are superimposed to form the third gate structure 304c.

[0170] The first source-drain region 206a is connected to the source through the contact hole 207a, Figure 3B where the source is also represented by Source; the second source-drain region 206b is connected to the drain through the contact hole 207b, Figure 3B where the drain is also represented by Drain. Moreover, the second source-drain region 206b of the middle active region bar 201 and the second source-drain region 206b of the right active region bar 201 are connected together by a metal wire, so the two share the drain, that is, Drain (share). Figure 3B Among them, each floating gate 203 that has nothing to do with the side of the middle active region bar 201 is represented by FG. The contact hole 207c on the upper side of the right active region bar 201 is connected to the inhibit potential, indicating that when the inhibit potential is required, the semiconductor device on the right active region bar 201 is not turned on.

[0171] Figure 3B During programming, FG2 corresponding to the dashed box 1 is the selected bit, that is, FG2 needs to be programmed. At this time, the applied voltages are as follows: the voltage of WL0-odd needs to turn on the channel segment controlled by WL0-odd, and the voltage of WL0-even needs to turn off the channel segment controlled by WL0-even; the voltage of CGL needs to turn on the channel segment controlled by FG1, and the voltage of CGR needs to be a high voltage to realize the source injection of channel electrons into FG2 to program FG2. The channel current is as shown by the arrow line 2, and the source injection of electrons is as shown by the arrow line 3. The injected electrons are represented by e. Among them, the source, that is, Source, is applied with a low voltage, and the drain, that is, Drain, is applied with a positive voltage, so that electrons can flow from Source to Drain, that is, along the arrow line 2. Inhibit needs to be applied with a voltage equal to Drain.

[0172] As Figure 3C shown, it is a schematic diagram of the current during the read operation of the semiconductor device according to an embodiment of the present invention; when reading FG2, the applied voltages are as follows: the voltage of WL0-odd needs to turn on the channel segment controlled by WL0-odd, and the voltage of WL0-even needs to turn off the channel segment controlled by WL0-even; the voltage of CGL needs to turn on the channel segment controlled by FG1, CGR is not powered, and the conduction state of the channel segment controlled by FG2 is completely determined by the storage state of FG2. A positive voltage is applied to the source, i.e., Source, and a voltage of 0V is applied to the drain, i.e., Drain, so that electrons can flow from Drain to Source, i.e., along arrow line 4, and the voltage equal to that of Drain needs to be applied to Inhibit.

[0173] As Figure 3D shown, it is a schematic diagram of the current during the erase operation of the semiconductor device according to an embodiment of the present invention; when erasing FG2, the erasure at this time includes erasing multiple memory bits including FG2. The applied voltages are as follows: the voltages of WL0-odd and WL0-even are both positive high voltages, and the voltages of CGL and CGR are both negative high voltages. The positive and negative high voltages cause the electrons in the corresponding floating gates 203, including those in FG2, to be erased, as shown by arrow line 5.

[0174] It is necessary to turn on the channel segment controlled by WL0-odd, and the voltage of WL0-even needs to turn off the channel segment controlled by WL0-even; the voltage of CGL needs to turn on the channel segment controlled by FG1, CGR is not powered, and the conduction state of the channel segment controlled by FG2 is completely determined by the storage state of FG2. A positive voltage is applied to the source, i.e., Source, and a voltage of 0V is applied to the drain, i.e., Drain, so that electrons can flow from Drain to Source, i.e., along arrow line 4, and the voltage equal to that of Drain needs to be applied to Inhibit.

[0175] In some embodiments, the specific values of the voltages applied during various operations of the semiconductor device according to an embodiment of the present invention can be as shown in Table 1.

[0176] Table 1

[0177] Operation WL0 - odd WL0 - even CGL CGR Source Drain Inhibit PGM 1.2V -0.2V 6V 9V Vdp 4V 4V Read 3V -0.2V 5.5V 0V 0.5V 0V 0V Erase 8V 8V -7V -7V -- -- --

[0178] In Table 1, PGM is the abbreviation of program for programming, read is for reading, and Erase is for erasing.

[0179] To understand the embodiment of the present invention more clearly, further reference can be made to Figure 5 , Figure 6A to Figure 6G , which respectively correspond to Figure 3A and Figure 4A - Figure 4G simulation diagrams.

[0180] In addition, as Figure 6H shown, it is a schematic diagram of preventing crosstalk of the side channel current inside the active region strip column in the semiconductor device according to an embodiment of the present invention; in Figure 6H , due to the isolation of the intermediate dielectric column 201b, the side channel on the right side of the active region strip column 201 corresponding to the arrow line 6 will not be crosstalked with the arrow line 7.

[0181] As Figure 6I shown, it is a schematic diagram of preventing crosstalk of the side channel current on the top surface of the active region strip column in the semiconductor device according to an embodiment of the present invention; Figure 6I in, even if a relatively high voltage CGL passes through the top surface of the active region strip column 201, due to the isolation of the intermediate dielectric column 201b, crosstalk corresponding to the arrow line 8 will not occur.

[0182] Each of the flash memory cells of the split-gate flash memory is arranged in an array structure.

[0183] As Figure 7 shown, it is a layout below the first via layer of the array structure of the semiconductor device according to an embodiment of the present invention; Figure 3A The corresponding area is Figure 7 the area shown by the dashed box 401 in Figure 7 . In order to more clearly represent the corresponding correlation,

[0184] The row structure of the array structure includes:

[0185] The flash memory cells in the same row are aligned, the first control gates 204a of each of the flash memory cells in the same row are connected together, and the second control gates 204b of each of the flash memory cells in the same row are connected together.

[0186] The word line gates 205 between two active region strip columns 201 in the same row are connected together, that is, Figure 3A in, the same word line gate 205 is shared by the two active region strip columns 201 on both sides. The word line gates 205 at the odd positions in the same row are all connected to the odd word line WL_odd, and the word line gates 205 at the even positions in the same row are all connected to the even word line WL_even.

[0187] The column structure of the array structure includes:

[0188] The flash memory cells in the same column are aligned, the first source / drain regions 206a of each of the flash memory cells in the same column are connected to the first bit line, and the second source / drain regions 206b of each of the flash memory cells in the same column are connected to the second bit line. ByFigure 7 As can be seen, taking the rightmost source region bar 201 as an example, one bit line BL is disposed on each side of the source region bar 201. One of them serves as the first bit line, and the other serves as the second bit line. Then, on the column corresponding to the rightmost source region bar 201, the source-drain regions 206 are alternately arranged on the bit lines BL on the left and right sides.

[0189] The first source-drain region 206a of each flash memory cell is shared with the first source-drain region 206a of an adjacent flash memory cell, and the second source-drain region 206b of each flash memory cell is shared with the second source-drain region 206b of an adjacent flash memory cell. For example, Figure 7 the second bit line BL on the right in the figure is shared by the source-drain regions 206 corresponding to the first and second source region bars 201 on the right. The two source-drain regions 206 sharing the bit line BL are connected together through Figure 8B the metal wire 404 composed of the second metal layer shown in the figure.

[0190] Two adjacent column structures have two independent first bit lines and share one second bit line, or have two independent second bit lines and share one first bit line.

[0191] As Figure 8A shown, it is the layout adding the first metal layer on the basis of Figure 7 ; Figure 8A The figure shows a plurality of metal wires 402 composed of the first metal layer. The metal wires 402 are used as the lead wires of the word line gates 205 at various positions. Figure 8A In the figure, the word line gates 205 at odd positions are led upward in the Y direction through the metal wires 402, and the word line gates 205 at even positions are led downward in the Y direction through the metal wires 402.

[0192] As Figure 8B shown, it is the layout adding the second metal layer on the basis of Figure 8A ; Figure 8A The figure shows a plurality of metal wires 403 and 404 composed of the second metal layer. The metal wires 403 serve as the word lines. Figure 8B The figure shows 4 rows. Each row has an odd word line WL_odd and an even word line WL_even. The word line gates 205 at odd positions in the same row are connected to the odd word line WL_odd located above in the Y direction through the upward-extending metal wires 402. The word line gates 205 at even positions in the same row are connected to the even word line WL_odd located below in the Y direction through the downward-extending metal wires 402. Figure 8B ; Figure 8B ;Figure 8B Among them, the 4 odd-numbered word lines WL_odd and one even-numbered word line WL_even are also respectively represented as: WL0_odd and WL0_even, WL1_odd and WL1_even, WL2_odd and WL2_even, WL3_odd and WL3_even.

[0193] Figure 8B Among them, the metal line 404 realizes the connection of the source-drain regions 206 with shared drains.

[0194] Such as Figure 8C shown, it is Figure 8B the layout with the addition of a third metal layer on the basis of Figure 8C Multiple bit lines BL composed of the third metal layer are shown, and the third-level vias 406 for leading out the control gates 204 are also shown. Figure 8C Nine bit lines are shown, represented by BL0, BL1 to BL8 respectively. Since the control gates 204 in the same row are connected together, they can be led out through a corresponding third-level via 406.

[0195] In the embodiment of the present invention, a special process structure is set for the active region bar column 201 protruding above the top surface of the semiconductor substrate 201'. Different from the prior art where the active region bar column 201 is directly formed by patterning and etching the material of the semiconductor substrate 201', an intermediate dielectric column 201b is provided in the middle region of the active region bar column 201 of the embodiment of the present invention. The intermediate dielectric column 201b separates the semiconductor material columns 201a on both sides, so that the crosstalk path of the side channels formed on the sides of the semiconductor material columns 201a on both sides will be cut off, thereby preventing crosstalk between the side channels on both sides of the active region bar column 201.

[0196] Since the top surface of the intermediate dielectric column 201b in the embodiment of the present invention is flush with the top surfaces of the semiconductor material columns 201a on both sides, even if top channels are formed on the top surfaces of the semiconductor metamaterial columns on both sides, and the top channels can be used as conduction channels during the normal operation of the semiconductor device or conduction channels formed by coupling when the gate voltage of the semiconductor device is too large, the intermediate dielectric column 201b can also cut off the top channels on both sides, thereby ensuring that crosstalk will not occur between the side channels on both sides of the active region bar column 201.

[0197] The intermediate dielectric pillar 201b and the semiconductor material pillar 201a in the embodiments of the present invention can be realized by a self-alignment process. Only by using a photomask for defining the active region strip pillar 201 once and combining with a self-alignment process such as the inner sidewall formed by self-alignment and the corresponding etching and dielectric layer deposition processes can the intermediate dielectric pillar 201b and the semiconductor material pillar 201a be obtained. Therefore, the embodiments of the present invention do not increase the lithography levels and have the characteristic of low process cost.

[0198] The semiconductor device in the embodiments of the present invention is particularly suitable for being used as the cell structure of a flash memory, that is, a flash memory cell. In the embodiments of the present invention, since the two side channels of the active region strip pillar 201 do not crosstalk, storage bits can be symmetrically arranged on both sides of the active region strip pillar 201 to realize multi-bit storage, and the storage bits do not interfere with each other.

[0199] The flash memory cell structure in the embodiments of the present invention can further adopt a NORD structure. In this way, a group of gate structures of the NORD structure can be formed on each side of the active region strip pillar 201, that is, the second gate structure 304b composed of the word line gate 205 and the first and third gate structures 304c symmetrically arranged on both sides of the second gate structure 304b and formed by superimposing a floating gate and a control gate. The NORD structure can realize the storage of 2-bit data; in this way, 4-bit data storage can be realized on the two sides of the active region strip pillar 201 between a group of source-drain regions, that is, between the first source-drain region 206a and the second source-drain region 206b. The channel between the first source-drain region 206a and the second source-drain region 206b is controlled by three gate structures, so it is equivalent to 3 transistors (T). Therefore, the embodiments of the present invention can realize a 0.75T flash memory cell and can improve the crosstalk between the side channels of the 0.75T flash memory, thereby improving the performance of the flash memory.

[0200] In the embodiments of the present invention, after the crosstalk of the side channels is eliminated, it is beneficial to reduce the width of the active region strip pillar 201, that is, the reduction of the width of the active region strip pillar 201 is not limited by the crosstalk of the side channels; at the same time, the length and width of the side channels are not limited by the width of the active region strip pillar 201. Therefore, after the width of the active region strip pillar 201 is reduced, the length and width of the side channels are not affected, and the conductivity of the device is not affected; in the application of the flash memory, the current window when the storage bit of the flash memory is "1", that is, conducting, is not affected during the miniaturization process.

[0201] In addition, in the embodiments of the present invention, the intermediate dielectric pillar 201b is located inside the active region strip pillar 201 and does not affect other structures of the device. Therefore, after being applied to the flash memory, the operation mode of the flash memory is not affected; after the active region strip pillar 201 is formed, the subsequent manufacturing process is not affected either.

[0202] Such as Figure 9A to Figure 9LAs shown, it is a schematic diagram of the device structure in each step of the manufacturing method of the semiconductor device according to the embodiment of the present invention; the manufacturing method of the semiconductor device according to the embodiment of the present invention includes the following steps:

[0203] Step 1, as Figure 9D shown, form a first opening 505 in the first mask layer 503 formed on the semiconductor substrate 201', and the first opening 505 opens the formation area of the active region bar 201.

[0204] In the method according to the embodiment of the present invention, Step 1 includes the following sub-steps:

[0205] Step 11, as Figure 9A shown, form a dummy mask layer.

[0206] Perform patterned etching on the dummy mask layer to form a first dummy mask bar 502, and the first dummy mask bar 502 covers the formation area of the active region bar 201, and the dummy mask layer outside the formation area of the active region bar 201 is removed.

[0207] In some embodiments of the method, the material of the dummy mask layer is silicon nitride.

[0208] Before Step 12, it further includes: forming a second oxide layer 501 on the surface of the semiconductor substrate 201' outside the first dummy mask bar 502.

[0209] In subsequent Step 5, the second oxide layer 501 serves as an etching stop layer.

[0210] Step 12, as Figure 9B shown, form the first mask layer 503 to completely fill the interval area between the first dummy mask bars 502.

[0211] In some embodiments of the method, the material of the first mask layer 503 is polysilicon.

[0212] In Step 12, deposit polysilicon to form the first mask layer 503 and use the CMP process to make the top surface of the first mask layer 503 flush with the top surface of the first dummy mask bar 502.

[0213] After Step 12 is completed and before Step 13, it further includes:

[0214] As Figure 9C shown, perform back-etching on the first mask layer 503 to make the top surface of the first mask layer 503 lower than the top surface of the first dummy mask bar 502.

[0215] Form a third oxide layer 504 on the top surface of the first mask layer 503.

[0216] Step 13, as Figure 9D shown, remove the first pseudo-mask bar 502 and form the first opening 505 in the area where the first pseudo-mask bar 502 is removed.

[0217] Step two, as Figure 9E shown, form a first inner wall 506 on the inner side surface of the first opening 505, and the first inner wall 506 encloses a second opening 505'.

[0218] In some embodiments of the method, the material of the first inner wall 506 includes silicon nitride.

[0219] Step three, as Figure 9F shown, etch the semiconductor substrate 201' to form a first trench 507 at the bottom of the second opening 505'.

[0220] Step four, as Figure 9G shown, fill a dielectric layer in the first trench 507 to form an intermediate dielectric column 201b and fill a dielectric layer in the second opening 505' to form a second filling layer, and the second mask layer 302 is composed of the first inner wall 506 and the second filling layer.

[0221] In the method of the embodiment of the present invention, the material of the intermediate dielectric column 201b includes an oxide layer or silicon nitride. Step four includes the following sub-steps:

[0222] As Figure 9F shown, oxidize the semiconductor substrate 201' exposed on the inner surface of the first trench 507 to form a first oxide layer 508.

[0223] As Figure 9G shown, form a second silicon nitride layer to completely fill the first trench 507 and the second opening 505'; the intermediate dielectric column 201b is formed by superimposing the first oxide layer 508 and the second silicon nitride layer filled in the first trench 507, and the second silicon nitride layer filled in the second opening 505' serves as the second filling layer and forms the second mask layer 302.

[0224] Step five, as Figure 9H shown, remove the first mask layer 503 and retain the second mask layer 302.

[0225] Step seven, as Figure 9I shown, etch the semiconductor substrate 201' to form a second trench 509 outside the area covered by the second mask layer 302 and form an active region bar column 201 in the area covered by the second mask layer 302.

[0226] The active region bar column 201 includes the intermediate dielectric column 201b and semiconductor material columns 201a composed of the semiconductor substrate 201' that are self-aligned on both sides of the intermediate dielectric column 201b. The top surface of the intermediate dielectric column 201b is flush with the top surfaces of the semiconductor material columns 201a.

[0227] In the method of the embodiment of the present invention, the bottom surface of the intermediate dielectric column 201b is located above the bottom surface of the active region bar column 201; the semiconductor material columns 201a on both sides of the intermediate dielectric column 201b are merged together under the bottom surface of the intermediate dielectric column 201b.

[0228] Step Eight: As Figure 9K shown, an isolation oxide layer 202 is formed in the bottom region of the second trench 509.

[0229] The bottom surface of the intermediate dielectric column 201b is located below the top surface of the isolation oxide layer 202.

[0230] Above the top surface of the isolation oxide layer 202, the semiconductor material column 201a at the first side of the intermediate dielectric column 201b serves as the first side active region, and the semiconductor material column 201a at the second side of the intermediate dielectric column 201b serves as the second side active region.

[0231] In the method of the embodiment of the present invention, Step Eight includes the following sub-steps:

[0232] As Figure 9J shown, an isolation oxide layer 202 is formed to completely fill the second trench 509 and extend outside the second trench 509. Chemical mechanical polishing is performed to make the top surface of the isolation oxide layer 202 flush with the top surface of the second mask layer 302.

[0233] As Figure 9K shown, the isolation oxide layer 202 is etched back so that the isolation oxide layer 202 remains only in the bottom region of the second trench 509.

[0234] Step Nine: Form a first side gate structure and a second side gate structure.

[0235] The first side gate structure covers the side of the first side active region and is used to control the on / off of the first side channel at the side of the first side active region.

[0236] The second side gate structure covers the side of the second side active region and is used to control the on / off of the second side channel at the side of the second side active region.

[0237] The intermediate dielectric column 201b isolates the first-side active region and the second-side active region from each other and thus prevents crosstalk from occurring between the first-side channel and the second-side channel.

[0238] Step ten: Along the length direction of the first-side channel, first source / drain regions 206a and second source / drain regions 206b are respectively formed in the active region strip columns 201 on both sides of the side surface of the first-side gate structure.

[0239] The first-side gate structure and the second-side gate structure are symmetrically arranged on both sides of the active region strip column 201.

[0240] The first source / drain regions 206a and the second source / drain regions 206b are also located on both sides of the side surface of the second-side gate structure along the length direction of the first-side channel.

[0241] When forming the first source / drain regions 206a and the second source / drain regions 206b, it further includes forming an embedded epitaxial layer in the first source / drain regions 206a and the second source / drain regions 206b.

[0242] In the method of the embodiment of the present invention, the semiconductor device is a flash memory cell of a split-gate flash memory.

[0243] The first-side gate structure includes:

[0244] A first gate structure 304a, a second gate structure 304b, and a third gate structure 304c on the side surface of the first-side active region are sequentially arranged in the direction from the first source / drain region 206a to the second source / drain region 206b.

[0245] The first gate structure 304a includes a first floating gate 203a and a first control gate 204a stacked in sequence. A first floating gate dielectric layer is interposed between the first floating gate 203a and the side surface of the first-side active region, and a first inter-gate dielectric layer 303 is interposed between the first control gate 204a and the first floating gate 203a.

[0246] The second gate structure 304b includes a word line gate 205, and a first word line gate dielectric layer is interposed between the word line gate 205 and the side surface of the first-side active region.

[0247] The third gate structure 304c includes a second floating gate 203b and a second control gate 204b stacked in sequence. A second floating gate dielectric layer is interposed between the second floating gate 203b and the side surface of the first-side active region, and a second inter-gate dielectric layer is interposed between the second control gate 204b and the second floating gate 203b.

[0248] The second side gate structure also includes the first gate structure 304a, the second gate structure 304b, and the third gate structure 304c disposed on the second side active region. The first gate structure 304a, the second gate structure 304b, and the third gate structure 304c of the second side gate structure and the first gate structure 304a, the second gate structure 304b, and the third gate structure 304c of the first side gate structure are symmetric about the center line in the length direction of the active region strip column 201.

[0249] In the method of the embodiment of the present invention, the first control gates 204a on both sides of the active region strip column 201 further extend to the top of the active region strip column 201 and are connected together.

[0250] The second control gates 204b on both sides of the active region strip column 201 further extend to the top of the active region strip column 201 and are connected together.

[0251] In the method of the embodiment of the present invention, after forming the first side gate structure and the second side gate structure, the second mask layer 302 remains on the top of the active region strip column 201. The top surface of the word line gate 205 is flush with the top surface of the second mask layer 302. The first control gate 204a further extends above the top surface of the second mask layer 302 on the top of the active region strip column 201.

[0252] As Figure 9L shown, first form the floating gate 203 on the side of the active region strip column 201.

[0253] After that, return to as Figure 4B and Figure 4C shown, and form the control gate 204 and the word line gate 205.

[0254] After that, form the embedded epitaxial layer of the source / drain region 206 and dope to form the source / drain region 206. In the method of the embodiment of the present invention, the forming process of the first side gate structure and the second side gate structure can be formed by using the existing process method, and the forming process of the source / drain region 206 can also be formed by using the existing method. Herein, the present application does not give a detailed description.

[0255] In the method of the embodiment of the present invention, the flash memory cells of the split gate flash memory are arranged in an array structure.

[0256] The row structure of the array structure includes:

[0257] The flash memory cells in the same row are aligned, and the first control gates 204a of the flash memory cells in the same row are connected together, and the second control gates 204b of the flash memory cells in the same row are connected together.

[0258] The word line gates 205 located between two active region bar columns 201 in the same row are connected together. The word line gates 205 at odd positions in the same row are all connected to the odd word line WL_odd, and the word line gates 205 at even positions in the same row are all connected to the even word line WL_even.

[0259] The column structure of the array structure includes:

[0260] The flash memory cells in the same column are aligned, the first source / drain regions 206a of the flash memory cells in the same column are connected to the first bit line, and the second source / drain regions 206b of the flash memory cells in the same column are connected to the second bit line.

[0261] The first source / drain regions 206a of the flash memory cells share with the first source / drain regions 206a of adjacent flash memory cells, and the second source / drain regions 206b of the flash memory cells share with the second source / drain regions 206b of adjacent flash memory cells.

[0262] Two adjacent column structures have two independent first bit lines and share one second bit line, or have two independent second bit lines and share one first bit line.

[0263] In addition, the embodiment of the present invention does not need to reduce the thickness of the top barrier layer, so the Al diffusion problem will not be caused.

[0264] Based on the existing 0.75T self-aligned split-gate flash memory, the embodiment of the present invention uses a self-aligned method to etch the channel and bury dielectric layers such as oxides to isolate the two side channels in order to suppress the possible leakage crosstalk between the sidewall channels on the same active region. At the same time, it completely avoids the potential crosstalk caused by the opening and connection of the top channel under the high voltage coupling of the control gate or the word line.

[0265] Compared with the existing 0.75T self-aligned split-gate flash memory, the embodiment of the present invention only has a split-channel structure, and uses self-aligned etching and oxidation to isolate the two side channels in the process, and other structures and layouts remain unchanged. Therefore, the embodiment of the present invention can keep the size of the device cell (CELL) unchanged compared with the device cell size of the existing 0.75T self-aligned split-gate flash memory under the process allowable.

[0266] In addition, compared with the operation mode of the existing 0.75T self-aligned split-gate flash memory, the embodiments of the present invention remain unchanged.

[0267] In the embodiments of the present invention, the channel is located on the sidewall and does not affect the "1" current window of the flash memory during the lateral scaling process.

[0268] The present invention has been described in detail through specific embodiments above, but these do not constitute a limitation to the present invention. Without departing from the principle of the present invention, those skilled in the art can also make many modifications and improvements, which should also be regarded as the protection scope of the present invention.

Claims

1. A semiconductor device, characterized in that, Comprising: Active region strip columns protruding above the top surface of a semiconductor substrate; Isolation oxide layers formed on both sides of the active region strip columns; The active region strip columns include intermediate dielectric columns and semiconductor material columns self-aligned on both sides of the intermediate dielectric columns. The top surface of the intermediate dielectric columns is flush with the top surfaces of the semiconductor material columns, and the bottom surface of the intermediate dielectric columns is located below the top surface of the isolation oxide layers; Above the top surface of the isolation oxide layers, the semiconductor material columns at the first side of the intermediate dielectric columns serve as the first side active regions, and the semiconductor material columns at the second side of the intermediate dielectric columns serve as the second side active regions; A first side gate structure covers the side of the first side active region and is used to control the on / off of a first side channel at the side of the first side active region; A second side gate structure covers the side of the second side active region and is used to control the on / off of a second side channel at the side of the second side active region; The intermediate dielectric columns isolate the first side active region and the second side active region from each other and thus prevent crosstalk from occurring between the first side channel and the second side channel.

2. The semiconductor device according to claim 1, wherein: The bottom surface of the intermediate dielectric columns is located above the bottom surface of the active region strip columns; the semiconductor material columns on both sides of the intermediate dielectric columns merge together below the bottom surface of the intermediate dielectric columns.

3. The semiconductor device according to claim 1, wherein: Along the length direction of the first side channel, a first source / drain region and a second source / drain region are respectively formed in the active region strip columns on both sides of the side of the first side gate structure; The first side gate structure and the second side gate structure are symmetrically arranged on both sides of the active region strip columns; The first source / drain region and the second source / drain region are also located on both sides of the side of the second side gate structure along the length direction of the first side channel.

4. The semiconductor device according to claim 3, characterized in that: An embedded epitaxial layer is formed in the first source / drain region and the second source / drain region.

5. The semiconductor device according to claim 3, wherein: The semiconductor device is a flash memory cell of a split-gate flash memory; The first side gate structure includes: A first gate structure, a second gate structure, and a third gate structure are sequentially arranged on the side of the first side active region in the direction from the first source / drain region to the second source / drain region; The first gate structure includes a first floating gate and a first control gate stacked in sequence. A first floating gate dielectric layer is interposed between the first floating gate and the side of the first side active region, and a first inter-gate dielectric layer is interposed between the first control gate and the first floating gate; The second gate structure includes a word line gate. A first word line gate dielectric layer is interposed between the word line gate and the side of the first side active region; The third gate structure includes a second floating gate and a second control gate stacked in sequence. A second floating gate dielectric layer is interposed between the second floating gate and the side of the first side active region, and a second inter-gate dielectric layer is interposed between the second control gate and the second floating gate; The second side gate structure also includes the first gate structure, the second gate structure, and the third gate structure disposed on the second side active region. The first gate structure, the second gate structure, and the third gate structure of the second side gate structure and the first gate structure, the second gate structure, and the third gate structure of the first side gate structure are symmetric about the center line in the length direction of the active region strip column.

6. The semiconductor device according to claim 5, wherein: The first control gates on both sides of the active region strip column also extend to the top of the active region strip column and are connected together; The second control gates on both sides of the active region strip column also extend to the top of the active region strip column and are connected together.

7. The semiconductor device according to claim 6, characterized in that: Each of the flash memory cells of the split gate flash memory is arranged in an array structure; The row structure of the array structure includes: The flash memory cells in the same row are aligned. The first control gates of each of the flash memory cells in the same row are connected together, and the second control gates of each of the flash memory cells in the same row are connected together; The word line gates located between two active region strip columns in the same row are connected together. The word line gates at odd positions in the same row are all connected to the odd bit lines, and the word line gates at even positions in the same row are all connected to the even bit lines; The column structure of the array structure includes: The flash memory cells in the same column are aligned. The first source / drain regions of each of the flash memory cells in the same column are connected to the first bit line, and the second source / drain regions of each of the flash memory cells in the same column are connected to the second bit line; The first source / drain region of each of the flash memory cells is shared with the first source / drain region of an adjacent flash memory cell, and the second source / drain region of each of the flash memory cells is shared with the second source / drain region of an adjacent flash memory cell; Two adjacent column structures have two independent first bit lines and share one second bit line or have two independent second bit lines and share one first bit line.

8. The semiconductor device according to claim 1, wherein: The material of the intermediate dielectric column includes an oxide layer or silicon nitride.

9. A method for manufacturing a semiconductor device, characterized in that, Including the following steps: Step 1, form a first opening in a first mask layer formed on a semiconductor substrate. The first opening opens the formation region of the active region strip column; Step 2, form a first inner sidewall on the inner side surface of the first opening. The first inner sidewall encloses a second opening; Step 3, etch the semiconductor substrate to form a first trench at the bottom of the second opening; Step 4, fill a dielectric layer in the first trench to form an intermediate dielectric column and fill a dielectric layer in the second opening to form a second filling layer. The second mask layer is composed of the first inner sidewall and the second filling layer; Step 5, remove the first mask layer and retain the second mask layer; Step 7, etch the semiconductor substrate to form a second trench outside the region covered by the second mask layer and form an active region strip column in the region covered by the second mask layer; The active region bar column includes the intermediate dielectric column and semiconductor material columns composed of the semiconductor substrate that are self-aligned on both sides of the intermediate dielectric column. The top surfaces of the intermediate dielectric column and the semiconductor material columns are flush with each other. Step eight: Form an isolation oxide layer in the bottom region of the second trench. The bottom surface of the intermediate dielectric column is located below the top surface of the isolation oxide layer. Above the top surface of the isolation oxide layer, the semiconductor material column at the first side of the intermediate dielectric column serves as the first side active region, and the semiconductor material column at the second side of the intermediate dielectric column serves as the second side active region. Step nine: Form a first side gate structure and a second side gate structure. The first side gate structure covers the side of the first side active region and is used to control the on / off of the first side channel at the side of the first side active region. The second side gate structure covers the side of the second side active region and is used to control the on / off of the second side channel at the side of the second side active region. The intermediate dielectric column isolates the first side active region and the second side active region from each other, thereby preventing crosstalk between the first side channel and the second side channel.

10. The manufacturing method of the semiconductor device according to claim 9, characterized in that: The bottom surface of the intermediate dielectric column is located above the bottom surface of the active region bar column; the semiconductor material columns on both sides of the intermediate dielectric column merge together below the bottom surface of the intermediate dielectric column.

11. The manufacturing method of the semiconductor device according to claim 9, characterized in that, It further includes: Step ten: In the active region bar columns on both sides of the side of the first side gate structure along the length direction of the first side channel, form a first source / drain region and a second source / drain region respectively. The first side gate structure and the second side gate structure are symmetrically arranged on both sides of the active region bar column. The first source / drain region and the second source / drain region are also located on both sides of the side of the second side gate structure along the length direction of the first side channel.

12. The manufacturing method of the semiconductor device according to claim 11, characterized in that: When forming the first source / drain region and the second source / drain region, it further includes forming an embedded epitaxial layer in the first source / drain region and the second source / drain region.

13. The manufacturing method of the semiconductor device according to claim 11, characterized in that: The semiconductor device is a flash memory cell of a split-gate flash memory. The first side gate structure includes: In the direction from the first source / drain region to the second source / drain region, a first gate structure, a second gate structure, and a third gate structure are arranged in sequence on the side of the first side active region. The first gate structure includes a first floating gate and a first control gate stacked in sequence. There is a first floating gate dielectric layer between the first floating gate and the side of the first side active region, and a first inter-gate dielectric layer between the first control gate and the first floating gate. The second gate structure includes a word line gate. There is a first word line gate dielectric layer between the word line gate and the side of the first side active region. The third gate structure includes a second floating gate and a second control gate stacked in sequence. There is a second floating gate dielectric layer between the second floating gate and the side of the first side active region, and a second inter-gate dielectric layer between the second control gate and the second floating gate. The second side gate structure also includes the first gate structure, the second gate structure, and the third gate structure disposed on the second side active region. The first gate structure, the second gate structure, and the third gate structure of the second side gate structure and the first gate structure, the second gate structure, and the third gate structure of the first side gate structure are symmetric about the center line in the length direction of the active region strip column.

14. The manufacturing method of the semiconductor device according to claim 13, wherein: The first control gates on both sides of the active region strip column also extend to the top of the active region strip column and are connected together; The second control gates on both sides of the active region strip column also extend to the top of the active region strip column and are connected together.

15. The manufacturing method of the semiconductor device according to claim 14, characterized in that: Each of the flash memory cells of the split gate flash memory is arranged in an array structure; The row structure of the array structure includes: The flash memory cells in the same row are aligned and arranged. The first control gates of each of the flash memory cells in the same row are connected together, and the second control gates of each of the flash memory cells in the same row are connected together; The word line gates located between two active region strip columns in the same row are connected together. The word line gates at odd positions in the same row are all connected to the odd bit lines, and the word line gates at even positions in the same row are all connected to the even bit lines; The column structure of the array structure includes: The flash memory cells in the same column are aligned and arranged. The first source / drain regions of each of the flash memory cells in the same column are connected to the first bit line, and the second source / drain regions of each of the flash memory cells in the same column are connected to the second bit line; The first source / drain regions of each of the flash memory cells are shared with the first source / drain regions of adjacent flash memory cells, and the second source / drain regions of each of the flash memory cells are shared with the second source / drain regions of adjacent flash memory cells; Two adjacent column structures have two independent first bit lines and share one second bit line or have two independent second bit lines and share one first bit line.

16. The manufacturing method of the semiconductor device according to claim 9, characterized in that: The material of the intermediate dielectric column includes an oxide layer or silicon nitride.

17. The manufacturing method of the semiconductor device according to claim 16, characterized in that: The material of the first sidewall includes silicon nitride; Step four includes the following sub-steps: Oxidize the semiconductor substrate exposed on the inner surface of the first trench to form a first oxide layer; Form a second silicon nitride layer to completely fill the first trench and the second opening; the intermediate dielectric column is formed by stacking the first oxide layer and the second silicon nitride layer filled in the first trench, and the second silicon nitride layer filled in the second opening serves as the second filling layer and forms the second mask layer.

18. The manufacturing method of a semiconductor device according to claim 16, characterized in that, Step one includes the following sub-steps: Step 11, form a pseudo mask layer; Perform patterned etching on the pseudo mask layer to form a first pseudo mask strip. The first pseudo mask strip covers the formation region of the active region strip column, and the pseudo mask layer outside the formation region of the active region strip column is removed; Step 12, form the first mask layer to completely fill the interval region between the first pseudo mask strips; Step 13, remove the first pseudo mask strip and form the first opening in the region where the first pseudo mask strip is removed.

19. The method for manufacturing a semiconductor device according to claim 18, characterized in that: The material of the pseudo mask layer is silicon nitride; The material of the first mask layer is polysilicon; Before step 12, it further includes: forming a second oxide layer on the surface of the semiconductor substrate outside the first pseudo mask strip; In subsequent step five, the second oxide layer serves as an etching stop layer.

20. The manufacturing method of the semiconductor device according to claim 19, characterized in that: In step 12, the first mask layer is formed by polysilicon deposition and the top surface of the first mask layer is made flush with the top surface of the first pseudo mask strip by using the CMP process; After step 12 is completed and before step 13, it further includes: Performing back etching on the first mask layer to make the top surface of the first mask layer lower than the top surface of the first pseudo mask strip; Forming a third oxide layer on the top surface of the first mask layer.

21. The manufacturing method of the semiconductor device according to claim 14, characterized in that: In step nine, after the first side gate structure and the second side gate structure are formed, the second mask layer remains on the top of the active region strip column, the top surface of the word line gate is flush with the top surface of the second mask layer, and the first control gate further extends above the top surface of the second mask layer on the top of the active region strip column.

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