Semiconductor structure and forming method thereof

Abstract

The invention provides a semiconductor structure and a forming method thereof, and the semiconductor structure comprises a substrate which comprises a first device region and a second device region; the first gate structure is positioned on a part of the surface of the substrate in the first device region; the second gate structure is positioned on a part of the surface of the substrate in the second device region; the first source-drain doped region is positioned in the substrate at two sides of the first gate structure; the second source-drain doped region is positioned in the substrate at two sides of the second gate structure; the silicide barrier layer is located on the side wall of the first gate structure, and the silicide barrier layer further covers the surface of the second source-drain doped region and the top surface and the side wall surface of the second gate structure; the silicide layer is located on the surface of the first source-drain doped region and the top surface of the first gate structure; according to the method, the side wall of the gate structure in the region where the silicide layer needs to be formed is adjusted, the silicide barrier layer is directly used as the side wall corresponding to the first gate structure, compared with a traditional process, the distance between the gate structures is increased, a large space is provided for forming the silicide layer, and the forming difficulty of the silicide layer is reduced.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and particularly to a semiconductor structure and a method for forming the same. Background Art

[0002] In modern communication technologies, the BCD (Bipolar-CMOS-DMOS) process is widely used due to its unique technical advantages. By integrating CMOS (Complementary Metal Oxide Semiconductor) and DMOS (Double-diffused Metal Oxide Semiconductor) technologies, the BCD process can achieve high-voltage and high-current integrated circuit designs, thus meeting the requirements of communication devices for power management, signal processing, and high performance. With the continuous development of communication technologies, the performance requirements for integrated circuits are increasing day by day. Especially in high-voltage and high-power application scenarios, the reliability and efficiency of the BCD process become key factors.

[0003] However, in the BCD process, the design and manufacturing of LDMOS (Laterally Diffused Metal Oxide Semiconductor) devices face many challenges. LDMOS devices are widely used due to their excellent performance in high-voltage applications, but there are some technical problems in their manufacturing process. Especially in the design of the poly to poly pitch, due to the small poly to poly pitch of some devices, it is difficult to have enough space to form a salicide layer after stacking a silicide blocking layer (SAB) on the spacer during the manufacturing process. The deficiency of the salicide layer directly affects the connection quality of the subsequent contact holes, which may lead to poor contact or connection failure, thus affecting the performance and reliability of the entire device.

[0004] However, there are still some problems in the current BCD (Bipolar-CMOS-DMOS) process. Summary of the Invention

[0005] The technical problem solved by the present invention is to provide a semiconductor structure and a method for forming the same. By adjusting the sidewall of the gate structure in the region where the salicide layer needs to be formed, the silicide blocking layer is directly used as the corresponding sidewall, increasing the spacing between the gate structures compared to the traditional process, providing a larger space for the formation of the salicide layer, and reducing the difficulty of forming the salicide layer.

[0006] To solve the above problems, the present invention provides a semiconductor structure, comprising: a substrate including a first device region and a second device region; a first gate structure located on a partial surface of the substrate in the first device region; a second gate structure located on a partial surface of the substrate in the second device region; a first source / drain doping region located in the substrate on both sides of the first gate structure; a second source / drain doping region located in the substrate on both sides of the second gate structure; a silicide blocking layer located on the sidewalls of the first gate structure, and the silicide blocking layer further covers the surface of the second source / drain doping region and the top surface and sidewall surfaces of the second gate structure; a silicide layer located on the surface of the first source / drain doping region and the top surface of the first gate structure.

[0007] Optionally, the material of the silicide blocking layer includes one or a combination of silicon oxide, silicon-rich oxide, silicon oxynitride, and silicon nitride.

[0008] Correspondingly, the present invention further provides a method for forming a semiconductor structure, comprising: providing a substrate including a first device region and a second device region; forming a first gate structure on a partial surface of the substrate in a partial first device region; forming a second gate structure on a partial surface of the substrate in a partial second device region; forming sidewalls on the sidewall surfaces of the first gate structure and the sidewall surfaces of the second gate structure; forming a first source / drain doping region in the substrate on both sides of the sidewalls on the sidewall surface of the first gate structure; forming a second source / drain doping region in the substrate on both sides of the sidewalls on the sidewall surface of the second gate structure; etching to remove the sidewalls; forming an initial silicide blocking layer covering the first source / drain doping region, the sidewalls and the top surface of the first gate structure, the second source / drain doping region, and the sidewalls and the top surface of the second gate structure on the surface of the substrate; etching the initial silicide blocking layer on the first device region to form a silicide blocking layer on the sidewalls of the first gate structure, the surface of the second source / drain doping region, and the top surface and sidewall surfaces of the second gate structure; forming a silicide layer on the surface of the first source / drain doping region and the top surface of the first gate structure.

[0009] Optionally, the material of the silicide blocking layer includes one or a combination of silicon oxide, silicon-rich oxide, silicon oxynitride, and silicon nitride.

[0010] Optionally, it further comprises: forming a well region in the substrate in the second device region.

[0011] Optionally, it further comprises: forming a shallow trench isolation structure in the substrate.

[0012] Optionally, it further includes: forming a drift region in the substrate of the first device region, with the bottom of part of the first gate structure formed on the top surface of part of the drift region; forming a field plate layer on the top surface of the drift region, with a gap existing between adjacent field plate layers.

[0013] Optionally, a body region is formed in the substrate between adjacent first gate structures, the doping ions in the body region are opposite to those in the drift region, and the body region is located between adjacent drift regions.

[0014] Optionally, the first source / drain doping regions are respectively formed in the body region and the drift region on both sides of the first gate structure, and a reverse doping region is further formed between adjacent first source / drain doping regions in the drift region.

[0015] Optionally, the process of etching the initial silicide blocking layer on the first device region is an anisotropic etching process.

[0016] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0017] In the method for forming a semiconductor structure of the present invention, the substrate includes a first device region and a second device region, a first gate structure is located on a partial surface of the substrate in the first device region, a second gate structure is located on a partial surface of the substrate in the second device region, sidewalls are located on the sidewalls of the second gate structure, first source / drain doping regions are located in the substrate on both sides of the first gate structure, second source / drain doping regions are located in the substrate on both sides of the second gate structure, a silicide blocking layer is located on the sidewalls of the first gate structure, the silicide blocking layer also covers the surface of the second source / drain doping region, the sidewall surfaces of the sidewalls, and the top surface of the second gate structure, and a silicide layer is located on the surface of the first source / drain doping region and the top surface of the first gate structure; by directly using the silicide blocking layer as the sidewall of the first gate structure, compared with the sidewall and the silicide blocking layer of the gate structure in the traditional formation method, the spacing between the first gate structures is greatly increased, thereby providing a better process window for the region where the silicide layer needs to be formed, reducing the formation difficulty of the silicide layer, and having a wide range of applications. Description of the Drawings

[0018] Figures 1 to 8 are schematic structural diagrams of each step of the method for forming a semiconductor structure in an embodiment of the present invention. Detailed Embodiments

[0019] As in the background art, currently, there are still some problems in the BCD (Bipolar-CMOS-DMOS) process.

[0020] The inventors found that in the BCD (Bipolar-CMOS-DMOS) process, the poly-to-poly spacing of some devices is relatively small. After the SAB residue is stacked on the spacer, it is difficult to form a sufficient salicide layer, resulting in the inability to connect the subsequent contact holes.

[0021] Through research, the inventors found that by directly using the salicide blocking layer as the spacer of the first gate structure in the area where the salicide layer needs to be formed, compared with having a spacer and a salicide blocking layer on the sidewall of the second gate structure, the spacing between the first gate structures is greatly increased. Thus, a better process window is provided for the area where the salicide layer needs to be formed, reducing the difficulty of forming the salicide layer and having a wide range of applications.

[0022] To make the above objects, features, and advantages of the present invention more obvious and understandable, the following specifically describes the embodiments of the present invention in detail with reference to the accompanying drawings.

[0023] Figures 1 to 8 It is a schematic diagram of the structures of each step of the method for forming a semiconductor structure in an embodiment of the present invention.

[0024] First, please refer to Figure 1 , a substrate 100 is provided, and the substrate 100 includes a first device region I and a second device region II.

[0025] In this embodiment, the first device region I is used to form an LDMOS device, and the second device region II is used to form a CMOS device.

[0026] In this embodiment, the material of the substrate 100 is silicon.

[0027] In some embodiments, the material of the substrate 100 may also be semiconductor materials such as silicon germanium and germanium.

[0028] In this embodiment, it further includes: forming a shallow trench isolation structure 112 in the substrate 100.

[0029] In this embodiment, impurity atoms are introduced into the substrate 100 by doping to change its conductivity, thereby forming active regions (not marked in the figure) in the substrate 100. For example, boron is doped into the substrate 100 to form a P-type region, and phosphorus is doped into the substrate 100 to form an N-type region.

[0030] In this embodiment, a well region 101 (WELL) is formed in the substrate 100 of the second device region II.

[0031] In this embodiment, it further includes: forming a drift region 102 in the substrate 100 of the first device region I, forming a field plate layer 103 on the top surface of the drift region 102, and there is a gap between adjacent field plate layers 103.

[0032] In this embodiment, the drift region 102 is doped with N-type ions.

[0033] In this embodiment, the material of the field plate layer 103 is silicon oxide.

[0034] In this embodiment, the field plate layer 103 is used to form a shielding layer between the first drain and the first gate structure, reducing the direct influence of the drain electric field on the gate, making the electric field distribution near the first drain more uniform, and reducing the interference of the first drain electric field on the first gate structure.

[0035] Please refer to Figure 2 , and form a first gate structure 104 on a part of the surface of the substrate 100 in a part of the first device region I.

[0036] In this embodiment, the first gate structure 104 includes a first gate oxide layer (not shown in the figure) formed on the surface of the substrate 100 and a first gate layer formed on the surface of the first gate oxide layer.

[0037] In this embodiment, the material of the first gate layer is polysilicon.

[0038] In this embodiment, the bottom of a part of the first gate structure 104 is formed on the top surface of a part of the drift region 102.

[0039] In this embodiment, after forming the first gate structure 104, it further includes: forming a body region 113 in the substrate 100 between adjacent first gate structures 104, the doping ions in the body region 113 are opposite to the doping ions in the drift region 102, and the body region 113 is located between adjacent drift regions 102.

[0040] Please continue to refer to Figure 2 , and form a second gate structure 105 on a part of the surface of the substrate 100 in a part of the second device region II.

[0041] In this embodiment, the second gate structure 105 includes a second gate oxide layer (not shown in the figure) formed on the surface of the substrate 100 and a second gate layer formed on the surface of the second gate oxide layer.

[0042] In this embodiment, the material of the second gate layer is polysilicon.

[0043] In this embodiment, after forming the first gate structure 104 and the second gate structure 105, the following steps are further included: performing an LDD process, that is, forming a lightly doped extension region (not shown in the figure) between the source and drain under the boundary of the first gate structure 104 and the second gate structure 105, and this extension region forms an impurity concentration gradient between the source / drain and the channel.

[0044] Please refer to Figure 3 , and form spacers 106 on the sidewall surfaces of the first gate structure 104 and the sidewall surfaces of the second gate structure 105.

[0045] In this embodiment, the material of the spacer 106 is silicon nitride.

[0046] In some embodiments, the material of the spacer 106 can also be silicon oxide, silicon carbide, etc.

[0047] In this embodiment, the method of forming the spacer 106 includes: forming an initial spacer layer (not shown in the figure) on the surface of the substrate 100, and the initial spacer layer (not shown in the figure) covers the sidewalls and the top surfaces of the first gate structure 104 and the second gate structure 105; etching away part of the initial spacer layer (not shown in the figure) until the surface of the substrate 100, the top surface of the first gate structure 104, and the top surface of the second gate structure 105 are exposed, and forming spacers 106 on the sidewalls of the first gate structure 104 and the sidewalls of the second gate structure 105.

[0048] Please refer to Figure 4 , and form a first source / drain doping region 107 in the substrate 100 on both sides of the spacer 106 on the sidewall surface of the first gate structure 104.

[0049] In this embodiment, the first source / drain doping regions 107 are respectively formed in the body regions on both sides of the first gate structure 104 and in the drift region 102, and a reverse doping region 108 is further formed between adjacent first source / drain doping regions 107 in the drift region 102.

[0050] In this embodiment, the type of doping ions in the first source / drain doping region 107 is the same as the type of doping ions in the drift region 102, that is, N-type ions.

[0051] In this embodiment, the type of doping ions in the reverse doping region 108 is opposite to the type of doping ions in the first source / drain doping region, that is, P-type ions.

[0052] Please continue to refer to Figure 4 , and form a second source / drain doping region 109 in the substrate 100 on both sides of the spacer 106 on the sidewall surface of the second gate structure 105.

[0053] In this embodiment, the second source / drain doping region 109 is doped with P-type ions.

[0054] Please refer to Figure 5 , and etch away the sidewall 106.

[0055] In this embodiment, a dry etching process is used to remove the sidewall 106.

[0056] In other embodiments, a wet etching process may also be used to remove the sidewall 106.

[0057] Please refer to Figure 6 , and form an initial silicide blocking layer 110 on the surface of the substrate 100 to cover the first source / drain doping region 107, the first gate structure 104, the second source / drain doping region 109, and the second gate structure 105.

[0058] In this embodiment, a chemical vapor deposition process is used to form the initial silicide blocking layer 110.

[0059] In other embodiments, a physical vapor deposition process or an atomic layer deposition process may also be used to form the initial silicide blocking layer 110.

[0060] In this embodiment, the material of the initial silicide blocking layer 110 is silicon oxide.

[0061] In some embodiments, the material of the initial silicide blocking layer 110 may also be silicon-rich oxide, silicon oxynitride, or silicon nitride.

[0062] Please refer to Figure 7 , and etch the initial silicide blocking layer 110 on the first device region I to form a silicide blocking layer 111 on the sidewall of the first gate structure 104, the surface of the second source / drain doping region 109, and the top surface and sidewall surface of the second gate structure 105.

[0063] In this embodiment, the process of etching the initial silicide blocking layer 110 on the first device region I is an anisotropic etching process.

[0064] In this embodiment, the silicide blocking layer 111 is used to prevent the formation of a silicide layer (salicide), and is also called the SAB layer.

[0065] In this embodiment, the silicide blocking layer 111 directly serves as the sidewall of the first gate structure 104, replacing the traditional sidewall, which helps to increase the spacing between adjacent first gate structures 104.

[0066] In this embodiment,Figure 7 Only the device portions on the first device region I where a silicide layer needs to be formed are shown. There are also devices on the first device region I where a silicide layer does not need to be formed.

[0067] In this embodiment, the device portions on the first device region I where a silicide layer needs to be formed are shown. Of course, there may also be device portions on the second device region II where a silicide layer needs to be formed. The same method is also used to directly use the silicide blocking layer 111 as a sidewall, thereby increasing the spacing between the gates and providing sufficient space for the formation of the silicide layer.

[0068] In this embodiment, in the region where a silicide layer needs to be formed, the silicide blocking layer 111 is directly used as the sidewall of the first gate structure 104. The spacing between the first gate structures 104 is greatly increased, thereby providing a better process window for the region where a silicide layer needs to be formed, reducing the difficulty of forming the silicide layer, and having a wide range of applications.

[0069] Please refer to Figure 8 , a silicide layer 114 is formed on the surface of the first source / drain doping region 107 and the top surface of the first gate structure 104.

[0070] In this embodiment, since the spacing between adjacent first gate structures 104 is increased, the difficulty of forming the silicide layer 114 is greatly reduced, which helps to form a silicide layer 114 with good quality, improves the connection quality of the subsequent contact holes, reduces contact failure or connection failure, and thus improves the performance and reliability of the entire device, having a wide range.

[0071] Correspondingly, the present invention also provides a semiconductor structure. Please refer to Figure 8 , a substrate 100, the substrate 100 includes a first device region I and a second device region II; a first gate structure 104 located on a partial surface of the substrate 100 in the first device region I; a second gate structure 105 located on a partial surface of the substrate 100 in the second device region II; a first source / drain doping region 107 located in the substrate 100 on both sides of the first gate structure 104; a second source / drain doping region 109 located in the substrate 100 on both sides of the second gate structure 105; a silicide blocking layer 111 located on the sidewall of the first gate structure 104, and the silicide blocking layer 111 also covers the surface of the second source / drain doping region 109, the top surface and the sidewall surface of the second gate structure 105; a silicide layer 114 located on the surface of the first source / drain doping region 107 and the top surface of the first gate structure 104.

[0072] In this embodiment, in the region where the silicide layer 114 needs to be formed (such as the first device region I), the silicide blocking layer 111 is directly used as the sidewall of the first gate structure 104, and the spacing between the first gate structures 104 is greatly increased, thereby providing a better process window for the region where the silicide layer 114 needs to be formed, reducing the difficulty of forming the silicide layer 114, and having a wide range of applications.

[0073] In this embodiment, the material of the silicide blocking layer 111 includes one or a combination of silicon oxide, silicon-rich oxide, silicon oxynitride, and silicon nitride.

[0074] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be determined by the scope defined by the claims.

Claims

1. A semiconductor structure, characterized in that, Comprising: A substrate, the substrate including a first device region and a second device region; A first gate structure located on a partial surface of the substrate in the first device region; A second gate structure located on a partial surface of the substrate in the second device region; A first source / drain doping region located in the substrate on both sides of the first gate structure; A second source / drain doping region located in the substrate on both sides of the second gate structure; A silicide blocking layer located on the sidewalls of the first gate structure, and the silicide blocking layer further covers the surface of the second source / drain doping region and the top surface and sidewall surfaces of the second gate structure; A silicide layer located on the surface of the first source / drain doping region and the top surface of the first gate structure.

2. The semiconductor structure according to claim 1, wherein, The material of the silicide blocking layer includes one or a combination of silicon oxide, silicon-rich oxide, silicon oxynitride, and silicon nitride.

3. A method for forming a semiconductor structure, characterized in that, Comprising: Providing a substrate, the substrate including a first device region and a second device region; Forming a first gate structure on a partial surface of the substrate in a partial first device region; Forming a second gate structure on a partial surface of the substrate in a partial second device region; Forming sidewalls on the sidewall surfaces of the first gate structure and the sidewall surfaces of the second gate structure; Forming a first source / drain doping region in the substrate on both sides of the sidewalls on the sidewall surface of the first gate structure; Forming a second source / drain doping region in the substrate on both sides of the sidewalls on the sidewall surface of the second gate structure; Etching to remove the sidewalls; Forming an initial silicide blocking layer on the surface of the substrate to cover the first source / drain doping region, the sidewalls and top surface of the first gate structure, the second source / drain doping region, and the sidewalls and top surface of the second gate structure; Etching the initial silicide blocking layer on the first device region to form a silicide blocking layer on the sidewalls of the first gate structure, the surface of the second source / drain doping region, and the top surface and sidewall surfaces of the second gate structure; Forming a silicide layer on the surface of the first source / drain doping region and the top surface of the first gate structure.

4. The method for forming a semiconductor structure according to claim 3, wherein, The material of the silicide blocking layer includes one or a combination of silicon oxide, silicon-rich oxide, silicon oxynitride, and silicon nitride.

5. The method for forming a semiconductor structure according to claim 3, wherein Further comprising: Forming a well region in the substrate in the second device region.

6. The method for forming a semiconductor structure according to claim 3, wherein, Further comprising: Forming a shallow trench isolation structure in the substrate.

7. The method for forming a semiconductor structure according to claim 3, wherein, Further comprising: Forming a drift region in the substrate in the first device region, and the bottom of a partial first gate structure is formed on the top surface of a partial drift region; Forming a field plate layer on the top surface of the drift region, and there is a gap between adjacent field plate layers.

8. The method for forming a semiconductor structure as claimed in claim 7, wherein Forming a body region in the substrate between adjacent first gate structures, the doping ions in the body region are opposite to those in the drift region, and the body region is located between adjacent drift regions.

9. The method for forming a semiconductor structure according to claim 8, wherein, The first source / drain doping regions are respectively formed in the body region and the drift region on both sides of the first gate structure, and a reverse doping region is further formed between adjacent first source / drain doping regions in the drift region.

10. The method for forming a semiconductor structure according to claim 3, wherein The process of etching the initial silicide blocking layer on the first device region is an anisotropic etching process.

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