Process method for preparing ohmic contact on pGaN gate enhanced gallium nitride HEMT (High Electron Mobility Transistor) device

Abstract

The invention discloses a process method for preparing ohmic contact on a pGaN gate enhanced gallium nitride HEMT (High Electron Mobility Transistor) device, relates to the technical field of ohmic contact, and relates to a process for preparing ohmic contact on a pGaN gate enhanced gallium nitride GaN HEMT device, which comprises the following steps of: defining an ohmic contact area on a pGaN layer through photoetching; mixed etching gas containing SF6 and BCl3 is utilized to remove the pGaN layer and etch the pGaN layer into the AlGaN surface; carrying out surface treatment on the etched AlGaN surface so as to remove an etching damage layer; sequentially depositing Ti / Al / Ni / Au metal layers in the ohmic contact area, and covering a passivation layer on the metal surface before annealing; and finally, performing rapid thermal annealing (RTA) on the device to enable the metal layer and the GaN / AlGaN epitaxial structure to form low ohmic contact. Through the process, the contact resistance and the square resistance of the pGaN gate enhanced GaN HEMT can be effectively reduced, and the working efficiency and the reliability of the device are improved.

Description

Technical Field

[0001] The present invention relates to the technical field of ohmic contact, and in particular to a process method for fabricating an ohmic contact on a pGaN-gate enhanced gallium nitride HEMT device. Background Art

[0002] In the process of fabricating a GaN HEMT device, ohmic contact is one of the important factors affecting the device performance and reliability; in the current fabrication process, most of them select a corresponding metal stack (such as Ti / Al / Ni / Au) and combine rapid thermal annealing (RTA) treatment to reduce the contact resistance, improve the power density and efficiency of the device.

[0003] For a GaN HEMT device with a pGaN gate structure, the pGaN layer etching process and the damage caused to the AlGaN surface after etching will, to a certain extent, increase the ohmic contact resistance and have an adverse impact on the subsequent device characteristics; therefore, it is necessary to comprehensively optimize the etching mechanism of the pGaN layer, the composition and ratio of the etching gas, the surface repair treatment, and the ohmic electrode metal annealing process, etc., in order to obtain a high-quality and low-resistance ohmic contact. Summary of the Invention

[0004] In view of the above existing problems, the present invention is proposed.

[0005] The present invention provides a process method for fabricating an ohmic contact on a pGaN-gate enhanced gallium nitride HEMT device to solve the problems of achieving low ohmic contact, suppressing damage, and improving the device consistency and reliability on a pGaN-gate enhanced GaN HEMT device.

[0006] To solve the above technical problems, the present invention provides the following technical solutions:

[0007] An embodiment of the present invention provides a process method for fabricating an ohmic contact on a pGaN-gate enhanced gallium nitride HEMT device, which includes,

[0008] Step S1, performing wet or dry cleaning on the pGaN layer to remove organic substances and particles;

[0009] Step S2, etching the pGaN layer with an SF6 / BCl3 mixed etching gas to the AlGaN surface or a preset depth;

[0010] Step S3, performing surface treatment on the exposed surface of the etched AlGaN layer to remove the damaged layer affected by etching;

[0011] Step S4, performing photolithographic patterning in the target ohmic contact area;

[0012] Step S5, deposit a Ti / Al / Ni / Au metal layer on the ohmic contact region successively;

[0013] Step S6, cover the device surface with a passivation layer after the metal deposition;

[0014] Step S7, open a window on the passivation layer through photolithography and etching to expose the Ti / Al / Ni / Au metal layer;

[0015] Step S8, perform rapid thermal annealing (RTA) on the device under a protective atmosphere to form an ohmic contact between Ti / Al / Ni / Au and the AlGaN and GaN layers.

[0016] As a preferred embodiment of the process for fabricating an ohmic contact on a pGaN-gate enhanced gallium nitride (GaN) HEMT device according to the present invention, wherein: the flow ratio of SF6 to BCl3 in the SF6 / BCl3 mixed etching gas is 1:1 to 1:10, and the etching time is controlled according to the thicknesses of the pGaN layer and the AlGaN layer, so that the etching depth does not exceed 50% of the thickness of the AlGaN layer.

[0017] As a preferred embodiment of the process for fabricating an ohmic contact on a pGaN-gate enhanced gallium nitride (GaN) HEMT device according to the present invention, wherein the surface treatment includes at least one of the following processes:

[0018] Using inert gas plasma to remove etching residues, performing wet cleaning with dilute acid or dilute alkali solution, and using vacuum annealing process to remove etching damage.

[0019] As a preferred embodiment of the process for fabricating an ohmic contact on a pGaN-gate enhanced gallium nitride (GaN) HEMT device according to the present invention, wherein: the thickness ranges of Ti, Al, Ni, and Au in the Ti / Al / Ni / Au metal layer are 5 nm to 50 nm, 30 nm to 200 nm, 5 nm to 50 nm, and 10 nm to 100 nm respectively, and the total thickness is 100 nm to 300 nm.

[0020] As a preferred embodiment of the process for fabricating an ohmic contact on a pGaN-gate enhanced gallium nitride (GaN) HEMT device according to the present invention, wherein: the passivation layer is made of at least one of Si3N4, SiO2, or Al2O3 or their composite structure, with a thickness of 20 nm to 200 nm. After passivation, the ohmic contact resistance and the semiconductor sheet resistance can be effectively reduced.

[0021] As a preferred embodiment of the process for fabricating an ohmic contact on a pGaN-gated enhancement-mode gallium nitride HEMT device according to the present invention, wherein: the temperature range of the rapid thermal annealing (RTA) is 750°C to 900°C, the holding time is 30 s to 120 s, and the protective atmosphere is N2 or Ar.

[0022] As a preferred embodiment of the process for fabricating an ohmic contact on a pGaN-gated enhancement-mode gallium nitride HEMT device according to the present invention, wherein: before lithographically defining the ohmic region in step S4, a second lithography or nitride etching is further included to remove the passivation layer and residual photoresist, so as to avoid contamination of the metal-semiconductor contact surface by residual organic substances.

[0023] As a preferred embodiment of the process for fabricating an ohmic contact on a pGaN-gated enhancement-mode gallium nitride HEMT device according to the present invention, wherein: the doping concentration of the pGaN layer is 10 18 ~10 19 cm -3 , and the Al component content in the AlGaN layer is 15% to 25%, so as to ensure the threshold and conduction characteristics required for the pGaN-gated enhancement-mode GaN HEMT device.

[0024] As a preferred embodiment of the process for fabricating an ohmic contact on a pGaN-gated enhancement-mode gallium nitride HEMT device according to the present invention, wherein: after the annealing in step S8, the contact resistance and sheet resistance of the ohmic contact are measured and linearly fitted through a transmission line model (TLM) structure to evaluate the ohmic contact performance.

[0025] As a preferred embodiment of the process for fabricating an ohmic contact on a pGaN-gated enhancement-mode gallium nitride HEMT device according to the present invention, wherein: the surface cleaning in step S1 and the surface treatment in step S3 can be combined or carried out step by step; so as to remove impurities from the pGaN layer while minimizing the etching damage to the AlGaN barrier layer to the greatest extent, thereby obtaining a lower contact resistance and better device reliability.

[0026] In view of the ohmic contact preparation method of a conventional AlGaN / GaN HEMT, the present invention overcomes the problems of surface damage or change of AlGaN caused by etching of the pGaN layer by means of surface treatment after etching and covering a passivation layer before annealing, and achieves the following beneficial effects:

[0027] By cleaning the etched AlGaN surface and removing the damage, and depositing a passivation layer before annealing, a more uniform alloying interface is formed between the metal and the semiconductor surface, significantly reducing the contact resistance; the pGaN gate structure is crucial in the enhancement-mode GaN HEMT design. The process of the present invention further optimizes the barrier layer conductivity while reducing the etching damage, thereby reducing the sheet resistance and improving the performance of the device under high-power and high-frequency operations; if there are residual damages or defects on the surface after etching, it will lead to threshold drift or increased leakage current of the device. However, in the present invention, a passivation layer is covered immediately after etching and surface treatment, which can reduce the trap density, alleviate the device instability problem caused by surface states, and improve the long-term working reliability of the device; in addition, for the pGaN gate enhancement structure, excellent ohmic contact performance can be obtained under various substrates (Si, SiC, Sapphire) and different etching and annealing temperature conditions, with universality and process flexibility; the present invention only makes moderate improvements and optimizations on the basis of the conventional GaN HEMT integrated manufacturing process, and the required equipment and processes are highly compatible with the existing semiconductor manufacturing platform, having good implementability and mass production potential. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present invention, and those of ordinary skill in the art can obtain other drawings based on these drawings without creative efforts.

[0029] Figure 1 It is a flow schematic diagram of the process method for preparing an ohmic contact on a pGaN gate enhancement-mode gallium nitride HEMT device in Embodiment 1.

[0030] Figure 2 It is a schematic diagram of the surface cleaning structure in Embodiment 1.

[0031] Figure 3 It is a schematic diagram of the SF6 / BCl3 etching of the pGaN layer to the self-stopping structure in Embodiment 1.

[0032] Figure 4 It is a schematic diagram of the surface treatment structure of the etched AlGaN in Embodiment 1.

[0033] Figure 5 It is a schematic diagram of using a photolithography process to demarcate the area for depositing ohmic contact metal on the device surface in Embodiment 1.

[0034] Figure 6 It is a schematic diagram of the deposited Ti / Al / Ni / Au composite metal structure in Embodiment 1.

[0035] Figure 7Schematic diagram of the passivation structure in Example 1.

[0036] Figure 8 Schematic diagram of the opening structure in Example 1.

[0037] Figure 9 Schematic diagram of the RTA structure in Example 1. Detailed implementation manners

[0038] To make the above objects, features and advantages of the present invention more obvious and understandable, the following detailed description of the specific implementation manners of the present invention will be given in conjunction with the accompanying drawings of the specification.

[0039] In the following description, many specific details are set forth in order to fully understand the present invention. However, the present invention can also be implemented in other ways different from those described herein. Those skilled in the art can make similar extensions without departing from the connotation of the present invention. Therefore, the present invention is not limited by the specific embodiments disclosed below.

[0040] Secondly, the so-called "one embodiment" or "embodiment" herein refers to a specific feature, structure or characteristic that can be included in at least one implementation manner of the present invention. The phrase "in one embodiment" appearing in different places in this specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments.

[0041] Example 1, referring to Figures 1-9 , which is the first embodiment of the present invention. This embodiment provides a process method for fabricating an ohmic contact on a pGaN gate-enhanced gallium nitride HEMT device, including the following steps:

[0042] 1. Substrate and epitaxial structure: A GaN layer and an AlGaN barrier layer are epitaxially grown on a Si substrate, and a pGaN layer is grown on the surface of the AlGaN barrier layer. The doping concentration of the pGaN layer is about 1×10 19 cm -3 , and the Al component content in the AlGaN layer is about 20%.

[0043] 2. Surface cleaning: Before etching, use acetone, isopropyl alcohol, and deionized water to ultrasonically clean for 10 minutes in sequence to remove organic substances and particles.

[0044] 3. Etching: Define the area where the pGaN layer is to be removed through photolithography, and use an SF6 / BCl3 mixed plasma to etch the pGaN to remove the pGaN layer and slightly etch into the AlGaN surface.

[0045] Typical gas flow ratio: SF6:BCl3 = 1:1, etching rate is about 30 nm / min, and the specific etching time depends on the thickness of the pGaN.

[0046] 4. Surface treatment: After etching, first use Ar plasma to perform low-power cleaning on the exposed AlGaN surface for 60 seconds to remove etching residues and damaged layers; wet immersion is carried out in combination with dilute acid (dilute hydrofluoric acid) as required.

[0047] 5. Lithography to define the ohmic region: Perform lithography again to determine the position for subsequent deposition of ohmic contact metal, ensuring that the metal is only deposited within the target area.

[0048] 6. Metal deposition: Deposit multiple layers of Ti / Al / Ni / Au metal in sequence. The specific thicknesses are: Ti 20 nm, Al 100 nm, Ni 30 nm, Au 50 nm, and the total thickness is approximately 200 nm. The deposition method uses electron beam evaporation.

[0049] 7. Passivation: Cover a layer of SiO2 on top of the metal layer and the device surface as a passivation layer, with a thickness of approximately 50 nm.

[0050] 8. Opening: Through lithography and etching, open windows on the passivation layer to expose the metal electrode area.

[0051] 9. Rapid thermal annealing RTA: Under a nitrogen protection atmosphere, perform rapid thermal annealing at about 800 °C for 60 seconds to form an alloy ohmic contact between the metal and AlGaN / GaN.

[0052] Example 2 is the second example of the present invention. This example provides a process method for fabricating an ohmic contact on a pGaN gate-enhanced gallium nitride HEMT device, including the following steps:

[0053] 1. Substrate and epitaxial structure: Use a GaN layer and an AlGaN barrier layer epitaxially grown on a Si substrate, and a pGaN layer is grown on the surface of the AlGaN barrier layer. The doping concentration of this pGaN layer is approximately 1×10 19 cm -3 , and the Al component content in the AlGaN layer is approximately 20%.

[0054] 2. Surface cleaning: Before etching, use acetone, isopropyl alcohol, and deionized water to perform ultrasonic cleaning for 10 minutes in sequence to remove organic substances and particles.

[0055] 3. Etching: Define the area where the pGaN layer needs to be removed through lithography, and use an SF6 / BCl3 mixed plasma to etch the pGaN to remove the pGaN layer and slightly etch into the AlGaN surface.

[0056] Typical gas flow ratio: SF6:BCl3 = 1:3, etching rate is approximately 30 nm / min, and the specific etching time depends on the thickness of the pGaN.

[0057] 4. Surface treatment: After etching, the exposed AlGaN surface can be first cleaned with low-power Ar plasma for 60 seconds to remove etching residues and damaged layers.

[0058] 5. Photolithography to define the ohmic region: Perform photolithography again to determine the position for subsequent ohmic contact metal deposition, ensuring that the metal is only deposited within the target area.

[0059] 6. Metal deposition: Deposit multi-layer metals of Ti / Al / Ni / Au in sequence. Thickness: Ti 20nm, Al 100nm, Ni 30nm, Au 50nm, with a total thickness of about 200nm. The deposition method uses electron beam evaporation.

[0060] 7. Passivation: Cover a layer of Si3N4 on the metal layer and the device surface as a passivation layer, with a thickness of about 50nm.

[0061] 8. Opening holes: Through photolithography and etching, open windows on the passivation layer to expose the metal electrode area.

[0062] 9. Rapid thermal annealing RTA: Under a nitrogen protection atmosphere, perform rapid thermal annealing at about 800°C for 60 seconds to form an alloy ohmic contact between the metal and AlGaN / GaN.

[0063] Example 3 is the third example of the present invention. This example provides a process method for fabricating an ohmic contact on a pGaN gate-enhanced gallium nitride HEMT device, including the following steps:

[0064] 1. Substrate and epitaxial structure: Use a GaN layer and an AlGaN barrier layer epitaxially grown on a Si substrate, and grow a pGaN layer on the surface of the AlGaN barrier layer. The doping concentration of this pGaN layer is about 1×10 19 cm -3 , and the Al component content in the AlGaN layer is about 20%.

[0065] 2. Surface cleaning: Before etching, ultrasonically clean with acetone, isopropanol, and deionized water in sequence for 10 minutes to remove organic substances and particles.

[0066] 3. Etching: Define the area where the pGaN layer is to be removed through photolithography, and use an SF6 / BCl3 mixed plasma to etch the pGaN, removing the pGaN layer and slightly etching into the AlGaN surface.

[0067] Typical gas flow ratio: SF6:BCl3 = 1:5, etching rate is about 30nm / min, and the specific etching time depends on the thickness of the pGaN.

[0068] 4. Surface treatment: After etching, the exposed AlGaN surface is first cleaned with low-power Ar plasma for 60 seconds to remove etching residues and damaged layers.

[0069] 5. Lithography to define the ohmic region: Perform lithography again to determine the positions for subsequent ohmic contact metal deposition, ensuring that the metal is only deposited within the target area.

[0070] 6. Metal deposition: Deposit multiple layers of Ti / Al / Ni / Au metals in sequence, with thicknesses: Ti 20 nm, Al 100 nm, Ni 30 nm, Au 50 nm, and a total thickness of approximately 200 nm. The deposition method can use electron beam evaporation.

[0071] 7. Passivation: Cover a layer of SiO2 with a thickness of approximately 100 nm as a passivation layer on top of the metal layer and the device surface.

[0072] 8. Opening holes: Through lithography and etching, open windows on the passivation layer to expose the metal electrode areas.

[0073] 9. Rapid thermal annealing RTA: Under a nitrogen protection atmosphere, perform rapid thermal annealing at around 850 °C for 60 seconds to form an alloy ohmic contact between the metal and AlGaN / GaN.

[0074] Experimental Example 1 verifies the effects of covering the passivation layer before annealing and surface treatment after etching on reducing the ohmic contact resistance and semiconductor sheet resistance, and simultaneously examines the effects of process parameters such as different etching gas ratios and annealing conditions on device performance:

[0075] 1. Experimental objects and grouping

[0076] Select a batch of pGaN gate-enhanced GaN HEMT wafers with the same substrate and epitaxial layer, and the epitaxial structures are consistent:

[0077] Substrate: Si(111)

[0078] GaN barrier layer thickness: approximately 3.0 μm

[0079] AlGaN barrier layer thickness: approximately 22 nm, Al content approximately 20%

[0080] pGaN layer thickness: 60 - 70 nm, doping concentration approximately 1×10 19 cm -3

[0081] For this batch of wafers, under the same lithography and metal deposition conditions, comparative grouping tests are carried out based on whether to cover the passivation layer before annealing, different etching gas ratios, and annealing temperatures. The specific grouping and process parameters are shown in the following table.

[0082] 2. Experimental procedure

[0083] Use photoresist to define the source and drain ohmic contact regions on the pGaN surface.

[0084] Use SF6 / BCl3 plasmas with different ratios to etch the selected ohmic regions, removing the pGaN layer and slightly etching into the AlGaN surface.

[0085] After etching, clean the etching residues, or use Ar / O2 plasma to remove the damaged layer, and perform a quick soak in dilute acid if necessary.

[0086] Deposit Ti / Al / Ni / Au in sequence as the ohmic electrode metal, with a total thickness of 200 nm.

[0087] After completing the metal deposition, cover some of the devices with a SiN or SiO2 passivation layer (with a thickness of 50 - 100 nm).

[0088] Use photolithography and etching processes to open windows on the devices covered with the passivation layer, exposing the ohmic electrode regions.

[0089] Under an Ar atmosphere, the typical annealing temperature is 850 °C, and hold for 60 s to fully alloy the metal with the semiconductor surface to form an ohmic contact.

[0090] Use the TLM (Transmission Line Model) method to measure the contact resistance and sheet resistance respectively, and evaluate the quality of the ohmic contact through linear fitting.

[0091] 3. Experimental comparison

[0092] The following table shows some selected typical groups and test results. The control group omitted the passivation coverage before annealing, and the example group fully implemented the surface treatment after etching and the passivation layer coverage process before annealing.

[0093] Table 1:

[0094]

[0095] From Table 1, it can be obtained that:

[0096] On the premise that other parameters of the control group and the invention group are similar, the only difference is whether to cover the passivation layer before annealing. Its contact resistance is reduced from about 0.80 - 0.85 Ω·mm to about 0.42 - 0.55 Ω·mm, proving that the surface treatment after etching combined with the passivation layer coverage has an obvious effect on forming a good ohmic contact.

[0097] The sheet resistance of the devices in the invention group is generally lower than that of the control group, which helps to reduce the on-state loss of the devices and improve the efficiency of high-power and high-frequency operation.

[0098] Increasing the ratio of SF6:BCl3 can improve the pGaN removal rate, but may also increase the surface damage of AlGaN; through passivation and surface repair before annealing, the negative impact on contact resistance can be effectively reduced.

[0099] Appropriately increasing the RTA temperature (such as 850 °C) can further promote the alloying of the metal and nitride interface, and the contact resistance can reach as low as 0.42 Ω·mm; however, if the temperature is too high or the time is too long, it may cause uneven metal diffusion or surface roughening.

[0100] The test results of multiple batches show that the devices implementing the process of the present invention perform better in terms of repeatability and consistency.

[0101] In summary, from the above experimental data and analysis, it can be seen that the process for fabricating ohmic contacts on pGaN gate-enhanced GaN HEMT devices described in the present invention, especially the combination of surface treatment after etching, covering a passivation layer before annealing, and annealing conditions, is crucial for obtaining low contact resistance and low sheet resistance. Compared with the control group without covering the passivation layer, the contact resistance can generally be reduced by about 30% - 50%, and the sheet resistance also decreases by 10% - 20%, providing better conduction characteristics and reliability for GaN devices for high-power, high-frequency, and high-temperature applications.

[0102] It should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit them. Although the present invention has been described in detail with reference to the preferred embodiments, those of ordinary skill in the art should understand that the technical solutions of the present invention can be modified or equivalently replaced without departing from the spirit and scope of the technical solutions of the present invention, and they should all be covered within the scope of the claims of the present invention.

Claims

1. A process for fabricating an ohmic contact on a pGaN gate-enhanced gallium nitride HEMT device, characterized in that: including Step S1: Wet or dry clean the pGaN layer to remove organic matters and particles Step S2: Etch the pGaN layer with an SF6 / BCl3 mixed etching gas until reaching the AlGaN surface or a preset depth Step S3: Perform surface treatment on the exposed surface of the etched AlGaN layer to remove the damaged layer affected by etching Step S4: Perform photolithographic patterning in the target ohmic contact area Step S5: Deposit a Ti / Al / Ni / Au metal layer successively in the ohmic contact area Step S6: Cover a passivation layer on the device surface after completing the metal deposition Step S7: Open a window in the passivation layer through photolithography and etching to expose the Ti / Al / Ni / Au metal layer Step S8: Perform rapid thermal annealing (RTA) on the device under a protective atmosphere to form an ohmic contact between Ti / Al / Ni / Au and the AlGaN and GaN layers 2. The process method for fabricating an ohmic contact on a pGaN gate-enhanced gallium nitride HEMT device as described in claim 1, characterized in that: In the SF6 / BCl3 mixed etching gas, the flow ratio of SF6 to BCl3 is 1:1 to 1:10, and the etching time is controlled according to the thicknesses of the pGaN layer and the AlGaN layer so that the etching depth does not exceed 50% of the thickness of the AlGaN layer 3. A process method for fabricating an ohmic contact on a pGaN gate-enhanced gallium nitride HEMT device as claimed in claim 1, wherein, The surface treatment includes at least one of the following processes Removing etching residues using inert gas plasma, performing wet cleaning with dilute acid or dilute alkali solution, and removing etching damage using a vacuum annealing process 4. A process for fabricating an ohmic contact on a pGaN gate-enhanced gallium nitride HEMT device as claimed in claim 1, characterized in that: In the Ti / Al / Ni / Au metal layer, the thickness ranges of Ti, Al, Ni, and Au are 5 nm to 50 nm, 30 nm to 200 nm, 5 nm to 50 nm, and 10 nm to 100 nm respectively, and the total thickness is 100 nm to 300 nm 5. A process for fabricating an ohmic contact on a pGaN gate-enhanced gallium nitride HEMT device as claimed in claim 1, characterized in that: The passivation layer is made of at least one of Si3N4, SiO2, or Al2O3 or their composite structure, and the thickness is 20 nm to 200 nm 6. The process method for fabricating an ohmic contact on a pGaN gate-enhanced gallium nitride HEMT device as described in claim 1, characterized in that: The temperature range of the rapid thermal annealing (RTA) is 750 °C to 900 °C, the holding time is 30 s to 120 s, and the protective atmosphere is N2 or Ar 7. A process for fabricating an ohmic contact on a pGaN gate-enhanced gallium nitride HEMT device as claimed in claim 1, characterized in that: Before photolithographically defining the ohmic region in Step S4, a second photolithography or nitride etching is also included to remove the passivation layer and residual photoresist 8. A process for fabricating an ohmic contact on a pGaN gate-enhanced gallium nitride HEMT device as claimed in claim 1, characterized in that: The doping concentration of the pGaN layer is 10 18 ~10 19 cm -3 , and the Al component content in the AlGaN layer is 15% to 25%.

9. A process method for fabricating an ohmic contact on a pGaN gate-enhanced gallium nitride HEMT device as described in claim 1, characterized in that: After annealing in Step S8, measure and linearly fit the contact resistance and sheet resistance of the ohmic contact through a transmission line model (TLM) structure 10. A process for fabricating an ohmic contact on a pGaN gate-enhanced gallium nitride HEMT device as claimed in claim 1, characterized in that: The surface cleaning in Step S1 and the surface treatment in Step S3 can be combined or carried out step by step

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