Process method applied to manufacturing of semiconductor device
By using dry and wet etching processes in semiconductor device manufacturing, the stress layer is removed and the nitride layer is retained, combined with heat treatment, the poor focus problem caused by back unevenness is solved, and the uniformity and yield of the device are improved.
Patent Information
- Application Number
- CN202510379395.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-28
- Publication Date
- 2025-07-11
AI Technical Summary
In the existing semiconductor device manufacturing processes, the device uniformity and yield are poor, especially the problem of poor focus caused by uneven back is not effectively solved.
During the manufacturing process of semiconductor devices, the stress layer is removed through dry etching and wet etching processes, the nitride layer on the back of the wafer is retained, and combined with the heat treatment process, the back flatness is improved and the uniformity of the metal layer film thickness is improved.
Improves the poor focus defects caused by back unevenness and improves the yield of semiconductor devices.
Smart Images
Figure CN120302708A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the technical field of semiconductor devices and integrated circuits, and particularly to a process method applied to the manufacturing of semiconductor devices. Background Art
[0002] With the continuous development of the integrated circuit manufacturing process of semiconductor devices and the continuous reduction of device sizes, the influence of errors caused by the manufacturing process itself on devices is increasing. For example, the flatness of the back of the wafer also affects the uniformity and yield of the devices.
[0003] In view of this, there is an urgent need to provide a process method for improving the original manufacturing process, which does not require an additional photomask and can significantly improve the device uniformity and yield. Summary of the Invention
[0004] This application provides a process method applied to the manufacturing of semiconductor devices, which can solve the problem of poor uniformity and yield of the manufacturing process of semiconductor devices provided in the related art. The method includes:
[0005] Providing a wafer, on the front surface of which a semiconductor device is formed, on the back surface of which a first oxide layer is formed, a polysilicon layer is formed on the first oxide layer, and a first nitride layer is formed on the polysilicon layer;
[0006] Depositing a second oxide layer on the front surface of the wafer, the second oxide layer covering the semiconductor device, and the second oxide layer being a protective layer for the semiconductor device;
[0007] Depositing a second nitride layer on the front surface of the wafer, the second nitride layer covering the second oxide layer, and the second nitride layer being a stress layer for the semiconductor device;
[0008] Performing a heat treatment on the back surface of the wafer;
[0009] Removing the second nitride layer by a dry etching process and a wet etching process in sequence, and retaining the first nitride layer on the back surface of the wafer;
[0010] Performing a heat treatment on the front surface of the wafer.
[0011] In some embodiments, the depositing a second oxide layer on the front surface of the wafer includes:
[0012] Depositing silicon dioxide on the front surface of the wafer by a CVD process to form the second oxide layer.
[0013] In some embodiments, the depositing a second nitride layer on the front surface of the wafer includes:
[0014] The second nitride layer is formed by depositing silicon nitride on the front side of the wafer through a CVD process.
[0015] In some embodiments, heat treatment is performed on the back side of the wafer, including:
[0016] Performing the heat treatment on the back side of the wafer through an RTA process.
[0017] In some embodiments, heat treatment is performed on the front side of the wafer, including:
[0018] Performing the heat treatment on the front side of the wafer through an LSA process.
[0019] In some embodiments, the semiconductor devices formed on the front side of the wafer include CMOS devices.
[0020] In some embodiments, the semiconductor devices formed on the front side of the wafer include N-type CMOS devices and P-type CMOS devices.
[0021] The technical solution of this application has at least the following advantages:
[0022] By removing the stress layer of the semiconductor device through a dry etching process and a wet etching process in sequence during the manufacturing process of the semiconductor device and retaining the nitride layer on the back side of the wafer, the erosion of the back side by the wet etching process can be reduced, thereby improving the defects caused by poor focusing due to the uneven back side in the subsequent process, improving the uniformity of the film thickness of the metal layer formed subsequently, and further improving the yield. Description of the Drawings
[0023] In order to more clearly illustrate the specific embodiments of the present application or the technical solutions in the prior art, the following will briefly introduce the drawings required for use in the description of the specific embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.
[0024] Figure 1 is a flowchart of a process method applied to the manufacturing of semiconductor devices provided by an exemplary embodiment of the present application;
[0025] Figures 2 to 7 is a manufacturing schematic diagram of the process method provided by an exemplary embodiment of the present application. Detailed Embodiments
[0026] The technical solutions in the present application will be clearly and completely described below with reference to the accompanying drawings. Apparently, the described embodiments are only a part of the embodiments of the present application, rather than all of the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present application without creative efforts shall fall within the scope of protection of the present application.
[0027] In the description of the present application, it should be noted that the orientation or positional relationship indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. is based on the orientation or positional relationship shown in the drawings. It is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as a limitation to the present application. In addition, the terms "first", "second", "third" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance.
[0028] In the description of the present application, it should be noted that unless otherwise clearly defined and limited, the terms "mounted", "connected", "coupled" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, an electrical connection; it can be directly connected, or indirectly connected through an intermediate medium, and can also be the communication inside two elements. It can be a wireless connection or a wired connection. For those of ordinary skill in the art, the specific meanings of the above terms in the present application can be understood according to specific situations.
[0029] In addition, the technical features involved in different embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.
[0030] Reference Figure 1 , which shows a flowchart of a process method applied to semiconductor device manufacturing provided by an exemplary embodiment of the present application. As Figure 1 shown, the method includes:
[0031] Step S1, providing a wafer, on the front surface of which a semiconductor device is formed, on the back surface of which a first oxide layer is formed, a polysilicon layer is formed on the first oxide layer, and a first nitride layer is formed on the polysilicon layer.
[0032] Among them, the semiconductor devices formed on the front side of the wafer include complementary metal-oxide semiconductor (CMOS) devices. The area on the wafer for forming CMOS devices includes a first area and a second area. The first area is used to form N (negative) type CMOS devices, and the second area is used to form P (positive) type CMOS devices.
[0033] Step S2: Deposit a second oxide layer on the front side of the wafer. The second oxide layer covers the semiconductor devices and serves as a protective layer for the semiconductor devices.
[0034] Reference Figure 2 , which shows a cross-sectional schematic diagram after the formation of the second oxide layer. Exemplarily, as Figure 2 shown, CMOS devices are formed on the front side of the wafer 210. A first oxide layer 251 is formed on the back side of the wafer 210. A polysilicon layer 232 is formed on the first oxide layer 251. A first nitride layer 261 is formed on the polysilicon layer 232. The second oxide layer 252 can be deposited by chemical vapor deposition (CVD) process to form silicon dioxide (SiO2). The second oxide layer 252 covers the CMOS devices on the front side of the wafer 210. The thickness of the second oxide layer 252 is to 200 angstroms.
[0035] Among them, the epitaxial layer CMOS device includes a polysilicon gate 231, a gate dielectric layer 220, and heavily doped regions 2141 and 2142 in the wafer 210 on both sides of the polysilicon gate 231 (when the CMOS device operates, the polysilicon gate 231 can serve as the gate of the CMOS device, and the heavily doped regions 2141 and 2142 can serve as the source and drain of the CMOS device respectively). The CMOS devices are isolated by a shallow trench isolation (STI) structure 212 formed in the wafer 210. Lightly doped drain (LDD) regions 213 are also formed in the wafer 210 on both sides of the polysilicon gate 231. The depth of the LDD regions 213 is deeper than that of the heavily doped regions 2141 and 2142. The LDD regions 213 are formed in the well region 211. A first isolation layer 241 and a second isolation layer 242 are sequentially formed on the peripheral side of the polysilicon gate 231. The first isolation layer 241 includes an oxide layer, and the second isolation layer 242 includes a nitride layer. Among them, the concentration of the impurities doped in the heavily doped regions 2141 and 2142 is greater than that of the impurities doped in the LDD regions 213 and the well region 211.
[0036] Step S3, deposit a second nitride layer on the front side of the wafer. The second nitride layer covers the second oxide layer, and the second nitride layer is a stress layer of the semiconductor device.
[0037] Reference Figure 3 , which shows a cross-sectional schematic diagram after the formation of the second nitride layer. Exemplarily, as Figure 3 shown, the second nitride layer 253 can be deposited by chemical vapor deposition (CVD) process to form silicon nitride (Si3N4). The thickness of the second nitride layer 253 is from 200 angstroms to 400 angstroms. The second nitride layer 253 is used to accelerate the electron mobility of the CMOS device through stress, thereby increasing the drive current of the device.
[0038] Step S4, perform heat treatment on the back side of the wafer.
[0039] Reference Figure 4 , which shows a cross-sectional schematic diagram of heat treatment on the back side of the wafer. Exemplarily, as Figure 4 shown, the back side of the wafer 210 can be heat treated by rapid thermal anneal (RTA) process. While the back side of the wafer 210 is heat treated, the heavily doped regions 2141 and 2142 are activated. Among them, the temperature of the RTA process is from 1010 degrees Celsius (°C) to 1050 degrees Celsius.
[0040] Step S5, remove the second nitride layer by dry etching process and wet etching process in sequence, and retain the first nitride layer on the back side of the wafer.
[0041] Reference Figure 5 , which shows a cross-sectional schematic diagram after dry etching on the front side of the wafer; reference Figure 6 , which shows a cross-sectional schematic diagram after wet etching to remove the second nitride layer. Exemplarily, as Figure 5 and Figure 6 shown, after the dry etching process and the wet etching process are carried out in sequence, the second nitride layer 253 is removed. Among them, the reaction gases used in the dry etching process include oxygen (O2) and / or nitrogen (N2), and the chemicals in the wet etching process are SPM (which includes sulfuric acid (H2SO4) and hydrogen peroxide (H2O2)), hydrogen fluoride (HF) and SC1 (which includes ammonium hydroxide (NH4OH), hydrogen peroxide and deionized water). Since the second nitride layer 253 is not completely removed by the wet etching process, the first nitride layer 261 on the back side of the wafer 210 is retained.
[0042] Step S6, perform heat treatment on the front side of the wafer.
[0043] Reference Figure 7, which shows a schematic diagram of the heat treatment profile of the front side of the wafer. Exemplarily, as Figure 7 shown, the front side of the wafer 210 can be heat-treated by a laser spike annealing (LSA) process. Among them, the temperature of the LSA process is 1010 degrees Celsius to 1070 degrees Celsius.
[0044] In summary, in the embodiments of the present application, during the manufacturing process of semiconductor devices, when performing the stress memorization technique (SMT) process, the stress layer of the semiconductor device is removed successively by a dry etching process and a wet etching process, and the nitride layer on the back side of the wafer is retained, which can reduce the erosion of the back side by the wet etching process, thereby improving the defects caused by poor focus due to unevenness of the back side in the subsequent process, improving the uniformity of the film thickness of the metal layer formed subsequently, and further improving the yield.
[0045] Obviously, the above embodiments are merely examples for clear illustration and are not limitations on the implementation manners. For those of ordinary skill in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to enumerate all the implementation manners here. And the obvious changes or modifications derived therefrom are still within the protection scope of the present application.
Claims
1. A process method applied in the manufacture of semiconductor devices, characterized in that, Comprising: Providing a wafer, on the front surface of which a semiconductor device is formed, on the back surface of which a first oxide layer is formed, on which a polysilicon layer is formed, and on which a first nitride layer is formed; Depositing a second oxide layer on the front surface of the wafer, the second oxide layer covering the semiconductor device, and the second oxide layer being a protective layer for the semiconductor device; Depositing a second nitride layer on the front surface of the wafer, the second nitride layer covering the second oxide layer, and the second nitride layer being a stress layer for the semiconductor device; Performing a heat treatment on the back surface of the wafer; Removing the second nitride layer by a dry etching process and a wet etching process in sequence, and retaining the first nitride layer on the back surface of the wafer; Performing a heat treatment on the front surface of the wafer.
2. The method according to claim 1, wherein The depositing a second oxide layer on the front surface of the wafer includes: Depositing silicon dioxide on the front surface of the wafer by a CVD process to form the second oxide layer.
3. The method according to claim 2, wherein The depositing a second nitride layer on the front surface of the wafer includes: Depositing silicon nitride on the front surface of the wafer by a CVD process to form the second nitride layer.
4. The method according to claim 3, characterized in that The performing a heat treatment on the back surface of the wafer includes: Performing the heat treatment on the back surface of the wafer by an RTA process.
5. The method according to claim 4, characterized in that, The performing a heat treatment on the front surface of the wafer includes: Performing the heat treatment on the front surface of the wafer by an LSA process.
6. The method according to any one of claims 1 to 5, characterized in that The semiconductor device formed on the front surface of the wafer includes a CMOS device.
7. The method according to claim 6, wherein The semiconductor device formed on the front surface of the wafer includes an N-type CMOS device and a P-type CMOS device.