Chip packaging structure and detector

Abstract

The invention relates to the technical field of semiconductor packaging, and provides a chip packaging structure which comprises a chip and a cover cap, the cover cap is supported on the chip through a dielectric layer, one side, facing the cover cap, of the chip is provided with a light sensing area, the dielectric layer is provided with a field angle expanding structure used for expanding the field angle of the light sensing area, and the field angle expanding structure is used for expanding the field angle of the light sensing area. The center of the field angle expanding structure is provided with an opening for light to pass through to reach the photosensitive area. The invention further provides a detector which comprises the chip packaging structure. By arranging the dielectric layer, the quality problem caused by tiny defects or dust on the cap can be solved, meanwhile, the dielectric layer is improved, the field angle of the light sensing area of the chip can be expanded by designing the field angle expanding structure, and the problem of optical light blocking is avoided.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor packaging, and specifically provides a chip packaging structure and a detector. Background Art

[0002] In wafer-level packaging, due to process limitations, as Figure 1 shown, the distance between the cap and the photosensitive area is very close, and the minute defects on the cap and the minute dust outside are extremely likely to cause imaging quality problems. This results in a narrow processing window for the cap and a low yield; the external dust affects imaging and leads to poor user experience.

[0003] Therefore, in the prior art, a dielectric layer is added between the cap and the chip for packaging. As Figure 2 shown, after adding the dielectric layer, the distance between the cap and the photosensitive area can be significantly increased. Thus, the quality problems caused by minute defects or dust on the cap can be solved, and the yield and user experience can be improved.

[0004] However, after adding the dielectric layer, the field of view angle becomes smaller, causing the problem of optical light blocking. Summary of the Invention

[0005] The purpose of the present invention is to provide a chip packaging structure and a detector, which can at least solve some defects in the prior art.

[0006] To achieve the above purpose, an embodiment of the present invention provides the following technical solution: A chip packaging structure includes a chip and a cap, the cap is supported on the chip through a dielectric layer, a photosensitive area is provided on one side of the chip facing the cap, the dielectric layer has a field-of-view angle expanding structure for expanding the field of view angle of the photosensitive area, and an opening for light to pass through to reach the photosensitive area is provided at the center of the field-of-view angle expanding structure.

[0007] Further, the diameter of the opening on the side close to the chip is smaller than the diameter of the opening on the side close to the cap.

[0008] Further, at least part of the inner sidewall of the field-of-view angle expanding structure is in a slope shape, and along the direction from the cap to the chip, the inner sidewall of the field-of-view angle expanding structure tapers.

[0009] Further, at least part of the inner sidewall of the field-of-view angle expanding structure is in a stepped shape, the inner sidewall of the field-of-view angle expanding structure has several layers of platforms, the uppermost platform is close to the cap, and the lowermost platform is close to the chip.

[0010] Further, one side of the field-of-view angle expanding structure close to the cap is fixedly connected to the cap through a first connection area, and the inner edge of one side of the field-of-view angle expanding structure close to the chip is fixedly connected to the chip through a second connection area.

[0011] Further, at least one of the side of the chip facing the cap, the side of the cap facing the chip, and the wide field of view angle structure is provided with a getter, and the getter is located in the interval formed by enclosing the wide field of view angle structure, the cap, and the chip.

[0012] Further, the dielectric layer is electrically connected to the chip through a third connection area. The dielectric layer has a protruding portion extending outside the chip, and a pad is provided on the protruding portion. A conduction member for electrically connecting the pad and the third connection area is also provided in the dielectric layer.

[0013] Further, the side of the protruding portion away from the wide field of view angle structure has an extension section, the extension section extends along the direction from the cap to the chip, and the pad is provided on the extension section.

[0014] Further, an electrode is integrated on the dielectric layer, a getter is welded on the electrode, and the electrode is electrically connected to the pad.

[0015] Another technical solution provided by an embodiment of the present invention is: a detector, including the above chip packaging structure.

[0016] Compared with the prior art, the beneficial effects of the present invention are: by providing a dielectric layer, the quality problems caused by minute defects or dust on the cap can be solved. At the same time, by further improving the dielectric layer, the field of view angle of the photosensitive area of the chip can be enlarged by designing a wide field of view angle structure, avoiding the problem of optical light shielding. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 is a schematic vertical cross-sectional view of a conventional wafer-level package;

[0018] Figure 2 is Figure 1 a schematic diagram after adding a dielectric layer;

[0019] Figure 3 is a schematic diagram of using a ceramic nozzle for bonding (showing the obliquely arranged dielectric layer);

[0020] Figure 4 is a schematic vertical cross-sectional view of a chip packaging structure provided by an embodiment of the present invention (showing the protruding portion and the dielectric layer in a ramp structure);

[0021] Figure 5 is a schematic vertical cross-sectional view of a chip packaging structure provided by an embodiment of the present invention (showing the protruding portion and the dielectric layer in a stepped structure);

[0022] Figure 6 is a schematic vertical cross-sectional view of a chip packaging structure provided by an embodiment of the present invention (showing the dielectric layer using a combination of stepped and ramp structures);

[0023] Figure 7 A vertical cross-sectional view of a chip of a chip packaging structure provided by an embodiment of the present invention;

[0024] Figure 8 A vertical cross-sectional view of a dielectric layer of a chip packaging structure provided by an embodiment of the present invention (showing the protruding part and the dielectric layer with a slope structure);

[0025] Figure 9 A vertical cross-sectional view of a cap of a chip packaging structure provided by an embodiment of the present invention;

[0026] Figure 10 A vertical cross-sectional view of a chip packaging structure provided by an embodiment of the present invention (showing the extension section of the dielectric layer);

[0027] Figure 11 A vertical cross-sectional view of a chip packaging structure provided by an embodiment of the present invention with a getter provided (showing the extension section of the dielectric layer);

[0028] Figure 12 A vertical cross-sectional view of a chip packaging structure provided by an embodiment of the present invention (showing the dielectric layer integrated with electrodes);

[0029] In the reference numerals: 1 - chip; 10 - photosensitive area; 2 - cap; 3 - pad; 4 - ceramic nozzle; 5 - dielectric layer; 50 - protruding part; 6 - extension section; 70 - wide viewing angle structure near the cap side; 71 - wide viewing angle structure near the chip side; 72 - ramp-like structure; 73 - stepped structure; 80 - first connection area; 800 - first connection point; 801 - second connection point; 81 - second connection area; 810 - third connection point; 811 - fourth connection point; 82 - third connection area; 820 - fifth connection point; 821 - sixth connection point; 90 - getter; 91 - electrode. Detailed implementation manners

[0030] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0031] Please refer to Figures 3 to 12, an embodiment of the present invention provides a chip packaging structure, including a chip 1 and a cap 2. The cap 2 is supported on the chip 1 through a dielectric layer 5. One side of the chip 1 facing the cap 2 has a photosensitive area 10. The dielectric layer 5 also has an enlarged field-of-view angle structure for enlarging the field-of-view angle of the photosensitive area 10. The enlarged field-of-view angle structure is formed on the inner side of the dielectric layer 5, and the center of the enlarged field-of-view angle structure has an opening through which light can pass to reach the photosensitive area. Compared with the Figure 2 vertical dielectric layer 5, by forming an enlarged field-of-view angle structure on the inner side of the dielectric layer, the field-of-view angle of the photosensitive area 10 can be enlarged, avoiding the problem of optical light blocking caused by the dielectric layer. The present invention can not only solve the quality problems caused by tiny defects or dust on the cap, but also does not affect the field-of-view angle of the photosensitive area of the chip. Moreover, the enlarged field-of-view angle structure is directly formed on the dielectric layer, only the shape of the dielectric layer needs to be improved, without adding additional components, and the overall structure is simple and easy to manufacture.

[0032] Please refer to Figures 4 to 12 , to refine the above-mentioned enlarged field-of-view angle structure, the diameter of the opening near the chip side 71 is smaller than the diameter of the opening near the cap side 70. The inner edge of the enlarged field-of-view angle structure near the chip 1 is connected to the chip 1. Generally speaking, when the size of the chip 1 is fixed, the position where the dielectric layer is connected to the chip 1 is also relatively fixed, that is, the diameter of the opening of the enlarged field-of-view angle structure near the chip side 71 is relatively fixed. By designing the diameter of the opening near the chip side 71 to be smaller than the diameter of the opening near the cap side 70, the opening of the enlarged field-of-view angle structure expands outward from the chip 1 to the cap 2, so that external light within a larger angular range can enter the photosensitive area 10 through the cap 2, thereby playing a role in increasing the field-of-view angle of the photosensitive area 10.

[0033] Please refer to Figure 4 , at least part of the inner side wall of the enlarged field-of-view angle structure is in a slope shape, and along the direction from the cap to the chip, the inner side wall of the enlarged field-of-view angle structure tapers. The dielectric layer 5 increases the field-of-view angle through the design of the slope-shaped structure 72.

[0034] Please refer to Figure 5 , at least part of the inner side wall of the enlarged field-of-view angle structure is in a stepped shape. The inner side wall of the enlarged field-of-view angle structure has several layers of platforms. The topmost platform is close to the cap 2, and the lowermost platform is close to the chip 1. The dielectric layer 5 can also adopt a stepped structure 73 to achieve the function of increasing the field-of-view angle. The number of platforms of the steps is not limited, and multiple layers of steps can be made according to needs.

[0035] Please refer to Figure 6 , the function of increasing the field-of-view angle can also be achieved by adopting a combined structure of slope and step.

[0036] Please refer to Figures 4 to 12 , one side 70 of the wide field of view structure close to the cap is fixedly connected to the cap 2 through the first connection area 80, and one side 71 of the wide field of view structure close to the chip is fixedly connected to the chip 1 through the second connection area 81. The first connection area 80 includes a first connection point 800 and a second connection point 801, and the second connection area 81 includes a third connection point 810 and a fourth connection point 811. Among them, the first connection point 800 and the second connection point 801 are fixedly connected (only physical connection), and this connection method can be bonding, welding (solder welding, laser welding), etc., to achieve hermetic packaging. The third connection point 810 and the fourth connection point 811 are fixedly connected (only physical connection), and this connection method can be bonding, welding (solder welding, laser welding), etc., to achieve hermetic packaging. Preferably, the surfaces of the first connection point 800, the second connection point 801, the third connection point 810, and the fourth connection point 811 can be subjected to processing methods such as silk screening and gold plating. Preferably, the cap 2 can transmit the spectrum of the working band of the chip 1, and can also filter out the invalid band according to the working requirements. The surface of the cap 2 is coated with an optical film corresponding to the working band.

[0037] As Figure 3 shown, due to the limited size of the chip, after forming the wide field of view structure on the dielectric layer 5, there will be a problem of interference between the bonding tool (the bonding tool is the bonding tool) and the structure during wire bonding. If the bonding process is to be satisfied, it is necessary to increase the size of the chip 1 to design the pad 3 more outward, resulting in an increase in the cost of the chip 1. Please refer to Figures 4 to 12 , the dielectric layer 5 has a protruding portion 50 extending outside the chip 1, and the pad 3 electrically connected to the chip 1 is provided on the protruding portion 50. By forming a wide field of view structure on the dielectric layer 5 to expand the field of view angle of the chip photosensitive area, and then improving the dielectric layer 5, the protruding portion 50 is designed to provide a place for the pad 3, so that interference with the bonding tool can be avoided during bonding, and the bonding process requirements can be met without increasing the size of the chip 1, reducing the size of the chip 1 in the traditional package and reducing the cost. In this embodiment, the protruding portion 50 is designed on the dielectric layer 5, and the protruding portion 50 can extend outside the range covered by the chip 1, so that the pad 3 on the chip 1 can be transferred to the protruding portion 50, and then electrically connected to the chip 1, so that the bonding problem can be solved without increasing the chip 1, compared with Figure 3 the form of Figure 2 and Figure 3Both of the two structures can only lead out signals by wire bonding. The process form is single, and the wires need to be protected, resulting in a complex structure and high cost. In this embodiment, without changing the design of the chip 1, the defects caused by the conventional wafer-level packaging cap 2 and dust can be solved, and the field of view angle requirements can also be met. For the above features, the chip 1 plays a role in photoelectric conversion, and the cap 2 plays a role in transmitting specific band spectra and filtering out invalid band spectra. There is a photosensitive area 10 on the chip 1, and the photosensitive area 10 has the function of converting optical signals into electrical signals, and the electrical signals are led out through the pads 3. This embodiment uses the intermediate structure of the dielectric layer 5 to increase the distance between the focal plane and the window, reduce the influence of minute defects of the window and external dust on the imaging quality. Increase the process window, improve the production yield, and at the same time enhance the user experience. Electrically conduct through the dielectric layer 5 and the chip 1, so that the electrical lead-out space is not restricted, and the field of view angle can be increased.

[0038] In this embodiment, the dielectric layer is electrically connected to the chip through the third connection area 82, and a conduction member for electrically connecting the pad 3 and the third connection area 82 is also provided in the dielectric layer. The third connection area 82 includes a fifth connection point 820 and a sixth connection point 821. The fifth connection point 820 and the sixth connection point 821 are connected, and the third connection area 82 is electrically conducted with the pad 3. Electrical connection methods such as bonding (selecting a glue with conductive function, such as conductive silver paste) or soldering (selecting solder welding, such as tin, etc.) can be used, and the surface is plated with metal materials such as nickel, gold, silver, etc. It can be either through internal wiring or external wire bonding. The materials used can be ceramic materials, silicon materials, etc.

[0039] Preferably, the surface of the pad 3 can conduct electricity, and a conventional aluminum pad 3 or a gold-plated pad 3 can be used.

[0040] Please refer to Figure 10 and Figure 11 , one side of the protrusion 50 away from the wide field of view angle structure has an extension section 6, and the extension section 6 extends along the direction from the cap 2 to the chip 1, and the pad 3 is provided on the extension section 6. After designing the extension section 6, the pad 3 is no longer limited to being set only on the upper surface of the dielectric layer 5, and the pad 3 can also be set on the bottom layer or the side wall of the dielectric layer 5. In this way, surface mount technology can be used, without wire bonding and secondary packaging, and electrical connection methods such as reflow soldering or laser ball soldering can be directly used, increasing the user's process selectivity.

[0041] Please refer to Figures 4 to 12 , the wide field of view angle structure and the protrusion 50 are integrally formed, that is, the dielectric layer can be integrally formed, and it is only divided into two parts by attributes. Of course, they can also be spliced by independent parts, as long as the corresponding performance requirements are met.

[0042] Please refer to Figure 11 , on at least one place on the side of the chip 1 facing the cap 2, the side of the cap 2 facing the chip 1, and the wide field of view structure, there is an getter 90, and the getter 90 is located in the interval formed by enclosing the wide field of view structure, the cap, and the chip. For devices that require vacuum packaging, on the basis of hermetic packaging, the getter 90 is arranged in the area outside the effective optical area on the inner side of the cap 2, or the getter 90 is arranged on the inner side of the dielectric layer 5, or the getter 90 is arranged on the chip 1. During the vacuum packaging process, the getter 90 is heated and activated, so that the surface of the getter 90 has activity to maintain a long-term high vacuum in the packaging cavity. The getter 90 can adopt a thin film getter 90.

[0043] Please refer to Figure 12 , an electrode 91 is integrated on the dielectric layer 5, the getter 90 is welded on the electrode 91, and the electrode 91 is conducted with the pad 3. For devices that require vacuum packaging, on the basis of hermetic packaging, the electrode 91 is integrated on the dielectric layer 5, and the getter 90 is welded on the electrode 91. The electrode 91 is conducted with the pad 321. After vacuum packaging, the pad 3 is electrified, and the getter 90 material is activated by the resistance heat of the getter 90 substrate, so that the surface of the getter 90 has activity to maintain a long-term high vacuum in the packaging cavity.

[0044] Please refer to Figures 4 to 12 , the dielectric layer 5 has an annular structure, and the photosensitive area 10 is located in the central annular area of the annular structure. The dielectric layer 5 as a whole has an annular structure, and its base material can be selected from resin, glass, ceramic, etc. As Figure 8 shown, it is a structural form of one of the dielectric layers 5, and this structure is an annular structure, Figure 8 which is a schematic vertical cross-section. Of course, the position of the hermetic packaging is also annular, and this position of the hermetic packaging can also be called the bonding area.

[0045] An embodiment of the present invention provides a detector, including the above-mentioned chip packaging structure. By adopting the above-mentioned wafer-level chip packaging structure, by setting the dielectric layer 5, the quality problems caused by tiny defects or dust on the cap 2 can be solved. At the same time, by improving the dielectric layer 5, the convex portion 50 is designed to provide a place for the pad 3 to be arranged, so that interference with the bonding nozzle 4 can be avoided during bonding, and the bonding process requirements can be met without increasing the size of the chip 1, reducing the size of the chip 1 in traditional packaging and reducing the cost.

[0046] Although the embodiments of the present invention have been shown and described, for those of ordinary skill in the art, it can be understood that various changes, modifications, substitutions, and variations can be made to these embodiments without departing from the principles and spirits of the present invention, and the scope of the present invention is defined by the appended claims and their equivalents.

Claims

1. A chip packaging structure, comprising a chip and a cap, wherein the cap is supported on the chip through a dielectric layer, and is characterized in that: One side of the chip facing the cap has a photosensitive area. The dielectric layer has a wide field-of-view angle structure for expanding the field-of-view angle of the photosensitive area. The center of the wide field-of-view angle structure has an opening through which light can pass to reach the photosensitive area.

2. The chip packaging structure according to claim 1, wherein: The diameter of the opening near the chip side is smaller than the diameter of the opening near the cap side.

3. The chip packaging structure according to claim 2, characterized in that: At least a part of the inner sidewall of the wide field-of-view angle structure is ramp-shaped. Along the direction from the cap to the chip, the inner sidewall of the wide field-of-view angle structure tapers.

4. The chip packaging structure according to claim 2 or 3, characterized in that: At least a part of the inner sidewall of the wide field-of-view angle structure is stepped. The inner sidewall of the wide field-of-view angle structure has several layers of platforms. The uppermost platform is close to the cap, and the lowermost platform is close to the chip.

5. The chip packaging structure according to claim 2, characterized in that: One side of the wide field-of-view angle structure close to the cap is fixedly connected to the cap through a first connection area. The inner edge of the side of the wide field-of-view angle structure close to the chip is fixedly connected to the chip through a second connection area.

6. The chip packaging structure according to claim 1, wherein: At least one of the side of the chip facing the cap, the side of the cap facing the chip, and the wide field-of-view angle structure is provided with a getter. The getter is located in the interval formed by the enclosure of the wide field-of-view angle structure, the cap, and the chip.

7. The chip packaging structure according to claim 1, wherein: The dielectric layer is electrically connected to the chip through a third connection area. The dielectric layer has a protrusion extending outside the chip. A pad is provided on the protrusion. A conduction member for electrically connecting the pad and the third connection area is also provided inside the dielectric layer.

8. The chip package structure according to claim 7, wherein: The side of the protrusion away from the wide field-of-view angle structure has an extension section. The extension section extends along the direction from the cap to the chip. The pad is provided on the extension section.

9. The chip packaging structure according to claim 1, wherein: An electrode is integrated on the dielectric layer. A getter is welded on the electrode. The electrode is electrically connected to the pad.

10. A detector, characterized in that: It includes the chip packaging structure according to any one of claims 1-9.

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