Method for improving heat dissipation performance of AlGaInP red light Micro LED chip

Abstract

The invention discloses a method for improving the heat dissipation performance of an AlGaInP red light Micro LED chip. The method comprises the following steps: S1, preparing an epitaxial structure: processing a substrate and a buffer layer, growing an etching barrier layer and an ohmic contact layer, and carrying out stacking epitaxy on a functional layer; s2, patterning the silicon-based substrate: preparing a dielectric layer and a metal structure; s3, diamond ohmic contact layer integration: processing a p-type conductive diamond film layer, and carrying out metal reflection and bonding; s4, removing the substrate and forming an n-type structure: stripping the substrate to be in n-type contact; s5, back-end process integration: preparing an electrode and an optical structure; according to the invention, the heat dissipation performance of the chip is significantly improved; the series resistance is reduced by 30%-50%; the resistivity of the p / n type diamond ohmic contact layer is reduced by 1-2 orders of magnitude compared with ITO; gaAs material light absorption and metal shading are avoided, and the red light transmittance is improved from 75% to more than 90% by combining with the micro lens array; the method is compatible with existing MOCVD, CVD and photoetching processes, large-scale production of wafers of 2-12 inches can be achieved, and the manufacturing cost is reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of Micro LED chip preparation, and specifically relates to a method for improving the heat dissipation performance of AlGaInP red MicroLED chips. Background Art

[0002] In AlGaInP red Micro LED chips, the traditional ITO (indium tin oxide) material as an ohmic contact layer has significant defects: its thermal conductivity is only 10-20 , and the heat accumulation under high current density causes the chip junction temperature to rise, leading to a decrease in the quantum well efficiency and wavelength drift; at the same time, the transmittance of ITO in the red light band (620-660nm) is about 80%-90%, and an additional metal layer is required to reduce the contact resistance, further introducing a light shielding effect; diamond materials, with their ultra-high thermal conductivity (above 2000 ), high red light transmittance (>95%) and doping-adjustable conductivity, become an ideal solution to solve the above problems; however, the lattice mismatch (about 12%) between diamond and AlGaInP materials and the patterning preparation process of the ohmic contact layer are the key technical difficulties restricting its practical application. Summary of the Invention

[0003] The purpose of the present invention is to provide a method for improving the heat dissipation performance of AlGaInP red Micro LED chips, which realizes the coordinated improvement of high-efficiency heat dissipation, low contact resistance and high transmittance by replacing the traditional ITO material with a conductive diamond material and combining epitaxial structure design and chip process optimization.

[0004] To solve the above technical problems, the technical solution adopted by the present invention is: A method for improving the heat dissipation performance of AlGaInP red Micro LED chips, comprising the following steps: S1, epitaxial structure preparation: Substrate and buffer layer treatment: Select an n-type GaAs substrate, clean it and then epitaxially grow an n-type GaAs buffer layer by MOCVD, controlling the doping concentration, thickness and temperature; Etch stop layer and ohmic contact layer growth: Epitaxially grow an n-type etch stop layer on the buffer layer, and then grow an n-type GaN / InGaN ohmic contact layer by MOCVD; Functional layer stacked epitaxy: Epitaxially grow an n-type AlInP confinement layer, an n-type superlattice structure, an undoped spacer layer, a quantum well structure, a p-type spacer layer, a p-type confinement layer, a p-type superlattice, a p-type graded layer and a p-type heavily doped layer in sequence on the ohmic contact layer, precisely controlling the parameters of each layer; S2, patterning of the silicon-based substrate: Preparation of dielectric layer and metal structure: Clean the silicon wafer / silicon-based CMOS, and deposit by PECVD the dielectric layer, lithographically form a Cr metal mask, sputter the seed layer and electroplate Cu metal after etching, and perform CMP polishing. For the height difference between the dielectric layer and the Cu metal and the root mean square roughness of the dielectric layer are measured to ensure they are within the required range; S3, Integration of diamond ohmic contact layer: Processing of p-type conductive diamond film layer: After cleaning the epitaxial wafer, grow the p-type conductive diamond film layer by CVD / PVD, lithographically etch to form a mesa structure, etch through the quantum well structure, use ALE to repair sidewall damage and deposit a passivation layer; Metal reflection and bonding: Etch the passivation layer to open holes to the p-type conductive diamond film layer, deposit a metal reflection layer, and prepare a protective layer by PECVD, deposit a film layer to control warping; hybrid bond the silicon-based substrate and the epitaxial structure; S4, Substrate removal and n-type structure formation: Substrate stripping and n-type contact: Etch to remove the back plating film layer, wet-etch to remove the GaAs substrate and the buffer layer, expose the n-type GaN / InGaN layer, grow the n-type conductive diamond film layer by CVD / PVD and etch it into shape; S5, Integration of back-end processes: Preparation of electrodes and optical structures: Deposit metal electrodes, and form a microlens array or a metasurface structure by lithography and etching to improve the light extraction efficiency.

[0005] In a preferred embodiment, in step S1, the doping source of the n-type GaAs buffer layer is disilane, and the doping concentration is 2.0×10 18 -3.0×10 18 cm -3 , the thickness is 100 - 300 nm, and the film-forming temperature is 620 - 700 °C.

[0006] In a preferred embodiment, in step S1, the n-type etch stop layer, where x is 0.1 - 0.2, y is 0.5, its doping source is disilane, and the doping concentration is 1.0×10 17 -1.5×10 18 cm -3 , the thickness is 100 - 300 nm, and the film-forming temperature is 700 - 780 °C.

[0007] In a preferred embodiment, in step S1, the doping source of the n-type GaN / InGaN ohmic contact layer is monosilane, and the doping concentration is 5.0×1018 -2.0×10 19 cm -3 , with a thickness of 10 - 40 nm, a film formation temperature of 700 - 950 °C, and a film formation method of rapid nucleation with a low V / III ratio and rapid film formation with a high V / III ratio.

[0008] In a preferred embodiment, in step S2, the dielectric layer has a thickness of 1 - 3 μm; the Cr metal mask has a thickness of 50 - 150 nm.

[0009] In a preferred embodiment, in step S2, after CMP polishing, the height difference between the dielectric layer and the Cu metal is ≤ 5 nm, the root mean square roughness (Rq) of the dielectric layer is < 0.2 nm, the test area is 2 μm × 2 μm, and there are no particles > 1 μm in a 10 μm × 10 μm area.

[0010] In a preferred embodiment, in step S3, the p-type conductive diamond film layer has a thickness of 10 - 300 nm, is prepared by chemical vapor deposition (CVD) or physical vapor deposition (PVD), the doping source is boron, and the mobility and carrier concentration are improved by optimizing the boron-carbon ratio, growth temperature, methane concentration, and annealing temperature.

[0011] In a preferred embodiment, in step S3, the mesa structure has an etched size of 1 - 50 μm in diameter, a pixel pitch of 2 - 75 μm, and the etching gas is and ; the passivation layer is , , or , with a thickness of 10 - 100 nm.

[0012] In a preferred embodiment, in step S3, the metal reflective layer is one or more of Cr, Au, Ag, has a thickness of 5 - 100 nm, and is deposited by sputtering or electron beam evaporation; the bonding accuracy of the hybrid bonding is 50 - 100 nm, the bonding temperature is 100 - 400 °C, and the pressure is 10 - 100 KN.

[0013] In a preferred embodiment, in step S4, the n-type conductive diamond film layer has a thickness of 10 - 300 nm, is prepared by CVD / PVD, the doping source is nitrogen or phosphorus, and the conductivity is improved by optimizing the growth temperature, doping, and annealing temperature.

[0014] Due to the application of the above technical solutions, the beneficial effects of this application compared with the prior art are as follows: 1. Significantly improved heat dissipation performance: The thermal conductivity of diamond is more than 100 times that of ITO. Under a high current density (50 A / cm²), the chip junction temperature is reduced by 15 - 20 °C, and the thermal-induced brightness attenuation rate is reduced from 15% to less than 8%.

[0015] 2. Optimized optoelectronic performance: The series resistance is reduced by 30% - 50%; the resistivity of the p / n-type diamond ohmic contact layer is reduced by 1 - 2 orders of magnitude compared to ITO.

[0016] 3. The light output power is increased by more than 25%: Absorption of light by GaAs material and light shielding by metal are avoided. Combined with a microlens array, the red light transmittance is increased from 75% to more than 90%.

[0017] 4. Strong process compatibility: Compatible with existing MOCVD, CVD, and lithography processes, enabling large-scale production of 2 - 12-inch wafers and reducing manufacturing costs. Description of the Drawings

[0018] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following will briefly introduce the drawings required for use in the description of the specific embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0019] Figure 1 It is a flowchart of a method for improving the heat dissipation performance of AlGaInP red Micro LED chips according to the present invention; Figure 2 It is a processing schematic diagram of steps S1-1 to S1-4 in the method of Embodiment 1 of the present invention; Figure 3 It is a processing schematic diagram of step S2-1 in the method of Embodiment 1 of the present invention; Figure 4 It is a processing schematic diagram of step S2-2 in the method of Embodiment 1 of the present invention; Figure 5 It is a processing schematic diagram of step S2-3 in the method of Embodiment 1 of the present invention; Figure 6 It is a processing schematic diagram of step S2-4 in the method of Embodiment 1 of the present invention; Figure 7 It is a processing schematic diagram of steps S3-1 to S3-2 in the method of Embodiment 1 of the present invention; Figure 8 It is a processing schematic diagram of step S3-3 in the method of Embodiment 1 of the present invention; Figure 9 It is a processing schematic diagram of step S3-4 in the method of Embodiment 1 of the present invention; Figure 10 It is a processing schematic diagram of step S3-5 in the method of Embodiment 1 of the present invention; Figure 11 It is a processing schematic diagram of step S3-6 in the method of Embodiment 1 of the present invention; Figure 12 It is a processing schematic diagram of step S3-7 in the method of Embodiment 1 of the present invention; Figure 13 It is a processing schematic diagram of step S4-1 in the method of Embodiment 1 of the present invention; Figure 14 It is a processing schematic diagram of step S4-2 in the method of Embodiment 1 of the present invention; Figure 15 It is a processing schematic diagram of step S4-3 in the method of Embodiment 1 of the present invention; Figure 16 It is a processing schematic diagram of step S5-1 in the method of Embodiment 1 of the present invention; Wherein, 1. GaAs substrate; 2. n-type GaAs buffer layer; 3. n-type etch stop layer; 4. n-type GaN / InGaN ohmic contact layer; 5. n-type AlInP confinement layer; 6. n-type superlattice structure; 7. undoped spacer layer; 8. undoped graded layer; 9. InGaP / undoped quantum well structure; 10. p-type spacer layer; 11. p-type AlInP or confinement layer; 12. p-type superlattice structure; 13. p-type graded layer; 14. p-type heavily doped layer; 15. silicon wafer or silicon-based CMOS; 16. dielectric layer; 17. Cr metal mask; 18. seed layer; 19. Cu metal; 20. p-type conductive diamond film layer; 21. mask layer; 22. passivation layer; 23. metal reflection layer; 24. film layer; 25. film layer; 26. n-type conductive diamond film layer; 27. electrode metal film layer; 28. microlens array. Detailed implementation manners

[0020] In order to enable those skilled in the art to better understand the solution of the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present application.

[0021] It should be noted that the terms "first", "second", etc. in the description, claims and the above-mentioned drawings of this application are used to distinguish similar objects, and do not necessarily need to describe a specific order or sequence. It should be understood that such data used can be interchanged under appropriate circumstances, so as to implement the embodiments of this application described herein. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device that includes a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0022] In this application, the orientation or positional relationship indicated by the terms "upper", "lower", "left", "right", "front", "rear", "top", "bottom", "inner", "outer", "middle", "vertical", "horizontal", "lateral", "longitudinal", etc. is based on the orientation or positional relationship shown in the drawings. These terms are mainly used to better describe the present invention and its embodiments, and are not used to limit that the indicated devices, elements or components must have a specific orientation, or be constructed and operated in a specific orientation.

[0023] Moreover, in addition to being able to represent an orientation or positional relationship, some of the above terms may also be used to represent other meanings. For example, the term "upper" may also be used to represent a certain attachment relationship or connection relationship in some cases. For those of ordinary skill in the art, the specific meanings of these terms in the present invention can be understood according to specific circumstances.

[0024] In addition, the terms "mount", "set", "provided with", "connected", "coupled", "socketed" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral structure; it can be a mechanical connection or an electrical connection; it can be directly connected, or indirectly connected through an intermediate medium, or there can also be internal communication between two devices, elements or components. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0025] It should be noted that, without conflict, the embodiments and features in the embodiments of this application can be combined with each other. The following will detail this application with reference to the drawings and in combination with embodiments.

[0026] Embodiment 1 Please refer to Figure 1-16 , this application provides a method for improving the heat dissipation performance of an AlGaInP red Micro LED chip, including the following specific steps: S1-1. Select an n-type doped GaAs substrate 1 (wafer size 2 - 12 inches, thickness 350 - 650 μm, single-side polished / double-side polished). After cleaning it with acetone, isopropyl alcohol (IPA), and deionized water, use an MOCVD system to epitaxially grow an n-type GaAs buffer layer 2 on the substrate, and control the doping concentration, thickness, and film formation temperature of this buffer layer within the required range. Specifically, the doping source of the n-type GaAs buffer layer 2 is disilane, and the doping concentration is 2.0×10 18 -3.0×10 18 cm -3 , the thickness is 100 - 300 nm, and the film formation temperature is 620 - 700 °C; relieve the stress between the substrate and the epitaxial layer and provide a uniform conductive channel; S1-2. At the required temperature, epitaxially grow an n-type etch stop layer 3 on the above buffer layer, and determine the value ranges of x and y and the film formation thickness range of the etch stop layer. Specifically, in the n-type etch stop layer 3, x is 0.1 - 0.2, y is 0.5, its doping source is disilane, and the doping concentration is 1.0×10 17 -1.5×10 18 cm -3 , the thickness is 100 - 300 nm, and the film formation temperature is 700 - 780 °C; the etch stop layer provides a selective etching boundary; S1-3. Place the substrate in the MOCVD reaction chamber and epitaxially grow an n-type GaN / InGaN ohmic contact layer 4 at a certain temperature. Specifically, the doping source of the n-type GaN / InGaN ohmic contact layer 4 is silane, and the doping concentration is 5.0×10 18 -2.0×10 19 cm -3 , the thickness is 10 - 40 nm, the film formation temperature is 700 - 950 °C, and the film formation method is low V / III ratio rapid nucleation and high V / III ratio rapid film formation; the n-type GaN / InGaN ohmic contact layer 4 has a large bandgap (3.4 eV), very weak absorption of red light, and a high doping concentration (>10 19 cm -3 ) to reduce the contact resistance; S1-4. Epitaxially grow multiple functional layers on the ohmic contact layer in sequence, including an n-type AlInP confinement layer 5, an n-type superlattice structure 6, an undoped spacer layer, a quantum well structure, a p-type spacer layer, a p-type confinement layer, a p-type superlattice structure 12, a p-type graded layer 13, and a p-type heavily doped layer 14, and precisely control the growth temperature, thickness, doping concentration, and doping source of each layer. Specifically; n-type AlInP confinement layer 5: Grow a 10-400nm n-type AlInP confinement layer 5 at 700-780°C with a doping concentration of 1.0×10 17 -1.5×10 18 cm -3 , limit carrier diffusion and improve injection efficiency; n-type superlattice structure 6: growing 5-25 periods of n-type at the same temperature / Superlattice structure, where x1 is 0.1-0.2, y1=0.5, x2 is 0.8-0.9, y2=0.5, the single layer thickness is 2.5-25nm, and the doping concentration is 1.0×10 17 -1.5×10 18 cm -3 ; Adjust the band structure and optimize electron transport; Non-doped spacer layer: grow 40-80nm non-doped Spacer layer 7, wherein x is 0.6-0.8, y=0.5, and a plurality of non-doped layers are grown between the non-doped spacer layer and the n-type superlattice structure 6 Gradient layer 8, x changes gradually from 0.8-0.9 to 0.6-0.8, y=0.5; relieves interface stress and reduces carrier scattering; Quantum well structure: 1-5 cycles of InGaP / grown at 710-790°C Undoped quantum well structure 9, where x is 0.7-0.8, y=0.5, InGaP thickness is 2-4 nm, The thickness is 5-8nm; red light emission (wavelength 620-660nm) is achieved through quantum confinement effect; P-type spacer layer: 40-80nm p-type grown at 700-780℃ Spacer layer 10, x is 0.8-0.9, y=0.5, doping source is , the doping concentration is 1.0×10 18 -3.0×10 18 cm -3 ; P-type confinement layer: 10-400nm p-type AlInP or Restriction layer 11, x is 0.9-0.95, y=0.5, doping source is , the doping concentration is 1.0×10 18 -3.0×10 18 cm -3 ; p-type superlattice structure 12: p-type with 5-25 periods grown at the same temperature / Superlattice structure, where x1 is 0.1 - 0.2, y1 = 0.5, x2 is 0.8 - 0.9, y2 = 0.5, the thickness of each layer is 2.5 - 25 nm, and the doping concentration is 1.0×10 18 -3.0×10 18 cm -3 ; p-type graded layer 13: Sequentially grow p-type graded layer (x1 is 0.8 - 0.9, y1 = 0.5) with a thickness of 20 - 60 nm, p-type graded layer (x2 gradually changes from 0.8 - 0.9 to 0.2 - 0.3, y2 = 0.5) with a thickness of 10 - 20 nm, p-type graded layer (x3 gradually changes from 0.2 - 0.3 to 0.01, y3 = 0.5) with a thickness of 10 - 20 nm. The doping concentration of the three layers is 1.0×10 18 -3.0×10 18 cm -3 ; p-type heavily doped layer 14: Sequentially grow p-type GaP-1 with a thickness of 20 - 60 nm at 720 - 800 °C, the film formation rate is about 1 - 3 μm / h, and the doping source is or C, and the doping concentration is 2.0×10 18 -4.0×10 18 cm -3 ; Grow p-type GaP-2 with a thickness of 80 - 120 nm at 520 - 560 °C, the film formation rate is about 6 - 10 μm / h, and the doping source is or C, and the doping concentration is 2.0×10 18 -4.0×10 18 cm -3 ; Grow p-type GaP-3 with a thickness of 10 - 30 nm at 520 - 560 °C, the doping source is C, and the doping concentration is 1.0×10 19 -3.0×10 19 cm -3 ; Form a hole transport channel, and finally reduce the p-side contact resistance through the p-type GaP-3 heavily doped layer; S2-1, select a silicon wafer or silicon-based CMOS15 (wafer size 2 - 12 inches). After cleaning it with acetone, isopropyl alcohol (IPA), and deionized water, use PECVD equipment to generate a dielectric layer 16 with a thickness of 1 - 3 μm on its surface; then A Cr metal mask 17 with a thickness of 50 - 150 nm is formed by photolithography on the dielectric layer 16, and the photoresist is removed; a high-precision patterned substrate is formed to provide a flat interface for subsequent bonding; S2 - 2, the processed silicon wafer or silicon-based CMOS 15 is cleaned and dried with acetone, isopropyl alcohol (IPA), and deionized water, and then an ICP etching equipment is used to etch the dielectric layer 16, and the etching gas is , , Ar, , etc., the etching depth is 1 - 3 μm, and the width is 1 - 5 μm; S2 - 3, the etched silicon wafer or silicon-based CMOS 15 is cleaned and dried with acetone, isopropyl alcohol (IPA), and deionized water, and then a sputtering equipment is used to generate a seed layer 18 on the dielectric layer 16. The metal of the seed layer 18 is not limited to Ti, Cu, etc., and the film thickness of the seed layer 18 is 10 - 300 nm; subsequently, a Cu metal 19 is deposited on the seed layer 18 by an electroplating equipment; S2 - 4, polish the dielectric layer 16, Cr metal mask 17, seed layer 18, and Cu metal 19, and measure the height difference between the dielectric layer 16 and Cu metal 19 and the root mean square roughness of the dielectric layer 16 to ensure it is within the required range. Specifically, the height difference between the dielectric layer 16 and Cu metal 19 ≤ 5 nm, the root mean square roughness (Rq) of the dielectric layer 16 < 0.2 nm, the test area is 2 μm × 2 μm, and there are no particles > 1 μm in the 10 μm × 10 μm area; S3 - 1, the epitaxial wafer prepared in step S1 - 4 is cleaned and dried with acetone, isopropyl alcohol (IPA), and deionized water, and a p-type conductive diamond film layer 20 is grown on its surface by a chemical vapor deposition (CVD) or physical vapor deposition (PVD) equipment. The doping source is boron, and the mobility and carrier concentration are improved by optimizing the boron-carbon ratio (1:50 - 1:200), growth temperature (700 - 900 °C), methane concentration (5% - 15%), and annealing temperature (800 - 1000 °C); S3 - 2, after cleaning and drying with acetone, isopropyl alcohol (IPA), and deionized water, a mask layer 21 is prepared on the p-type conductive diamond film layer 20 through spin coating, exposure, and development. The material type includes PR colloid, A dielectric layer 16, a Cr metal mask 17, etc.; Plasma etching, reactive ion etching (RIE) and other etching equipment are used to etch the p-type conductive diamond film layer 20; After that, ICP etching is used to perform mesa etching on the epitaxial wafer, and the etching size is 1 - 50 μm in diameter and 2 - 75 μm in pixel pitch. The etching gas is and ; The quantum well structure is etched through; S3 - 3, after cleaning and drying with acetone, isopropyl alcohol (IPA), and deionized water, an ALE device is used to repair the etched damaged layer on the sidewall of the mesa etching, and then a passivation layer 22 of the sidewall is deposited. The passivation layer 22 is 、 、 or with a thickness of 10 - 100 nm; Through processes such as spin coating, exposure, development, and ICP etching, an opening is made in the passivation layer 22 on the top of the mesa etching until the p-type conductive diamond film layer 20 is etched; Subsequently, a degluing process is performed, and after spin coating, exposure, and development again, a metal reflective layer 23 is deposited by sputtering or electron beam evaporation. The metal reflective layer 23 is one or more of Cr, Au, and Ag, with a thickness of 5 - 100 nm, and a degluing treatment is performed; S3 - 4, after cleaning and drying with acetone, isopropyl alcohol (IPA), and deionized water, a protective layer is formed on the surface of the epitaxial wafer by using a PECVD or ICPCVD device, with a film formation thickness of approximately 0.5 - 1 μm, and a film layer 24 of 0.5 - 1 μm is deposited on the back to effectively control the wafer warping; S3 - 5, a film layer 25 of 0.5 - 2 μm is deposited on the surface of the epitaxial wafer by using a PECVD or ICPCVD device to eliminate pore anomalies during the process. Subsequently, after cleaning and drying with acetone, isopropyl alcohol (IPA), and deionized water, CMP polishing is performed, where the root mean square roughness (Rq) of the film layer 25 < 0.2 nm, and the test area is 2 μm × 2 μm; S3 - 6, using an electron beam evaporation or sputtering device on the film layer 25, after spin coating, exposure, and development, a Cr metal mask 17 of 50 - 150 nm is deposited and a degluing treatment is performed; After cleaning and drying with acetone, isopropyl alcohol (IPA), and deionized water, an ICP etching device is used to etch the film layer 25, and the etching gas is , , ,Ar, , Etch to a depth of 1 - 2 μm and a width of 1 - 5 μm. After cleaning and drying with acetone, isopropyl alcohol (IPA), and deionized water, a seed layer 18 is formed. The metal of the seed layer 18 is not limited to Ti, Cu, etc. The film thickness of the seed layer 18 is 10 - 300 nm. Subsequently, Cu metal 19 is deposited using an electroplating device. Using a CMP device, polish the film layer 25, Cr metal mask 17, seed layer 18, and Cu metal 19. Measure the height difference between the film layer 25 and the Cu metal 19 and the root mean square roughness of the film layer 25 to ensure it is within the required range. Specifically, the height difference between the film layer 25 and the Cu metal 19 ≤ 5 nm, the root mean square roughness (Rq) of the film layer 25 < 0.2 nm, the test area is 2 μm × 2 μm, and there are no particles > 1 μm in the 10 μm × 10 μm area; S3 - 7, hybrid - bond the silicon wafer or silicon - based CMOS 15 with the GaAs substrate 1. The bonding accuracy requirement is 50 - 100 nm. In addition, parameters such as temperature (100 - 400 °C) and pressure (10 - 100 KN) need to be controlled and optimized to ensure the quality of the bonding interface. The diamond film layer has both high light transmittance (red light band > 95%) and low resistivity (< 10 -4 ), the reflective layer improves the light extraction efficiency, and the bonding process realizes electrical interconnection and mechanical support; S4 - 1, use an ICP etching device to remove the film layer 24 on the back of the silicon wafer or silicon - based CMOS 15; S4 - 2, use and solutions to remove the GaAs substrate 1 and the n - type GaAs buffer layer 2. After cleaning and drying with acetone, isopropyl alcohol (IPA), and deionized water, use HCl and solutions for wet etching until the n - type GaN / InGaN ohmic contact layer 4 is exposed. Completely remove the highly absorptive GaAs substrate 1; S4 - 3, use chemical vapor deposition (CVD) and physical vapor deposition (PVD) equipment to grow a 10 - 300 nm n - type conductive diamond film layer 26 on the n - type GaN / InGaN ohmic contact layer 4. By optimizing process parameters such as growth temperature (600 - 850 °C), nitrogen, and phosphorus doping concentrations (5.0×10 17 -2.0×10 19 cm -3, Annealing temperature (700 - 950 °C), etc. can improve the mobility and carrier concentration of the conductive diamond film layer. The n-type diamond layer forms a low-resistance contact with the n-type GaN / InGaN ohmic contact layer 4, thereby improving its conductivity. After cleaning and drying with acetone, isopropyl alcohol (IPA), and deionized water, a mask is prepared through spin coating, exposure, and development. The n-type conductive diamond film layer 26 is etched using plasma etching and reactive ion etching (RIE) equipment; S5-1, Using ICP etching, dry-etch the epitaxial wafer, and the etching gas is and ; After removing the relevant mask, clean and dry with acetone, isopropyl alcohol (IPA), and deionized water, and deposit the electrode metal film layer 27 and the microlens array 28 or the metasurface structure through processes such as spin coating, exposure, and development. The microlens array 28 reduces total reflection loss. Combining with the high light transmittance of the diamond film, the light extraction efficiency (LEE) is increased by 30% - 50% compared with the traditional scheme, improving the performance of the Micro LED chip.

[0027] Example Two This application provides a method for fabricating a 4-inch AlGaInP red Micro LED chip, including the following steps: S1-1, Select a 4-inch n-type GaAs substrate 1 with a thickness of 350 μm and a double-polished surface. After ultrasonic cleaning in acetone for 10 minutes, ultrasonic cleaning in isopropyl alcohol (IPA) for 10 minutes, and rinsing with deionized water for 5 minutes, dry with nitrogen. Use an MOCVD system to epitaxially grow an n-type GaAs buffer layer 2 on the substrate. The doping source is disilane, with a flow rate of 50 sccm and a doping concentration of 2.5×10 18 cm -3 , with a thickness of 200 nm and a film formation temperature of 650 °C; relieve the stress between the substrate and the epitaxial layer and provide a uniform conductive channel; S1-2, At the required temperature, epitaxially grow an n-type etch stop layer 3 on the above buffer layer, and determine the value ranges of x and y and the film formation thickness range of the etch stop layer; specifically, in the n-type etch stop layer 3, x is 0.15, y is 0.5, its doping source is disilane, with a flow rate of 30 sccm and a doping concentration of 1.20×10 17 cm -3 , with a thickness of 200 nm and a film formation temperature of 750 °C; the etch stop layer provides a selective etching boundary; S1-3, Place the substrate in the MOCVD reaction chamber and epitaxially grow an n-type GaN / InGaN ohmic contact layer 4 at a certain temperature; specifically, the doping source of the n-type GaN / InGaN ohmic contact layer 4 is monosilane, with a flow rate of 80 sccm and a doping concentration of 1.8×1019 cm -3 with a thickness of 25 nm, a film formation temperature of 850 °C, and a film formation method of rapid nucleation with a low V / III ratio and rapid film formation with a high V / III ratio. Specifically, the V / III ratio (TMG / ) = 50 (nucleation stage), and the V / III ratio (TMG / ) = 200 (film formation stage); the n-type GaN / InGaN ohmic contact layer 4 has a large bandgap (3.4 eV), very weak absorption of red light, and a high doping concentration (> 10 19 cm -3 ) to reduce the contact resistance; S1-4, a variety of functional layers are sequentially epitaxially grown on the ohmic contact layer, including an n-type AlInP confinement layer 5, an n-type superlattice structure 6, an undoped spacer layer, a quantum well structure, a p-type spacer layer, a p-type confinement layer, a p-type superlattice structure 12, a p-type graded layer 13, and a p-type heavily doped layer 14. The growth temperature, thickness, doping concentration, and doping source of each layer are precisely controlled; specifically: n-type AlInP confinement layer 5: An n-type AlInP confinement layer 5 with a thickness of 300 nm is grown at 750 °C, and the doping concentration is 1.5×10 18 cm -3 to confine the carrier diffusion and improve the injection efficiency; n-type superlattice structure 6: An 8-period n-type / superlattice structure is grown at the same temperature, where x1 is 0.1, y1 = 0.5, x2 is 0.85, y2 = 0.5, the single-layer thickness is 10 nm, and the doping concentration is 1.0×10 18 cm -3 ; adjust the energy band structure and optimize the electron transport; Undoped spacer layer: A 60-nm undoped spacer layer 7 is grown, where x is 0.75 and y = 0.5. A multi-layer undoped graded layer 8 is grown between the undoped spacer layer and the n-type superlattice structure 6, with x gradually changing from 0.8 to 0.6 and y = 0.5; relieve the interface stress and reduce the carrier scattering; Quantum well structure: A 3-period InGaP / undoped quantum well structure 9 is grown at 750 °C, where x is 0.75 and y = 0.5, the thickness of InGaP is 3 nm, and the thickness is 6 nm; realize red light emission (wavelength 630 nm) through the quantum confinement effect; p-type spacer layer: A 60-nm p-type spacer layer 10 is grown at 750 °C, where x is 0.85 and y = 0.5, and the doping source is , the doping concentration is 2.0×10 18 cm -3 ; p-type confinement layer: p-type AlInP with a thickness of 200 nm grown at the same temperature or confinement layer 11, where x is 0.9, y = 0.5, and the doping source is , the doping concentration is 2.0×10 18 cm -3 ; p-type superlattice structure 12: p-type / superlattice structure grown for 8 periods at the same temperature, where x1 is 0.1, y1 = 0.5, x2 is 0.85, y2 = 0.5, the thickness of each layer is 10 nm, and the doping concentration is 1.0×10 18 cm -3 ; p-type graded layer 13: p-type graded layer with a thickness of 40 nm (x1 is 0.8, y1 = 0.5), 10 nm of p-type graded layer (x2 gradually changes from 0.8 to 0.2, y2 = 0.5), 10 nm of p-type graded layer (x3 gradually changes from 0.2 to 0.01, y3 = 0.5). The doping concentration of the three layers is 2.0×10 18 cm -3 ; p-type heavily doped layer 14: At 750 °C, p-type GaP-1 with a thickness of 40 nm is grown in sequence, the film deposition rate is about 3 μm / h, and the doping source is or C, and the doping concentration is 2.0×10 18 cm -3 ; At 550 °C, p-type GaP-2 with a thickness of 100 nm is grown, the film deposition rate is about 10 μm / h, and the doping source is or C, and the doping concentration is 2.0×10 18 cm -3 ; At 550 °C, p-type GaP-3 with a thickness of 20 nm is grown, the doping source is C, and the doping concentration is 2.0×10 19 cm -3 ; Form a hole transport channel, and finally reduce the p-side contact resistance through the p-type GaP-3 heavily doped layer; S2-1. Select a 4-inch silicon wafer or silicon-based CMOS15. After cleaning it with acetone, isopropyl alcohol (IPA), and deionized water, use a PECVD device to generate a dielectric layer 16 with a thickness of 2 μm on its surface; then ; Then A Cr metal mask 17 with a thickness of 80 nm is formed by lithography on the dielectric layer 16, and the photoresist is removed; a high-precision patterned substrate is formed to provide a flat interface for subsequent bonding; S2-2. After the above-mentioned silicon wafer or silicon-based CMOS 15 is processed, it is cleaned and dried with acetone, isopropyl alcohol (IPA), and deionized water, and then an ICP etching equipment is used to etch the dielectric layer 16. The etching gas is , the etching depth is 2 μm, and the width is 3 μm; S2-3. After the etched silicon wafer or silicon-based CMOS 15 is cleaned and dried with acetone, isopropyl alcohol (IPA), and deionized water, a seed layer 18 is formed on the dielectric layer 16 by a sputtering equipment. The metal of the seed layer 18 is not limited to Ti, Cu, etc. The film thickness of the seed layer 18 is 100 nm; subsequently, a Cu metal 19 is deposited on the seed layer 18 by an electroplating equipment, the electroplating thickness is 5 μm, and the current density is 20 mA / cm²; S2-4. Polish the dielectric layer 16, Cr metal mask 17, seed layer 18, and Cu metal 19, and measure the height difference between the dielectric layer 16 and Cu metal 19 and the root mean square roughness of the dielectric layer 16 to ensure that they are within the required ranges. Specifically, the height difference between the dielectric layer 16 and Cu metal 19 is 2 nm, the root mean square roughness Rq of the dielectric layer 16 is 0.15 nm, the test area is 2 μm × 2 μm, and there are no particles > 1 μm in the 10 μm × 10 μm area; S3-1. After the epitaxial wafer prepared in step S1-4 is cleaned and dried with acetone, isopropyl alcohol (IPA), and deionized water, a p-type conductive diamond film layer 20 is grown on its surface by a chemical vapor deposition (CVD) or physical vapor deposition (PVD) equipment. The doping source is boron. By optimizing the boron-carbon ratio 1:100 ( / ), growth temperature (800 °C), methane concentration (10%), and annealing temperature (900 °C), the mobility and carrier concentration are improved; S3-2. After being cleaned and dried with acetone, isopropyl alcohol (IPA), and deionized water, a mask layer 21 is prepared on the p-type conductive diamond film layer 20 through spin coating, exposure, and development. The material type includes PR colloid, The dielectric layer 16, Cr metal mask 17, etc.; Plasma etching, reactive ion etching (RIE) and other etching equipment are used to etch the p-type conductive diamond film layer 20; After that, ICP etching is used to perform mesa etching on the epitaxial wafer. The size of the etching is a diameter of 10 μm and a pixel pitch of 35 μm. The etching gas is and ; Etch through the quantum well structure; S3-3. After cleaning and drying with acetone, isopropyl alcohol (IPA), and deionized water, an ALE device is used to repair the etched damaged layer on the sidewall of the mesa etching. After that, a passivation layer 22 of the sidewall is deposited. The passivation layer 22 is , with a thickness of 20 nm; Through processes such as spin coating, exposure, development, and ICP etching, an opening is made in the passivation layer 22 on the top of the mesa etching until the p-type conductive diamond film layer 20 is etched; Subsequently, a degluing process is performed, and after spin coating, exposure, and development again, a metal reflective layer 23 is deposited by sputtering or electron beam evaporation. The metal reflective layer 23 is Cr and Au, with a thickness of 30 nm, and a degluing treatment is performed; S3-4. After cleaning and drying with acetone, isopropyl alcohol (IPA), and deionized water, a PECVD or ICPCVD device is used to generate a protective layer on the surface of the epitaxial wafer. The film formation thickness is about 0.5 μm, and a film layer 24 with a thickness of 0.5 μm is deposited on the back to effectively control the wafer warping; S3-5. A PECVD or ICPCVD device is used to deposit a 1-μm film layer 25 on the surface of the epitaxial wafer to eliminate pore anomalies during the process. After that, after cleaning and drying with acetone, isopropyl alcohol (IPA), and deionized water, CMP polishing is performed. Among them, the root mean square roughness Rq of the film layer 25 is 0.15 nm, and the test area is 2 μm × 2 μm; S3-6. An electron beam evaporation or sputtering device is used on the film layer 25. After spin coating, exposure, and development, a 100-nm Cr metal mask 17 is deposited, and a degluing treatment is performed; After cleaning and drying with acetone, isopropyl alcohol (IPA), and deionized water, an ICP etching device is used to etch the film layer 25. The etching gas is , the etching depth is 2 μm, and the width is 5 μm; After cleaning and drying with acetone, isopropyl alcohol (IPA), and deionized water, a seed layer 18 is formed. The metal of the seed layer 18 is not limited to Ti, Cu, etc. The film formation thickness of the seed layer 18 is 200 nm; Subsequently, a Cu metal 19 is deposited using an electroplating device; Using a CMP device, the film layer 25, Cr metal mask 17, seed layer 18, and Cu metal 19 are polished. The height difference between the film layer 25 and the Cu metal 19 and the root mean square roughness of the film layer 25 are measured to ensure that they are within the required ranges. Specifically, the height difference between the film layer 25 and the Cu metal 19 is 2 nm, the root mean square roughness Rq of the film layer 25 is 0.15 nm, the test area is 2 μm × 2 μm, and there are no particles larger than 1 μm in the 10 μm × 10 μm area; S3-7, The silicon wafer or silicon-based CMOS 15 is hybrid bonded with the GaAs substrate 1, and the bonding accuracy requirement is 80 nm. In addition, parameters such as temperature (300 °C) and pressure (80 KN) need to be controlled and optimized to ensure the quality of the bonding interface; The diamond film layer has both high light transmittance (red light band > 95%) and low resistivity (< 10 -4 ), The reflective layer improves the light extraction efficiency, and the bonding process realizes electrical interconnection and mechanical support; S4-1, Use an ICP etching equipment to remove the film layer 24 on the back of the silicon wafer or silicon-based CMOS 15; S4-2, Use a solution with a volume ratio of 7:1 of and to remove the GaAs substrate 1 and the n-type GaAs buffer layer 2, with an etching rate of 6 μm / min; After cleaning and drying with acetone, isopropyl alcohol (IPA), and deionized water, wet etching is carried out with HCl and solution until the n-type GaN / InGaN ohmic contact layer 4 is exposed; The highly absorbent GaAs substrate 1 is completely removed; S4-3, Use chemical vapor deposition (CVD) and physical vapor deposition (PVD) equipment to grow a 150-nm n-type conductive diamond film layer 26 on the n-type GaN / InGaN ohmic contact layer 4. By optimizing process parameters such as growth temperature (650 °C), nitrogen and phosphorus doping concentrations (1.0×10 19 cm -3 ), annealing temperature (800 °C), etc., the mobility and carrier concentration of the conductive diamond film layer can be improved. The n-type diamond layer forms a low-resistance contact with the n-type GaN / InGaN ohmic contact layer 4, thereby improving its electrical conductivity; After cleaning and drying with acetone, isopropyl alcohol (IPA), and deionized water, a mask is prepared through spin coating, exposure, and development; Use plasma etching and reactive ion etching (RIE) equipment to etch the n-type conductive diamond film layer 26; S5-1, Use ICP etching to perform dry etching on the epitaxial wafer, and the etching gas is and After removing the relevant mask, it is cleaned and dried with acetone, isopropyl alcohol (IPA), and deionized water, and then coated with glue, exposed, developed, etc. to deposit the electrode metal film layer 27 and the microlens array 28 or the metasurface structure. The microlens array 28 reduces the total reflection loss. Combining with the high light transmittance of the diamond film, the light extraction efficiency (LEE) is increased by 45% compared with the traditional scheme, improving the performance of the Micro LED chip.

[0028] The Micro LED chips obtained through the above steps and the chips of the traditional ITO scheme will be tested for series resistance, light output power, junction temperature, and light extraction efficiency. The specific test methods are as follows: I. Series Resistance Test 1. Test principle: By measuring the voltage drop of the chip at different current densities and using Ohm's law to calculate the series resistance, the formula is: , where is the threshold voltage and I is the injection current.

[0029] 2. Test equipment: Semiconductor parameter analyzer (such as Keysight B1500A), probe station (accuracy ±1μm), constant temperature sample stage (temperature control ±0.5°C).

[0030] 3. Test steps: Fix the chip on the probe station and use tungsten probes (diameter 25μm) to contact the p / n electrodes; Apply a forward bias voltage (0 - 5V) and scan the current density range: 10 - 1000 A / cm²; Record the current-voltage (I-V) curve and calculate the series resistance by linearly fitting the curve slope.

[0031] Test environment: Room temperature (25°C), nitrogen atmosphere (to avoid oxidation).

[0032] 4. Data processing Exclude the influence of the built-in electric field generated by quantum well luminescence and take the linear region with a current density > 100 A / cm² for fitting.

[0033] Unit conversion: Chip area × resistance value = (specific contact resistivity).

[0034] II. Light Output Power Test 1. Test principle: Measure the light emission power of the chip through a photodetector and calculate the light emission efficiency in combination with the injection current. The spectral response of the detector (red light band 620 - 660 nm) needs to be calibrated.

[0035] 2. Test equipment: Spectrometer (such as Ocean Optics HR4000), integrating sphere (diameter 15 cm, reflectivity > 99%), current source (accuracy ±0.1%).

[0036] 3. Test steps: Place the chip at the center of the integrating sphere, make the probe contact the electrode, and inject a current of 10 μA (corresponding to a current density of about 100 A / cm²); The spectrometer scans the wavelength range of 600 - 700 nm, with a resolution of 1 nm and an integration time of 100 ms; Deduct the dark current background (the noise value when the light source is off), and calculate the integrated optical power value in the wavelength band of 620 - 660 nm; Repeat the test 3 times and take the average value to reduce random errors.

[0037] 4. Calibration method: Use a standard red LED (traceable to NIST, wavelength 630 nm, power 10 μW) to calibrate the response of the integrating sphere.

[0038] The spectrometer needs to be regularly calibrated for the light intensity - wavelength curve using a tungsten - halogen lamp.

[0039] Junction temperature test 1. Test principle: Use an infrared thermal imager to measure the chip surface temperature, and combine with the thermal resistance model to deduce the junction temperature. The formula is: , where is the surface temperature, is the thermal resistance, and P is the power consumption.

[0040] 2. Test equipment: Infrared thermal imager (resolution 640×512, wavelength range 7 - 14 μm), DC power supply (power accuracy ±0.5%), heat sink (temperature control ±1°C).

[0041] 3. Test steps: Fix the chip on the heat sink (temperature 25°C), and apply a continuous current density of 1000 A / cm² (close to the actual working conditions); Wait for 30 minutes until thermal equilibrium (temperature fluctuation < 0.5°C), and the thermal imager takes a picture of the chip surface temperature distribution; Select the central pixel of the light - emitting area (spatial resolution < 10 μm) to record the temperature ;

[0042] Obtain the thermal resistance through ANSYS simulation , and calculate the junction temperature .

[0043] 4. Error correction: The thermal imager needs to be calibrated for the emissivity (diamond surface emissivity 0.7, GaAs emissivity 0.3);

[0044] Exclude environmental light interference, and the test is carried out in a dark room.

[0045] IV. Measurement of Light Extraction Efficiency (LEE) 1. Measurement principle: The light extraction efficiency is defined as the ratio of the light output power of the chip to the internal light emission power, and is indirectly measured by the following methods: Measuring the actual light output power by the integrating sphere method ; Measuring the internal quantum efficiency (IQE) by the electroluminescence spectrum (EL) method and calculating the internal light emission power in combination with the injection current ; LEE = / × 100%.

[0046] 2. Measuring equipment: Electroluminescence spectrometer (EL, resolution 0.1 nm), fluorescence quantum efficiency measurement system (such as Horiba FluoroMax).

[0047] 3. Measurement steps Step 1, EL spectrum and IQE calculation: Apply a current density of 100 A / cm² and collect the EL spectrum (620 - 660 nm); Calculate through the formula where hv is the photon energy and e is the electron charge; Step 2, LEE calculation: Integrating sphere measurement = 15 μW (current 10 μA);

[0048] Assume IQE = 80%, then ( is the radiative recombination efficiency, take 0.9);

[0049] Calculate the LEE.

[0050] Through the above measurement methods, after measuring the Micro LED chips prepared in the second embodiment of the present application and the chips of the traditional ITO scheme (purchasing 4-inch GaAs LED epitaxial chips from Jiangxi Zhaochi Semiconductor Co., Ltd.), the following comparison information is obtained: The performance test comparison table is as follows:

[0051] The beneficial effects of the present application compared with the prior art are as follows: 1. The heat dissipation performance is significantly improved: The thermal conductivity of diamond is more than 100 times that of ITO. Under a high current density (50 A / cm²), the chip junction temperature is reduced by 15 - 20 °C, and the thermal-induced brightness attenuation rate is reduced from 15% to less than 8%.

[0052] 2. Optimization of optoelectronic performance: The series resistance is reduced by 30% - 50%: The resistivity of the p / n-type diamond ohmic contact layer is reduced by 1 - 2 orders of magnitude compared with ITO.

[0053] 3. The light output power is increased by more than 25%: Absorption of light by GaAs material and light shielding by metal are avoided. Combined with a microlens array, the red light transmittance is increased from 75% to over 90%.

[0054] 4. Strong process compatibility: Compatible with existing MOCVD, CVD and lithography processes, large-scale production of 2 - 12-inch wafers can be achieved, reducing the manufacturing cost.

[0055] Finally, it should be noted that the above are only the preferred embodiments of the present invention and are not used to limit the present invention. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements for some of the technical features. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A method for improving the heat dissipation performance of an AlGaInP red Micro LED chip, characterized in that, It includes the following steps: S1, Preparation of epitaxial structure: Substrate and buffer layer treatment: Select an n-type GaAs substrate. After cleaning, grow an n-type GaAs buffer layer by MOCVD, and control the doping concentration, thickness and temperature; Etch stop layer and ohmic contact layer growth: An n-type etch stop layer is epitaxially grown on the buffer layer, and then an n-type GaN / InGaN ohmic contact layer is grown by MOCVD; Stacked epitaxy of functional layers: Sequentially grow an n-type AlInP confinement layer, an n-type superlattice structure, an undoped spacer layer, a quantum well structure, a p-type spacer layer, a p-type confinement layer, a p-type superlattice, a p-type graded layer and a p-type heavily doped layer on the ohmic contact layer, and precisely control the parameters of each layer; S2, Patterning of silicon-based substrate: Preparation of dielectric layer and metal structure: Clean the silicon wafer / silicon-based CMOS, and deposit the dielectric layer by PECVD, lithographically form a Cr metal mask, sputter the seed layer and electroplate Cu metal after etching, and perform CMP polishing on the height difference between the dielectric layer and the Cu metal and the root mean square roughness of the dielectric layer are measured to ensure that they are within the required ranges; S3, Integration of diamond ohmic contact layer: Processing of p-type conductive diamond film layer: After cleaning the epitaxial wafer, grow a p-type conductive diamond film layer by CVD / PVD, and form a mesa structure by photolithography and etching, etch through the quantum well structure, and use ALE to repair sidewall damage and deposit a passivation layer; Metal reflection and bonding: Open holes in the etched passivation layer to the p-type conductive diamond film layer, deposit a metal reflection layer, and prepare by PECVD Protective layer, deposited on the back Film layer regulates warping; Hybrid bonding of the silicon-based substrate and the epitaxial structure; S4, Substrate removal and formation of n-type structure: Substrate stripping and n-type contact: Etch away the back plating film layer, wet-etch away the GaAs substrate and buffer layer to expose the n-type GaN / InGaN layer, grow an n-type conductive diamond film layer by CVD / PVD and etch it into shape; S5, Integration of back-end processes: Preparation of electrodes and optical structures: Deposit metal electrodes, and form a microlens array or a metasurface structure by photolithography and etching to improve the light extraction efficiency.

2. The method for improving the heat dissipation performance of an AlGaInP red Micro LED chip according to claim 1, wherein In step S1, the doping source of the n-type GaAs buffer layer is disilane, and the doping concentration is 2.0×10 18 -3.0×10 18 cm -3 , the thickness is 100 - 300 nm, and the film forming temperature is 620 - 700 °C.

3. The method for improving the heat dissipation performance of an AlGaInP red Micro LED chip according to claim 1, wherein In step S1, the n-type etch stop layer has x ranging from 0.1 to 0.2, y being 0.5, its doping source is disilane, and the doping concentration is 1.0×10 17 -1.5×10 18 cm -3 , the thickness is 100 - 300 nm, and the film formation temperature is 700 - 780 °C.

4. The method for improving the heat dissipation performance of an AlGaInP red Micro LED chip according to claim 1, wherein In step S1, the doping source of the n-type GaN / InGaN ohmic contact layer is silane, and the doping concentration is 5.0×10 18 -2.0×10 19 cm -3 . The thickness is 10 - 40 nm, the film formation temperature is 700 - 950 °C, and the film formation method is rapid nucleation with a low V / III ratio and rapid film formation with a high V / III ratio.

5. The method for improving the heat dissipation performance of an AlGaInP red Micro LED chip according to claim 1, characterized in that, In step S2, the thickness of the dielectric layer is 1-3 μm; the thickness of the Cr metal mask is 50-150 nm.

6. The method for improving the heat dissipation performance of an AlGaInP red Micro LED chip according to claim 1, wherein In step S2, after CMP polishing, the height difference between the dielectric layer and the Cu metal ≤ 5 nm, the root mean square roughness (Rq) of the dielectric layer < 0.2 nm, the test area is 2 μm × 2 μm, and there are no particles > 1 μm in the 10 μm × 10 μm area.

7. The method for improving the heat dissipation performance of an AlGaInP red Micro LED chip according to claim 1, wherein In step S3, the thickness of the p-type conductive diamond film layer is 10 - 300 nm, which is prepared by chemical vapor deposition (CVD) or physical vapor deposition (PVD). The doping source is boron, and the mobility and carrier concentration are improved by optimizing the boron-carbon ratio, growth temperature, methane concentration and annealing temperature.

8. The method for improving the heat dissipation performance of an AlGaInP red Micro LED chip according to claim 1, characterized in that In step S3, the etched mesa structure has a size of a diameter of 1 - 50 μm, a pixel pitch of 2 - 75 μm, and the etching gas is and ; the passivation layer is 、 、 or , with a thickness of 10 - 100 nm.

9. The method for improving the heat dissipation performance of an AlGaInP red Micro LED chip according to claim 1, wherein In step S3, the metal reflective layer is one or more of Cr, Au, Ag, with a thickness of 5 - 100 nm, and is deposited by sputtering or electron beam evaporation process; the bonding accuracy of the hybrid bonding is 50 - 100 nm, the bonding temperature is 100 - 400 °C, and the pressure is 10 - 100 KN.

10. The method for improving the heat dissipation performance of an AlGaInP red Micro LED chip according to claim 1, characterized in that, In step S4, the thickness of the n-type conductive diamond film layer is 10 - 300 nm, which is prepared by CVD / PVD. The doping source is nitrogen or phosphorus, and the conductivity is improved by optimizing the growth temperature, doping and annealing temperature.

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