High-In-component gallium nitride-based LED epitaxial structure, device and preparation method of high-In-component gallium nitride-based LED epitaxial structure

Abstract

The invention discloses a high-In-component gallium nitride-based LED epitaxial structure and device and a preparation method thereof, and belongs to the technical field of semiconductor device manufacturing. The epitaxial structure comprises a patterned InGaN template substrate, an epitaxial transverse overgrowth InGaN layer, an n-type semiconductor layer, a V-pits stress release layer, a multi-quantum well active region, a first p-type layer, an electron blocking layer and a second p-type layer from bottom to top. According to the epitaxial structure, the dislocation gathering position of a bottom layer template can be regulated and controlled, uniform distribution of space low stress of an epitaxial layer is promoted, and growth of a subsequent high-quality high-In-component LED epitaxial layer is facilitated, in the preparation method, on one hand, in-situ surface treatment is carried out on a quantum well region, impurity peaks related to defects can be relieved, and the light emitting purity of a device is guaranteed; and on the other hand, preparation of a small-size high-In-component GaN-based LED device can be realized in a low-dislocation and low-stress region, the risk of electric leakage is reduced, and the reliability of the device is improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor manufacturing, and particularly relates to a high-In-composition gallium nitride-based LED epitaxial structure, a device and a preparation method thereof. Background Art

[0002] Micro-LEDs exhibit great application potential in the field of full-color displays due to their high brightness, low power consumption, and ultrafast response. Currently, commercially available red LEDs generally use the AlGaInP material system, but this system has significant limitations: First, the high surface recombination rate and long carrier diffusion length result in a sharp increase in the proportion of non-radiative recombination induced by sidewall damage during the miniaturization process, leading to a sharp drop in the efficiency of small-sized devices; Second, the bandgap of AlGaInP is extremely sensitive to temperature, and the thermal stability of the device is severely challenged; Third, its operating voltage (2.0 - 2.5V) is significantly different from that of GaN-based micro-LEDs, increasing the complexity of the drive circuit design and making it difficult to meet the future development needs of high-integration and high-performance display devices. Therefore, researchers have focused on InGaN-based red LEDs that are homogeneously compatible with the blue-green light material system. InGaN-based red LEDs not only have the advantages of excellent thermal stability and no significant size effect, but also the homologous hetero-integration characteristics can accelerate the innovation of full-color display technology. However, the preparation of InGaN-based red LEDs still faces many challenges. On the one hand, long-wavelength emission requires a high In composition, and the stress mismatch between InGaN and GaN is large, which hinders the effective incorporation of In and easily induces a large number of dislocations; on the other hand, the method of reducing the growth temperature to improve the incorporation of In composition usually introduces a large number of defects, increasing non-radiative recombination and leakage current paths, and reducing the internal quantum efficiency and reliability of the device. It is worth noting that the V-type micropits (V-pits) induced by dislocations can provide a localized carrier transport path to enhance hole injection, and its surface barrier can also shield the capture of carriers by dislocations, thereby suppressing the leakage effect. However, too high a V-pits density may lead to a reduction in the effective light-emitting area of the active region and may also cause strong sidewall emission of the V-pits, affecting the spectral purity. Research shows that the epitaxial lateral overgrowth (ELO) technology can effectively reduce the dislocation density of heteroepitaxy, thereby improving the material quality and device performance. However, due to the non-uniform distribution of dislocations during the ELO process, it may lead to non-uniform stress fields, resulting in spatial distribution differences in the incorporation of In composition, and further affecting the wavelength uniformity of the device, which has an adverse impact on the final display effect. Summary of the Invention

[0003] Objects of the Invention: The first object of the present invention is to provide a high In-content gallium nitride-based LED epitaxial structure capable of achieving low stress and high quality. The second object of the present invention is to provide a method for preparing the above high In-content gallium nitride-based LED epitaxial structure. The third object of the present invention is to provide a device comprising the above high In-content gallium nitride-based LED epitaxial structure. The fourth object of the present invention is to provide a method for preparing the above device.

[0004] Technical Solution: The high In-content gallium nitride-based LED epitaxial structure of the present invention comprises, from bottom to top: a patterned InGaN template substrate, an epitaxial lateral overgrowth InGaN layer, an n-type semiconductor layer, a V-pits stress release layer, a multi-quantum well active region, a first p-type layer, an electron blocking layer, and a second p-type layer.

[0005] Further, the patterned InGaN template substrate comprises, from bottom to top: a growth substrate, a buffer layer, an InGaN layer, and a mask layer.

[0006] Further, the growth substrate includes sapphire, silicon carbide, silicon, gallium oxide, or zinc oxide.

[0007] Further, the material of the buffer layer is one or a combination of AlGaN, AlN, and GaN, the growth temperature is 700 - 1100 °C, and the thickness is 500 - 5000 nm.

[0008] Further, the material of the mask layer is a single-layer film of any one of silicon-containing oxide film (SiO x ), titanium nitride film (TiN, etc.), silicon nitride film (SiN x ), silicon oxynitride film (SiON), and a metal film with a high melting point (e.g., above 1000 °C), or a laminated film comprising at least two of these.

[0009] Further, the material of the n-type semiconductor layer is Al x In y Ga 1-x-y N, 0 ≤ 1 - x - y ≤ 1, the growth temperature is 800 - 1100 °C, the thickness is 100 - 5000 nm, and the Si doping concentration is 1 × 10 15 -1 × 10 21 cm -3 .

[0010] Further, the thickness of the V-pits stress release layer is 50 - 1000 nm, and the material is In x Ga 1-x N / n-GaN, where 0 ≤ x / y ≤ 1, the growth temperature is 700 - 1100 °C, the thicknesses of the single quantum well and the barrier are 1 - 10 nm / 1 - 20 nm respectively, and the Si doping concentration in the barrier is 1 × 1015 -1×10 21 cm -3 。

[0011] Furthermore, the growth temperature of the multiple quantum well active region is 700 - 900 °C, and the material is In x Ga 1-x N / Al y In z Ga 1-y-z N / Al x1 Ga 1-x1 N, where 0 ≤ x ≤ 1, 0 < 1 - y - z < 1, 0 ≤ x1 ≤ 1, the thickness of the In x Ga 1-x N well is 1 - 5 nm, the thickness of the Al y Ga 1-y N cap layer is 0.1 - 3 nm, the thickness of the Al x1 Ga 1-x1 N barrier is 5 - 50 nm, the Si doping concentration is 1×10 15 -1×10 21 cm -3 , and the logarithm is 1 - 20 pairs.

[0012] Furthermore, the material of the first p-type semiconductor layer is Al x In y Ga 1-x-y N, 0 ≤ 1 - x - y ≤ 1, the growth temperature is 600 - 900 °C, the thickness is 5 - 500 nm, and the Mg doping concentration is 1×10 15 -1×10 21 cm -3 。

[0013] Furthermore, the material of the electron blocking layer is Al x Ga 1-x N / Al y Ga 1-y N-based material, where 0 ≤ x < y ≤ 1, the Al component is higher than that of the quantum barrier, and it can be grown by a multi-segment pulse method with a gradually changing Al component, the temperature is 800 - 1100 °C, and the thickness is 10 - 500 nm to prevent electron overshoot.

[0014] Furthermore, the material of the second p-type semiconductor layer is Al x In y Ga 1-x-y N, 0 ≤ 1 - x - y ≤ 1, the growth temperature is 800 - 1100 °C, the thickness is 5 - 500 nm, and the Mg doping concentration is 1×10 19 -1×10 22 cm -3 。

[0015] The preparation method of the above-mentioned high-In-content gallium nitride-based LED epitaxial structure comprises the following steps:

[0016] (1) Prepare a patterned InGaN template substrate;

[0017] (2) Epitaxially grow an epitaxial lateral overgrowth InGaN layer and an n-type semiconductor layer in sequence on the upper side of the patterned InGaN template substrate, and epitaxially grow a V-pits stress relaxation layer on the n-type semiconductor layer;

[0018] (3) Epitaxially grow a multi-quantum well active region on the epitaxial V-pits stress relaxation layer;

[0019] (4) Epitaxially grow a first p-type layer, an electron blocking layer and a second p-type layer in sequence on the multi-quantum well active region.

[0020] Further, in step (1), the preparation method of the patterned InGaN template substrate is as follows:

[0021] S1. Prepare a growth substrate;

[0022] S2. Epitaxially grow a buffer layer on the upper side of the above-mentioned growth substrate;

[0023] S3. Epitaxially grow an InGaN layer on the above-mentioned buffer layer;

[0024] S4. Perform photolithography on the above-mentioned InGaN layer and perform dry etching to achieve patterning, thus obtaining a patterned InGaN template;

[0025] S5. Evaporate a mask on the above-mentioned patterned InGaN template;

[0026] S6. Remove the photoresist and the mask on its upper part, and obtain a patterned InGaN template substrate with periodic windows.

[0027] Further, in step (3), in the growth chamber, after each layer of quantum well is grown, in-situ treatment is carried out, and a single or combined mixed gas of NH3, H2, N2, and TBCl3 is introduced in a continuous or staged pulse manner. At a growth temperature of 700-1000 °C and a chamber pressure of 50-400 torr, in-situ thermal annealing is carried out for 3 s-5 min.

[0028] The device of the present invention comprises the above-mentioned high-In-content gallium nitride-based LED epitaxial structure, ITO, a passivation layer and electrodes.

[0029] The preparation method of the above-mentioned device comprises the following steps:

[0030] (11) Evaporate ITO on the above-mentioned high-In-content gallium nitride-based LED epitaxial structure;

[0031] (12) On the above-mentioned high-In composition gallium nitride-based LED epitaxial structure, a mesa region is defined by means of photolithography, electron beam direct writing or a mask template, and then the mesa is etched out by dry etching;

[0032] (13) A passivation layer is deposited for sidewall protection, and then the passivation layer is etched by means of photolithography, electron beam direct writing or a mask template to expose the electrode contact region,

[0033] (14) Metal is evaporated to form n and p electrodes;

[0034] (15) The redundant high dislocation density region is etched away both horizontally and vertically to define independent LED chips;

[0035] Or, the steps are as follows:

[0036] (11) ITO is evaporated on the above-mentioned high-In composition gallium nitride-based LED epitaxial structure;

[0037] (12) On the above-mentioned high-In composition gallium nitride-based LED epitaxial structure, a mesa region is defined by means of photolithography, electron beam direct writing or a mask template, and then the mesa is etched out by dry etching;

[0038] (13) The redundant high dislocation density region is etched away both horizontally and vertically to define independent LED chips;

[0039] (14) A passivation layer is deposited for sidewall protection, and then the passivation layer is etched by means of photolithography, electron beam direct writing or a mask template to expose the electrode contact region,

[0040] (15) Metal is evaporated to form n and p electrodes.

[0041] Principle of the invention: In the present invention, the ELO technology is combined with the V-pits stress relaxation layer to induce dislocations to form V-pits to achieve stress relaxation, improve the uniformity of the spatial stress distribution, avoid the problem of uneven distribution of the In composition in the subsequent quantum well due to the existence of a stress gradient, and at the same time relax the stress and improve the incorporation efficiency of In. In addition, the preparation of the device avoids the high dislocation region, reducing the risk of leakage. At the same time, the small amount of V-pits induced in the low dislocation region provides an additional path for the injection of holes, improving the radiative recombination efficiency. Secondly, in-situ treatment after the growth of the quantum well can improve the surface flatness of the c-plane multiple quantum well, relieve the compositional non-uniformity, reduce the full width at half maximum of the spectrum, and has an etching effect on the sidewalls of the V-pits, which can effectively suppress the sidewall luminescence and improve the purity of the spectrum.

[0042] Beneficial effects: Compared with the prior art, the present invention has the following remarkable advantages: (1) By epitaxially growing a Vpits stress release layer on the ELO layer, the present invention can effectively relax stress, avoid the generation of stress gradients in the same epitaxial layer, and thereby improve the incorporation efficiency of In while enhancing the uniformity of the composition; (2) The Vpits stress release layer grown by the present invention, in the effective region of device fabrication, a small number of V-pits can not only provide an additional hole injection path, but also shield the capture of carriers by dislocations, thereby enhancing radiative recombination and improving the internal quantum efficiency of the device; (3) The in-situ treatment of the quantum well by the present invention can improve the flatness of the epitaxial layer, etch defects such as In clusters, improve the quality of the quantum well, and at the same time have an etching effect on the sidewalls of the V-pits, which can suppress sidewall luminescence and improve spectral purity; (4) The present invention can selectively fabricate the device in the low dislocation region, isolate individual devices through the high dislocation region, facilitate the fabrication of small-size mciro-LEDs, and effectively avoid leakage caused by high dislocation density, thereby improving the reliability of the device. Description of the Drawings

[0043] Figure 1 It is a schematic structural diagram during the fabrication process of a semiconductor device including a gallium nitride-based LED epitaxial structure with a high In composition in Embodiment 1;

[0044] Figure 2 It is a top view schematic diagram during the fabrication process of a semiconductor device including a gallium nitride-based LED epitaxial structure with a high In composition in Embodiment 1. Detailed Embodiments

[0045] Next, the present invention will be further described in conjunction with specific embodiments and drawings.

[0046] Embodiment 1: As Figure 1 shown, the device provided in this embodiment including a gallium nitride-based LED epitaxial structure with a high In composition sequentially includes from top to bottom: a growth substrate 101, a buffer layer 102, an InGaN template layer 103, a mask layer 105, a laterally epitaxially regrown layer 106, an n-InGaN layer 107 (i.e., an n-type semiconductor layer), a V-pits stress release layer 108, a multi-quantum well active region 109, a first p-type layer p-AlInGaN 110, an electron blocking layer 111, a second p-type layer p-AlInGaN 112, ITO 113, a passivation layer 114, and an electrode.

[0047] As Figure 1 shown, the preparation method of the above device is as follows:

[0048] (1) Prepare a patterned InGaN template as follows: Grow a gallium nitride-based buffer layer 102 on a sapphire substrate 101 by MOCVD, grow an InGaN layer 103, then spin-coat a photoresist 104 and perform photolithography etching to obtain patterned InGaN. Further deposit a mask layer 105, and then remove the mask with the photoresist part.

[0049] The specific growth conditions are as follows:

[0050] S101: Growth of the buffer layer 102; The epitaxial buffer layer 102 is AlN, the growth temperature is 800 °C, and the thickness is 30 nm;

[0051] S102: For the InGaN layer 103, at 1000 - 1200 °C, introduce TMGa, NH3, SiH4, N2, and H2 to grow an InGaN layer with a thickness of 2000 nm;

[0052] S103: Spin-coat a negative photoresist on the above InGaN layer, then pre-bake for a period of time at a specific temperature. Subsequently, use a lithography machine to expose the sample, and put the exposed sample into a negative photoresist developer for development for some time to successfully prepare an epitaxial wafer with a periodic photoresist pattern. Among them, AZ7133 negative photoresist is spin-coated, and the spin-coating conditions are as follows: The low rotation speed is 500 - 700 s -1 ; The time is 5 - 7 s; The high rotation speed is 3500 - 4500 s -1 ; The pre-bake temperature is 100 - 110 °C; The time is 2 - 3 min; The exposure time is 2.3 - 2.8 s; The pre-bake temperature is 100 - 110 °C; The time is 2 - 3 min; The development treatment time is 30 - 40 s. Then use inductively coupled plasma etching (ICP) technology to etch the InGaN layer outside the photoresist. The etching conditions are as follows: The etching gases are Cl2 and BCl3, the gas flow rates are 48 sccm and 6 sccm respectively, the gas pressure is 10 mTorr, the RF power is 300 W, the ICP power is 100 W, and the etching depth is 300 nm.

[0053] S104: Deposit a SiN mask by PECVD with a thickness of 10 - 300 nm. The growth conditions are as follows: Introduce a mixed gas of SiH4 and NH3 into the reaction chamber, use N2 as the carrier gas, control the gas flow rate, and keep the chamber pressure, temperature, and power constant for a certain growth time. The flow rate range of NH3 is 100 - 400 sccm, the flow rate range of SiH4 gas is 20 - 50 sccm, the chamber pressure range is 100 - 1000 mTorr, the temperature range is 250 - 400 °C, the power range is 5 - 150 W, and the growth time is 0.5 - 20 min.

[0054] S105: Strip the SiN. Immerse the sample in acetone, alcohol, and deionized water in sequence until the photoresist and the SiN thereon are completely peeled off, and finally obtain a patterned InGaN template.

[0055] (2) Using MOCVD, epitaxially regrow an InGaN layer 106 on the upper side of the above-mentioned patterned InGaN template. At 800 - 1000 °C, introduce TMGa, TMIn, NH3, N2, and H2 into the chamber, with a thickness of 1000 nm. The width of this layer is 10 - 100 μm, and the width of this layer can be adjusted by the width of the patterned InGaN window and the conditions of lateral epitaxial regrowth. Further, epitaxially grow n-InGaN 107 on the InGaN layer 106, with a growth temperature of 800 - 1100 °C, a thickness of 1000 nm, and a Si doping concentration of 2×10 19 cm -3 . Then, epitaxially grow a V-pits stress relaxation layer 108 on the n-InGaN 107, with a thickness of 105 nm, and the material is In 0.1 Ga 0.9 N / n-GaN, with a growth temperature of 800 - 1100 °C, and the thicknesses of the single-well and the barrier are 3 nm / 4 nm respectively, and the Si doping concentration in the barrier is 5×10 17 cm -3 .

[0056] (3) Epitaxially grow a multi-quantum well active region 109 on the V-pits stress relaxation layer 108. At 700 - 900 °C, introduce TEGa, TMIn, TMAl, NH3, SiH4, N2, and H2. The growth consists of alternating barrier layers, capping layers, and well layers. The barrier layer is GaN, with a thickness of 15 nm and a Si doping concentration of 5×10 17 cm -3 , the capping layer is Al 0.1 Ga 0.9 N, with a thickness of 1 - 2 nm, the well layer is In 0.2 Ga 0.8 N, with a thickness of 2.5 - 3.5 nm, and there are 9 pairs. In-situ treatment is performed on each pair of quantum wells. Introduce a mixed gas of NH3 and H2 into the growth chamber, with a temperature of 700 - 900 °C, a chamber pressure of 200 torr, and the in-situ treatment lasts for 5 s.

[0057] (4) Further, epitaxially grow a first p-type layer 110 on the above-mentioned treated multi-quantum well active region 109. At 700 - 900 °C, introduce TEGa, TMIn, TMAl, NH3, Cp2Mg, N2, and H2. Its material is Al 0.02 In 0.03 Ga 0.95 N, with a thickness of 20 - 50 nm and a Mg doping concentration of 1×1020 cm -3 ; Further epitaxially grow an electron blocking layer 111. At 900 - 1100 °C, using Al 0.4 Ga 0.6 N as the barrier and GaN as the well, grow 6 pairs cyclically with thicknesses of 2 nm and 1 nm respectively, then use Al 0.2 Ga 0.8 N as the barrier and GaN as the well, grow 3 pairs cyclically with thicknesses of 2 nm and 1 nm respectively, then use Al 0.1 Ga 0.9 N as the barrier and GaN as the well, grow 3 pairs cyclically with thicknesses of 2 nm and 1 nm respectively, with a total thickness of 36 nm; Further epitaxially grow a second p-type layer 112. At 900 - 1000 °C, introduce TEGa, NH3, Cp2Mg, N2, H2, its material is GaN, with a thickness of 2 - 50 nm, and the Mg doping concentration is 5×10 19 cm -3 ;

[0058] (5) Further grow ITO 113 on the above epitaxial wafer. Using magnetron sputtering technology, introduce Ar 40 sccm and O2 0.4 sccm into the reaction chamber. Under the conditions of a pressure of 0.5 Pa and a power of 0.8 w, the growth time is 1750 s and the thickness is 100 nm. Form an ohmic contact between ITO and P-GaN through RTA rapid annealing, with an annealing temperature of 500 °C, a time of 3 min, a heating-up time of 20 s, and a cooling-down time of 120 s;

[0059] (6) As Figure 2 shown, perform photolithography and etching on the mesa of the above epitaxial wafer. Spin-coat positive photoresist on the epitaxial wafer, then pre-bake for a period of time at a specific temperature. Subsequently, use a photolithography machine to expose the sample, and put the exposed sample into the positive photoresist developer for development for a certain period of time to successfully prepare the mesa pattern of the epitaxial wafer. Among them, the spin-coated is AZ6130 positive photoresist, and the spin-coating conditions are as follows: the low rotation speed is 500 - 700 s -1 ; the time is 5 - 7 s; the high rotation speed is 3500 - 4500 s -1 ; the pre-bake temperature is 100 - 110 °C; the time is 2 - 3 min; the exposure time is 2.3 - 2.8 s; the development time is 80 - 100 s. Use inductively coupled plasma etching (ICP) technology to etch the ITO layer outside the mesa to the n-InGaN layer, and the etching conditions are as follows: the etching gases are Cl2 and BCl3, the gas flow rates are 48 sccm and 6 sccm respectively, the gas pressure is 10 mTorr, the RF power is 300 W, the ICP power is 100 W, and the etching time is 15 min.

[0060] (7) Prepare a passivation layer with openings in the electrode region. Using plasma-enhanced chemical vapor deposition (PECVD) technology, grow a SiO2 thin film on the surface. The growth conditions are as follows: Introduce a mixed gas of 5% SiH4 / N2 and N2O into the reaction chamber, control the gas flow rate, and keep the chamber pressure, temperature, and power constant for a certain growth time. The thickness range of the grown SiO2 thin film layer is 200 - 400 nm; the N2O gas flow rate range is 300 - 500 sccm; the 5% SiH4 / N2 gas flow rate range is 100 - 200 sccm; the chamber pressure range is 200 - 400 mTorr; the temperature range is 200 - 400 °C; the power range is 5 - 20 W; the growth time is 2 - 4 min. Then etch the passivation layer by photolithography to expose the electrode contact area. Spin-coat a negative photoresist on the epitaxial wafer, then pre-bake for a certain time at a specific temperature, and subsequently use a lithography machine to expose the sample. Place the exposed sample in a developer solution for development for some time to successfully prepare the epitaxial wafer mesa pattern. Among them, AZ7133 negative photoresist is spin-coated, and the spin-coating conditions are as follows: The low rotation speed is 500 - 700 s -1 ; the time is 5 - 7 s; the high rotation speed is 3500 - 4500 s -1 ; the pre-bake temperature is 100 - 110 °C; the time is 2 - 3 min; the exposure time is 2.3 - 2.8 s; the post-bake temperature is 100 - 110 °C; the time is 2 - 3 min; the development time is 30 - 40 s. Then use reactive ion etching (RIE) technology to etch the SiO2 not covered by the photoresist. The etching conditions are as follows: The etching gas is CF4, the gas flow rate is 30 sccm, the gas pressure is 40 Pa, the power is 120 w, and the etching time is 10 - 20 min.

[0061] (8) Preparation of N and P electrodes. Evaporate N and P electrodes. Use electron beam evaporation (EBE) technology to evaporate a Ti / Al / Ti / Au stacked metal electrode. The conditions are: The EBE chamber pressure is 1E - 6 Torr, Ti: 0.02 - 0.05 nm / s, 20 - 50 nm; Al: 0.1 - 0.2 nm / s, 150 - 250 nm; Ti: 0.05 - 0.1 nm / s, 50 - 100 nm; Au: 0.1 - 0.2 nm / s, 100 - 300 nm. Then soak the sample in acetone, alcohol, and deionized water in sequence until the metal outside the photoresist electrode is completely stripped.

[0062] (9) Fabricate independent LED chips. Use photolithography to define the lateral segmentation regions, first etch the lateral trenches, and then use photolithography to define the longitudinal segmentation regions. Note that there is a connection region between two symmetrically left and right LED chips to fix the LED chips. In both photolithography processes, a positive photoresist is used to protect the LED chip regions not to be etched, and the regions outside the ICP-etched chips are etched until the InGaN template. Then, perform photoresist cleaning to finally obtain independent LED chips on the epitaxial wafer.

[0063] The present invention can effectively alleviate the problems of poor wavelength uniformity caused by uneven In composition of long-wavelength GaN-based LEDs and the difficulty in increasing the wavelength, and can avoid the problem of sidewall light emission in the V-pits strategy, which is of great significance for fabricating high-quality GaN-based micro-LEDs with high In composition.

Claims

1. A gallium nitride-based LED epitaxial structure with a high In component, characterized in that, From bottom to top, it includes: a patterned InGaN template substrate, an epitaxial lateral overgrowth InGaN layer, an n-type semiconductor layer, a V-pits stress relaxation layer, a multi-quantum well active region, a first p-type layer, an electron blocking layer, and a second p-type layer.

2. The gallium nitride-based LED epitaxial structure with a high In component according to claim 1, wherein The patterned InGaN template substrate sequentially includes, from bottom to top: a growth substrate, a buffer layer, an InGaN layer, and a mask layer.

3. The gallium nitride-based LED epitaxial structure with a high In component according to claim 1, characterized in that, The material of the n-type semiconductor layer is Al x In y Ga 1-x-y N, where 0 ≤ 1 - x - y ≤ 1, the growth temperature is 800 - 1100 °C, the thickness is 100 - 5000 nm, and the Si doping concentration is 1×10 15 - 1×10 21 cm -3 。 4. The high-In-component gallium nitride-based LED epitaxial structure according to claim 1, wherein The thickness of the V-pits stress release layer is 50 - 1000 nm, and the material is In x Ga 1-x N / n-GaN, where 0 ≤ x / y ≤ 1, the growth temperature is 700 - 1100 °C, the thicknesses of the single quantum well and the barrier are 1 - 10 nm / 1 - 20 nm respectively, and the Si doping concentration in the barrier is 1×10 15 -1×10 21 cm -3 .

5. The gallium nitride-based LED epitaxial structure with a high In component according to claim 1, characterized in that, The growth temperature of the multi-quantum well active region is 700 - 900 °C, and the material is In x Ga 1-x N / Al y In z Ga 1-y-z N / Al x1 Ga 1-x1 N, where 0 ≤ x ≤ 1, 0 < 1 - y - z < 1, 0 ≤ x1 ≤ 1, the thickness of the In x Ga 1-x N well is 1 - 5 nm, the thickness of the Al y Ga 1-y N capping layer is 0.1 - 3 nm, the thickness of the Al x1 Ga 1-x1 N barrier is 5 - 50 nm, the Si doping concentration is 1×10 15 -1×10 21 cm -3 , logarithm 1 - 20 pairs.

6. A method for preparing a high-In-component gallium nitride-based LED epitaxial structure according to claim 1, characterized in that, It includes the following steps: (1) Prepare a patterned InGaN template substrate; (2) Epitaxially grow an epitaxial lateral overgrowth InGaN layer and an n-type semiconductor layer on the upper side of the patterned InGaN template substrate in sequence, and epitaxially grow a V-pits stress relaxation layer on the n-type semiconductor layer; (3) Epitaxially grow a multi-quantum well active region on the epitaxial V-pits stress relaxation layer; (4) Epitaxially grow a first p-type layer, an electron blocking layer, and a second p-type layer on the multi-quantum well active region in sequence.

7. The preparation method according to claim 6, characterized in that, In step (1), the preparation method of the patterned InGaN template substrate is as follows: S1. Prepare a growth substrate; S2. Epitaxially grow a buffer layer on the upper side of the above-mentioned growth substrate; S3. Epitaxially grow an InGaN layer on the above-mentioned buffer layer; S4. Perform photolithography on the above-mentioned InGaN layer and perform dry etching to achieve patterning, obtaining a patterned InGaN template; S5. Evaporate a mask layer on the above-mentioned patterned InGaN template; S6. Remove the photoresist and the upper mask thereof to obtain a patterned InGaN template substrate with periodic windows.

8. The preparation method according to claim 6, characterized in that, In step (3), in the growth chamber, after each layer of quantum well is grown, in-situ treatment is performed. A single or combined mixture gas of NH3, H2, N2, and TBCl3 is introduced in a continuous or staged pulse manner. At a growth temperature of 700 - 1000 °C and a chamber pressure of 50 - 400 torr, in-situ thermal annealing is performed for 3 s - 5 min.

9. A device, characterized in that, It includes the high In-content gallium nitride-based LED epitaxial structure, ITO, a passivation layer, and electrodes described in claim 1.

10. A method for preparing the device according to claim 9, characterized in that, It includes the following steps: (11) Evaporate ITO on the high In-content gallium nitride-based LED epitaxial structure described in claim 1; (12) Define a mesa region on the high In-content gallium nitride-based LED epitaxial structure described in claim 1 by photolithography, electron beam direct writing, or a mask plate method, and then dry-etch the mesa; (13) Deposit a passivation layer for sidewall protection, and then etch the passivation layer by photolithography, electron beam direct writing, or a mask plate method to expose the electrode contact region; (14) Evaporate metal to make n and p electrodes; (15) Remove the redundant high dislocation density region by lateral and longitudinal etching to define independent LED chips; Alternatively, the steps are as follows: (11) Evaporate ITO on the high In-content gallium nitride-based LED epitaxial structure described in claim 1; (12) Define a mesa region on the high In-content gallium nitride-based LED epitaxial structure described in claim 1 by photolithography, electron beam direct writing, or a mask plate method, and then dry-etch the mesa; (13) Remove the redundant high dislocation density region by lateral and longitudinal etching to define independent LED chips; (14) Deposit a passivation layer for sidewall protection, and then etch the passivation layer by lithography, electron beam direct writing or using a mask template to expose the electrode contact area. (15) Evaporate metal to form n and p electrodes.

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