Light sensing device

Abstract

Disclosed herein is a light detection device including a first substrate portion, a second substrate portion, and a first light shielding wall disposed in the first substrate portion and the second substrate portion. The first substrate includes a first semiconductor substrate and a plurality of photodiodes in the first semiconductor substrate. The second substrate portion is laminated on the first substrate portion, and the second substrate portion includes a second semiconductor substrate and a plurality of avalanche photodiodes in the second semiconductor substrate. A portion of the first light shielding wall surrounds, in a cross-sectional view, a region that is disposed above a first avalanche photodiode of the plurality of avalanche photodiodes in a light receiving direction.

Description

[Cross - reference to related applications]

[0001] This application claims the benefit of Japanese Priority Patent Application JP 2022 - 200023, filed on December 15, 2022, the entire contents of which are incorporated herein by reference. Technical Field

[0002] The present invention relates to a light - sensing device. Background Art

[0003] Generally, in the case of adding three - dimensional data to an image captured by an image sensor by synthesizing information about the image and information about the distance measured by a distance sensor, the chip of the image sensor and the chip of the distance sensor are fabricated and arranged in separate camera modules, and data processing in a downstream circuit establishes the consistency between the image information and the distance information. In this case, multiple camera modules are required, and the cost increases. In addition, the occupied area of these modules also increases. Moreover, since the optical axes of the respective modules are different from each other, the parallax increases in the case of short distances, and data processing considering the parallax must be performed.

[0004] To solve the above - mentioned problems, a multilayered sensor has been proposed, in which a logic circuit and a chip including array - shaped SPAD (single photon avalanche diode) pixels are stacked on top of each other (for example, see Patent Document 1). [Citation List] [Patent Documents]

[0005] [Patent Document 1]: JP 2019 - 47486A Summary of the Invention [Technical Problem to be Solved]

[0006] By laminating a substrate on which visible - light pixels are arranged in a matrix (hereinafter referred to as a visible - light pixel array) on the light - incident surface side of a substrate on which SPAD pixels (or avalanche photodiodes) are arranged in an array (hereinafter referred to as an SPAD pixel array), it is possible to make the optical axis for distance measurement and the optical axis for imaging coincide (or almost coincide) with each other. However, since the light transmitted through the visible - light pixel array enters the SPAD pixel array in this multilayer light - sensing device, there is a problem that the light entering the SPAD pixels tends to be color - mixed or attenuated, and the sensing characteristics of the SPAD pixels tend to deteriorate.

[0007] The present invention has been made in view of these circumstances, and it is an object of the present invention to provide a multilayered light sensing device capable of suppressing characteristic degradation. [Solution to the Problem]

[0008] According to an embodiment of the present invention, there is provided a light detection device including a first substrate portion, a second substrate portion, and a first light shielding wall provided in the first substrate portion and the second substrate portion. The first substrate portion includes: a first semiconductor substrate; and a plurality of photodiodes in the first semiconductor substrate. The second substrate portion is laminated on the first substrate portion, and the second substrate portion includes: a second semiconductor substrate; and a plurality of avalanche photodiodes in the second semiconductor substrate. A part of the first light shielding wall surrounds, in a cross-sectional view, a region that is disposed above the first avalanche photodiode among the plurality of avalanche photodiodes in the light reception direction. According to an aspect of the present invention, there is provided a light detection device, wherein the second substrate portion further includes a separation region provided in the second semiconductor substrate. The separation region separates the first avalanche photodiode from a second avalanche photodiode adjacent to the first avalanche photodiode, and the first light shielding wall is disposed above the separation region in the light reception direction. According to an aspect of the present invention, there is provided a light detection device, wherein each of the plurality of first light shielding walls surrounding the region is connected to another one of the plurality of first light shielding walls. According to an aspect of the present invention, there is provided a light detection device, wherein a first portion of the first light shielding wall is provided in the first substrate portion, and a second portion of the first light shielding wall is provided in the second substrate portion. According to an aspect of the present invention, there is provided a light detection device, wherein the first substrate portion further includes a first wiring layer provided on a surface side of the first semiconductor substrate and facing the second semiconductor substrate. The second substrate portion further includes a second wiring layer provided on a surface side of the second semiconductor substrate and facing the first semiconductor substrate. The first wiring layer includes a first interlayer dielectric film and a first wire. The second wiring layer includes a second interlayer dielectric film and a second wire. The first portion of the first light shielding wall includes the first wire, and the second portion of the first light shielding wall includes the second wire. According to one aspect of the present invention, there is provided an optical detection device, wherein the first wiring layer includes a first connection pad, and the first connection pad contains one or more of copper (Cu) and Cu alloy. The second wiring layer includes a second connection pad, and the second connection pad contains one or more of Cu and Cu alloy. The first connection pad and the second connection pad are joined together at the joining portion between the first substrate portion and the second substrate portion. The first portion of the first light-shielding wall includes the first connection pad, and the second portion of the first light-shielding wall includes the second connection pad. According to one aspect of the present invention, there is provided an optical detection device, wherein the first connection pad included in the first portion of the first light-shielding wall and the second connection pad included in the second portion of the first light-shielding wall are arranged between the first semiconductor substrate and the second semiconductor substrate. According to one aspect of the present invention, there is provided an optical detection device, wherein the region is a waveguide region, and the first avalanche photodiode is not arranged in the waveguide region. According to one aspect of the present invention, there is provided an optical detection device, wherein the first substrate portion includes the waveguide region. According to one aspect of the present invention, there is provided an optical detection device, further comprising: a second light-shielding wall located between the first light-shielding wall and the waveguide region. According to one aspect of the present invention, there is provided an optical detection device, further comprising: a second waveguide located in the second substrate portion. According to one aspect of the present invention, there is provided an optical detection device, wherein the waveguide region is surrounded by the first light-shielding wall in the cross-sectional view. According to one aspect of the present invention, there is provided an optical detection device, wherein a through hole penetrates the first substrate portion in the waveguide region. According to one aspect of the present invention, there is provided an optical detection device, wherein the waveguide region contains silicon oxide (SiO). According to one aspect of the present invention, there is provided an optical detection device, wherein the optical detection device further includes a third substrate portion, and the third substrate portion includes: a third semiconductor substrate; and a processing circuit system provided in the third semiconductor substrate. According to one aspect of the present invention, there is provided an optical detection device, wherein the processing circuit system includes: at least any one of an avalanche photodiode circuit connected to the avalanche photodiode and an imaging pixel circuit connected to the photodiode. According to one aspect of the present invention, there is provided a light detection device, further comprising a lens body disposed opposite to the second substrate portion, and the first substrate portion is inserted between the lens body and the second substrate portion. Moreover, the lens body includes: a first lens that focuses light onto the photodiode; and a second lens that focuses light onto the avalanche photodiode. Moreover, the first lens and the second lens have different curvatures from each other. According to one aspect of the present invention, there is provided a light detection device, wherein the avalanche photodiode is a single-photon avalanche diode pixel. According to one embodiment of the present invention, there is provided a light detection device, which includes a plurality of lenses, a first substrate portion, a second substrate portion, and a first light-shielding wall provided in the first substrate portion and the second substrate portion. The first substrate portion includes: a first semiconductor substrate; and a plurality of photodiodes in the first semiconductor substrate. The second substrate portion is laminated on the first substrate portion, and the second substrate portion includes: a second semiconductor substrate; and a plurality of avalanche photodiodes in the second semiconductor substrate. A plurality of the first light-shielding walls surround the waveguide region in a cross-sectional view. According to one aspect of the present invention, there is provided a light detection device, wherein the second substrate portion further includes a separation region provided in the second semiconductor substrate, and the separation region separates a first avalanche photodiode from a second avalanche photodiode adjacent to the first avalanche photodiode. Moreover, the first light-shielding wall is provided above the separation region in the light reception direction. A light sensing device according to one mode of the present invention includes a light sensing device that includes a multilayer substrate having a first substrate portion and a second substrate portion bonded to one surface of the first substrate portion. The first substrate portion has: a first semiconductor substrate; and a plurality of imaging pixels provided in the first semiconductor substrate. The second substrate portion has: a second semiconductor substrate facing the first semiconductor substrate; and a plurality of ranging pixels provided in the second semiconductor substrate. The multilayer substrate further has a first light-shielding wall provided between the first semiconductor substrate and the second semiconductor substrate, and the first light-shielding wall surrounds each of the plurality of ranging pixels in a plan view observed from the thickness direction of the multilayer substrate.

[0009] Therefore, the optical path from the light-emitting surface of the first semiconductor substrate to each ranging pixel is surrounded by the first light-shielding wall. As a result, diffusion of light to the outside of the path can be suppressed, and color mixing between the ranging pixels can be suppressed. Even when the first substrate portion is laminated on the light-incident surface side of the second substrate portion having the ranging pixels, light can be efficiently introduced into the ranging pixels. Therefore, deterioration of the characteristics of the ranging pixels (for example, conversion efficiency (QE)) can be suppressed.

[0010] A light sensing device according to another mode of the present invention includes a light sensing device including a multilayer substrate having a first substrate portion and a second substrate portion bonded to one surface of the first substrate portion. The first substrate portion has: a first semiconductor substrate; and a plurality of imaging pixels provided in the first semiconductor substrate. The second substrate portion has: a second semiconductor substrate facing the first semiconductor substrate; and a plurality of ranging pixels provided in the second semiconductor substrate. The first semiconductor substrate has waveguide regions located at respective positions overlapping the ranging pixels in the thickness direction of the multilayer substrate, and the waveguide regions are configured to introduce light that has entered the other surface of the first substrate portion opposite to the one surface into the ranging pixels in the second substrate portion. The imaging pixels are not arranged in the waveguide regions. The multilayer substrate has a waveguide provided between the waveguide regions in the first semiconductor substrate and the ranging pixels in the second semiconductor substrate, and the waveguide is configured to introduce the light from the waveguide regions into the ranging pixels.

[0011] Therefore, since the imaging pixels are not arranged on the optical path from the other surface of the first semiconductor substrate to the ranging pixels, it becomes easier to arrange wires connected to the imaging pixels and the like at positions away from the optical path. It is possible to prevent the light going to the ranging pixels from being attenuated or reflected by hitting the imaging pixels or wires connected to the imaging pixels. Therefore, for example, deterioration of the conversion efficiency (QE) can be further suppressed. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 is a block diagram depicting a configuration example of a light sensing device according to a first embodiment of the present invention. Figure 2 is a block diagram depicting a configuration example of an imaging unit according to a first embodiment of the present invention. Figure 3 is a block diagram depicting a configuration example of a ranging unit according to a first embodiment of the present invention. Figure 4A is a plan view depicting a configuration example of a first substrate portion according to a first embodiment of the present invention. Figure 4BIt is a plan view depicting a structural example of a second substrate portion according to the first embodiment of the present invention. Figure 4C It is a plan view depicting a structural example of a third substrate portion according to the first embodiment of the present invention. Figure 5 It is a diagram depicting a structural example of a SPAD circuit. Figure 6 It is a flowchart depicting operation examples of each of the SPAD circuit and the CIS circuit in a light sensing device. Figure 7 It is a cross-sectional view depicting a structural example of a light sensing device according to the first embodiment of the present invention. Figure 8 It is depicting Figure 7 a diagram of an enlarged view of a part of the cross-section shown. Figure 9 It is a cross-sectional view depicting a structural example of a SPAD pixel according to the first embodiment of the present invention. Figure 10 It is a plan view depicting the positional relationship between a first light-shielding wall and a second light-shielding wall and a waveguide region in a light sensing device according to the first embodiment of the present invention. Figure 11 It is a plan view depicting a dimensional example (first modification example) of a waveguide region of a light sensing device according to the first embodiment of the present invention. Figure 12 It is a plan view depicting a dimensional example (second modification example) of a waveguide region of a light sensing device according to the first embodiment of the present invention. Figure 13 It is a plan view depicting a dimensional example (third modification example) of a waveguide region of a light sensing device according to the first embodiment of the present invention. Figure 14 It is a plan view depicting a dimensional example (fourth modification example) of a waveguide region of a light sensing device according to the first embodiment of the present invention. Figure 15 It is a cross-sectional view depicting a structural example of a light sensing device according to the second embodiment of the present invention. Figure 16 It is a cross-sectional view depicting a structural example of a light sensing device according to the third embodiment of the present invention. Figure 17 It is a step diagram depicting a method of forming a bonding pad and a light-shielding sidewall, which is a part of the steps for manufacturing a light sensing device according to the third embodiment of the present invention. Figure 18 It is a plan view showing the positional relationship between a first connection pad and a second connection pad and a waveguide region and a CIS pixel in a light sensing device according to the third embodiment of the present invention. Figure 19 is a cross-sectional view depicting a structural example of the light sensing device according to the fourth embodiment of the present invention. Figure 20 is a cross-sectional view depicting a structural example of the light sensing device according to the fifth embodiment of the present invention. Figure 21 is a plan view depicting the positional relationship between the first light shielding wall and the CIS pixel in the light sensing device according to the fifth embodiment of the present invention. Figure 22 is a block diagram depicting an example of the schematic configuration of the vehicle control system. Figure 23 is an auxiliary view for explaining an example of the installation positions of the out-of-vehicle information detection unit and the imaging unit. Detailed Embodiments

[0013] Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the description of the drawings mentioned in the following description, the same or similar parts are given the same or similar reference numerals. However, it should be noted that these figures are schematic diagrams, and the relationship between the thickness and the planar dimensions, the ratio of the thicknesses of the respective layers, etc. are different from the actual situation. Therefore, specific thicknesses and dimensions should be determined by considering the following description. Additionally, of course, the dimensions in different figures may have different relationships and ratios.

[0014] The definitions of directions such as the up-down direction in the following description are merely definitions used for convenience of description and do not limit the technical idea of the present invention. For example, of course, if the target object is observed after rotating 90°, the up-down direction mentioned in the description of the target object is interpreted as the left-right direction, and if the target object is observed after rotating 180°, the up-down direction mentioned in the description is interpreted as the inverted direction.

[0015] In some cases, in the following description, directions are explained by using the phrases the X-axis direction, the Y-axis direction, and the Z-axis direction. Both the X-axis direction and the Y-axis direction are directions parallel to the rear surface 5b (light incident surface) of the first semiconductor substrate 5. The X-axis direction and the Y-axis direction may be referred to as the horizontal directions. The Z-axis direction is a direction that perpendicularly intersects the rear surface 5b (light incident surface) of the first semiconductor substrate 5 and is also the thickness direction of the multilayer substrate 200. The Z-axis direction is an example of the "thickness direction of the multilayer substrate" in the embodiments of the present invention. The X-axis direction, the Y-axis direction, and the Z-axis direction are orthogonal to each other.

[0016] <First Embodiment> (Structural Example of the Light Sensing Device) Figure 1 is a block diagram depicting a structural example of the light sensing device 100 according to the first embodiment of the present invention. As Figure 1As shown, the light sensing device 100 according to the first embodiment of the present invention includes an imaging unit 1 and a distance measuring unit 2. The light sensing device 100 is a light sensing device having a multi-layer structure, and the multi-layer structure includes a first substrate portion FB (see Figure 7 ), and a second substrate portion SB joined to one surface side of the first substrate portion FB (see Figure 7 ). A plurality of CIS pixels 20 of the imaging unit 1 (CIS is a CMOS image sensor; an example of an "imaging pixel" in the embodiment of the present invention) are provided in the first substrate portion FB, and a plurality of SPAD pixels 10 of the distance measuring unit 2 (an example of a "distance measuring pixel" in the embodiment of the present invention) are provided in the second substrate portion SB. In addition, the light sensing device 100 further includes a third substrate portion TB (see Figure 7 ), which is disposed opposite to the first substrate portion FB, and the second substrate portion SB is inserted between the first substrate portion FB and the third substrate portion TB. First, construction examples of each of the imaging unit 1 and the distance measuring unit 2 will be described.

[0017] (Construction example of the imaging unit) Figure 2 is a block diagram depicting a construction example of the imaging unit 1 according to the first embodiment of the present invention. As Figure 2 shown, the imaging unit 1 includes: a plurality of CIS pixels 20 provided in a pixel region 51; a vertical driving circuit 13; a column signal processing circuit 14; a horizontal driving circuit 15; an output circuit 16; and a control circuit 17. For example, the CIS pixels 20 sense visible light.

[0018] The CIS pixel 20 is a light receiving region for receiving visible light focused by an optical system (not shown). A plurality of CIS pixels 20 are arranged in an array (for example, a plurality of CIS pixels 20 are arranged in the X-axis direction and the Y-axis direction, respectively). The plurality of CIS pixels 20 are connected to the vertical driving circuit 13 in units of rows via horizontal signal lines 22, and are also connected to the column signal processing circuit 14 in units of columns via vertical signal lines 23. Each of the plurality of CIS pixels 20 outputs a pixel signal having a level corresponding to the amount of visible light received. An image of the subject is constructed based on these pixel signals.

[0019] The vertical driving circuit 13 supplies, via the horizontal signal lines 22, driving signals for sequentially driving (transferring, selecting, resetting, etc.) each of the CIS pixels 20 in units of rows of the plurality of CIS pixels 20. The column signal processing circuit 14 performs AD conversion on the pixel signals output from the plurality of CIS pixels 20 via the vertical signal lines 23, and also removes reset noise by performing correlated double sampling (CDS: Correlated Double Sampling) processing on the pixel signals.

[0020] The horizontal drive circuit 15 supplies a drive signal to the column signal processing circuit 14 for causing the column signal processing circuit 14 to output pixel signals to the data output signal line 24 in sequence for each column of the plurality of CIS pixels 20. The output circuit 16 amplifies the pixel signals supplied from the column signal processing circuit 14 via the data output signal line 24 in accordance with the timing of the drive signal of the horizontal drive circuit 15, and outputs the amplified pixel signals to the downstream signal processing circuit. The control circuit 17 controls the driving of each block inside the imaging unit 1. For example, the control circuit 17 generates a clock signal according to the driving period of each block, and supplies the generated clock signal to each block.

[0021] Each CIS pixel 20 includes: a PN photodiode 31 that performs photoelectric conversion on visible light; a transfer transistor 32; a floating diffusion section 33; an amplifying transistor 34; a selection transistor 35; and a reset transistor 36. The transfer transistor 32, the floating diffusion section 33, the amplifying transistor 34, the selection transistor 35, and the reset transistor 36 are included in a readout circuit 30 that reads out the charge (pixel signal) that has undergone photoelectric conversion at the PN photodiode 31.

[0022] The PN photodiode 31 is a photoelectric conversion section that converts incident visible light into charge by photoelectric conversion, and the charge is accumulated therein. The anode terminal of the PN photodiode 31 is connected to ground, and the cathode terminal is connected to the transfer transistor 32. The transfer transistor 32 is driven according to a transfer signal (TRG) supplied from the vertical drive circuit 13, and when the transfer transistor 32 is turned on, the charge accumulated in the PN photodiode 31 is transferred to the floating diffusion section 33. The floating diffusion section 33 is a floating diffusion region connected to the gate electrode of the amplifying transistor 34 and having a predetermined integration capacitance, and the charge transferred from the PN photodiode 31 is temporarily accumulated in the floating diffusion region 33.

[0023] The amplifying transistor 34 outputs a pixel signal having a level corresponding to the charge (i.e., the potential of the floating diffusion section 33) accumulated in the floating diffusion section 33 to the vertical signal line 23 via the selection transistor 35. That is, in a configuration where the floating diffusion section 33 is connected to the gate electrode of the amplifying transistor 34, the floating diffusion section 33 and the amplifying transistor 34 function as a conversion section that amplifies the charge generated at the PN photodiode 31 and converts the amplified charge into a pixel signal having a level corresponding to the charge.

[0024] The selection transistor 35 is driven according to a selection signal SEL provided from the vertical drive circuit 13, and when the selection transistor 35 is turned on, the pixel signal output from the amplification transistor 34 can be output to the vertical signal line 23. The reset transistor 36 is driven according to a reset signal RST provided from the vertical drive circuit 13, and when the reset transistor 36 is turned on, the charge accumulated in the floating diffusion portion 33 is discharged to the drain power supply (Vdd), and the floating diffusion region 34 is reset.

[0025] In Figure 2 the pixel region 51 shown, regions represented by blanks are mixedly present in the array of the array-shaped CIS pixels 20. For example, the SPAD pixels 10 are arranged below those regions represented by blanks. These blank regions are regions for introducing light into the SPAD pixels 10, and no CIS pixels 20 are arranged in these regions. Hereinafter, these blank regions are also referred to as waveguide regions.

[0026] (Configuration example of the distance measurement unit) Figure 3 is a block diagram depicting a configuration example of the distance measurement unit 2 according to the first embodiment of the present invention. For example, the distance measurement unit 2 is a device that performs distance measurement by the direct ToF (time of flight) method and calculates the distance based on the time length required for illumination light emitted from an external light source (not shown) to be reflected and returned. As Figure 3 shown, the distance measurement unit 2 includes: one or more SPAD pixels 10 arranged in the pixel region 51; a distance measurement processing unit 101; a pixel control unit 102; an overall control unit 103; a clock generation unit 104; and an interface (I / F: interface) 106. For example, the SPAD pixels 10 sense infrared rays as monitoring light. The SPAD pixels 10, the distance measurement processing unit 101, the pixel control unit 102, the overall control unit 103, the clock generation unit 104, and the I / F 106 are arranged in the second substrate portion SB or the third substrate portion TB of the multilayer substrate 200 (see Figure 7 ) below).

[0027] In Figure 3 , for example, the overall control unit 103 controls the overall operation of the distance measurement unit 2 according to a program incorporated in advance. In addition, the overall control unit 103 can also perform control according to an external control signal provided from the outside. The clock generation unit 104 generates one or more clock signals to be used in the distance measurement unit 2 based on a reference clock signal provided from the outside.

[0028] The operation of the SPAD pixel 10 is controlled by the pixel control unit 102 according to an instruction from the overall control unit 103. For example, the pixel control unit 102 can also control the SPAD pixel individually or control the SPAD pixel in units of blocks each including a plurality of SPAD pixels 10.

[0029] The pixel signals read out from the respective SPAD pixels 10 are supplied to the distance measurement processing unit 101. The distance measurement processing unit 101 includes a conversion unit 110, a generation unit 111, and a signal processing unit 112.

[0030] The pixel signals read out from the respective SPAD pixels 10 are supplied to the conversion unit 110. Here, the pixel signals are read out from the SPAD pixels 10 asynchronously and supplied to the conversion unit 110. That is, the pixel signals are read out and output from the SPAD pixels 10 in accordance with the timing at which light is received at the SPAD pixels 10.

[0031] The conversion unit 110 converts the pixel signals output from the respective SPAD pixels 10 into digital information. That is, the pixel signals output from the respective SPAD pixels 10 are output in accordance with the timing at which light is received by the SPAD pixels 10 corresponding to the pixel signals. The conversion unit 110 converts the pixel signals output from the SPAD pixels 10 into time information representing the timing. The generation unit 111 generates a histogram based on the time information generated by the conversion unit 110 for converting the pixel signals. The signal processing unit 112 performs a predetermined calculation process based on the data of the histogram generated by the generation unit 111 and calculates distance information. For example, the signal processing unit 112 creates a fitting curve of the histogram based on the data of the histogram generated by the generation unit 111. The signal processing unit 112 can sense the peak of the fitting curve of the histogram and determine the distance based on the sensed peak.

[0032] When performing curve fitting of the histogram, the signal processing unit 112 can perform a filtering process on the fitting curve of the histogram. For example, the signal processing unit 112 can suppress noise components by performing a low-pass filtering process on the fitting curve of the histogram.

[0033] The distance information determined at the signal processing unit 112 is supplied to the interface 106. The interface 106 outputs the distance information supplied from the signal processing unit 112 as output data to the outside. For example, a Mobile Industry Processor Interface (MIPI) can be used as the interface 106.

[0034] Note that, although in the above-mentioned example, the distance information determined at the signal processing unit 112 is output to the outside via the interface 106, this is not the only example. That is to say, in other possible configurations, the histogram data, which is the data of the histogram generated by the generation unit 111, can be output from the interface 106 to the outside. For example, the histogram data output from the interface 106 is provided to an external information processing device as the case may be, and is processed at the external information processing device.

[0035] Note that Figure 3 at least some of the functions of the illustrated ranging processing unit 101 are performed by the SPAD circuit 210 mentioned later. Refer to Figure 5 later to illustrate the relationship between each of the functions of the ranging processing unit 101 and the SPAD circuit 210. Next, construction examples of the first substrate portion FB, the second substrate portion SB, and the third substrate portion TB are described.

[0036] (Construction Example of the First Substrate Portion) Figure 4A is a plan view depicting a construction example of the first substrate portion FB according to the first embodiment of the present invention. As Figure 4A shown, the first substrate portion FB has: a first semiconductor substrate 5; a plurality of CIS pixels 20 provided in the first semiconductor substrate 5; and a plurality of waveguide regions 11 provided in the first semiconductor substrate. As described above, the waveguide region 11 is a region for introducing light into the SPAD pixel 10, and no CIS pixel 20 is arranged in this region.

[0037] Although Figure 4A only one waveguide region 11 is depicted, a plurality of waveguide regions 11 are arranged in an array at a constant interval in the first semiconductor substrate 5. In a plan view observed from the thickness direction (e.g., the Z-axis direction) of the first semiconductor substrate 5, each of the plurality of waveguide regions 11 is surrounded by CIS pixels 20. One waveguide region 11 is adjacent to a plurality of CIS pixels 20.

[0038] In the pixel region 51, the plurality of waveguide regions 11 and the plurality of CIS pixels 20 are arranged in an array in a mixed manner. The waveguide regions 11 and the CIS pixels 20 are not arranged in the peripheral region 52 located around the pixel region 51.

[0039] Note that although Figure 4A the peripheral region 52 is depicted as a region relatively larger than the pixel region 51, this is only an example. The peripheral region 52 may also be small enough in the first substrate portion FB relative to the pixel region 51.

[0040] In addition, although Figure 4AIllustrates a case where the size of the SPAD pixel 10 (i.e., the pixel area size of the SPAD pixel 10) located below the waveguide region 11 in a planar view is sixteen times the pixel area size of the CIS pixel 20 (four times the length in the X-axis direction and also four times the length in the Y-axis direction), but this is just an example. For example, as mentioned later Figure 10 As shown, the pixel area size of the SPAD pixel 10 can be four times the pixel area size of the CIS pixel 20 (two times the length in the X-axis direction and also two times the length in the Y-axis direction).

[0041] (Configuration example of the second substrate portion) Figure 4B is a plan view depicting a configuration example of the second substrate portion SB according to the first embodiment of the present invention. As Figure 4B shown, the second substrate portion SB has: a second semiconductor substrate 6; a plurality of SPAD pixels 10 provided in the second semiconductor substrate 6; and a first circuit region 61 and a second circuit region 62 provided in the second semiconductor substrate 6. The SPAD pixels 10 are arranged at positions overlapping with the Figure 7 shown waveguide region 11 in the thickness direction (e.g., Z-axis direction) of the multi-layer substrate 200 mentioned later. For example, the SPAD pixels 10 are arranged directly below the waveguide region 11. Note that although Figure 4A only one SPAD pixel 10 is depicted, in the second semiconductor substrate 6, a plurality of SPAD pixels 10 are arranged in an array at regular intervals. Figure 4B

[0042] For example, the first circuit region 61 is provided at a position overlapping with the Figure 4A shown pixel region 51 in the Z-axis direction except for the waveguide region 11. In addition, a part of the first circuit region 61 can be arranged at a position overlapping with the peripheral region 52 in the Z-axis direction. Readout circuits 30 (see Figure 2 ) each connected to one of the plurality of CIS pixels 20 are arranged in the first circuit region 61.

[0043] For example, the second circuit region 62 is provided at a position overlapping with the Figure 4A shown peripheral region 52 in the Z-axis direction. CIS circuits 220 (an example of the "imaging pixel circuit" of the embodiment of the present invention) connected to the plurality of CIS pixels 20 are arranged in the second circuit region 62. Each CIS circuit 220 includes Figure 2 the vertical drive circuit 13, column signal processing circuit 14, horizontal drive circuit 15, output circuit 16, and control circuit 17 shown.

[0044] (Configuration example of the third substrate portion)​ Figure 4C is a plan view depicting a structural example of the third substrate portion TB according to the first embodiment of the present invention. As Figure 4C shown, the third circuit region 71 is provided in the third semiconductor substrate 7 of the third substrate portion TB. For example, the third circuit region 71 is provided at a position overlapping with the pixel region 51 shown in the Z-axis direction. In the third circuit region 71, an SPAD circuit 210 (an example of the "electronic circuit" and "range-finding pixel circuit" of the embodiment of the present invention) connected to the SPAD pixel 10 provided in the second substrate portion SB is provided. For example, corresponding to Figure 4A the plurality of SPAD pixels 10 shown, a plurality of SPAD circuits 210 are arranged in the third circuit region 71 in the third semiconductor substrate 7. Directly below one SPAD pixel 10, one SPAD circuit 210 corresponding to the SPAD pixel is arranged. Figure 4B Note that the circuits arranged in the third circuit region 71 are not limited to the SPAD circuit 210. For example, at least any one of the SPAD circuit 210 and the CIS circuit 220 may be arranged in the third circuit region 71. In addition to the SPAD circuit 210, some CIS circuits 220 may also be arranged in the third circuit region 71, or any logic circuit or any analog circuit may also be arranged in the third circuit region 71. Further, in the third semiconductor substrate 7, some CIS circuits 220 may also be arranged in the region surrounding the third circuit region 71, or any logic circuit or any analog circuit may also be arranged in the region.

[0045] Note that the circuits arranged in the third circuit region 71 are not limited to the SPAD circuit 210. For example, at least any one of the SPAD circuit 210 and the CIS circuit 220 may be arranged in the third circuit region 71. Some CIS circuits 220 may also be arranged in the third circuit region 71 in addition to the SPAD circuit 210, or any logic circuit or any analog circuit may also be arranged in the third circuit region 71. Also, in the third semiconductor substrate 7, some CIS circuits 220 may also be arranged in the region surrounding the third circuit region 71, or any logic circuit or any analog circuit may also be arranged in the region.

[0046] (Structural example of SPAD circuit) Figure 5 is a diagram depicting a structural example of the SPAD circuit 210. As Figure 5 shown, each SPAD circuit 210 has an AFE (analog front end) circuit 211, a TDC (time to digital converter) circuit 212, a histogram circuit 213, and an output unit 214. Therefore, the SPAD circuit 210 executes at least some functions of the range-finding processing unit 101.

[0047] For example, as Figure 3 a part of the function of the conversion unit 110 of the range-finding processing unit 101 shown, the AFE circuit 211 converts the pixel signal output from each SPAD pixel 10 into digital information.

[0048] As another part of the function of the conversion unit 110, the TDC circuit 212 converts the digital information output from the AFE circuit 211 into time information. As Figure 3 functions of the generation unit 111 and the signal processing unit 112 of the ranging processing unit 101 shown, the histogram circuit 213 generates a histogram based on the time information output from the TDC circuit 212, and calculates distance information by performing a predetermined calculation process based on the data of the generated histogram. As a function of the interface 106, the output unit 214 outputs the calculated distance information as output data to the outside.

[0049] (Operation example of the circuit) Figure 6 is a flowchart depicting operation examples of the SPAD circuit 210 and the CIS circuit 220 in the optical sensing device 100. As Figure 6 shown, when reading the signal of one screen (i.e., from the start to the end of the frame), the CIS circuit 220 performs a serial row readout operation, and in parallel therewith, the SPAD circuit 210 performs a simultaneous all-pixel readout operation.

[0050] For example, when reading the signal of one screen, in the order of the nth row (n is an integer equal to or greater than 1), the (n + 1)th row, the (n + 2)th row, etc., the CIS circuit 220 sequentially performs PD (photodiode) reset, exposure, PD readout, row selection, and AD (analog to digital) conversion. The CIS circuit 220 performs PD reset of the (n + 1)th row when performing exposure of the nth row. In addition, when reading the signal of one screen, the SPAD circuit 210 performs counter reset, SPAD pixel (SPAD element) turn-on, laser irradiation, sensing, histogram processing, and distance sensing. The process from the SPAD pixel turn-on to the sensing is performed m times (m is an integer equal to or greater than 1) as needed.

[0051] (Example of cross-sectional structure) Figure 7 is a cross-sectional view depicting a structural example of the optical sensing device 100 according to the first embodiment of the present invention. Figure 8 is depicting Figure 7 a magnified view of a part of the cross-section shown. As Figure 7As shown, the light sensing device 100 includes a multi-layer substrate 200, a color filter CF, and a microlens array MLA (the "lens body" of the embodiment of the present invention). The multi-layer substrate 200 has: a first substrate portion FB; a second substrate portion SB bonded to one surface side of the first substrate portion FB; and a third substrate portion TB bonded to the surface of the second substrate portion SB opposite to the surface to which the first substrate portion FB is bonded.

[0052] For example, the light sensing device 100 is a back-illuminated optical sensor, and the back surface 5b side of the first semiconductor substrate 5 in the first substrate portion FB ( Figure 7 the upper surface side in ) is the light incident surface side. Therefore, the color filter CF and the microlens array MLA are arranged on the back surface 5b side of the first semiconductor substrate 5.

[0053] The first substrate portion FB has: a first semiconductor substrate 5; and a first wiring layer 55 provided on the front surface 5a side of the first semiconductor substrate 5 ( Figure 7 the lower surface side in ; an example of the "surface side facing the second semiconductor substrate" in the embodiment of the present invention).

[0054] For example, the first semiconductor substrate 5 is a silicon substrate formed by polishing a silicon wafer by CMP (Chemical Mechanical Polishing). A plurality of CIS pixels 20 are provided in the first semiconductor substrate 5.

[0055] A dielectric film 41 that allows light to transmit is provided on the back surface 5b of the first semiconductor substrate 5, and a dielectric film 42 that allows light to transmit is provided on the dielectric film 41. For example, the dielectric film 41 contains a material with a refractive index higher than that of the dielectric film 42. For example, the dielectric film 41 contains a silicon nitride (SiN) film, and the dielectric film 42 contains a silicon oxide (SiO) film. The dielectric films 41 and 42 can protect the back surface 5b of the first semiconductor substrate 5. In addition, the difference between the refractive index of the dielectric film 41 and the refractive index of the dielectric film 42 enables suppression of the reflection of light entering the back surface 5b side of the first semiconductor substrate 5.

[0056] The color filter CF and the microlens array MLA are sequentially stacked on the back surface 5b of the first semiconductor substrate 5 with the dielectric film 41 and the dielectric film 42 interposed therebetween. For example, the microlens array MLA is arranged in the pixel region 51, but not in the peripheral region 52. Each microlens array MLA has: a microlens ML1 (an example of the "first lens" in the embodiment of the present invention) arranged above the CIS pixel 20; and a microlens ML2 (an example of the "second lens" in the embodiment of the present invention) arranged above the SPAD pixel 10.

[0057] The microlens ML1 focuses the incident light entering the first substrate portion FB onto the CIS pixel 20 in the first substrate portion FB. The microlens ML2 focuses the incident light entering the first substrate portion FB onto the SPAD pixel 10 in the second substrate portion SB. The microlenses ML1 and ML2 have different curvatures from each other.

[0058] The ends of the microlenses ML1 and ML2 adjacent to each other or the ends of one microlens ML2 and another microlens ML2 adjacent to each other are connected together, thereby forming a microlens array MLA.

[0059] The color filter CF is disposed above the CIS pixel 20 but not above the SPAD pixel 10. The microlens ML1 is disposed on the color filter CF. The microlens ML2 is disposed on the dielectric film 42 that allows light transmission, and no color filter CF is inserted between the microlens ML2 and the dielectric film 42 that allows light transmission. Therefore, the light that has passed through the microlens ML1 travels through the color filter CF and then enters the CIS pixel 20. The light that has passed through the microlens ML2 enters the SPAD pixel 10 without passing through the color filter CF.

[0060] Note that although Figure 7 and Figure 8 are not shown in the figure, an element isolation portion having a trench structure may be provided in the first semiconductor substrate 5. One CIS pixel 20 and another CIS pixel 20 adjacent to each other among the plurality of CIS pixels 20 may be separated from each other by such an element isolation portion. In addition, the waveguide region 11 provided in the first semiconductor substrate 5 and the CIS pixel 20 adjacent to the waveguide region 11 may be separated from each other by such an element isolation portion.

[0061] The first wiring layer 55 has: a first wire 551 connected to the CIS pixel 20; a first connection pad 552; and a first interlayer dielectric film 553 covering the first wire 551.

[0062] For example, the first wire 551 is a multi-layer wire formed to span multiple layers. For example, the first interlayer dielectric film 553 is a multi-layer film formed by performing a film-forming step multiple times. The first wire 551 contains a metal such as aluminum (Al) or an Al alloy or copper (Cu) or a Cu alloy. In addition, at least a part of the first wire 551 may contain a high melting point metal such as tungsten (W) or a conductive material such as polysilicon doped with impurities.

[0063] For example, the first connection pad 552 is connected to the first wire 551 and contains Cu or a Cu alloy. The front surface of the first connection pad 552 ( Figure 7 and Figure 8 the lower surface inFigure 7 and Figure 8 exposed in the lower surface of Figure 8 .

[0064] For example, the first interlayer dielectric film 553 is a multilayer film formed by performing a film formation step multiple times, and includes multilayer dielectric films such as an SiO film, a SiN film, a silicon carbide (SiC) film, a TEOS film, or an HDP film. For example, as Figure 8 shown, the first interlayer dielectric film 553 has the following structure, in which, from the front surface 5a of the first semiconductor substrate 5 to the front surface side of the first interlayer dielectric film 553 ( Figure 7 and Figure 8 the lower surface side of Figure 8 ), an SiO film 5531; a SiC film 5532 and a TEOS film 5533 alternately laminated on the SiO film 5531; a SiN film 5534; an HDP film 5535; and a TEOS film 5536 are sequentially laminated.

[0065] The TEOS film is an oxide film formed by using tetraethoxysilane (Si(OC2H5)4) as a raw material. Both the TEOS films 5533 and 5536 are oxide films formed by using Si(OC2H5)4.

[0066] The HDP film is a dielectric film formed by a high-density plasma CVD (HDP-CVD: high-density plasma CVD) method. CVD represents Chemical Vapor Deposition. For example, the HDP film 5535 is an SiO film formed by the HDP-CVD method.

[0067] Among the respective layers, the SiC film 5532 has a function of suppressing the diffusion of Cu contained in the first wire 551 in the Z-axis direction (i.e., interlayer diffusion).

[0068] In addition, as Figure 7 and Figure 8 shown, the first interlayer dielectric film 553 is provided with an opening H1 from the front surface of the first interlayer dielectric film 553 to the front surface 5a side of the first semiconductor substrate 5. The opening H1 is a through hole that penetrates the first interlayer dielectric film 553 in the thickness direction (e.g., the Z-axis direction). In this case, the front surface 5a of the first semiconductor substrate 5 exists at the bottom plane of the opening H1. Alternatively, the opening H1 may not be a through hole. In this case, an unremoved portion (e.g., the SiO film 5531) of the first interlayer dielectric film 553 may exist at the bottom plane of the opening H1.

[0069] An opening H1 is provided directly below the waveguide region 11 and filled with an HDP film 5535. The HDP film 5535 filling the opening H1 is used as a first waveguide LGR1 which is part of the waveguide LGR. The first waveguide LGR1 may be located in the first substrate portion (FB), while the second waveguide region LGR2 may be located in the second substrate portion (SB).

[0070] As Figure 7 and Figure 8 shown, the second substrate portion SB has: a second semiconductor substrate 6; a second wiring layer 65 provided on the rear surface 6b side of the second semiconductor substrate 6 (an example of the "surface side facing the first semiconductor substrate" in the embodiment of the present invention); and a third wiring layer 67 provided on the front surface 6a side of the second semiconductor substrate 6.

[0071] For example, the second semiconductor substrate 6 is a silicon substrate formed by polishing a silicon wafer by CMP. The second semiconductor substrate 6 is provided with SPAD pixels 10 and a CIS circuit 220 (see Figure 4B ). Construction examples of the SPAD pixels 10 will be described later.

[0072] The second wiring layer 65 has: a second wire 651; a second connection pad 652; and a second interlayer dielectric film 653 covering the second wire 651. The second wire 651 may be a single-layer wire or a multi-layer wire formed to span multiple layers. For example, the second interlayer dielectric film 653 is a multi-layer film formed by performing a film-forming step multiple times. The second wire 651 contains a metal such as aluminum (Al) or an Al alloy or copper (Cu) or a Cu alloy. In addition, at least a part of the second wire 651 may contain a high melting point metal such as tungsten (W) or a conductive material such as polysilicon doped with impurities.

[0073] For example, the second connection pad 652 is connected to the second wire 651 and contains Cu or a Cu alloy. The front surface ( Figure 7 and Figure 8 the upper surface in) of the second connection pad 652 is exposed from the front surface ( Figure 7 and Figure 8 the upper surface in) of the second interlayer dielectric film 653.

[0074] For example, the second interlayer dielectric film 653 is a multi-layer film formed by performing a film-forming step multiple times and includes multi-layer dielectric films such as SiO film, SiN film, TEOS film or HDP film. For example, as Figure 8 shown, the second interlayer dielectric film 653 has the following structure: in this structure, from the rear surface 6b of the second semiconductor substrate 6 to the front surface side of the second interlayer dielectric film 653 ( Figure 7 and Figure 8On the upper surface side), an SiO film 6531, a TEOS film 6532, a SiN film 6533, an HDP film 6534, and a TEOS film 6535 are stacked in sequence.

[0075] The second interlayer dielectric film 653 is provided with an opening H2 from the front surface of the second interlayer dielectric film 652 to the rear surface 6b side of the second semiconductor substrate 6. The opening H2 is a through hole that penetrates the second interlayer dielectric film 653 in the thickness direction (e.g., the Z-axis direction). In this case, the rear surface 6b of the second semiconductor substrate 6 exists at the bottom plane of the opening H2. Alternatively, the opening H2 may not be a penetrating through hole. In this case, the unremoved portion (e.g., the SiO film 6531) of the second interlayer dielectric film 653 may exist at the bottom plane of the opening H2.

[0076] The opening H2 is provided directly below the waveguide region 11 and is filled with the HDP film 6534. The HDP film 6534 filling the opening H2 is used as the second waveguide LGR2 that is part of the waveguide LGR.

[0077] As Figure 7 shown, the third wiring layer 67 has: a third wire 671; a third connection pad 672; and a third interlayer dielectric film 673 covering the third wire 671. The third wire 671 can be a single-layer wire or a multi-layer wire formed to span multiple layers. For example, the third interlayer dielectric film 673 is a multi-layer film formed by performing a film-forming step multiple times. The third wire 671 contains metals such as aluminum (Al) or an Al alloy or copper (Cu) or a Cu alloy. In addition, at least a part of the third wire 671 may contain a high-melting-point metal such as tungsten (W) or a conductive material such as polysilicon doped with impurities.

[0078] For example, the third connection pad 672 is connected to the third wire 671 and contains Cu or a Cu alloy. The front surface ( Figure 7 the lower surface in) of the third connection pad 672 is exposed from the front surface ( Figure 7 the lower surface in) of the third interlayer dielectric film 673. For example, the third interlayer dielectric film 673 includes a multi-layer dielectric film such as an SiO film or a TEOS film.

[0079] As described above, the second substrate portion SB is joined to one surface side of the first substrate portion FB ( Figure 7 and Figure 8On the lower surface side (in the figure). For example, the first wiring layer 55 of the first substrate portion FB and the second wiring layer 65 of the second substrate portion SB are joined together. More specifically, the first interlayer dielectric film 553 and the second interlayer dielectric film 653 are joined together at the joining surface BS1 between the first wiring layer 55 and the second wiring layer 65. In addition, the first connection pad 552 and the second connection pad 652 are joined together at the joining surface BS1. Both the first connection pad 552 and the second connection pad 652 contain Cu or a Cu alloy, and are joined together by Cu-Cu bonding. Thereby, the second substrate portion SB is joined to one surface side of the first substrate portion FB. In addition, the first wire 551 is connected to the second wire 651 via the first connection pad 552 and the second connection pad 652.

[0080] In addition, the first waveguide LGR1 and the second waveguide LGR2 are joined together to form a waveguide LGR, which guides the light from the waveguide region 11 in the first semiconductor substrate 5 into the SPAD pixel 10 in the second semiconductor substrate 6. For example, the first waveguide LGR1 and the second waveguide LGR2 are joined together via the TEOS films 5533 and 6535 to form the waveguide LGR. The first waveguide LGR1 penetrates the SiN film 5534, and the second waveguide LGR2 penetrates the SiN film 6533.

[0081] For example, the waveguide LGR only contains SiO. In this waveguide LGR, there is no SiN film (such as an HDP film or a TEOS film) whose refractive index is significantly different from that of SiO. Therefore, this waveguide LGR can efficiently guide the light from the waveguide region 11 into the SPAD pixel 10 (that is, light attenuation or reflection can be suppressed).

[0082] As Figure 7 shown, the third substrate portion TB has: a third semiconductor substrate 7; and a fourth wiring layer 75 provided on the front surface 7a side of the third semiconductor substrate 7.

[0083] For example, the third semiconductor substrate 7 is a silicon substrate formed by grinding a silicon wafer by CMP. The third semiconductor substrate 7 is provided with a SPAD circuit 210 (see Figure 4C ). In addition, the third semiconductor substrate 7 may be provided with at least some CIS circuits 220 (see Figure 4C ).

[0084] The fourth wiring layer 75 includes: a fourth wire 751; a fourth connection pad 752; and a fourth interlayer dielectric film 753 that covers the fourth wire 751. The fourth wire 751 may be a single-layer wire or a multi-layer wire formed to span multiple layers. For example, the fourth interlayer dielectric film 753 is a multi-layer film formed by performing a film-forming step multiple times. The fourth wire 751 contains a metal such as aluminum (Al) or an Al alloy or copper (Cu) or a Cu alloy. In addition, at least a part of the fourth wire 751 may contain a high-melting-point metal such as tungsten (W) or a conductive material such as polysilicon doped with impurities.

[0085] For example, the fourth connection pad 752 is connected to the fourth wire 751 and contains Cu or a Cu alloy. The front surface ( Figure 7 the upper surface in) of the fourth connection pad 752 is exposed from the front surface ( Figure 7 the upper surface in) of the fourth interlayer dielectric film 753. For example, the fourth interlayer dielectric film 753 is a multi-layer film formed by performing a film-forming step multiple times and includes a multi-layer dielectric film such as an SiO film or a TEOS film.

[0086] The third substrate portion TB is joined to one surface side ( Figure 7 and Figure 8 the lower surface side in) of the second substrate portion SB. For example, the third wiring layer 67 of the second substrate portion SB and the fourth wiring layer 75 of the third substrate portion TB are joined together. More specifically, the third interlayer dielectric film 673 and the fourth interlayer dielectric film 753 are joined together at a joining surface BS2 between the third wiring layer 67 and the fourth wiring layer 75. In addition, the third connection pad 672 and the fourth connection pad 752 are joined together at the joining surface BS2. Both the third connection pad 672 and the fourth connection pad 752 contain Cu or a Cu alloy and are joined together by Cu-Cu bonding. Thereby, the third substrate portion TB is joined to one surface of the second substrate portion SB. In addition, the third wire 671 is connected to the fourth wire 751 via the third connection pad 672 and the fourth connection pad 752.

[0087] As Figure 7 shown, bonding pads 114 are arranged in the peripheral region 52. Although Figure 7 one bonding pad 114 is depicted, a plurality of bonding pads 14 are provided in the peripheral region 52. For example, each of the plurality of bonding pads 114 is arranged along one of the four sides on the two-dimensional plane of the semiconductor chip (i.e., the multi-layer substrate 200 formed as a single piece by dicing). Each of the plurality of bonding pads 114 is an input / output terminal used when the semiconductor chip is electrically connected to an external device.

[0088] The pad opening H11 is provided above the bonding pad 114. The pad opening H11 penetrates the first semiconductor substrate 5, and the bonding pad 114 exists at the bottom plane of the pad opening H11. One end of a bonding wire BW containing a conductive material such as gold (Au) is bonded to the bonding pad 114 exposed from the pad opening H11.

[0089] For example, among the plurality of bonding pads 114, one bonding pad 114 is connected to the first wire 551 in the first wiring layer 55. Additionally, another bonding pad 114 is connected to the second wire 651 in the second wiring layer 65 via the first wiring layer 55. Still another bonding pad 114 is connected to the third wiring layer 67 or the fourth wiring layer 75 via the first wiring layer 55, the second wiring layer 65, and a conductor 120 (e.g., a through-silicon via (TSV: Vertical Interconnect Access)) mentioned later.

[0090] A conductor 120 that penetrates the second semiconductor substrate 6 in the thickness direction (e.g., the Z-axis direction) of the second semiconductor substrate 6 is provided below the bonding pad 114. Additionally, a dielectric film 121 is provided on the side surfaces of the through-holes in the second semiconductor substrate 6 where the conductor 120 is arranged. The dielectric film 121 insulates the conductor 120 from the second semiconductor substrate 6.

[0091] The conductor 120 is an electrode that penetrates the second semiconductor substrate 6. For example, since the second semiconductor substrate 6 contains silicon in this embodiment, the conductor 120 is a TSV (Through-Silicon Via). However, the use of the conductor 120 is not limited to any type in this embodiment. For example, they can be used as a power supply line, a reference potential (e.g., ground potential) line, or a signal line. Therefore, the conductor 120 preferably contains a low-resistance material. For example, examples of the low-resistance material include copper (Cu) or a Cu alloy.

[0092] Note that although Figure 7Illustrates a pattern in which conductors 120 (e.g., TSVs) penetrating the second semiconductor substrate 6 are arranged in the peripheral region 52, but the arrangement position of the conductors 120 is not limited to the peripheral region 52. The conductors 120 penetrating the second semiconductor substrate 6 may also be arranged in the pixel region 51. In addition, the conductors 120 arranged in the peripheral region 52 and the conductors 120 arranged in the pixel region 51 may include the same material as each other or may include different materials from each other. The conductors 120 arranged in the peripheral region 52 and the conductors 120 arranged in the pixel region 51 may have the same width as each other or may have different widths from each other. For example, the width of the conductors 120 arranged in the peripheral region 52 may be greater than the width of the conductors 20 arranged in the pixel region 51. Therefore, compared with the resistance of the conductors 120 arranged in the pixel region 51, the resistance of the conductors 120 arranged in the peripheral region 52 can be reduced by an amount corresponding to the difference between their widths.

[0093] (Configuration Example of SPAD Pixel) Figure 9 is a cross-sectional view illustrating a configuration example of an SPAD pixel 10 according to the first embodiment of the present invention. Figure 9 is a cross-sectional view illustrating a configuration example of an SPAD pixel 10 that can be applied to the direct ToF distance measurement unit 2 according to the first embodiment of the present invention.

[0094] As Figure 9 shown, the SPAD pixel 10 is provided with an N-type conductive semiconductor region 501 and a P-type semiconductor region 502 in contact with the N-type semiconductor region 501. The N-type semiconductor region 501 and the P-type semiconductor region 502 are provided in the well layer 503.

[0095] The well layer 503 may be an N-type conductive semiconductor region or a P-type conductive semiconductor region. In addition, for example, the well layer 503 is preferably an N-type or P-type semiconductor region having a low concentration of about 1×10 14 / cm 3 or less order of magnitude. Therefore, it becomes easier to deplete the well layer 503, and it is possible to attempt to enhance the sensing efficiency called photon detection efficiency (PDE).

[0096] For example, the N-type semiconductor region 501 is an N-type semiconductor region containing Si (silicon) and having a high impurity concentration. The P-type semiconductor region 502 is a P-type semiconductor region having a high impurity concentration. The P-type semiconductor region 502 forms a pn junction at the interface between the P-type semiconductor region 502 and the N-type semiconductor region 501. The P-type semiconductor region 502 has a multiplication region that avalanche multiplies carriers generated due to the entry of light to be sensed. The P-type semiconductor region 502 is preferably depleted so as to attempt to enhance the PDE.

[0097] The N-type semiconductor region 501 serves as a cathode and is connected to the SPAD circuit 210 via a contact 504 (for example, see Figure 5 ). The hole accumulation region 411 is a P-type semiconductor region. For example, the hole accumulation region 411 is substantially the same region as the anode 505 and is set to be in a state of being electrically connected to the anode 505 via a contact 506. The anode 505 is connected to the SPAD circuit 210 (for example, see Figure 5 ).

[0098] A separation region 508 for separating the SPAD pixels 10 from each other is formed, and the hole accumulation region 411 is provided between the separation region 508 and the well layer 503. The separation region 508 can separate the first avalanche photodiode from a second avalanche photodiode adjacent to the first avalanche photodiode.

[0099] The hole accumulation region 411 is formed at a portion where different materials come into contact. Since in the Figure 9 example shown, the separation region 508 contains a material different from that of the well layer 503, the hole accumulation region 411 is provided to suppress dark current generated at the interface between the separation region 508 and the well layer 503. The hole accumulation region 411 can also be further provided at the upper part (the light incident surface side of the SPAD pixel 10) of the well layer 503.

[0100] The separation region 508 is formed between the SPAD pixels 10 and separates the SPAD pixels 10 from each other. The separation region 508 is formed in a two-dimensional lattice shape so as to completely surround the periphery of each multiplication region (SPAD pixel 10).

[0101] For example, the separation region 508 has: a trench H21; a light-shielding film 5081 filling the trench H21; and a dielectric film 5082 inserted between the side surface of the trench H21 and the light-shielding film 5081. For example, the light-shielding film 5081 contains tungsten (W), Al or an Al alloy, Cu or a Cu alloy, polysilicon, or the like. For example, the dielectric film 5082 contains a SiO film.

[0102] Although in the pattern shown in the example shown in Figure 9 the separation region 508 is set to penetrate the well layer 503 from the upper surface side to the lower surface side of the well layer 503 in the thickness direction (e.g., the Z-axis direction) of the multilayer substrate 200, the pattern of the separation region 508 is not limited thereto. For example, the separation region 508 may not penetrate the well layer 503 in the Z-axis direction. The separation region 508 may be set at an intermediate position of the well layer 503 in the Z-axis direction.

[0103] (Configuration example of light-shielding wall around waveguide) As Figure 7 and Figure 8 shown, the light sensing device 100 has a first light-shielding wall 150, and each light-shielding wall 150 includes a first wire 551, a first connection pad 552, a second connection pad 652, and a second wire 651. Each first light-shielding wall 150 is disposed between the first semiconductor substrate 5 and the second semiconductor substrate 6, and is disposed, for example, at a position overlapping (i.e., above) the separation region 508 in the Z-axis direction. The first light-shielding wall 150 is continuously disposed from the first wire 551 to the second wire 651 along the thickness direction (e.g., the Z-axis direction) of the multilayer substrate 200.

[0104] For example, the first light-shielding wall 150 has a first portion disposed in the first substrate portion FB and facing the second substrate portion SB. The first portion includes the first wire 551 and the first connection pad 552. In addition, the first light-shielding wall 150 has a second portion disposed in the second substrate portion SB and facing the first substrate portion FB. The second portion includes the second wire 651 and the second connection pad 652. The first connection pad 552 and the second connection pad 652 included in the first light-shielding wall 150 are joined together by Cu-Cu bonding.

[0105] Similarly, the light sensing device 100 has a second light-shielding wall 160, and each light-shielding wall 160 includes a first wire 551, a first connection pad 552, and a second connection pad 652. Each second light-shielding wall 160 is disposed between the first semiconductor substrate 5 and the second semiconductor substrate 6, and is disposed, for example, between the second light-shielding wall 160 and the waveguide LGR. The second light-shielding wall 160 is continuously disposed from the first wire 551 to the second connection pad 652 along the thickness direction (e.g., the Z-axis direction) of the multilayer substrate 200.

[0106] For example, the second light-shielding wall 160 has a third portion disposed within the first substrate portion FB and facing the second substrate portion SB. The third portion includes a first wire 551 and a first connection pad 552. In addition, the second light-shielding wall 160 has a fourth portion disposed within the second substrate portion SB and facing the first substrate portion FB. The fourth portion includes a second connection pad 652. The first connection pad 552 and the second connection pad 652 included in the second light-shielding wall 160 are joined together by Cu-Cu bonding.

[0107] Figure 10 is a plan view depicting the positional relationship between the first light-shielding wall 150 and the second light-shielding wall 160 and the waveguide region 11 in the light-sensing device 100 according to the first embodiment of the present invention. Note that in Figure 10 CIS pixel 20(R) represents the CIS pixel located below the red filter CF (see Figure 7 and Figure 8 ), CIS pixel 20(G) represents the CIS pixel located below the green filter CF, and CIS pixel 20(B) represents the CIS pixel located below the blue filter CF.

[0108] As Figure 10 shown, in the plan view observed from the thickness (or light-receiving) direction (e.g., the Z-axis direction) of the multilayer substrate 200, the first light-shielding wall 150 is arranged to continuously surround the waveguide region 11 without interruption. Although Figure 10 only one waveguide region 11 is depicted, the first light-shielding wall 150 is arranged to surround each of the plurality of waveguide regions 11. Although in some embodiments, the light-shielding wall 150 may continuously surround the waveguide region 11 without interruption, in some embodiments, the waveguide region 11 may be surrounded by a plurality of discontinuous walls.

[0109] The second light-shielding wall 160 is disposed between the first light-shielding wall 150 and the waveguide LGR. In the plan view observed from the Z-axis direction, the second light-shielding wall 160 is arranged to continuously surround the waveguide LGR. Although Figure 10 only one waveguide region 11 is depicted, the second light-shielding wall 160 is arranged to surround each of the plurality of waveguide regions 11.

[0110] (Advantages of the First Embodiment) As described above, the light sensing device 100 according to the first embodiment of the present invention includes a multilayer substrate 200 having a first substrate portion FB and a second substrate portion SB joined to one surface of the first substrate portion FB. The first substrate portion FB has a first semiconductor substrate 5 and a plurality of CIS pixels 20 provided in the first semiconductor substrate 5. The second substrate portion SB has a second semiconductor substrate 6 facing the first semiconductor substrate 5 and a plurality of SPAD pixels 10 provided in the second semiconductor substrate 6. The multilayer substrate 200 further has a first light shielding wall 150 provided between the first semiconductor substrate 5 and the second semiconductor substrate 6 and surrounding each of the plurality of SPAD pixels 10 in a plan view observed from the thickness direction (e.g., Z-axis direction) of the multilayer substrate 200.

[0111] Therefore, by laminating the first substrate portion FB having a plurality of CIS pixels 20 and the second substrate portion SB having a plurality of SPAD pixels 10, it is possible to make the optical axis of imaging and the optical axis of distance measurement coincide with each other (or almost coincide). Therefore, the light sensing device 100 can acquire images in the form of an imaging image and a distance image having the same optical axis.

[0112] In addition, the optical path from the front surface 5a (light emitting surface) of the first semiconductor substrate 5 to each SPAD pixel 10 (e.g., a path including the waveguide LGR) is surrounded by the first light shielding wall 150. Therefore, it is possible to suppress the diffusion of light to the outside of the path and suppress color mixing between the SPAD pixels 10. Even when the first substrate portion FB is laminated on the light incident surface side of the second substrate portion SB having the SPAD pixels 10, light can enter the SPAD pixels 10 efficiently. Therefore, deterioration of the characteristics (e.g., conversion efficiency (QE: conversion efficiency)) of the SPAD pixels 10 can be suppressed.

[0113] In addition, the second substrate portion SB further has a separation region 508 provided in the second semiconductor substrate 6 and separating one SPAD pixel 10 adjacent to another SPAD pixel 10 among the plurality of SPAD pixels 10. The first light shielding wall 150 is disposed at a position overlapping the separation region 508 in the thickness direction (e.g., Z-axis direction) of the multilayer substrate 200.

[0114] Therefore, the combination of the first light shielding wall 150 and the separation region 508 can substantially extend the light shielding wall in the thickness direction (e.g., Z-axis direction) of the multilayer substrate and further suppress color mixing between the SPAD pixels 10. For example, deterioration of the conversion efficiency (QE) can be further suppressed.

[0115] In addition, the first semiconductor substrate 5 has a waveguide region 11 located at a position overlapping the SPAD pixel 10 in the thickness direction of the multilayer substrate 200 (e.g., the Z-axis direction), and the waveguide region 11 is configured to introduce light that has entered the other surface of the first substrate portion FB opposite to the one surface into the SPAD pixel 10 in the second substrate portion SB. The CIS pixel 20 is not disposed in the waveguide region 11.

[0116] Therefore, the CIS pixel 20 is not disposed on the optical path from the rear surface 5b (light incident surface) of the first semiconductor substrate 5 to the SPAD pixel 10, and it becomes easier to dispose wires connected to the CIS pixel 20 and the like at positions away from the optical path. It is possible to prevent the light going to the SPAD pixel 10 from being attenuated or reflected by hitting the CIS pixel 20 or wires connected to the CIS pixel 20. Therefore, for example, it is possible to further suppress the deterioration of the conversion efficiency (QE).

[0117] In addition, the multilayer substrate 200 has a waveguide LGR provided between the waveguide region 11 and the SPAD pixel 10 and configured to introduce light from the waveguide region 11 into the SPAD pixel 10. Therefore, it is possible to efficiently propagate the light from the waveguide region 11 to the SPAD pixel 10.

[0118] In addition, the multilayer substrate 200 further has a second light-shielding wall 160 provided between the first light-shielding wall 150 and the waveguide LGR. Therefore, for example, the combination of the first light-shielding wall 150 and the second light-shielding wall 160 can doubly surround the optical path from the front surface 5a (light exit surface) of the first semiconductor substrate 5 to the SPAD pixel 10 and can doubly surround the waveguide LGR. Therefore, it is possible to further suppress color mixing between the SPAD pixels 10. For example, it is possible to further suppress the deterioration of the conversion efficiency (QE).

[0119] (Modification of the First Embodiment) In the case described in the above first embodiment, for example, as Figure 10 shown, the area of the waveguide region 11 is four times the pixel area of the CIS pixel 20 (corresponding to the length of two pixels in the X-axis direction and the length of two pixels in the Y-axis direction). In addition, as Figure 7 shown, the arrangement interval between the waveguide regions 11 is four times the arrangement interval between the CIS pixels 20 (i.e., corresponding to the length of four CIS pixels 20). However, the embodiments of the present invention are not limited thereto. For example, the modes shown in the following Figures 11 to 14 first modification to fourth modification can be adopted. Even with such a configuration, advantages similar to those of the above first embodiment can be obtained.

[0120] (1) First Modification Example Figure 11 is a plan view depicting a dimensional example (first modification example) of the waveguide region 11 of the light sensing device 100 according to the first embodiment of the present invention. In Figure 11 the first modification example shown, the area size of the waveguide region 11 is four times the pixel area size of the CIS pixel 20 (corresponding to the length of two pixels in the X-axis direction and the length of two pixels in the Y-axis direction). The arrangement interval between the waveguide regions 11 is six times the arrangement interval between the CIS pixels 20 (i.e., corresponding to the length of six CIS pixels 20).

[0121] (2) Second Modification Example Figure 12 is a plan view depicting a dimensional example (second modification example) of the waveguide region 11 of the light sensing device 100 according to the first embodiment of the present invention. In Figure 12 the second modification example shown, the area size of the waveguide region 11 is sixteen times the pixel area size of the CIS pixel 20 (corresponding to the length of four pixels in the X-axis direction and the length of four pixels in the Y-axis direction). For example, although not shown, the arrangement interval between the waveguide regions 11 is ten times the arrangement interval between the CIS pixels 20 (i.e., corresponding to the length of ten CIS pixels 20).

[0122] (3) Third Modification Example Figure 13 is a plan view depicting a dimensional example (third modification example) of the waveguide region 11 of the light sensing device 100 according to the first embodiment of the present invention. In Figure 13 the third modification example shown, the area size of the waveguide region 11 is four times the pixel area size of the CIS pixel 20 (corresponding to the length of two pixels in the X-axis direction and the length of two pixels in the Y-axis direction). For example, although not shown, the arrangement interval between the waveguide regions 11 is ten times the arrangement interval between the CIS pixels 20 (i.e., corresponding to the length of ten CIS pixels 20).

[0123] (4) Fourth Modification Example Figure 14 is a plan view depicting a dimensional example (fourth modification example) of the waveguide region 11 of the light sensing device 100 according to the first embodiment of the present invention. In Figure 14In the fourth modification example shown, the area of the waveguide region 11 is equal to the pixel area of the CIS pixel 20 (the length corresponding to one pixel in the X-axis direction and the length corresponding to one pixel in the Y-axis direction). For example, although not shown, the arrangement interval between the waveguide regions 11 is six times the arrangement interval between the CIS pixels 20 (i.e., the length corresponding to six CIS pixels 20).

[0124] <Second Embodiment> In the above first embodiment, the second light-shielding wall 160 disposed between the first light-shielding wall 150 and the waveguide LGR is described as including the first wire 551, the first connection pad 552, and the second connection pad 652. However, the embodiments of the present invention are not limited thereto. For example, the second light-shielding wall 160 may include only the first wire 551, or may include the first wire 551 and the first connection pad 552.

[0125] Figure 15 is a cross-sectional view depicting a configuration example of the light sensing device 100A according to the second embodiment of the present invention. As Figure 15 shown, the light sensing device 100A has a second light-shielding wall 160A. The second light-shielding wall 160A includes only the first wire 551 in the first wiring layer 55. The second light-shielding wall 160A does not include the first connection pad 552 and the second connection pad 652.

[0126] The second light-shielding wall 160A is disposed between the first light-shielding wall 150 and the waveguide LGR. In a plan view observed from the Z-axis direction, the second light-shielding wall 160A is disposed to continuously surround the waveguide LGR. The second light-shielding wall 160A is disposed to surround each of the plurality of waveguide regions 11.

[0127] Even with such a configuration, in the light sensing device 100A, for example, the combination of the first light-shielding wall 150 and the second light-shielding wall 160 can doubly surround the optical path from the front surface 5a (light-emitting surface) of the first semiconductor substrate 5 to the SPAD pixel 10, and can doubly surround the waveguide LGR. Therefore, color mixing between the SPAD pixels 10 can be further suppressed. For example, like the light sensing device 100 according to the first embodiment, deterioration of the conversion efficiency (QE) can be further suppressed.

[0128] <Third Embodiment> In the embodiments of the present invention, a third light-shielding wall may be provided between the second light-shielding wall and the waveguide. Figure 16 is a cross-sectional view depicting a configuration example of the light sensing device 100B according to the third embodiment of the present invention. As Figure 16As shown, the photosensing device 100B has a light-shielding sidewall 170 (an example of the "third light-shielding wall" of the embodiment of the present invention) located between the second light-shielding wall 160 and the waveguide LGR. For example, the light-shielding sidewall 170 is disposed along the outer peripheral side of the waveguide LGR. For example, the light-shielding sidewall 170 includes aluminum (Al) or an Al alloy. When forming the bonding pad 114 by dry etching, the light-shielding sidewall 170 can be formed incidentally. The following will be described with reference to Figure 17 this.

[0129] Figure 17 is a step diagram depicting the formation method of the bonding pad 114 and the light-shielding sidewall 170, which is part of the steps for manufacturing the photosensing device 100B according to the third embodiment of the present invention. Note that this photosensing device is manufactured by using various types of devices such as a film-forming device (including a chemical vapor deposition (CVD) device, a sputtering device, and a thermal oxidation device), an exposure device, a dry etching device, a wet etching device, or a CMP device. Hereinafter, these devices are collectively referred to as manufacturing devices.

[0130] In Figure 17 step ST1 of, a first interlayer dielectric film 553 including a SiN film 5534 is disposed on the front surface 5a side of the first semiconductor substrate 5. The first interlayer dielectric film 553 is provided with an opening H31 and an opening H32. The opening H31 is an opening for the region where the bonding pad 114 is to be disposed and the regions around and above this region, and the opening H32 is an opening above the waveguide region 11. In addition, a metal film 114' is disposed on the SiN film 5534 in the first interlayer dielectric film 553. The metal film 114' fills the openings H31 and H32.

[0131] In Figure 17 step ST1 of, the manufacturing device forms a resist pattern RP on the metal film 114'. The resist pattern RP has a shape that covers the region where the bonding pad 114 is to be formed (see Figure 16 ) from above and has openings in other regions. Next, the manufacturing device performs dry etching on the metal film 114' using the resist pattern RP as a mask. Therefore, as shown in step ST2 of Figure 17 , the bonding pad 114 and the light-shielding sidewall 170 are formed from the metal film 114'. The light-shielding sidewall 170 is formed at the side of the opening H31 where the bonding pad 114 exists, and is formed at the side of the opening H32 located above the waveguide region 11. Thereafter, the manufacturing device removes the resist pattern RP. Through this manufacturing method, the light-shielding sidewall 170 is formed.

[0132] Note that, for example, the openings H31 and H32 are filled with an HDP film 5535 (see Figure 8 ) provided on the front surface 5a side of the first semiconductor substrate 5. The HDP film 5535 is a dielectric film for forming the first waveguide LGR1 shown in Figure 16 . Further, after the openings H31 and H32 are filled with the HDP film 5535, a pad opening H11 shown in Figure 16 is formed by etching the back surface 5b side of the first semiconductor substrate 5 in an optional step.

[0133] In the Figure 16 shown photosensing device 100B, the outer peripheral side of the first waveguide LGR1 is covered by a light-shielding sidewall 170. Therefore, the combination of the first light-shielding wall 150, the second light-shielding wall 160, and the light-shielding sidewall 170 can triple surround the waveguide LGR. Accordingly, color mixing between the SPAD pixels 10 can be further suppressed, and for example, deterioration of the conversion efficiency (QE) can be further suppressed.

[0134] Further, as shown in Figure 16 , the first wiring layer 55 of the photosensing device 100B has a first connection pad 552B, and the first connection pad 552B is a modified example of the first connection pad 552 (see Figure 7 ). The second wiring layer 65 has a second connection pad 652B, and the second connection pad 652B is a modified example of the second connection pad 652 (see Figure 7 ). Both the first connection pad 552B and the second connection pad 652B contain copper (Cu) or a Cu alloy, and are joined together by Cu-Cu bonding. The first connection pad 552B and the second connection pad 652B are arranged between the CIS pixel 20 and the second semiconductor substrate 6.

[0135] Figure 18 is a plan view depicting the positional relationship between the first connection pad 552B and the second connection pad 652B and the waveguide region 11 and the CIS pixel 20 in the photosensing device 100B according to the third embodiment of the present invention. Figure 18 is a view depicting the first connection pad 552B and the second connection pad 652B when viewed from the side where the second substrate portion SB is located.

[0136] As shown in Figure 16 , the first connection pad 552B and the second connection pad 652B are arranged below the CIS pixel 20. As shown in Figure 18 , in a plan view observed from the thickness direction (e.g., the Z-axis direction) of the multilayer substrate 200, the CIS pixel 20 is arranged at a position overlapping the first connection pad 552B and the second connection pad 652B.

[0137] Therefore, the first connection pad 552B and the second connection pad 652B serve as light-shielding walls to shield the CIS pixel 20 from the light from the SPAD pixel 10. The first connection pad 552B and the second connection pad 652B can prevent the light reflected from the SPAD pixel 10 or the light generated due to the avalanche emission in the SPAD pixel 10 from entering the CIS pixel 20. Thus, for example, the noise generated in the CIS pixel 20 due to the light from the SPAD pixel 10 can be reduced.

[0138] In addition, the first wire 551 in the first wiring layer 55 can be connected to the first connection pad 552B. For example, as Figure 16 and Figure 18 shown, the wire 5511 included in the second light-shielding wall 160 in the first wire 551 can be connected to the first connection pad 552B. The wire 5511 is connected to the outer peripheral portion of the first connection pad 552B. Thus, the reflected light from the SPAD pixel 10 or the light generated due to the avalanche emission of the SPAD pixel 10 can be blocked by the wire 5511, which helps to enhance the light-shielding property and the color mixing prevention ability. Note that the wire 5511 can be a signal wire or an electrically-floating dummy wire.

[0139] Similarly, the second wire 651 in the second wiring layer 65 can be connected to the second connection pad 652B. For example, as Figure 16 and Figure 18 shown, the wire 6511 included in the first light-shielding wall 150 in the second wire 651 can be connected to the second connection pad 652B. The wire 6511 is located above the separation region 508. Thus, the light from one SPAD pixel 10 can be blocked by the wire 6511 from entering another adjacent SPAD pixel 10, and the light-shielding property between the adjacent SPAD pixels 10 can be enhanced. Note that the wire 6511 can be a signal wire or an electrically-floating dummy wire. In addition, as Figure 16 shown, the wire 6511 and the separation region 508 can be insulated by the second interlayer dielectric film 653.

[0140] <Fourth Embodiment> In the embodiment of the present invention, the waveguide region 11 in the first semiconductor substrate 5 can be provided with a through hole that penetrates the first semiconductor substrate 5 in the thickness direction (e.g., the Z-axis direction). In addition, the through hole can be provided with a waveguide by filling with a light-transmissive member.

[0141] Figure 191 is a cross-sectional view illustrating a configuration example of a light sensing device 100C according to a fourth embodiment of the present invention. Figure 19 As shown, in the optical sensing device 100C, the first substrate portion FB including the first semiconductor substrate 5 and the first wiring layer 55 is provided with a through hole H41 penetrating the first substrate portion FB in the thickness direction (eg, Z-axis direction). The through hole H41 is provided in the waveguide region 11 in the first semiconductor substrate 5.

[0142] The bottom and side surfaces of the through hole H41 are covered by a dielectric film 41 that allows light to be transmitted. In addition, a dielectric film 42 that allows light to be transmitted is filled in the through hole H41 via the dielectric film 41. The dielectric film 42 that fills the through hole H41 forms a waveguide LGRC to the SPAD pixel 10. Therefore, the waveguide LGRC penetrates the waveguide region 11 in the first semiconductor substrate 5 in the Z-axis direction.

[0143] For example, the dielectric film 41 is silicon nitride (SiN), and the dielectric film 42 is a silicon oxide (SiO) film. The refractive index of the dielectric film 41 is higher than the refractive index of the dielectric film 42. Therefore, it is possible to prevent the light that has entered the waveguide LGRC from being reflected at the interface between the dielectric film 41 and the dielectric film 42 included in the waveguide LGRC. In addition, due to the difference between the refractive indices described above, it is possible to suppress the reflected light from the SPAD pixel 10 or the light generated due to avalanche emission in the SPAD pixel 10 from entering the waveguide.

[0144] In addition, like the light sensing device 100 according to the first embodiment, the dielectric films 41 and 42 function as protective films to protect the rear surface 5 b of the first semiconductor substrate 5. Since the dielectric films 41 and 42 can also function as waveguides, rather than forming dielectric films that function only as waveguides for forming the waveguide LGRC, an increase in the number of manufacturing steps can be suppressed.

[0145] The method for forming the dielectric film 42 included in the waveguide LGRC is not particularly limited to any kind, and, for example, a spin on glass (SOG) method may be used. For example, in the SOG method, a wafer has an opening H41 formed through the wafer and a dielectric film 41 formed on the wafer, siloxane is discharged onto the rear surface 5b of the wafer (i.e., the first semiconductor substrate 5 before dicing), the wafer is rotated rapidly, and siloxane is caused to diffuse by centrifugal force to form a thin film. By heat-treating the thin film, a SiO film containing siloxane as a raw material can be formed. The SOG method excels in the ability to fill the opening and obtain flatness, and can form the waveguide LGRC relatively easily.

[0146] <Fifth Implementation Plan> In the mode described in the first to fourth embodiments above, the waveguide region is disposed above the SPAD pixel 10 (i.e., on the light incident surface side). However, the embodiments of the present invention are not limited thereto.

[0147] Figure 20 FIG. is a cross-sectional view depicting a structural example of a light sensing device 100D according to a fifth embodiment of the present invention. As Figure 20 shown, in the light sensing device 100D, the waveguide region 11 (see Figure 7 ) is not disposed above the SPAD pixel 10. Instead of the waveguide region 11, the CIS pixel 20 is disposed above the SPAD pixel 10.

[0148] Figure 21 FIG. is a plan view depicting the positional relationship between the first light shielding wall 150 and the CIS pixel 20 in the light sensing device 100D according to the fifth embodiment of the present invention. In Figure 21 , the CIS pixel 20(R) represents the CIS pixel located below the red color filter CF (see Figure 20 ), the CIS pixel 20(G) represents the CIS pixel located below the green color filter CF, and the CIS pixel 20(B) represents the CIS pixel located below the blue color filter CF.

[0149] As Figure 21 shown, the light sensing device 100D does not have the waveguide region 11. The area size of the SPAD pixel 10 (see Figure 20 ) located below the CIS pixel 20 is not particularly limited, and in the Figure 21 shown example, the area size of the SPAD pixel 10 is sixteen times the pixel area size of the CIS pixel 20 (corresponding to the length of four pixels in the X-axis direction and the length of four pixels in the Y-axis direction). In this case, the arrangement interval between the SPAD pixels 10 is four times the arrangement interval between the CIS pixels 20 (i.e., corresponding to the length of four CIS pixels 20).

[0150] As Figure 21 shown, in a plan view observed from the thickness direction (e.g., the Z-axis direction) of the multilayer substrate 200, the first light shielding wall 150 is disposed to continuously surround each of the plurality of SPAD pixels 10.

[0151] In the light sensing device 100D according to the fifth embodiment, the light that has passed through the CIS pixel 20 without passing through the waveguide region 11 enters the SPAD pixel 10 located below the CIS pixel 20. The light sensing device 100D has a separation region 508 that separates adjacent SPAD pixels 10 from each other, and a first light-shielding wall 150 is provided in the separation region 508. Since the first light-shielding wall 150 can surround the path of the light that has passed through the CIS pixel 20 and enters the SPAD pixel 10 for each SPAD pixel 10, color mixing between the SPAD pixels 10 can be suppressed. For example, deterioration of the conversion efficiency (QE) can be suppressed.

[0152] In addition, the light sensing device 100D has a second light-shielding wall 160 in addition to the first light-shielding wall 150. For example, the second light-shielding wall 160 includes only the first wire 551 in the first wiring layer 55. Since in the light sensing device 100D, the combination of the first light-shielding wall 150 and the second light-shielding wall 160 can doubly surround the optical path from the front surface 5a (light-emitting surface) of the first semiconductor substrate 5 to the SPAD pixel 10, color mixing between the SPAD pixels 10 and color mixing between the CIS pixels 20 due to reflected light or the like can be further suppressed.

[0153] Note that, as in other embodiments, the second light-shielding wall 160 may not be present in the fifth embodiment. In the light sensing device 100D, the second light-shielding wall 160 is not an essential component, and the second light-shielding wall 160 may not be present in other possible configurations.

[0154] <Application Example of a Moving Body> The technology according to the present invention (this technology) can be applied to various products. For example, the technology according to the present invention can be implemented as a device mounted on any type of moving body such as an automobile, an electric vehicle, a hybrid vehicle, a motorcycle, a bicycle, a personal mobility vehicle, an airplane, an unmanned aerial vehicle, a ship, a robot, or the like.

[0155] Figure 22 is a block diagram showing an example of a schematic configuration of a vehicle control system, which is an example of a moving body control system to which the technology according to the embodiment of the present invention is applicable.

[0156] The vehicle control system 12000 includes a plurality of electronic control units interconnected via a communication network 12001. In Figure 22In the illustrated example, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside vehicle information detection unit 12030, an inside vehicle information detection unit 12040, and an integrated control unit 12050. In addition, as a functional configuration of the integrated control unit 12050, a microcomputer 12051, a sound / image output unit 12052, and an in-vehicle network I / F (interface) 12053 are shown.

[0157] The drive system control unit 12010 controls the operation of devices related to the drive system of the vehicle according to various programs. For example, the drive system control unit 12010 functions as a control device for various devices such as a driving force generation device for generating the driving force of the vehicle, such as an internal combustion engine or a drive motor; a driving force transmission mechanism for transmitting the driving force to the wheels; a steering mechanism for adjusting the steering angle of the vehicle; and a braking device for generating the braking force of the vehicle.

[0158] The body system control unit 12020 controls the operation of various devices provided on the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for various devices such as a keyless entry system; a smart key system; an electric window device; or various lights such as headlights, reverse lights, brake lights, turn signals, and fog lights. In this case, radio waves emitted from a portable device replacing the key or signals from various switches can be input to the body system control unit 12020. The body system control unit 12020 receives these input radio waves or signals and controls the door lock device, electric window device, lights, etc. of the vehicle.

[0159] The outside vehicle information detection unit 12030 detects information on the outside of the vehicle including the vehicle control system 12000. For example, an imaging unit 12031 is connected to the outside vehicle information detection unit 12030. The outside vehicle information detection unit 12030 causes the imaging unit 12031 to capture an image of the outside of the vehicle and receives the captured image. Based on the received image, the outside vehicle information detection unit 12030 can perform processing for detecting objects such as people, vehicles, obstacles, signs, and characters on the road surface or processing for detecting the distance to the object.

[0160] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of the received light. The imaging unit 12031 can output the electrical signal as an image or can output the electrical signal as ranging information. In addition, the light received by the imaging unit 12031 can be visible light or non-visible light such as infrared light.

[0161] The in-vehicle information detection unit 12040 detects information inside the vehicle. For example, the in-vehicle information detection unit 12040 is connected to a driver state detection unit 12041 for detecting the state of the driver. For example, the driver state detection unit 12041 includes a camera for photographing the driver. Based on the detection information input from the driver state detection unit 12041, the in-vehicle information detection unit 12040 can calculate the fatigue level or concentration level of the driver, or can determine whether the driver is dozing off.

[0162] Based on the information outside or inside the vehicle obtained by the out-vehicle information detection unit 12030 or the in-vehicle information detection unit 12040, the microcomputer 12051 can calculate the control target values of the driving force generation device, the steering mechanism, or the braking device, and output a control command to the drive system control unit 12010. For example, the microcomputer 12051 can perform coordinated control for realizing the functions of ADAS (Advanced Driver Assistance System), and the functions of the ADAS include collision avoidance or shock mitigation of the vehicle, following driving based on the inter-vehicle distance, vehicle constant-speed driving, vehicle collision warning, vehicle lane departure warning, etc.

[0163] In addition, based on the information outside or inside the vehicle obtained by the out-vehicle information detection unit 12030 or the in-vehicle information detection unit 12040, the microcomputer 12051 can perform coordinated control such as autonomous driving, which aims to enable the vehicle to drive autonomously without relying on the driver's operation, by controlling the driving force generation device, the steering mechanism, the braking device, etc.

[0164] In addition, based on the information outside the vehicle obtained by the out-vehicle information detection unit 12030, the microcomputer 12051 can output a control command to the body system control unit 12020. For example, according to the position of the vehicle in front or oncoming vehicle detected by the out-vehicle information detection unit 12030, the microcomputer 12051 can perform coordinated control for realizing anti-glare, such as controlling the headlight to switch from high beam to low beam.

[0165] The sound / image output unit 12052 transmits the output signal of at least one of sound and image to an output device capable of notifying information visually or auditorily to vehicle occupants or outside the vehicle. In Figure 22 the example shown, as the output device, an audio speaker 12061, a display unit 12062, and an instrument panel 12063 are shown. For example, the display unit 12062 can include at least one of an on-board display and a head-up display.

[0166] Figure 23This is a diagram depicting an example of the installation position of the imaging unit 12031.

[0167] In Figure 23 the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.

[0168] For example, the imaging units 12101, 12102, 12103, 12104, and 12105 are provided at the positions of the front nose of the vehicle 12100, side mirrors, rear bumper, trunk lid, and the upper part of the windshield inside the vehicle compartment. The imaging unit 12101 provided at the front nose and the imaging unit 12105 provided at the upper part of the windshield inside the vehicle compartment mainly acquire images in front of the vehicle 12100. The imaging units 12102 and 12103 provided at the side mirrors mainly acquire images on the sides of the vehicle 12100. The imaging unit 12104 provided at the rear bumper or trunk lid mainly acquires images behind the vehicle 12100. The imaging unit 12105 provided at the upper part of the windshield inside the vehicle compartment is mainly used to detect vehicles, pedestrians, obstacles, signal lights, traffic signs, lanes, etc. in front.

[0169] Incidentally, Figure 23 examples of the imaging ranges of the imaging units 12101 to 12104 are shown. The imaging range 12111 represents the imaging range of the imaging unit 12101 provided at the front nose. The imaging ranges 12112 and 12113 respectively represent the imaging ranges of the imaging units 12102 and 12103 provided at the side mirrors. The imaging range 12114 represents the imaging range of the imaging unit 12104 provided at the rear bumper or trunk lid. For example, by superimposing the image data captured by the imaging units 12101 to 12104, an overhead image of the vehicle 12100 viewed from above is obtained.

[0170] At least one of the imaging units 12101 to 12104 may have a function capable of acquiring distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera composed of multiple imaging elements, or may be an imaging element having pixels for phase difference detection.

[0171] For example, based on the distance information obtained from the imaging units 12101 to 12104, the microcomputer 12051 can calculate the distance to each three-dimensional object within the imaging ranges 12111 to 12114 and the change in this distance over time (relative speed with respect to the vehicle 12100), and thus can extract a three-dimensional object as the preceding vehicle: which is particularly the closest three-dimensional object on the driving path of the vehicle 12100 and is a three-dimensional object traveling in a direction substantially the same as that of the vehicle 12100 at a predetermined speed (e.g., 0 km / h or more). In addition, the microcomputer 12051 can set the inter-vehicle distance that should be ensured in advance for the preceding vehicle and can execute automatic braking control (including follow-stop control), automatic acceleration control (including follow-start control), etc. Therefore, it is possible to execute coordinated control such as autonomous driving aimed at enabling the vehicle to autonomously travel without relying on the driver's operation.

[0172] For example, based on the distance information obtained from the imaging units 12101 to 12104, the microcomputer 12051 can classify the three-dimensional object data of the three-dimensional objects into the three-dimensional object data of two-wheeled vehicles, ordinary cars, large vehicles, pedestrians, utility poles, and other three-dimensional objects, extract the classified three-dimensional object data, and use the extracted three-dimensional object data to automatically avoid obstacles. For example, the microcomputer 12051 identifies the obstacles around the vehicle 12100 as obstacles that the driver of the vehicle 12100 can visually identify and obstacles that the driver of the vehicle 12100 has difficulty visually identifying. Then, the microcomputer 12051 determines the collision risk indicating the degree of risk of collision with each obstacle. In the case where the collision risk is equal to or greater than the set value and a collision is likely to occur, the microcomputer 12051 issues a warning to the driver via the audio speaker 12061 or the display unit 12062, or executes forced deceleration or avoidance steering via the drive system control unit 12010. Therefore, the microcomputer 12051 can provide assisted driving for avoiding collisions.

[0173] At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 may identify a pedestrian by determining whether there is a pedestrian in the captured images of the imaging units 12101 to 12104. For example, such identification of a pedestrian is performed through the following processes: a process of extracting feature points from the captured images of the imaging units 12101 to 12104 that are infrared cameras; and a process of performing a pattern matching process on a series of feature points representing an object contour to determine whether the object is a pedestrian. When the microcomputer 12051 determines that there is a pedestrian in the captured images of the imaging units 12101 to 12104 and thus identifies the pedestrian, the sound / image output unit 12052 controls the display unit 12062 to superimpose and display a square contour line for emphasis on the identified pedestrian. The sound / image output unit 12052 may also control the display unit 12062 to display an icon or the like for representing a pedestrian at a desired position.

[0174] So far, examples of vehicle control systems to which the technology according to the embodiments of the present invention can be applied have been explained. The technology according to the embodiments of the present invention can be applied to the imaging unit 12031 and the like among the above configurations. Specifically, the light sensing devices 100 and 100A to 100D can be applied to the imaging unit 12031. By applying the technology according to the embodiments of the present invention to the imaging unit 12031, light can efficiently enter the SPAD pixel 10 in the imaging device included in the imaging unit 12031, and for example, deterioration of the conversion efficiency (QE) can be suppressed.

[0175] (Other embodiments) Although the present invention has been described above by using embodiments, modification examples, and application examples, the textual descriptions and drawings constituting a part of the present invention should not be construed as limiting the present invention. Various alternative embodiments, examples, and operation techniques will be apparent to those skilled in the art from the present invention.

[0176] For example, the photosensing devices 100 and 100A to 100D according to the first to fifth embodiments described above may have a configuration in which neither the first light-shielding wall 150 nor the second light-shielding wall 160 is provided, and only one of them is provided. The photosensing devices 100 and 100A to 100C may have a configuration including a waveguide region 11 and a waveguide LGR, where CIS pixels are not arranged in the first semiconductor substrate 5, and neither the first light-shielding wall 150 nor the second light-shielding wall 160 is provided. The light-shielding sidewall 170 of the photosensing device 100B may be applied to the photosensing devices 100, 100A, 100C, and 100D. The configurations of the first connection pad 552B and the second connection pad 652B of the photosensing device 100B may also be applied to the photosensing devices 100, 100A, 100C, and 100D.

[0177] In this way, of course, the present technology includes various embodiments and the like not described herein. At least one of various omissions, substitutions, and deformations of components may be made without departing from the gist of the above-described embodiments and deformation examples. In addition, the advantages described in this specification are merely illustrated as examples, and the advantages of the present invention are not limited to these, and there may be other advantages.

[0178] Note that the present invention may also adopt the following configuration. (1) A photosensing device, comprising: A multilayer substrate having a first substrate portion and a second substrate portion bonded to one surface of the first substrate portion, wherein the first substrate portion has: A first semiconductor substrate; and A plurality of imaging pixels provided in the first semiconductor substrate, The second substrate portion has: A second semiconductor substrate facing the first semiconductor substrate; and A plurality of ranging pixels provided in the second semiconductor substrate, and The multilayer substrate further includes a first light-shielding wall provided between the first semiconductor substrate and the second semiconductor substrate, and the first light-shielding wall surrounds each of the plurality of ranging pixels in a plan view observed from the thickness direction of the multilayer substrate. (2) The photosensing device according to (1) above, wherein The second substrate portion further includes a separation region provided in the second semiconductor substrate, and the separation region separates one ranging pixel and another ranging pixel adjacent to each other among the plurality of ranging pixels, and The first light-shielding wall is disposed at a position overlapping the separation region in the thickness direction. (3)The photosensing device according to one or more of the above (1) and (2), wherein, In the plan view observed from the thickness direction, the first light-shielding wall continuously surrounds the ranging pixel without interruption. (4)The photosensing device according to any one or more of the above (1) to (3), wherein, The first light-shielding wall has: A first portion, which is disposed in the first substrate portion and faces the second substrate portion; and A second portion, which is disposed in the second substrate portion and faces the first substrate portion. (5)The photosensing device according to any one or more of the above (1) to (4), wherein, The first substrate portion has: a first wiring layer, which is disposed on the surface side of the first semiconductor substrate facing the second semiconductor substrate, The second substrate portion has: a second wiring layer, which is disposed on the surface side of the second semiconductor substrate facing the first semiconductor substrate, The first wiring layer has a first interlayer dielectric film and a first wire, The second wiring layer has a second interlayer dielectric film and a second wire, The first portion includes the first wire, and The second portion includes the second wire. (6)The photosensing device according to any one or more of the above (1) to (5), wherein, The first wiring layer has a first connection pad containing copper (Cu) or a Cu alloy, The second wiring layer has a second connection pad containing Cu or a Cu alloy, The first connection pad and the second connection pad are joined together by Cu-Cu bonding at the joint between the first substrate portion and the second substrate portion, The first portion includes the first connection pad, and The second portion includes the second connection pad. (7)The photosensing device according to any one or more of the above (1) to (6), wherein, The first connection pad included in the first portion and the second connection pad included in the second portion are arranged between the imaging pixel and the second semiconductor substrate. (8)The photosensing device according to any one or more of the above (1) to (7), wherein, The first semiconductor substrate has a waveguide region located at a position overlapping the ranging pixel in the thickness direction, and the waveguide region is configured to introduce light that has entered the other surface opposite to the one surface of the first substrate portion into the ranging pixel in the second substrate portion, and the imaging pixel is not arranged in the waveguide region. (9) The light sensing device according to any one or more of the above (1) to (8), wherein, the waveguide region is adjacent to the imaging pixel. (10) The light sensing device according to any one or more of the above (1) to (9), wherein, the multi-layer substrate has a waveguide disposed between the waveguide region and the ranging pixel, and the waveguide is configured to introduce the light from the waveguide region into the ranging pixel. (11) The light sensing device according to any one or more of the above (1) to (10), wherein, the waveguide only contains silicon oxide. (12) The light sensing device according to any one or more of the above (1) to (11), wherein, the waveguide penetrates the waveguide region in the thickness direction. (13) The light sensing device according to any one or more of the above (1) to (12), wherein, the multi-layer substrate further has: a second light-shielding wall disposed between the first light-shielding wall and the waveguide. (14) The light sensing device according to any one or more of the above (1) to (13), wherein, the multi-layer substrate further has a third light-shielding wall disposed on a side surface of the waveguide. (15) The light sensing device according to any one or more of the above (1) to (14), wherein, the multi-layer substrate further includes: a third substrate portion disposed opposite to the first substrate portion, the second substrate portion is inserted between the third substrate portion and the first substrate portion, and the third substrate portion includes: a third semiconductor substrate; and an electronic circuit disposed in the third semiconductor substrate. (16) The light sensing device according to any one or more of the above (1) to (15), wherein, the electronic circuit includes: at least any one of a ranging pixel circuit connected to the ranging pixel and an imaging pixel circuit connected to the imaging pixel. (17)The light sensing device according to any one or more of the above (1) to (16) further includes: A lens body, which is disposed opposite to the second substrate portion, and the first substrate portion is inserted between the lens body and the second substrate portion, wherein, The lens body has: A first lens that focuses light onto the imaging pixel; and A second lens that focuses light onto the distance measurement pixel, and The first lens and the second lens have different curvatures from each other. (18)The light sensing device according to any one or more of the above (1) to (17), wherein, The distance measurement pixel is a single photon avalanche diode pixel. (19)A light sensing device, comprising: A multilayer substrate having a first substrate portion and a second substrate portion bonded to one surface of the first substrate portion, wherein, the first substrate portion has: A first semiconductor substrate; and A plurality of imaging pixels disposed in the first semiconductor substrate, The second substrate portion has: A second semiconductor substrate facing the first semiconductor substrate; and A plurality of distance measurement pixels disposed in the second semiconductor substrate, The first semiconductor substrate has a waveguide region located at a position overlapping with the distance measurement pixel in the thickness direction of the multilayer substrate, and the waveguide region is used to introduce light that has entered the other surface of the first substrate portion opposite to the one surface into the distance measurement pixel in the second substrate portion, The imaging pixels are not disposed in the waveguide region, and The multilayer substrate has a waveguide disposed between the waveguide region in the first semiconductor substrate and the distance measurement pixel in the second semiconductor substrate, and the waveguide is used to introduce the light from the waveguide region into the distance measurement pixel. (20)A light detection device, comprising: A first substrate portion, which includes: A first semiconductor substrate; and A plurality of photodiodes in the first semiconductor substrate; A second substrate portion, which is laminated on the first substrate portion, and the second substrate portion includes: A second semiconductor substrate; and a plurality of avalanche photodiodes in the second semiconductor substrate; and a first light-shielding wall provided in the first substrate portion and the second substrate portion, wherein a part of the first light-shielding wall surrounds, in a cross-sectional view, a region that is located above the first avalanche photodiode among the plurality of avalanche photodiodes in a light reception direction. (21)The light detection device according to (20), wherein the second substrate portion further includes a separation region provided in the second semiconductor substrate, the separation region separating the first avalanche photodiode from a second avalanche photodiode adjacent to the first avalanche photodiode, and the first light-shielding wall is provided above the separation region in a light reception direction. (22)The light detection device according to (20) and / or (21), wherein each of the plurality of first light-shielding walls surrounding the region is connected to another one of the plurality of first light-shielding walls. (23)The light detection device according to any one or more of (20) to (22), wherein a first portion of the first light-shielding wall is provided in the first substrate portion, and a second portion of the first light-shielding wall is provided in the second substrate portion. (24)The light detection device according to any one or more of (20) to (23), wherein the first substrate portion further includes a first wiring layer provided on a surface side of the first semiconductor substrate and facing the second semiconductor substrate, the second substrate portion further includes a second wiring layer provided on a surface side of the second semiconductor substrate and facing the first semiconductor substrate, the first wiring layer includes a first interlayer dielectric film and a first wire, the second wiring layer includes a second interlayer dielectric film and a second wire, the first portion of the first light-shielding wall includes the first wire, and the second portion of the first light-shielding wall includes the second wire. (25)The light detection device according to any one or more of (20) to (24), wherein the first wiring layer includes a first connection pad including one or more of copper (Cu) and a Cu alloy, The second wiring layer includes second connection pads, and the second connection pads include one or more of Cu and Cu alloys. The first connection pad and the second connection pad are joined together at the joining portion between the first substrate portion and the second substrate portion. The first portion of the first light-shielding wall includes the first connection pad, and The second portion of the first light-shielding wall includes the second connection pad. The light detection device according to any one or more of (20) to (25), wherein The first connection pad included in the first portion of the first light-shielding wall and the second connection pad included in the second portion of the first light-shielding wall are arranged between the first semiconductor substrate and the second semiconductor substrate. The light detection device according to any one or more of (20) to (26), wherein The region is a waveguide region, and The first avalanche photodiode is not arranged in the waveguide region. The light detection device according to any one or more of (20) to (27), wherein The first substrate portion includes the waveguide region. The light detection device according to any one or more of (20) to (28) further includes: A second light-shielding wall located between the first light-shielding wall and the waveguide region. The light detection device according to any one or more of (20) to (29) further includes: A second waveguide located in the second substrate portion. The light detection device according to any one or more of (20) to (30), wherein The waveguide region is surrounded by the first light-shielding wall in the cross-sectional view. The light detection device according to any one or more of (20) to (31), wherein A through hole penetrates the first substrate portion in the waveguide region. The light detection device according to any one or more of (20) to (32), wherein The waveguide region contains silicon oxide (SiO). The light detection device according to any one or more of (20) to (33), wherein The light detection device further includes a third substrate portion, and The third substrate portion includes: a third semiconductor substrate; and a processing circuit system disposed in the third semiconductor substrate. (35)The optical detection device according to any one or more of (20) to (34), wherein the processing circuit system includes at least one of an avalanche photodiode circuit connected to the avalanche photodiode and an imaging pixel circuit connected to the photodiode. (36)The optical detection device according to any one or more of (20) to (35), further comprising: a lens body disposed opposite to the second substrate portion, with the first substrate portion inserted between the lens body and the second substrate portion, wherein the lens body includes: a first lens that focuses light onto the photodiode; and a second lens that focuses light onto the avalanche photodiode, and the first lens and the second lens have different curvatures from each other. (37)The optical detection device according to any one or more of (20) to (36), wherein the avalanche photodiode is a single-photon avalanche diode pixel. (38)An optical detection device, comprising: a plurality of lenses; a first substrate portion, which includes: a first semiconductor substrate; and a plurality of photodiodes in the first semiconductor substrate; a second substrate portion laminated on the first substrate portion, the second substrate portion including: a second semiconductor substrate; and a plurality of avalanche photodiodes in the second semiconductor substrate; and a first light-shielding wall disposed in the first substrate portion and the second substrate portion, wherein a plurality of the first light-shielding walls surround a waveguide region in a cross-sectional view. (39)The optical detection device according to (38), wherein the second substrate portion further includes a separation region disposed in the second semiconductor substrate, the separation region separating a first avalanche photodiode from a second avalanche photodiode adjacent to the first avalanche photodiode, and the first light-shielding wall is disposed above the separation region in the light-receiving direction. [List of reference numerals]

[0179] 1: Imaging unit 2: Distance measurement unit 5: First semiconductor substrate 5a, 6a, 7a: Front surface 5b, 6b: Rear surface 6: Second semiconductor substrate 7: Third semiconductor substrate 7a: Front surface 10: SPAD (Single Photon Avalanche Diode) pixel 11: Waveguide region 13: Vertical drive circuit 14: Column signal processing circuit 15: Horizontal drive circuit 16: Output circuit 17: Control circuit 20: CIS (CMOS Image Sensor) pixel 22: Horizontal signal line 23: Vertical signal line 24: Data output signal line 30: Readout circuit 31: PN photodiode 32: Transfer transistor 33: Floating diffusion section 34: Amplifying transistor 35: Selective transistor 36: Reset transistor 41, 42, 121, 5082: Dielectric film 51: Pixel region 52: Peripheral region 55: First wiring layer 61: First circuit region 62: Second circuit region 65: Second wiring layer 67: Third wiring layer 71: Third circuit region 75: Fourth wiring layer 100, 100A, 100B, 100C, 100D: Light sensing device 101: Distance measurement processing unit 102: Pixel control unit 103: Overall control unit 104: Clock generation unit 106: Interface (I / F: Interface) 110: Conversion unit 111: Generation unit 112: Signal processing unit 114: Bonding pad 114’: Metal film 120: Conductor 150: First light-shielding wall 160: Second light-shielding wall 160A: Second light-shielding wall 170: Light-shielding side wall 200: Multilayer substrate 210: SPAD (Single Photon Avalanche Diode) circuit 211: AFE (Analog Front End) circuit 212: TDC (Time-to-Digital Converter) circuit 213: Histogram circuit 214: Output unit 220: CIS (CMOS Image Sensor) circuit 411: Hole accumulation region 501: N-type semiconductor region 502: P-type semiconductor region 503: Well layer 504, 506: Contact 505: Anode 508: Separation region 551: First wire 552, 552B: First connection pad 553: First interlayer dielectric film 651: Second wire 652, 652B: Second connection pad 653: Second interlayer dielectric film 671: Third wire 672: Third connection pad 673: Third interlayer dielectric film 751: Fourth wire 752: Fourth connection pad 753: Fourth interlayer dielectric film 5081: Light-shielding film 5511, 6511: Wire 5531, 6531: SiO film 5532: SiC film 5533, 6535: TEOS film 5534, 6533: SiN film 5535, 6534: HDP film 5536, 6532: TEOS film 12000: Vehicle control system 12001: Communication network 12010: Drive system control unit 12020: Body system control unit 12030: External vehicle information detection unit 12031: Imaging section 12040: Internal vehicle information detection unit 12041: Driver state detection section 12050: Integrated control unit 12051: Microcomputer 12052: Sound / image output section 12061: Audio speaker 12062: Display section 12063: Instrument panel 12100: Vehicle 12101, 12102, 12103, 12104, 12105: Imaging section 12111, 12112, 12113, 12114: Imaging range BS1, BS2: Bonding surface BW: Bonding wire CF: Color filter FB: First substrate section H1, H2, H31, H32, H41: Opening H11: Pad opening H21: Groove H41: Through hole I: In-vehicle network I: Clock generation section LGR, LGRC, LGRD: Waveguide LGR 1: First waveguide LGR 2: Second waveguide ML1, ML2: Microlens MLA: Microlens array RP: Resist pattern SB: Second substrate section TB: Third substrate section

Claims

1. A light detection device, comprising: A first substrate portion, which includes: A first semiconductor substrate; and A plurality of photodiodes in the first semiconductor substrate; A second substrate portion, which is stacked on the first substrate portion, and the second substrate portion includes: A second semiconductor substrate; and A plurality of avalanche photodiodes in the second semiconductor substrate; and A first light-shielding wall provided in the first substrate portion and the second substrate portion, wherein a part of the first light-shielding wall surrounds the following area in a cross-sectional view: the area is located above the first avalanche photodiode among the plurality of avalanche photodiodes in the light reception direction.

2. The light detection device according to claim 1, wherein The second substrate portion further includes a separation region provided in the second semiconductor substrate, the separation region separates the first avalanche photodiode from the second avalanche photodiode adjacent to the first avalanche photodiode, and The first light-shielding wall is provided above the separation region in the light reception direction.

3. The light detection device according to claim 1, wherein Each of the plurality of first light-shielding walls surrounding the area is connected to another one of the plurality of first light-shielding walls.

4. The light detection device according to claim 1, wherein A first part of the first light-shielding wall is provided in the first substrate portion, and a second part of the first light-shielding wall is provided in the second substrate portion.

5. The light detection device according to claim 4, wherein The first substrate portion further includes a first wiring layer, the first wiring layer is provided on the surface side of the first semiconductor substrate, and the first wiring layer faces the second semiconductor substrate, The second substrate portion further includes a second wiring layer, the second wiring layer is provided on the surface side of the second semiconductor substrate, and the second wiring layer faces the first semiconductor substrate, The first wiring layer includes a first interlayer dielectric film and a first wire, The second wiring layer includes a second interlayer dielectric film and a second wire, The first part of the first light-shielding wall includes the first wire, and The second part of the first light-shielding wall includes the second wire.

6. The light detection device according to claim 5, wherein The first wiring layer includes a first connection pad, the first connection pad includes one or more of copper (Cu) and Cu alloys, The second wiring layer includes a second connection pad, the second connection pad includes one or more of Cu and Cu alloys, The first connection pad and the second connection pad are joined together at the joining portion between the first substrate portion and the second substrate portion, The first part of the first light-shielding wall includes the first connection pad, and The second part of the first light-shielding wall includes the second connection pad.

7. The light detection device according to claim 6, wherein The first connection pad included in the first part of the first light-shielding wall and the second connection pad included in the second part of the first light-shielding wall are arranged between the first semiconductor substrate and the second semiconductor substrate.

8. The optical detection device according to claim 1, wherein, the region is a waveguide region, and the first avalanche photodiode is not disposed in the waveguide region.

9. The optical detection device according to claim 8, wherein, the first substrate portion includes the waveguide region.

10. The optical detection device according to claim 8, further comprising: a second light-shielding wall located between the first light-shielding wall and the waveguide region.

11. The optical detection device according to claim 8, further comprising: a second waveguide located in the second substrate portion.

12. The optical detection device according to claim 8, wherein, the waveguide region is surrounded by the first light-shielding wall in the cross-sectional view.

13. The optical detection device according to claim 8, wherein, a through hole penetrates the first substrate portion in the waveguide region.

14. The optical detection device according to claim 10, wherein, the waveguide region contains silicon oxide (SiO).

15. The optical detection device according to claim 1, wherein, the optical detection device further includes a third substrate portion, and the third substrate portion includes: a third semiconductor substrate; and a processing circuit system disposed in the third semiconductor substrate.

16. The optical detection device according to claim 15, wherein, the processing circuit system includes at least any one of an avalanche photodiode circuit connected to the avalanche photodiode and an imaging pixel circuit connected to the photodiode.

17. The optical detection device according to claim 1, further comprising: a lens body disposed opposite to the second substrate portion, with the first substrate portion inserted between the lens body and the second substrate portion, wherein the lens body includes: a first lens that focuses light onto the photodiode; and a second lens that focuses light onto the avalanche photodiode, and the first lens and the second lens have different curvatures from each other.

18. The optical detection device according to claim 1, wherein, the avalanche photodiode is a single-photon avalanche diode pixel.

19. An optical detection device, comprising: a plurality of lenses; a first substrate portion, which includes: a first semiconductor substrate; and a plurality of photodiodes in the first semiconductor substrate; a second substrate portion, which is laminated on the first substrate portion, and the second substrate portion includes: a second semiconductor substrate; and a plurality of avalanche photodiodes in the second semiconductor substrate; and a first light-shielding wall disposed in the first substrate portion and the second substrate portion, wherein a plurality of the first light-shielding walls surround a waveguide region in a cross-sectional view.

20. The optical detection device according to claim 19, wherein, the second substrate portion further includes a separation region disposed in the second semiconductor substrate, and the separation region separates a first avalanche photodiode from a second avalanche photodiode adjacent to the first avalanche photodiode, and the first light-shielding wall is disposed above the separation region in the light reception direction.

Images