Substrate internal stress control for piezoelectric films during piezoelectric device fabrication using dynamic biasing
By applying dynamic electrical bias control substrate stress in piezoelectric device manufacturing, the problems of brittleness and stress of piezoelectric materials are solved, and uniform deposition and performance improvement of piezoelectric layer are achieved.
Patent Information
- Application Number
- CN202380083844.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2022-10-31
- Filing Date
- 2023-10-27
- Publication Date
- 2025-07-11
AI Technical Summary
The brittle properties of piezoelectric materials and the stress in the substrate cause difficulties in the manufacturing of piezoelectric devices, affecting device performance and output.
By applying a dynamic electrical bias to the stage during deposition of the piezoelectric layer, the stress range on the substrate is controlled, and the average stress of forming the piezoelectric layer is from about 50 MPa to about 300 MPa, and the electrode layer is deposited using a physical vapor deposition, chemical vapor deposition or atomic layer deposition process.
The uniform deposition of the piezoelectric layer and higher manufacturing yield are achieved, and the performance and output of piezoelectric devices are improved.
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Figure CN120304047A_ABST
Abstract
Description
BACKGROUND OF THE INVENTION
[0001] FIELD
[0002] Embodiments of the present disclosure generally relate to piezoelectric devices. More specifically, embodiments disclosed herein relate to piezoelectric devices and methods of forming a piezoelectric layer for use in manufacturing piezoelectric devices.
[0003] RELATED ART
[0004] Piezoelectric materials are materials that accumulate charge when a mechanical stress is applied and are often used in piezoelectric devices in sensors and transducers such as gyro sensors, inkjet printer heads, ultrasonic technology, and other microelectromechanical systems (MEMS) devices, including acoustic resonators for mobile phones and other wireless electronic devices. Manufacturing piezoelectric devices can be difficult due to the brittle nature of the piezoelectric material and stress within the substrate. The range of stress within the substrate can be as high as 100 MPa due to factors such as the thickness of the film, the stress gradient of the film in the vertical direction, and other factors. These high stress ranges affect the performance and yield of piezoelectric devices.
[0005] Accordingly, what is needed in the art is an improved method of manufacturing piezoelectric materials. SUMMARY OF THE INVENTION
[0006] In one embodiment, a method of forming a piezoelectric device is disclosed. The method of forming a piezoelectric device includes disposing a bottom electrode layer over a substrate, the substrate being supported by a stage. A piezoelectric layer is disposed over the bottom electrode layer along a horizontal plane. The electrical bias to the stage is varied during deposition of the piezoelectric layer. A top electrode layer is formed over the piezoelectric layer in a top electrode pattern.
[0007] In another embodiment, a piezoelectric device is disclosed. The device includes: a substrate; a bottom electrode layer formed over the substrate; a piezoelectric layer formed over the bottom electrode layer along a horizontal plane; and a top electrode layer formed over the piezoelectric layer. In the piezoelectric layer, an average stress of a plurality of stresses along the horizontal plane is from about 50 Mpa to about 300 MPa.
[0008] In yet another embodiment, a controller for a process system is disclosed. The controller includes storage instructions that, when executed by a processor, cause the system to process a substrate in a processing chamber by disposing a bottom electrode layer over the substrate. The substrate is supported by a stage. A piezoelectric layer is disposed over the bottom electrode layer. The electrical bias to the stage is varied during deposition of the piezoelectric layer. A top electrode layer is formed over the piezoelectric layer in a top electrode pattern. BRIEF DESCRIPTION OF THE DRAWINGS
[0009] In order to understand the above - stated features of the present disclosure in a manner that enables a detailed comprehension, a more specific description of the present disclosure, briefly outlined above, may be referred to the embodiments, some of which are illustrated in the accompanying drawings. However, it should be noted that the drawings only show exemplary embodiments and should not be considered as limiting the scope, since the present disclosure may admit other equally effective embodiments.
[0010] Figure 1 is a schematic top - view of a piezoelectric device according to an embodiment described herein.
[0011] Figure 2 is a schematic cross - sectional view of a piezoelectric device according to an embodiment described herein.
[0012] Figure 3 is a flow - chart of a method of forming a piezoelectric device according to an embodiment described herein.
[0013] Figures 4A to 4C is according to an embodiment described herein during Figure 3 a schematic side - view of a substrate during the method of forming a piezoelectric device.
[0014] For the sake of facilitating understanding, the same reference numerals have been used, wherever possible, to denote the same elements common to the figures. It is contemplated that the elements and features of one embodiment may be beneficially incorporated into other embodiments without further recitation. Detailed Description
[0015] Embodiments of the present disclosure generally relate to piezoelectric devices. More specifically, the embodiments disclosed herein relate to piezoelectric devices and methods of fabricating a piezoelectric layer for use in fabricating piezoelectric devices.
[0016] Patterning the piezoelectric material in a piezoelectric device may pose challenges due to the brittle and hard nature of the piezoelectric material. For a piezoelectric device, it is beneficial to pattern the piezoelectric material while controlling the stress range on the substrate. By the methods disclosed herein, improvements in patterning the piezoelectric material can be achieved. The methods disclosed herein enable the patterning of the piezoelectric material to be carried out with increased yield.
[0017] Figure 1 is a schematic top - view of a piezoelectric device 100. Figure 1 The illustrated piezoelectric device 100 may be partially fabricated and may require additional processing steps to form a functional device. The piezoelectric device 100 can be used in sensing applications (e.g., gyro sensors), ultrasonic technology, ink - jet printing, or micro - electro - mechanical systems (MEMS) devices, including acoustic resonators for mobile phones and other wireless electronic devices.
[0018] The piezoelectric device 100 includes a substrate 102 ( Figures 4A to 4Cshown), a bottom electrode layer 104, a piezoelectric layer 106, and a top electrode layer 108. In some embodiments, the piezoelectric device 100 may include a high-power seed layer disposed between the bottom electrode layer 104 and the piezoelectric layer 106. In another embodiment, the piezoelectric device 100 may include an intermediate electrode layer, a second high-power seed layer, and a second piezoelectric layer. The intermediate electrode layer is disposed above the piezoelectric layer 106, the second high-power seed layer is disposed above the intermediate electrode layer, and the second piezoelectric layer is disposed between the second high-power seed layer and the top electrode layer 108. In another embodiment, additional electrode layers, high-power seed layers, and piezoelectric layers may be deposited to achieve a desired thickness and functionality. In yet another embodiment, a primary seed layer may be disposed between the substrate and the bottom electrode layer 104.
[0019] The substrate 102 may have a diameter ranging from about 100 mm to about 750 mm and may include silicon (Si), silicon carbide (SiC), SiC-coated graphite, or silicon dioxide (SiO2). In one embodiment, the substrate 102 has a surface area of about 1,000 cm 2 or greater, such as about 2,000 cm 2 or greater, such as about 4,000 cm 2 or greater.
[0020] The bottom electrode layer 104 is disposed above the top surface of the substrate 102. The bottom electrode layer 104 is configured as the bottom electrode of the piezoelectric device 100. Examples of materials suitable for the bottom electrode layer 104 include platinum (Pt), molybdenum (Mo), SrRuO3, LaNiO3, CaRuO3, LaSrMnO3, etc. The bottom electrode layer 104 may have a thickness between about 25 nm and about 200 nm, such as between about 50 nm and about 175 nm, such as between about 75 nm and about 150 nm, for example about 125 nm.
[0021] The piezoelectric layer 106 is disposed above the bottom electrode layer 104. In some embodiments, the piezoelectric layer 106 is composed of one or more layers containing one or more of aluminum nitride (AlN), scandium-doped aluminum nitride (ScAlN), lead zirconate titanate (PZT), lead magnesium niobate-lead titanate (PMN-PT), or lithium niobate (LiNbO3 or LNO). The piezoelectric layer 106 may have a thickness between about 300 nm and about 2000 nm, such as between about 750 nm and about 1500 nm, such as about 1000 nm. In some embodiments that can be combined with other embodiments described herein, the thickness of the piezoelectric layer 106 may vary between about 300 nm and about 2000 nm on the surface of the bottom electrode layer 104. In other embodiments that can be combined with other embodiments described herein, the thickness of the piezoelectric layer 106 is constant on the surface of the bottom electrode layer 104. The piezoelectric layer 106 is selectively etched via a laser etching process to form an exposed portion 112 of the bottom electrode layer 104. The exposed portion 112 allows access to the bottom electrode layer 104.
[0022] The top electrode layer 108 is disposed above the surface of the piezoelectric layer 106. The top electrode layer 108 is configured as the top electrode of the finished piezoelectric device. In some embodiments, the top electrode layer 108 may be made of the same or different material as the bottom electrode layer 104. Examples of materials suitable for the top electrode layer 108 include platinum (Pt), molybdenum (Mo), SrRuO3, LaNiO3, CaRuO3, LaSrMnO3, etc. The top electrode layer 108 may have a thickness between about 25 nm and about 200 nm, such as between about 75 nm and about 150 nm, for example about 100 nm.
[0023] As Figure 1 shown, the top electrode layer 108 can be patterned on the surface of the piezoelectric layer 106 as needed. The top electrode layer 108 is formed in a top electrode pattern 110. The top electrode pattern 110 can be predetermined before manufacturing to conform to the specifications of the piezoelectric device 100. The top electrode pattern 110 of the top electrode layer 108 is not limited to Figure 1 the pattern shown and can be adjusted as needed. For example, the top electrode pattern 110 may include a circular, rectangular, square, or irregular pattern.
[0024] Figure 2FIG. 0 is a schematic cross-sectional view of piezoelectric device 100 along cutting line A-A. Bottom electrode layer 104 is disposed above the surface of substrate 102. Piezoelectric layer 106 is disposed above the surface of bottom electrode layer 104 along a horizontal plane. Top electrode layer 108 is disposed above the surface of piezoelectric layer 106. In one embodiment, bottom electrode layer 104, piezoelectric layer 106, and top electrode layer 108 may be deposited using physical vapor deposition (PVD). In other embodiments, chemical vapor deposition (CVD), atomic layer deposition (ALD), or other suitable deposition processes may be used. The deposition process occurs in a processing chamber configured to perform PVD, CVD, ALD, or other deposition processes.
[0025] During deposition of bottom electrode layer 104 and top electrode layer 108, an electrical bias is applied to the stage or substrate support within the processing chamber at a static value between approximately 400 W and approximately 3000 W. During deposition of piezoelectric layer 106, a dynamic electrical bias is applied to the stage at various power levels between no bias (e.g., 0 W) and approximately 200 W (such as approximately 20 W to approximately 100 W). The stage supports substrate 102 within the chamber.
[0026] The variation in bias (e.g., dynamic bias) results in an average stress within piezoelectric layer 106 of approximately 50 MPa to approximately 300 MPa. The average stress is the average of multiple stresses within piezoelectric layer 106 along the horizontal plane. The dynamic bias within piezoelectric layer 106 results in a stress range on substrate 102 of approximately + / - 0 MPa to approximately + / - 100 MPa, e.g., a maximum deviation from the average stress on the substrate of approximately 100 MPa and a minimum deviation from the average stress on the substrate of approximately 0 MPa. For example, in one embodiment, the dynamic bias results in an average stress within piezoelectric layer 106 of approximately 200 MPa and a stress range on substrate 102 between approximately 100 MPa and approximately 300 MPa (i.e., + / - 100 MPa of the average stress value). In another embodiment, the dynamic bias within piezoelectric layer 106 is approximately 100 MPa and the stress range on substrate 102 is between approximately 50 MPa and approximately 150 MPa (i.e., + / - 50 MPa). The dynamic bias may be further adjusted to produce an average stress value and stress range that conform to a predetermined function. Thus, the above examples are not intended to be limiting as the present disclosure contemplates other average stresses and stress ranges.
[0027] Dynamic biasing controls the substrate stress within piezoelectric layer 106. The controlled stress range means that the piezoelectric layer 106 is flatter (e.g., more planar) within the piezoelectric device 100. The improved planarity affects the performance of the piezoelectric device 100 and improves the manufacturing yield of the piezoelectric device 100. Increasing and decreasing the dynamic bias during the formation of the piezoelectric device 100 can both affect the stress level within the piezoelectric layer 106. A large stress range within the piezoelectric layer 106 can lead to degraded performance.
[0028] The system can be tuned to a predetermined average stress and then increase or decrease the dynamic bias based on a measured value of the stress within the piezoelectric layer 106 to keep the stress level and range close to the predetermined average stress. The dynamic bias can also control the average stress and stress range by controlling the deposition rate and material properties (such as crystallinity) of the piezoelectric layer 106. For example, improved crystallinity control allows the properties of the piezoelectric layer 106 to be more predictable, and thus tuning the dynamic bias to promote preferred crystal behavior can facilitate control of the stress within the substrate. Controlling the deposition rate further promotes uniform deposition, thereby contributing to consistent film properties on the piezoelectric layer 106 and achieving the predetermined average stress and stress range. Accordingly, high volume production (HVP) of these piezoelectric devices 100 is enabled.
[0029] Figure 3 is a flow chart of a method 300 of forming a piezoelectric device 100, as Figures 4A to 4C shown. Figures 4A to 4C is a schematic side view of a substrate 102 during a method 300 of forming a piezoelectric device 100.
[0030] At operation 301, as Figure 4A shown, a bottom electrode layer 104 is disposed above the substrate 102. The substrate 102 is supported by a substrate support or platen. The bottom electrode layer 104 can be disposed via a PVD process, a CVD process, or an ALD process performed in a suitable processing chamber. In certain embodiments, the deposition process is performed between about 25°C and about 600°C (such as between about 400°C and about 600°C, and such as about 500°C). In certain embodiments, when depositing via PVD, the platen within the processing chamber is negatively biased with a pulsed or continuous power supply that provides DC power to the platen at a static electrical bias power level between about 400 W and about 1000 W (such as between about 600 W and about 800 W) during the deposition process.
[0031] At operation 302, as Figure 4BAs shown, a piezoelectric layer 106 is disposed above the bottom electrode layer 104. The piezoelectric layer 106 is disposed via a PVD process, a CVD process, or an ALD process performed in a suitable processing chamber. In certain embodiments, the target in the processing chamber is negatively biased by a pulsed or continuous power source that supplies RF power to the stage. The power supplied to the stage is a dynamic bias with a power level between about 0 W and about 200 W (such as about 20 W to about 100 W). During the deposition of the piezoelectric layer 106, the power level is varied to control the stress within the piezoelectric layer 106.
[0032] A change in the bias (e.g., dynamic bias) results in an average stress within the piezoelectric layer 106 of about 50 MPa to about 300 MPa. The dynamic bias is intentionally varied throughout the substrate processing in order to achieve a predetermined function. The dynamic bias within the piezoelectric layer 106 results in a stress range on the substrate 102 between about + / - 0 MPa and about + / - 200 MPa. In one embodiment, the dynamic bias results in an average stress within the piezoelectric layer 106 of about 200 MPa, and a stress range on the substrate 102 between about 100 MPa and about 300 MPa (i.e., + / - 100 MPa of the average stress value). In another embodiment, the dynamic bias within the piezoelectric layer 106 is about 100 MPa, and the stress range on the substrate 102 is between about 50 MPa and about 150 MPa (i.e., + / - 50 MPa). The dynamic bias can be further adjusted to produce an average stress value and a stress range that conform to a predetermined function. Thus, the above examples are not intended to be limiting, as the present disclosure contemplates other average stresses and stress ranges.
[0033] At operation 303, as Figure 4C shown, a top electrode layer 108 is formed above the piezoelectric layer 106. The top electrode layer 108 is formed in a top electrode pattern 110. The top electrode layer 108 can be formed at one or more predetermined locations above the piezoelectric surface 107. In one embodiment that can be combined with other embodiments described herein, the top electrode layer 108 is deposited on the piezoelectric layer 106, followed by an etching process to form the top electrode pattern 110. The top electrode layer 108 is disposed via a PVD process, a CVD process, or an ALD process performed in a suitable processing chamber. Additionally, in another embodiment that can be combined with other embodiments described herein, the top electrode layer 108 is sputtered through a proximity mask to form the top electrode pattern 110. Multiple top electrode patterns 110 can be formed above the piezoelectric layer 106. The top electrode pattern 110 is not limited to Figure 1 the pattern shown.
[0034] Figure 5 is a schematic cross-sectional view of a processing chamber 500. The processing chamber 500 is used for depositing a piezoelectric layer during the manufacture of the piezoelectric device 100.
[0035] Processing chamber 500 includes placing piezoelectric device 100 on the surface of worktable 502. Worktable 502 is disposed in processing chamber 500 such that the surface of worktable 502 (e.g., susceptor) is positioned opposite to showerhead 504. Processing chamber 500 is operable to deposit piezoelectric device layers (i.e., top electrode layer 108, piezoelectric layer 106, and bottom electrode layer 104). Processing chamber 500 includes controller 508 and power supply 520. Controller 508 communicates with worktable 502, showerhead 504, and power supply 520.
[0036] Controller 508 is generally designed to facilitate the control and automation of the methods described herein. Depositing the piezoelectric device layers (i.e., top electrode layer 108, piezoelectric layer 106, and bottom electrode layer 104) occurs in process space 506 of processing chamber 500. Processing chamber 500 can be a PVD chamber, a CVD chamber, an ALD chamber, or other types of chambers for depositing films. Controller 508 can be coupled to or communicate with processing chamber 500 and is configured to receive data or inputs from a plurality of sensors within processing chamber 500 as sensor readings. Controller 508 is further configured to store these sensor readings in a memory.
[0037] Sensor readings include any other previous sensor readings within the processing chamber. Sensor readings include calculated values stored after the sensor readings are measured by controller 508 and passed through a system model. The system model is a program configured to estimate deposition time, thickness, and electrical bias within processing chamber 500 throughout the deposition process. Thus, controller 508 is configured to both retrieve stored sensor readings and save sensor readings for future use. Maintaining previous sensor readings enables controller 508 to adjust the system model over time to reflect a more accurate version of the processing chamber.
[0038] Controller 508 can include a CPU (i.e., computer system) and communicate with the CPU. The CPU can be a hardware unit or a combination of hardware units capable of executing software applications and processing data. The CPU can have a memory, a mass storage device, input controls, and a display unit. In some configurations, the CPU includes a digital signal processor (DSP), an application specific integrated circuit (ASIC), a graphics processing unit (GPU), and / or a combination of such units. The CPU is generally configured to execute one or more software applications and process stored data. Support circuits are coupled to the CPU to support the processor in a conventional manner.
[0039] The controller 508 is configured to control the deposition of the top electrode layer 108, the piezoelectric layer 106, and the bottom electrode layer 104, as well as any additional layers that may be deposited over the substrate 102. The controller 508 is further configured to communicate with the power supply 520 to control the electrical bias applied to the stage 502 during the deposition process. The controller 508 may include a non-transitory computer-readable medium for storing instructions for the deposition process of the piezoelectric device 100. These instructions include that when depositing the bottom electrode layer 104 via PVD as in operation 301 of method 300, the stage 502 in the processing chamber is negatively biased by a pulsed or continuous power supply (e.g., power supply 520) during the deposition process. The power supply 520 provides DC power to the stage 502 at a static electrical bias power level between approximately 400 W and approximately 1000 W (such as between approximately 600 W and approximately 800 W). These instructions further include varying the electrical bias of the power supply 520 applied during the deposition of the piezoelectric layer 106 when depositing the piezoelectric layer 106 as in operation 302. The stage 502 is negatively biased by a pulsed or continuous power supply that provides RF power to the stage 502. The power supplied to the stage 502 by the power supply 520 is a dynamic bias with a power level between approximately 0 W and approximately 200 W (such as between approximately 20 W and approximately 100 W).
[0040] The stage 502 includes a stage actuator 510. The stage actuator 510 allows the stage 502 to be scanned in the X-axis, Y-axis, and Z-axis directions, as indicated by the coordinate system shown Figure 5 The stage 502 is coupled to the controller 508 so as to provide information about the position of the stage 502 to the controller 508. Additionally, the stage 502 communicates with the controller 508 such that the stage 502 can be moved in a desired direction to etch the piezoelectric layer 106.
[0041] In yet another embodiment that may be combined with other embodiments described herein, the piezoelectric device 100 may undergo further processing to further characterize the piezoelectric device 100.
[0042] Although the foregoing is directed to embodiments of the present disclosure, other and further embodiments of the present disclosure may be devised without departing from the basic scope thereof, the scope of the present disclosure being determined by the appended claims.
Claims
1. A method of forming a piezoelectric device, the method comprising: Placing a bottom electrode layer above a substrate, the substrate being supported by a stage; Placing a piezoelectric layer in a horizontal plane above the bottom electrode layer; Changing an electrical bias of the stage during deposition of the piezoelectric layer; And Forming a top electrode layer in a top electrode pattern above the piezoelectric layer.
2. The method of claim 1, wherein the change in the electrical bias of the stage occurs between 0 W and 200 W.
3. The method of claim 1, wherein in the piezoelectric layer, an average stress of a plurality of stresses along the horizontal plane is from about 50 MPa to about 300 MPa.
4. The method of claim 3, wherein a maximum deviation from the average stress on the substrate is about 100 MPa, and a minimum deviation from the average stress on the substrate is about 0 MPa.
5. The method of claim 1, further comprising applying a static electrical bias between 400 W and 3000 W to the stage during deposition of the bottom electrode layer and the top electrode layer.
6. The method of claim 1, wherein the piezoelectric layer comprises one or more of aluminum nitride (AlN), scandium-doped aluminum nitride (ScAlN), lead zirconate titanate (PZT), lead magnesium niobate-lead titanate (PMN-PT), or lithium niobate (LiNbO3).
7. The method of claim 1, wherein the bottom electrode layer, the piezoelectric layer, and the top electrode layer are placed using physical vapor deposition (PVD), chemical vapor deposition (CVD), or atomic layer deposition (ALD).
8. The method of claim 1, wherein the top electrode layer and the bottom electrode layer comprise platinum (Pt), molybdenum (Mo), SrRuO3, LaNiO3, CaRuO3, or LaSrMnO3.
9. A piezoelectric device, the piezoelectric device comprising: A substrate; A bottom electrode layer formed above the substrate; A piezoelectric layer formed in a horizontal plane above the bottom electrode layer, wherein in the piezoelectric layer, an average stress of a plurality of stresses along the horizontal plane is from about 50 MPa to about 300 MPa; And A top electrode layer formed on the piezoelectric layer.
10. The piezoelectric device of claim 9, wherein the piezoelectric layer comprises one or more of aluminum nitride (AlN), scandium-doped aluminum nitride (ScAlN), lead zirconate titanate (PZT), lead magnesium niobate-lead titanate (PMN-PT), or lithium niobate (LiNbO3).
11. The piezoelectric device of claim 9, wherein the piezoelectric layer has a thickness between 300 nm and 2000 nm.
12. The piezoelectric device of claim 9, wherein the thickness of the piezoelectric layer varies between 300 nm and 2000 nm on the surface of the bottom electrode layer.
13. The piezoelectric device according to claim 9, wherein the top electrode layer and the bottom electrode layer comprise platinum (Pt), molybdenum (Mo), SrRuO3, LaNiO3, CaRuO3, or LaSrMnO3.
14. The piezoelectric device according to claim 9, wherein the bottom electrode layer has a thickness between 25 nm and 200 nm.
15. The piezoelectric device according to claim 9, wherein the top electrode layer has a thickness between 25 nm and 200 nm.
16. A controller for a process system, the controller storing instructions that, when executed by a processor, cause the system to: process a substrate in a processing chamber by placing a bottom electrode layer above the substrate, the substrate being supported by a stage; place a piezoelectric layer above the bottom electrode layer along a horizontal plane; vary an electrical bias to the stage during deposition of the piezoelectric layer; and form a top electrode layer in a top electrode pattern above the piezoelectric layer.
17. The controller according to claim 16, wherein the electrical bias to the stage varies between 0 W and 200 W.
18. The controller according to claim 16, wherein, within the piezoelectric layer, an average stress of a plurality of stresses along the horizontal plane is from about 50 MPa to about 300 MPa.
19. The controller according to claim 18, wherein a maximum deviation from the average stress on the substrate is about 100 MPa and a minimum deviation from the average stress on the substrate is about 0 MPa.
20. The controller according to claim 16, wherein the piezoelectric layer comprises one or more of aluminum nitride (AlN), scandium-doped aluminum nitride (ScAlN), lead zirconate titanate (PZT), lead magnesium niobate-lead titanate (PMN-PT), or lithium niobate (LNO).