Test system and test method

Abstract

The invention relates to the technical field of semiconductor testing, and provides a testing system and a testing method.The testing system comprises a testing machine and a stack testing structure formed by stacking a plurality of chips to be tested; each to-be-tested chip comprises a test bonding pad array, and in the stack test structure, the test bonding pad arrays between different to-be-tested chips are correspondingly and electrically connected; the test machine executes a parallel test on the stacked test structure based on the test bonding pad array of any chip to be tested; the test system and the test method provided by the invention aim at improving the test efficiency of the integrated circuit test.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor testing technologies, and particularly relates to a testing system and a testing method. Background Art

[0002] With the continuous expansion of the design scale of integrated circuits, the density of electronic devices on a single chip is increasing, the characteristic size of electronic devices is getting smaller, and the integrated circuit process flow includes many complex process steps, each with specific process manufacturing deviations. Therefore, integrated circuit testing is crucial for ensuring the yield of integrated circuit chips.

[0003] An addressable test chip is a type of test chip often used in the manufacturing process of integrated circuit chips. The addressable test chip configures an addressable circuit for the device under test, and uses a decoder and a switch selection circuit to achieve the purpose of sharing pads by multiple test structures.

[0004] However, the testing efficiency of performing integrated circuit testing based on an addressable test chip is relatively low, which indirectly affects the production capacity of the chips. Summary of the Invention

[0005] The present disclosure provides a testing system and a testing method, which can at least improve the testing efficiency of integrated circuit testing.

[0006] In a first aspect, an embodiment of the present disclosure provides a testing system, including: a tester, and a stacked test structure formed by stacking a plurality of chips under test; each of the chips under test includes: a test pad array, and in the stacked test structure, the test pad arrays between different chips under test are correspondingly electrically connected; the tester performs parallel testing on the stacked test structure based on the test pad array of any one of the chips under test.

[0007] In some embodiments, the tester includes at least one test unit, and each test unit includes: a test component, a switch component, and a probe group; the probe group connects the test component and the switch component; the switch component is configured to drive corresponding probes in the probe group; when the probe group is electrically connected to the test pad array, the test component is configured to perform testing on the stacked test structure.

[0008] In some embodiments, each of the chips under test includes a plurality of test structures, the test pad array includes address pins and test pins; the test structures are electrically connected to the address pins and the test pins, and a plurality of the test structures are connected in parallel; the address pins are configured to allow the tester to select a target test structure from the plurality of test structures; the test pins are configured to electrically connect the target test structure to the tester.

[0009] In some embodiments, the test pad array further includes: mode pins configured to enable a tester to select a target chip under test in the stacked test structure.

[0010] In some embodiments, the test pad array further includes: calibration pins configured to verify and calibrate the port voltage of the target test structure.

[0011] In some embodiments, the test pins include a source signal terminal, a drain signal terminal, a gate signal terminal, a substrate signal terminal, a source calibration terminal, a drain calibration terminal, and a gate calibration terminal, and the test structure includes a test transistor; wherein, the gate of the test transistor is electrically connected to the gate signal terminal and the gate calibration terminal, the source of the test transistor is electrically connected to the source signal terminal and the source calibration terminal, the drain of the test transistor is electrically connected to the drain signal terminal and the drain calibration terminal, and the substrate of the test transistor is electrically connected to the substrate signal terminal.

[0012] In some embodiments, the test transistor is electrically connected to the test pins based on an address switch; wherein, the address switch is electrically connected to the address pins.

[0013] In some embodiments, the address pins include row pins and column pins, and the address switch includes a first switch and a second switch; the source of the test transistor is electrically connected to the source signal terminal and the source calibration terminal based on the first switch; the drain of the test transistor is electrically connected to the drain signal terminal and the drain calibration terminal based on the first switch; the gate of the test transistor is electrically connected to the gate signal terminal and the gate calibration terminal based on the second switch; the first switch is electrically connected to the column pins, and the second switch is electrically connected to the row pins.

[0014] In some embodiments, the test structure is electrically connected to the test pad array based on transmission lines; wherein, the transmission lines are arranged based on the back-end metal parallel routing of the chip under test.

[0015] In some embodiments, the chip under test further includes an address recognition circuit electrically connected to the address pins and configured to generate an address signal based on an address pulse issued by a tester.

[0016] In some embodiments, the address recognition circuit includes: cascaded multi-stage flip-flops, wherein the input terminal of each stage of flip-flop is connected to the inverted output terminal, and the output terminal is used to output one bit of the address signal; the clock terminals of the non-first-stage and non-last-stage flip-flops are connected to the inverted output terminal of the previous-stage flip-flop; the clock terminal of the first-stage flip-flop is connected to the address pins, and the inverted output terminal of the last-stage flip-flop is left floating; the output data of the output terminals of the cascaded multi-stage flip-flops constitutes the address signal.

[0017] In some embodiments, the test pad arrays between different chips to be tested are electrically connected correspondingly based on interconnections.

[0018] In a second aspect, embodiments of the present disclosure provide a test method, including: a tester selects a target chip to be tested in a stacked test structure based on an enable signal; the tester selects a target test structure in the target chip to be tested based on an address signal; the tester completes a test based on the target test structure.

[0019] In some embodiments, the chip to be tested further includes an address recognition circuit, which is electrically connected to the address pins and is configured to generate an address signal based on an address pulse sent by the tester. The method for the tester to select a target test structure in the target chip to be tested based on the address signal includes: the tester provides an address pulse; the address recognition circuit decodes the address pulse to generate an address signal; the target chip to be tested selects the target test structure based on the address signal.

[0020] The technical solutions provided by the embodiments of the present disclosure at least have the following advantages:

[0021] 1. The tester is used to perform parallel tests on multiple stacked test structures, so as to perform parallel tests on the chips to be tested in the multiple stacked test structures, thereby improving the test efficiency of integrated circuit testing.

[0022] 2. By directly selecting the target chip to be tested through the mode pin, the test word lines and test bit lines of the chip to be tested can adopt the same encoding, simplifying the encoding process of the test word lines and test bit lines, and indirectly improving the test efficiency. Description of the Drawings

[0023] One or more embodiments are exemplarily illustrated by pictures in the corresponding drawings. These exemplary illustrations do not constitute limitations on the embodiments. Elements with the same reference numerals in the drawings are represented as similar elements. Unless otherwise stated, the drawings in the figures do not constitute a proportional limitation; in order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or in the prior art, the following will briefly introduce the drawings required to be used in the embodiments. Obviously, the following described drawings are only some embodiments of the present disclosure. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0024] Figure 1 Schematic diagram of the architecture of a test system provided by an embodiment of the present disclosure;

[0025] Figure 2 Schematic diagram of the structure of a stacked test structure provided by an embodiment of the present disclosure;

[0026] Figure 3 Schematic diagram of another stacked test structure provided by an embodiment of the present disclosure;

[0027] Figure 4 Schematic diagram of a testing machine provided by an embodiment of the present disclosure;

[0028] Figure 5 Schematic diagram of a corresponding test pad array and test structure provided by an embodiment of the present disclosure;

[0029] Figure 6 Schematic diagram of a corresponding test pad array with an address recognition circuit and test structure provided by an embodiment of the present disclosure;

[0030] Figure 7 Structural and working principle diagrams of an address recognition circuit provided by an embodiment of the present disclosure;

[0031] Figure 8 Circuit diagram of the connection between a test pad array and a test structure provided by an embodiment of the present disclosure;

[0032] Figure 9 Schematic diagram of the control principle of a test structure provided by an embodiment of the present disclosure;

[0033] Figure 10 Device schematic diagram of the connection between a test pad array and a test structure provided by an embodiment of the present disclosure;

[0034] Figure 11 Schematic diagram of the corresponding process of each step in a test method provided by another embodiment of the present disclosure. Detailed implementation manners

[0035] In the description of the embodiments of the present disclosure, technical terms such as "first" and "second" are only used to distinguish different objects, and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity, specific order or primary and secondary relationship of the indicated technical features. In the description of the embodiments of the present disclosure, "a plurality" means more than two, unless otherwise specifically and explicitly defined.

[0036] Referring to "embodiment" herein means that a specific feature, structure or characteristic described in connection with the embodiment may be included in at least one embodiment of the present disclosure. The phrase appearing in various positions in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment mutually exclusive with other embodiments. Those skilled in the art understand explicitly and implicitly that the embodiments described herein can be combined with other embodiments.

[0037] In the description of the embodiments of the present disclosure, the term "and / or" is merely a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent three situations: the existence of A, the coexistence of A and B, and the existence of B. Additionally, in this text, the character " / " generally represents an "or" relationship between the associated objects before and after.

[0038] In the description of the embodiments of the present disclosure, the term "plural" refers to two or more (including two). Similarly, "multiple groups" refers to two or more groups (including two groups), and "multiple pieces" refers to two or more pieces (including two pieces).

[0039] In the description of the embodiments of the present disclosure, for technical terms such as "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc., the orientation or positional relationship indicated is based on the orientation or positional relationship shown in the drawings. It is only for the convenience of describing the embodiments of the present disclosure and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be construed as a limitation on the embodiments of the present disclosure.

[0040] In the description of the embodiments of the present disclosure, unless otherwise clearly specified and limited, technical terms such as "installation", "connection", "coupling", "fixation", etc. should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or integrated; it can also be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, and it can be the internal communication of two elements or the interaction relationship between two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the embodiments of the present disclosure can be understood according to specific circumstances.

[0041] In the corresponding drawings of the embodiments of the present disclosure, for better understanding and convenience of description, the thickness and area of the layer are enlarged. When describing a component (such as a layer, film, region, or substrate) on or on the surface of another component, the component can be "directly" on the surface of the other component, or there can be a third component between the two components. On the contrary, when describing a component on the surface of another component or when a surface of a component forms or is provided with another component, it means that there is no third component between the two components. Additionally, when describing a component "substantially" formed on another component, it means that the component is not formed on the entire surface (or front surface) of the other component, nor on a partial edge of the entire surface.

[0042] In the description of the embodiments of the present disclosure, when a certain component "includes" another component, unless otherwise specified, other components are not excluded, and other components may further be included. In addition, when a component such as a layer, film, region, or plate is referred to as being "on / located on" another component, it may be "directly on" another component (i.e., located on the surface of another component with no other components therebetween), or there may be other components therebetween. In addition, when a component such as a layer, film, region, or plate is "directly located on" another component, or when a component such as a layer, film, region, or plate is located on the surface of another component, it means that no other components are located therebetween.

[0043] The terms used in the description of the various embodiments herein are only for the purpose of describing specific embodiments and are not intended to be limiting. As used in the description of the various embodiments and the appended claims, "the component" is also intended to include the plural form unless the context clearly indicates otherwise. Among them, the component includes components such as a layer, film, region, or plate.

[0044] As can be seen from the background art, currently, the test efficiency of performing integrated circuit tests based on an addressable test chip is relatively low, which indirectly affects the production capacity of the chip.

[0045] An embodiment of the present disclosure provides a test system, including: a tester, and a stacked test structure formed by stacking a plurality of chips under test; each of the chips under test includes: a test pad array, and in the stacked test structure, the test pad arrays between different chips under test are correspondingly electrically connected; the tester performs parallel tests on the stacked test structure based on the test pad array of any one of the chips under test.

[0046] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. However, those of ordinary skill in the art can understand that in the embodiments of the present disclosure, many technical details are proposed to help readers better understand the present disclosure. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions claimed in the present disclosure can still be implemented.

[0047] Reference Figure 1 , Figure 1 is a schematic diagram of the architecture of the test system provided in this embodiment. The test system 10 provided in this embodiment includes a tester 100 and a stacked test structure 200 formed by stacking a plurality of chips under test 201.

[0048] For the stacked test structure 200, the stacked test structure 200 includes a plurality of chips under test 201; wherein, each chip under test 201 includes: a test pad array 202, and in the stacked test structure 200, the test pad arrays 202 between different chips under test 201 are correspondingly electrically connected.

[0049] For the test machine 100, the test machine 100 performs parallel testing on the stacked test structure 200 based on the test pad array 202 of any chip 201 to be tested. For the test system 10 provided in this embodiment, the test machine 100 is used to perform parallel testing on multiple stacked test structures 200, so as to perform parallel testing on the chips 201 to be tested in multiple stacked test structures 200, thereby improving the test efficiency of integrated circuit testing.

[0050] Specifically, assume that there are x chips 201 to be tested in the stacked test structure 200, and each single chip 201 to be tested includes n test structures (DUTs). Due to the corresponding interconnection between the test pad arrays 202 of the chips 201 to be tested in the stacked test structure 200, when the test probe of the test machine 100 contacts the test pad array 202 of any chip 201 to be tested in the stacked test structure 200, that is, the test machine 100 is simultaneously connected to n*x test structures (DUTs), which greatly increases the number of test structures (DUTs) that can be tested by a single test probe of the test machine, so as to reduce the replacement frequency of the chips 201 to be tested and improve the test efficiency of the test system 10; in addition, assume that the test machine 100 includes y groups of test probes and can simultaneously perform tests on y stacked test structures 200. At this time, a single test of the test machine 100 can simultaneously test y test structures (DUTs), that is, the test efficiency of the test system 10 is further improved based on the parallel testing method.

[0051] Reference Figure 2 and Figure 3 , Figure 2 is a schematic structural diagram of a stacked test structure provided in this embodiment. Figure 3 is a schematic structural diagram of another stacked test structure provided in this embodiment.

[0052] In some embodiments, referring to Figure 2 , in the stacked test structure 200, different chips 201 to be tested are arranged staggeredly to expose the test pad arrays 202 in adjacent layers of chips 201 to be tested, and the test pad arrays 202 in different chips 201 to be tested are connected by wire bonding 204 to achieve corresponding electrical connection between the test pad arrays 202.

[0053] In some embodiments, referring to Figure 3, in the stacked test structure 200, the test pad arrays 202 between different chips under test 201 are electrically connected correspondingly based on vertical interconnection. In one example, the test pad arrays 202 between different chips under test 201 are electrically connected correspondingly based on through-silicon vias (TSVs); specifically, through-silicon vias can be provided in the chips under test 201. After the chips under test 201 are vertically stacked, the stacked chips under test 201 are in conductive contact through the corresponding through-silicon vias, thereby realizing the corresponding electrical connection between the test pad arrays 202. The corresponding electrical connection of the test pad arrays 202 between different chips under test 201 shortens the metal traces between the chips under test 201, avoids signal loss caused by too long metal traces, and is beneficial to improving the accuracy of measurement results.

[0054] It should be noted that Figure 2 and Figure 3 in the example, the fact that the stacked test structure 200 includes 3 chips under test 201 does not limit the number of chips under test 201 in the stacked test structure 200, Figure 2 and Figure 3 and the example is only used to illustrate the electrical connection method of multiple chips under test 201 in the stacked test structure 200.

[0055] Referring to Figure 4 , Figure 4 is a schematic structural diagram of the testing machine provided in this embodiment. In some embodiments, the testing machine 100 includes at least one testing unit 301, and each testing unit 301 includes a testing component 310, a switching component 320, and a probe group 330. Among them, the probe group 330 connects the testing component 310 and the switching component 320; the switching component 320 is configured to drive the corresponding probes in the probe group 330; when the probe group 330 is electrically connected to the test pad array 202, the testing component 310 is configured to perform tests on the stacked test structure 200.

[0056] In some embodiments, the probes in the probe group 330 can include, classified by function: one or more of mode probes, address probes, test probes, and calibration probes. Among them, the specific probe types and their corresponding functions are described correspondingly in the subsequent classification of the test pad array 202, and will not be elaborated here.

[0057] In one example, the testing machine 100 includes: a communication bus 302, a controller 303, and a memory 304. Among them, the memory 304 is used to store relevant test instructions required for the testing machine 100 to execute tests. The controller 303 reads the test instructions in the memory 304 and formulates relevant test logics to support the execution of tests. The communication bus 302 connects the controller 303 and the test unit 301 to transmit the relevant test instructions issued by the controller 303 to the corresponding test unit 301. Among them, the switch component 320 is used to control the power-on and power-off of the corresponding probes in the probe group 330. When the corresponding probes in the probe group 330 are electrically connected to the test pad array 202 in the chip under test 201 and the probes are powered on, the test component 310 completes the test of the specified test structure (DUT) in the chip under test 201 based on the data / level feedback from the probes.

[0058] Reference Figure 5 , Figure 5 FIG. is a schematic structural diagram corresponding to the test pad array and the test structure provided in this embodiment. In some embodiments, each chip under test 201 includes multiple test structures 205, and the test pad array 202 includes at least an address pin 402 and a test pin 403. The test structure 205 is electrically connected to the address pin 402 and the test pin 403, and multiple test structures 205 are arranged in parallel; the address pin 402 is configured to enable the testing machine 100 to select a target test structure from multiple test structures 205; the test pin 403 is configured to electrically connect the target test structure to the testing machine 100.

[0059] In some embodiments, the probe group 330 includes test probes. The test probes are used to contact the test pins 403. The test probes and the test pins 403 are used to electrically connect the test structure and the testing machine 100 to enable the testing machine 100 to complete the test of the chip under test 201.

[0060] In some embodiments, the probe group 330 includes address probes. The address probes are used to contact the address pins 402. The tester 100 selects a target test structure from multiple test structures 205 of the chip under test 201 based on the address information sent by the address probes. In one example, the multiple test structures 205 in the chip under test 201 are arranged in rows and columns. Among them, the test structures 205 in the same row are connected to the same test word line, and the test structures 205 in the same column are connected to the same test bit line. Correspondingly, the address probes include row probes and column probes, and the address pins 402 include row pins and column pins. The row probes contact the row pins to select a target test word line based on the test row address, and the column probes contact the column pins to select a target test bit line based on the test column address. In an application example, the number of row probes and row pins is determined based on the address of the test row address. For example, if the test row address sent by the tester 100 is 4 bits, then 4 row probes and 4 row pins are respectively used to transmit and receive 1-bit test row address. Correspondingly, if the test column address sent by the tester 100 is 4 bits, then 4 column probes and 4 column pins are respectively used to transmit and receive 4-bit test column address.

[0061] For the test of the stacked test structure 200 by the tester 100, first, the test row address and test column address in the stacked test structure 200 are encoded. For example, the test row address corresponding to the first chip under test 201 in the stacked test structure 200 is 0 to 3, and the test row address corresponding to the second chip under test 201 in the stacked test structure 200 is 4 to 7... until the encoding of the test row address and test column address of all chips under test 201 in the stacked test structure 200 is completed. At this time, the tester 100 can accurately select the target chip under test in the stacked test structure 200 and the target test structure in the target chip under test according to the test row address and test column address.

[0062] Continue to refer to Figure 5 , in some embodiments, the test pad array 202 further includes: mode pins 401, and the mode pins 401 are configured to allow the tester 100 to select a target chip under test in the stacked test structure 200.

[0063] In one example, the probe group 330 further includes mode probes. The mode probes contact the mode pins 401 to select a target chip under test in the stacked test structure 200 based on the mode signal, that is, the tester 100 first selects the target chip under test based on the mode signal, and then selects the target test structure in the target chip under test based on the test row address and test column address.

[0064] As can be seen from the foregoing, when the testing machine 100 selects a target test structure in the stacked test structure 200, it is necessary to encode the test word lines and test bit lines of the chips under test 201 in the stacked test structure 200 in sequence. By directly selecting the target chip under test through the mode pin 401, the test word lines and test bit lines of the chip under test 201 can adopt the same encoding, which simplifies the encoding process of the test word lines and test bit lines and indirectly improves the test efficiency.

[0065] Continuing to refer to Figure 5 , in some embodiments, the test pad array further includes: a calibration pin 404, and the calibration pin 404 is configured to verify and calibrate the port voltage of the target test structure.

[0066] In one example, the probe group 330 further includes a calibration probe, and the calibration probe contacts the calibration pin 404 to verify and calibrate the port voltage of the target test structure, so as to ensure the accuracy of the test result.

[0067] In Figure 5 On the basis of the example, this embodiment also proposes a strategy for simplifying the number of address probes and address pins 402. Refer to Figure 6 , Figure 6 FIG. is a schematic structural diagram corresponding to the test pad array and the test structure with an address recognition circuit provided in this embodiment. In some embodiments, the chip under test 201 further includes an address recognition circuit 601. The address recognition circuit 601 is electrically connected to the address pin 402, and the address recognition circuit 601 is configured to generate an address signal based on the address pulse issued by the testing machine 100.

[0068] The address recognition circuit 601 generates a corresponding address signal based on the number of address pulses issued by the testing machine 100. For a 4-bit address, if the address recognition circuit 601 receives 1 address pulse, it generates the address "0001"; if the address recognition circuit 601 receives 2 address pulses, it generates the address "0010"... Through the recognition function of the address recognition circuit 601, the address issued by the testing machine 100 is replaced with an issued address pulse, and the address pulse can be transmitted and received based on the same address probe and address pin 402, which simplifies the number of probes in the testing machine 100 and the number of pins in the chip under test 201.

[0069] Refer to Figure 7 , Figure 7The structure and working principle diagram of the address recognition circuit provided in this embodiment. In some embodiments, the address recognition circuit 601 includes cascaded multi-stage flip-flops. Among them, the input terminal D of each stage of flip-flop is connected to the inverted output terminal Q-, and the output terminal Q is used to output one bit of the address signal; the clock terminal Clk of the non-first-stage and non-last-stage flip-flops is connected to the inverted output terminal of the previous-stage flip-flop; the clock terminal Clk of the first-stage flip-flop is connected to the address pin (PAD, corresponding to Figure 6 in 402), and the inverted output terminal Q- of the last-stage flip-flop is left floating; the output of the output terminal Q of the cascaded multi-stage flip-flops and the data constitute the address signal.

[0070] It should be noted that Figure 7 the number of cascaded stages of the flip-flops shown does not limit this embodiment. In specific applications, the number of cascaded stages of the flip-flops is determined based on the number of bits of the address signal to be generated, where the number of cascaded stages of the flip-flops is greater than or equal to the number of bits of the address signal to be generated.

[0071] In some embodiments, if the address signal for the test system 10 to select the test structure is 5 bits, refer to Figure 7, when the address pin 402 does not receive an address pulse (clock pulse), the output Q of the first-stage flip-flop outputs "0" (D0 = 0, and the corresponding address signal is "00000" at this time), and the inverted output Q- outputs "1". When the address pin 402 receives the 1st address pulse (clock pulse), since the input D of the first-stage flip-flop is connected to the inverted output Q-, the output Q of the first-stage flip-flop outputs "1" based on the data of the input D at this time (D0 = 1, and the corresponding address signal is "00001" at this time). For non-first-stage flip-flops, when the clock terminal Clk does not receive a high level, the output Q of the flip-flop outputs "0", and the inverted output Q- outputs "1". When the clock terminal Clk receives a high level (i.e., the carry signal generated by the output of the previous-stage flip-flop transitioning from "1" to "0"), since the input D of the flip-flop is connected to the inverted output Q-, the output Q of the first-stage flip-flop outputs "1" based on the data of the input D at this time; at this time, the cascaded flip-flops can be regarded as binary counting of the address pulses to correspondingly generate the corresponding address signals. Specifically, when the address pin 402 receives the 2nd address pulse (clock pulse), since the input D of the first-stage flip-flop is connected to the inverted output Q-, the output Q of the first-stage flip-flop outputs "0" based on the data of the input D at this time (D0 = 0), and the inverted output Q- of the first-stage flip-flop outputs "1" to drive the clock terminal Clk of the second-stage flip-flop. Since the input D of the second-stage flip-flop is connected to the inverted output Q-, the output Q of the second-stage flip-flop outputs "1" based on the data of the input D at this time (D1 = 1, and the corresponding address signal is "00010" at this time). Similarly, when the address pin 402 receives the 4th address pulse (clock pulse), the output Q of the third-stage flip-flop outputs "1" based on the data of the input D (D2 = 1, and the corresponding address signal is "00100" at this time); when the address pin 402 receives the 8th address pulse (clock pulse), the output Q of the fourth-stage flip-flop outputs "1" based on the data of the input D (D3 = 1, and the corresponding address signal is "01000" at this time); when the address pin 402 receives the 16th address pulse (clock pulse), the output Q of the fifth-stage flip-flop outputs "1" based on the data of the input D (D4 = 1, and the corresponding address signal is "10000" at this time).

[0072] Reference Figure 8 and Figure 9 , Figure 8 is the circuit diagram connecting the test pad array provided in this embodiment to the test structure, Figure 9Schematic diagram of the control principle of the test structure provided in this embodiment. In some embodiments, the test pins include a source signal terminal (Sense_S) 502, a drain signal terminal (Sense_D) 506, a gate signal terminal (Sense_G) 504, a substrate signal terminal (Bulk) 507, a source calibration terminal (Force_S) 501, a drain calibration terminal (Force_D) 505, and a gate calibration terminal (Force_G) 503. The test structure includes a test transistor 520. Among them, the gate of the test transistor 520 is electrically connected to the gate signal terminal (Sense_G) 504 and the gate calibration terminal (Force_G) 503. The source of the test transistor 520 is electrically connected to the source signal terminal (Sense_S) 502 and the source calibration terminal (Force_S) 501. The drain of the test transistor 520 is electrically connected to the drain signal terminal (Sense_D) 506 and the drain calibration terminal (Force_D) 505. The substrate of the test transistor 520 is electrically connected to the substrate signal terminal (Bulk) 507.

[0073] In some embodiments, the test transistor 520 is electrically connected to the test pins 403 based on an address switch; among them, the address switch is electrically connected to the address pins 402. It should be noted that if the test pad array 202 further includes calibration pins 404, the test transistor 520 is electrically connected to the test pins 403 and the calibration pins 404 based on an address switch.

[0074] In one example, the address pins 402 include row pins and column pins, and the address switch includes a first switch (K11, K21, K12, and K22) and a second switch (K31, K32, K33, and K34); the source of the test transistor 520 is electrically connected to the source signal terminal (Sense_S) 502 and the source calibration terminal (Force_S) 501 based on the first switch; the drain of the test transistor 520 is electrically connected to the drain signal terminal (Sense_D) 506 and the drain calibration terminal (Force_D) 505 based on the first switch; the gate of the test transistor 520 is electrically connected to the gate signal terminal (Sense_G) 504 and the gate calibration terminal (Force_G) 503 based on the second switch; the first switch is electrically connected to the column pins, and the second switch is electrically connected to the row pins. Among them, the first switch is driven based on the test row address EN_G, and the second switch is driven based on the test column address EN_D.

[0075] Reference Figure 10 , Figure 10 Schematic diagram of the device where the test pad array and the test structure are connected provided in this embodiment. In some embodiments, the test structure 205 is electrically connected to the test pad array 202 based on a transmission line; among them, the transmission line is arranged based on the parallel running of the back-end metal of the chip under test 201.

[0076] In one example, the test structure 205 forms parallel traces based on the first metal layer M1, the second metal layer M2, the third metal layer M3, …, and the top metal layer TM to connect to the target pads pad in the test pad array 202. Assuming the resistance of the first metal layer M1 is R1, the resistance of the second metal layer M2 is R2, the resistance of the third metal layer M3 is R3, …, and the resistance of the top metal layer TM is Rx, the resistance between the test structure 205 and the target pad is R1 / / R2 / / R3 / / … / / Rx at this time, which greatly reduces the resistance of the transmission line and ensures the accuracy of the test.

[0077] For the test system 10 provided in this embodiment, the tester 100 is used to perform parallel tests on multiple stacked test structures 200, so as to perform parallel tests on the chips under test 201 in the multiple stacked test structures 200, thereby improving the test efficiency of integrated circuit testing. In addition, by directly selecting the target chip under test through the mode pin 401, the test word lines and test bit lines of the chip under test 201 can adopt the same encoding, which simplifies the encoding process of the test word lines and test bit lines and indirectly improves the test efficiency.

[0078] It should be noted that, without conflict, the features disclosed in the test systems provided in the above embodiments can be randomly combined to obtain new embodiments of the test system.

[0079] Another embodiment of the present disclosure further provides a test method, including: the tester selects a target chip under test in the stacked test structure based on an enable signal; the tester selects a target test structure in the target chip under test based on an address signal; the tester completes the test based on the target test structure.

[0080] The test method provided in this embodiment will be described below in conjunction with the accompanying drawings. It should be noted that for the same or corresponding parts in the foregoing embodiments, reference may be made to the corresponding descriptions in the foregoing embodiments, which will not be repeated below.

[0081] Reference Figure 11 , Figure 11 is the schematic flow diagram corresponding to each step in the test method provided in this embodiment.

[0082] The test method provided in this embodiment includes steps 701 to 703. In step 701, the tester selects a target chip under test in the stacked test structure based on an enable signal; in step 702, the tester selects a target test structure in the target chip under test based on an address signal; in step 703, the tester completes the test based on the target test structure.

[0083] For steps 701 and 702, in some embodiments, the probe group 330 includes address probes for contacting the address pins 402. The tester 100 selects a target test structure from among multiple test structures 205 in the chip under test 201 based on the address information sent by the address probes. In one example, the multiple test structures 205 in the chip under test 201 are arranged in rows and columns; among them, the test structures 205 in the same row are connected to the same test word line, and the test structures 205 in the same column are connected to the same test bit line. Correspondingly, the address probes include row probes and column probes, and the address pins 402 include row pins and column pins. The row probes contact the row pins to select the target test word line based on the test row address, and the column probes contact the column pins to select the target test bit line based on the test column address. In one application example, the number of row probes and row pins is determined based on the address of the test row address. For example, if the test row address sent by the tester 100 is 4 bits, then 4 row probes and 4 row pins are respectively used to transmit and receive 1-bit test row address; correspondingly, if the test column address sent by the tester 100 is 4 bits, then 4 column probes and 4 column pins are respectively used to transmit and receive 4-bit test column address. First, the test row address and test column address in the stacked test structure 200 are encoded. For example, the test row address corresponding to the first chip under test 201 in the stacked test structure 200 is 0 to 3, and the test row address corresponding to the second chip under test 201 in the stacked test structure 200 is 4 to 7... until the encoding of the test row address and test column address of all chips under test 201 in the stacked test structure 200 is completed. At this time, the tester 100 can accurately select the target chip under test in the stacked test structure 200 and the target test structure in the target chip under test according to the test row address and test column address.

[0084] In some embodiments, the test pad array 202 further includes: mode pins 401 configured to allow the tester 100 to select a target chip under test in the stacked test structure 200. The probe group 330 further includes mode probes that contact the mode pins 401 to select a target chip under test in the stacked test structure 200 based on the mode signal. That is, the tester 100 first selects the target chip under test based on the mode signal, and then selects the target test structure in the target chip under test based on the test row address and test column address.

[0085] In some embodiments, the chip under test further includes an address recognition circuit electrically connected to the address pins and configured to generate an address signal based on the address pulse sent by the tester. The method for the tester to select a target test structure in the target chip under test based on the address signal includes: the tester provides an address pulse; the address recognition circuit decodes the address pulse to generate an address signal; the target chip under test selects the target test structure based on the address signal.

[0086] Specifically, the chip 201 to be tested further includes an address recognition circuit 601. The address recognition circuit 601 is electrically connected to the address pin 402 and is configured to generate an address signal based on the address pulses issued by the tester 100. The address recognition circuit 601 generates corresponding address signals based on the number of address pulses issued by the tester 100. For a 4-bit address, if the address recognition circuit 601 receives 1 address pulse, it generates the address "0001"; if the address recognition circuit 601 receives 2 address pulses, it generates the address "0010"... Through the recognition function of the address recognition circuit 601, the address issued by the tester 100 is replaced with address pulses, and the address pulses can be transmitted and received based on the same address probe and the address pin 402, which simplifies the number of probes in the tester 100 and the number of pins in the chip 201 to be tested.

[0087] In the above embodiments, the descriptions of the various embodiments have their own emphases. For the parts not detailed in a certain embodiment, reference may be made to the detailed descriptions of other embodiments above, and details will not be repeated here.

[0088] The basic concepts have been described above. Obviously, for those skilled in the art, the above detailed disclosure is only an example and does not constitute a limitation to this application. Although not explicitly stated here, those skilled in the art may make various modifications, improvements, and corrections to this application. Such modifications, improvements, and corrections are proposed in this application, so such modifications, improvements, and corrections still fall within the spirit and scope of the exemplary embodiments of this application.

[0089] The above has introduced in detail a test system and a test method provided by the embodiments of this application. Specific examples are used in this article to elaborate on the principle and implementation manner of this application. The descriptions of the above embodiments are only used to help understand the method and its core idea of this application; at the same time, for those skilled in the art, according to the idea of this application, there will be changes in the specific implementation manner and application scope. In summary, the content of this specification should not be construed as a limitation to this application.

Claims

1. A test system, characterized in that, Comprising: A testing machine, and a stacked test structure formed by stacking a plurality of chips to be tested; Each of the chips to be tested includes: a test pad array, and in the stacked test structure, the test pad arrays between different chips to be tested are correspondingly electrically connected; The testing machine performs parallel testing on the stacked test structure based on the test pad array of any one of the chips to be tested.

2. The test system according to claim 1, wherein The testing machine includes at least one test unit, and each test unit includes: a test component, a switch component, and a probe group; The probe group connects the test component and the switch component; The switch component is configured to drive corresponding probes in the probe group; When the probe group is electrically connected to the test pad array, the test component is configured to perform testing on the stacked test structure.

3. The test system according to claim 1 or 2, characterized in that, Each of the chips to be tested includes a plurality of test structures, and the test pad array includes address pins and test pins; The test structures are electrically connected to the address pins and the test pins, and a plurality of the test structures are arranged in parallel; The address pins are configured to enable the testing machine to select a target test structure from the plurality of test structures; The test pins are configured to electrically connect the target test structure to the testing machine.

4. The test system according to claim 3, wherein The test pad array further includes: mode pins, which are configured to enable the testing machine to select a target chip to be tested in the stacked test structure.

5. The test system according to claim 3, wherein, The test pad array further includes: calibration pins, which are configured to verify and calibrate the port voltage of the target test structure.

6. The test system according to claim 3, wherein The test pins include a source signal terminal, a drain signal terminal, a gate signal terminal, a substrate signal terminal, a source calibration terminal, a drain calibration terminal, and a gate calibration terminal, and the test structure includes a test transistor; wherein, the gate of the test transistor is electrically connected to the gate signal terminal and the gate calibration terminal, the source of the test transistor is electrically connected to the source signal terminal and the source calibration terminal, the drain of the test transistor is electrically connected to the drain signal terminal and the drain calibration terminal, and the substrate of the test transistor is electrically connected to the substrate signal terminal.

7. The test system according to claim 6, characterized in that, The test transistor is electrically connected to the test pins based on an address switch; wherein, the address switch is electrically connected to the address pins.

8. The test system according to claim 7, wherein The address pins include row pins and column pins, and the address switch includes a first switch and a second switch; The source of the test transistor is electrically connected to the source signal terminal and the source calibration terminal based on the first switch; The drain of the test transistor is electrically connected to the drain signal terminal and the drain calibration terminal based on the first switch; The gate of the test transistor is electrically connected to the gate signal terminal and the gate calibration terminal based on the second switch; The first switch is electrically connected to the column pins, and the second switch is electrically connected to the row pins.

9. The test system according to claim 3, characterized in that, The test structure is electrically connected to the test pad array based on a transmission line; wherein, the transmission line is arranged based on the back-end metal parallel routing of the chip to be tested.

10. The test system according to claim 3, characterized in that, The chip to be tested further includes an address recognition circuit, which is electrically connected to the address pins and is configured to generate an address signal based on an address pulse issued by the testing machine.

11. The test system according to claim 10, characterized in that, The address recognition circuit includes: cascaded multi-stage flip-flops, wherein the input end of each stage of flip-flop is connected to the inverted output end, and the output end is used to output one bit of the address signal; The clock terminals of the non-first-stage and non-last-stage flip-flops are connected to the inverted output terminal of the previous-stage flip-flop; The clock terminal of the first-stage flip-flop is connected to the address pin, and the inverted output terminal of the last-stage flip-flop is left floating; The output data of the cascaded multi-stage flip-flops constitutes the address signal.

12. The test system according to claim 1, wherein The test pad arrays between different chips to be tested are correspondingly electrically connected based on interconnection.

13. A testing method, characterized in that, It includes: The tester selects a target chip to be tested in the stacked test structure based on the enable signal; The tester selects a target test structure in the target chip to be tested based on the address signal; The tester completes the test based on the target test structure.

14. The test method according to claim 13, wherein The chip to be tested further includes an address recognition circuit, electrically connected to the address pin, and configured to generate an address signal based on the address pulse issued by the tester. The method for the tester to select a target test structure in the target chip to be tested based on the address signal includes: The tester provides an address pulse; the address recognition circuit decodes the address pulse to generate an address signal; The target chip to be tested selects the target test structure based on the address signal.

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