A disorderly speculative execution launch queue and electronic device

Abstract

The present invention proposes an out-of-order speculative execution emission queue and electronic device, comprising a write buffer, an overflow area, a main entry area, and a first selector. The write buffer, overflow area, and main entry area are all connected to the first selector, and the write buffer and overflow area are all connected to the main entry area, and the write buffer is also connected to the overflow area. After providing a first type of instruction to the first selector, or when the first direct transmission condition is not met, if the number of valid instructions remaining in the write buffer is greater than or equal to 1, the write buffer is used to send the valid instructions therein to the overflow area and / or the main entry area according to a preset priority rule. The emission queue is divided into three areas: the write buffer, the overflow area, and the main entry area. Each area only needs to find the corresponding instruction as output according to the instruction age, which greatly reduces the logical depth of the entire emission queue age matrix, thereby reducing the difficulty of timing convergence of the emission queue.

Description

Technical Field

[0001] The present invention relates to the field of chips, and in particular to an out-of-order speculative execution transmission queue and an electronic device. Background Art

[0002] In recent years, whether in the high-end consumer electronics field or the server field, more powerful processor cores have become the core competitiveness of major chip companies, such as the M1 chip that has caused a sensation in the industry. High-performance processor cores have two main characteristics: out-of-order execution and superscalar. This type of processor core mainly consists of the following parts: (1) branch prediction module, (2) instruction fetch module, (3) decoding module, (4) renaming module, (5) dispatch module, (6) emission module, (7) execution module, (8) memory access module and (9) reordering module; most high-performance processor cores also have floating-point and vector execution modules. Generally, the operating frequency of high-performance processors is above 2 GHz and the superscalar width is greater than 4.

[0003] In high-performance processor cores, out-of-order speculative execution is a key method for improving performance. The size of the issue queue directly affects the processor's speculative execution capabilities. If the issue queue is too small to match the processor's front-end instruction fetch and execution capabilities, it will become a performance bottleneck for the entire processor. However, due to its logical complexity, increasing the issue queue size while meeting timing constraints at high clock frequencies is difficult. Summary of the Invention

[0004] The object of the present invention is to provide an out-of-order speculative execution launch queue and an electronic device to improve the above-mentioned problem.

[0005] In order to achieve the above objectives, the technical solutions adopted in the embodiments of the present invention are as follows:

[0006] In a first aspect, an embodiment of the present invention provides an out-of-order speculative execution issue queue, comprising: a write cache area, an overflow area, a main entry area, and a first selector; the write cache area, the overflow area, and the main entry area are all connected to the first selector, the write cache area and the overflow area are all connected to the main entry area, and the write cache area is further connected to the overflow area;

[0007] In the current clock cycle, if the number of first-category instructions in the write buffer is greater than the first gap number N1 and the first direct transmission condition is met, the write buffer is used to send the first N1 first-category instructions sorted in descending order of instruction age to the first selector as instructions to be transmitted;

[0008] The first direct-fire condition indicates that the number of first-category instructions provided by the overflow area and the main entry area to the first selector is less than a target number K, the first-category instructions are valid instructions without any hazards, and the first gap number N1 is the difference between the target number K and the number of first-category instructions provided by the overflow area and the main entry area to the first selector in the current clock cycle.

[0009] If the number of first-category instructions in the write cache is less than or equal to the first gap number N1, the write cache is used to send all first-category instructions therein to the first selector as instructions to be issued;

[0010] After providing the first type of instructions to the first selector, or when the first direct transmission condition is not met, if the number of valid instructions remaining in the write cache area is greater than or equal to 1, the write cache area is used to send the valid instructions therein to the overflow area and / or the main entry area according to a preset priority rule.

[0011] Optionally, if all secondary entries in the overflow area are in an idle state, and the number M of idle main entries in the main entry area is greater than or equal to the number of valid instructions remaining in the write cache area, the write cache area is used to send all valid instructions therein to the main entry area;

[0012] If all secondary entries in the overflow area are in an idle state, and the number M of idle main entries in the main entry area is less than the number of valid instructions remaining in the write cache area, the write cache area is used to send the first M valid instructions sorted in descending order of instruction age to the main entry area, and send the remaining valid instructions in the write cache area to the overflow area;

[0013] If any secondary entry in the overflow area is in an occupied state, and the number L of idle secondary entries in the overflow area is greater than or equal to the number of valid instructions remaining in the write cache area, the write cache area is used to send all valid instructions therein to the overflow area;

[0014] If the number L of idle secondary entries in the overflow area is less than the number of valid instructions remaining in the write cache area, the write cache area is used to send the first L valid instructions sorted in descending order of instruction age to the overflow area.

[0015] Optionally, the write cache area includes K cache entries, and the K cache entries are all connected to the first selector;

[0016] The external module is used to write instructions into the write cache area according to a pre-configured write rule, wherein the write rule is that the instruction ages of the instructions stored in the K cache entries increase in sequence;

[0017] After the write cache area completes the instruction outgoing work of the current clock cycle, if there are still valid instructions remaining in the write cache area, the write cache area is used to adjust the cache entries storing the remaining valid instructions according to the write rule.

[0018] Optionally, in the current clock cycle, if the number of first-category instructions in the overflow area is greater than the second gap number N2 and the second direct-issuance condition is met, the overflow area is used to send the first N2 first-category instructions sorted in descending order of instruction age to the first selector as instructions to be issued;

[0019] The second direct-issue condition indicates that the number of first-category instructions provided by the main entry area to the first selector is less than the target number K, and the second gap number N2 is the difference between the target number K and the number of first-category instructions provided by the main entry area to the first selector in the current clock cycle;

[0020] If the number of first-category instructions in the overflow area is less than or equal to the second gap number N2, the overflow area is used to send all first-category instructions therein to the first selector as instructions to be issued;

[0021] After providing the first type of instructions to the first selector, or when the second direct sending condition is not met, if the number of remaining valid instructions in the overflow area is greater than or equal to 1, the overflow area is used to send the valid instructions therein to the main entry area according to a preset priority rule.

[0022] Optionally, if the number M of idle main entries in the main entry area is greater than or equal to the target number K, and the number of remaining valid instructions in the overflow area is greater than or equal to the target number K, the overflow area is used to send the first K valid instructions sorted in descending order of instruction age to the main entry area;

[0023] If the number M of idle main entries in the main entry area is greater than or equal to the target number K, and the number of remaining valid instructions in the overflow area is less than the target number K, the overflow area is used to send all valid instructions therein to the main entry area;

[0024] If the number M of idle main entries in the main entry area is less than the target number K, and the number of remaining valid instructions in the overflow area is greater than or equal to the number M of idle main entries in the main entry area, the overflow area is used to send the first M valid instructions sorted in descending order of instruction age to the main entry area;

[0025] If the number M of idle main entries in the main entry area is less than the target number K, and the number of remaining valid instructions in the overflow area is less than the number M of idle main entries in the main entry area, the overflow area is used to send all valid instructions therein to the main entry area.

[0026] Optionally, the overflow area includes a second selector, a first age matrix, and a plurality of secondary entries;

[0027] The kth input terminal of the second selector is connected to the output terminal of the kth cache entry in the write cache area, each output terminal of the second selector is connected to the input terminal of a corresponding secondary entry, the output terminals of the plurality of secondary entries are all connected to the first age matrix, and the output terminals of the first age matrix are respectively connected to the first selector and the main entry area;

[0028] When it is necessary to store a valid instruction in the kth cache entry in the write cache area into the overflow area, the second selector is configured to connect the kth input terminal thereof to the output terminal connected to any secondary entry in an idle state;

[0029] The first age matrix is ​​used to obtain the overflow area writing time and hazard check information of the valid instruction stored in the secondary entry, the overflow area writing time corresponds to the instruction age, and the hazard check information is used to indicate whether the valid instruction has a hazard;

[0030] When the second direct sending condition is met, the first age matrix is ​​further used to send the corresponding first type of instructions in the overflow area to the first selector according to the overflow area writing time;

[0031] In the case where the valid instructions in the overflow area need to be stored in the main entry area, the first age matrix is ​​further used to send the corresponding valid instructions in the overflow area to the main entry area according to the overflow area write time.

[0032] Optionally, in the current clock cycle, if the number of first-category instructions in the main entry area is greater than or equal to a target number K, the main entry area is used to send first K first-category instructions sorted in descending order of instruction age to the first selector as instructions to be issued;

[0033] If the number of the first category instructions in the main entry area is less than the target number K, the main entry area is used to send all the first category instructions therein to the first selector as instructions to be issued.

[0034] Optionally, the main entry area includes a third selector, a second age matrix, and a plurality of main entries;

[0035] The kth input terminal of the third selector is connected to the output terminal of the kth cache entry in the write cache area, the K+kth input terminal of the third selector is connected to the kth output terminal in the overflow area, each output terminal of the third selector is connected to the input terminal of a corresponding main entry, the output terminals of the plurality of main entries are all connected to the second age matrix, and the output terminal of the second age matrix is ​​connected to the first selector;

[0036] When it is necessary to store a valid instruction in the kth cache entry in the write cache area into the main entry area, the kth input terminal of the third selector is connected to an output terminal connected to any main entry in an idle state;

[0037] When it is necessary to store the valid instructions in the overflow area into the main entry area, the third selector is configured to connect the K+kth input terminal thereof to the output terminal connected to any main entry in an idle state;

[0038] The second age matrix is ​​used to obtain the main entry area write time and hazard check information of the valid instructions stored in the main entry;

[0039] The second age matrix is ​​further used to send the corresponding first-category instructions in the main entry area to the first selector according to the writing time of the main entry area.

[0040] Optionally, the cache entries in the write cache area, the secondary entries in the overflow area, and the main entries in the main entry area are all provided with a static field and a dynamic field;

[0041] The static field is used for fixed information corresponding to the instruction, including instruction code, instruction type, source register and destination register;

[0042] The dynamic domain is used for the change information corresponding to the instruction, including risk check information, instruction execution stage information, result storage location information, and validity flag information.

[0043] In a second aspect, an embodiment of the present invention provides an electronic device, comprising: the above-mentioned out-of-order speculative execution transmit queue.

[0044] Compared with the prior art, an embodiment of the present invention provides an out-of-order speculative execution emission queue and electronic device, including a write cache, an overflow area, a main entry area, and a first selector; the write cache, the overflow area, and the main entry area are all connected to the first selector, the write cache and the overflow area are all connected to the main entry area, and the write cache is also connected to the overflow area; in the current clock cycle, if the number of first-category instructions in the write cache is greater than the first gap number N1 and meets the first direct transmission condition, the write cache is used to send the first N1 first-category instructions sorted from largest to smallest according to instruction age to the first selector as instructions to be emitted; if the number of first-category instructions in the write cache is less than or equal to the first gap number N1, the write cache is used to send all first-category instructions therein to the first selector as instructions to be emitted; after providing the first-category instructions to the first selector, or if the first direct transmission condition is not met, if the number of remaining valid instructions in the write cache is greater than or equal to 1, the write cache is used to send the valid instructions therein to the overflow area and / or the main entry area according to a preset priority rule. The transmit queue is divided into three areas: the write cache area, the overflow area, and the main entry area. Each area only needs to find the corresponding instruction as the output according to the instruction age, which greatly reduces the logical depth of the entire transmit queue age matrix, thereby reducing the difficulty of timing convergence of the transmit queue.

[0045] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, preferred embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments. It should be understood that the following drawings only illustrate certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without paying any creative work.

[0047] Figure 1 This is a structural diagram of an out-of-order speculative execution transmit queue provided by an embodiment of the present invention.

[0048] Figure 2 The second structural diagram of the out-of-order speculative execution emission queue provided by an embodiment of the present invention.

[0049] Figure 3 A schematic structural diagram of a third selector provided in an embodiment of the present invention.

[0050] In the figure: 10 - write buffer area; 20 - overflow area; 30 - main entry area; 40 - first selector. DETAILED DESCRIPTION

[0051] To make the objectives, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions of the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings herein can be arranged and designed in various different configurations.

[0052] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention as claimed, but rather merely represents selected embodiments of the present invention. All other embodiments derived by persons of ordinary skill in the art based on the embodiments of the present invention without creative effort shall fall within the scope of protection of the present invention.

[0053] It should be noted that similar reference numerals and letters represent similar items in the following drawings. Therefore, once an item is defined in one drawing, it does not need to be further defined or explained in subsequent drawings. At the same time, in the description of the present invention, the terms "first", "second", etc. are used only to distinguish the description and should not be understood as indicating or implying relative importance.

[0054] It should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply the existence of any such actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or device comprising the element.

[0055] In the description of the present invention, it should be noted that the terms "upper", "lower", "inside", "outside", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, or are the orientations or positional relationships in which the inventive product is usually placed when in use. They are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, they should not be understood as limiting the present invention.

[0056] In the description of the present invention, it should also be noted that, unless otherwise expressly specified or limited, the terms "disposed" and "connected" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integral connections; mechanical connections, or electrical connections; direct connections, indirect connections through an intermediate medium, or internal connections between two components. Those skilled in the art will understand the specific meanings of the above terms in the present invention based on the specific circumstances.

[0057] The following embodiments of the present invention are described in detail with reference to the accompanying drawings. In the absence of conflict, the following embodiments and features in the embodiments may be combined with each other.

[0058] The embodiment of the present invention provides an out-of-order speculative execution launch queue, please refer to Figure 1 , Figure 1 This is a structural diagram of an out-of-order speculative execution transmit queue provided by an embodiment of the present invention.

[0059] The out-of-order speculative execution emission queue includes: a write cache area 10, an overflow area 20, a main entry area 30 and a first selector 40; the write cache area 10, the overflow area 20, the main entry area 30 are all connected to the first selector 40, the write cache area 10, the overflow area 20 are all connected to the main entry area 30, and the write cache area 10 is also connected to the overflow area 20.

[0060] In the current clock cycle, if the number of first-category instructions in the write cache 10 is greater than the first gap number N1 and meets the first direct transmission condition, the write cache 10 is used to send the first N1 first-category instructions sorted from largest to smallest according to instruction age to the first selector 40 as instructions to be transmitted.

[0061] Among them, the first direct condition indicates that the number of first-category instructions provided by the overflow area 20 and the main entry area 30 to the first selector 40 is less than the target number K, the first-category instructions are valid instructions without any risks, the first gap number N1 is the difference between the target number K and the number of first-category instructions provided by the overflow area 20 and the main entry area 30 to the first selector 40 in the current clock cycle, and the instruction age indicates the generation time of the instruction.

[0062] Among them, valid instructions are instructions stored in entries with a valid indicator bit high in the transmit queue. Usually, new instructions are valid when they are written to the transmit queue. When the instruction is successfully transmitted and is not canceled or flushed by the pipeline within the specified cycle, it will become invalid.

[0063] It should be noted that in the figures provided in the embodiments of the present invention, the value of K is 2 as an example, but this is not intended to be limiting; K is greater than or equal to 1. When providing the first category of instructions to the first selector 40, the main entry area 30 has the highest priority, followed by the overflow area 20, and the write cache area 10 has the lowest priority. The first selector 40 then sends the acquired instructions to be issued to the backend module.

[0064] If the number of first-category instructions in the write buffer 10 is less than or equal to the first gap number N1, the write buffer 10 is used to send all first-category instructions therein to the first selector 40 as instructions to be issued.

[0065] After the write cache area 10 provides the first type of instructions to the first selector 40, or when the first direct transmission condition is not met, if the number of valid instructions remaining in the write cache area 10 is greater than or equal to 1, the write cache area 10 is used to send the valid instructions therein to the overflow area 20 and / or the main entry area 30 according to the preset priority rules.

[0066] In the out-of-order speculative execution emission queue provided in an embodiment of the present invention, the emission queue is divided into three areas, namely a write cache area, an overflow area, and a main entry area. Each area only needs to find the corresponding instruction as output according to the instruction age, which greatly reduces the logical depth of the entire emission queue age matrix, thereby reducing the difficulty of timing convergence of the emission queue.

[0067] Based on the foregoing, regarding how the write cache area sends valid instructions therein to the overflow area and / or the main entry area according to a preset priority rule, the embodiment of the present invention also provides an optional implementation method, please refer to the following.

[0068] If all secondary entries in the overflow area 20 are in an idle state (no valid instructions are stored), and the number M of idle main entries in the main entry area 30 is greater than or equal to the number of valid instructions remaining in the write cache area 10, then the write cache area 10 is used to send all valid instructions therein to the main entry area 30.

[0069] If all the secondary entries in the overflow area 20 are in an idle state, and the number M of idle main entries in the main entry area 30 is less than the number of valid instructions remaining in the write cache area 10, the write cache area 10 is used to send the first M valid instructions sorted from large to small according to instruction age to the main entry area 30, and send the remaining valid instructions in the write cache area 10 to the overflow area 20.

[0070] If any secondary entry in the overflow area 20 is in an occupied state, and the number L of idle secondary entries in the overflow area 20 is greater than or equal to the number of valid instructions remaining in the write cache area 10, the write cache area 10 is used to send all valid instructions therein to the overflow area 20.

[0071] If the number L of idle secondary entries in the overflow area 20 is less than the number of valid instructions remaining in the write cache area 10 , the write cache area 10 is used to send the first L valid instructions sorted by age from largest to smallest to the overflow area 20 .

[0072] If there are still valid instructions after the write cache area 10 sends the first L valid instructions sorted by instruction age from largest to smallest to the overflow area 20 , the valid instructions will continue to be stored in the write cache area 10 .

[0073] exist Figure 1 On the basis of the specific structure of the write buffer area, the embodiment of the present invention also provides an optional implementation method, please refer to Figure 2 , Figure 2 The second structural diagram of the out-of-order speculative execution emission queue provided by an embodiment of the present invention.

[0074] The write cache area 10 includes K cache entries, and each of the K cache entries is connected to the first selector 40 .

[0075] The external module is used to write instructions to the write cache area 10 according to a pre-configured write rule, wherein the external module can be a distribution module in the processor, and the write rule is that the instruction age of the instructions stored in the K cache entries increases successively, the instruction age of the instruction stored in the jth cache entry is greater than the instruction age of the instruction stored in the j+1th cache entry, and 1≤j≤K-1.

[0076] After the write cache 10 completes the instruction outgoing work of the current clock cycle, if there are still valid instructions remaining in the write cache 10, the write cache 10 is used to adjust the cache entries storing the remaining valid instructions according to the write rule.

[0077] It should be understood that after the write cache 10 completes the outgoing instruction work for the current clock cycle, the write cache 10 marks the cache entry corresponding to the outgoing instruction as idle. The outgoing instructions in the write cache 10 include instructions sent by the write cache 10 to the first selector 40, instructions sent by the write cache 10 to the overflow area 20, and instructions sent by the write cache 10 to the main entry area 30. At this time, if there are still valid instructions in the write cache 10, the cache entry storing the remaining valid instructions is adjusted according to the write rule. The kth valid instruction in the write cache 10, sorted by instruction age from largest to smallest, is stored in the kth cache entry in the write cache 10, where 1≤k≤K.

[0078] In an embodiment of the present invention, the write cache area 10 accepts input from an external module (such as a distribution module in a processor), and fewer entries means smaller input selection logic, so the existence of the write cache area 10 is also beneficial to the timing convergence of the distribution module.

[0079] Please continue to refer to Figure 1 Regarding the working logic of the overflow area, the embodiment of the present invention also provides an optional implementation method, please refer to the following.

[0080] In the current clock cycle, if the number of first-category instructions in the overflow area 20 is greater than the second gap number N2 and meets the second direct-transmission condition, the overflow area 20 is used to send the first N2 first-category instructions sorted from largest to smallest according to instruction age to the first selector 40 as instructions to be transmitted.

[0081] Among them, the second direct sending condition indicates that the number of first-category instructions provided by the main entry area 30 to the first selector 40 is less than the target number K, and the second gap number N2 is the difference between the target number K and the number of first-category instructions provided by the main entry area 30 to the first selector 40 in the current clock cycle.

[0082] If the number of first-category instructions in the overflow area 20 is less than or equal to the second gap number N2, the overflow area 20 is used to send all first-category instructions therein to the first selector 40 as instructions to be issued.

[0083] After the overflow area 20 provides the first type of instructions to the first selector 40, or when the second direct sending condition is not met, if the number of remaining valid instructions in the overflow area 20 is greater than or equal to 1, the overflow area 20 is used to send the valid instructions therein to the main entry area 30 according to the preset priority rules.

[0084] Based on the foregoing, regarding how the overflow area sends valid instructions therein to the main entry area according to a preset priority rule, the embodiment of the present invention further provides an optional implementation method, which is described below.

[0085] If the number M of idle main entries in the main entry area 30 is greater than or equal to the target number K, and the number of remaining valid instructions in the overflow area 20 is greater than or equal to the target number K, then the overflow area 20 is used to send the first K valid instructions sorted from largest to smallest according to instruction age to the main entry area 30.

[0086] If the number M of idle main entries in the main entry area 30 is greater than or equal to the target number K, and the number of remaining valid instructions in the overflow area 20 is less than the target number K, then the overflow area 20 is used to send all valid instructions therein to the main entry area 30, that is, the overflow area 20 is used to send all valid instructions therein to the main entry area 30.

[0087] If the number M of idle main entries in the main entry area 30 is less than the target number K, and the number of remaining valid instructions in the overflow area 20 is greater than or equal to the number M of idle main entries in the main entry area 30, then the overflow area 20 is used to send the first M valid instructions sorted from largest to smallest according to instruction age to the main entry area 30.

[0088] If the number M of idle main entries in the main entry area 30 is less than the target number K, and the number of remaining valid instructions in the overflow area 20 is less than the number M of idle main entries in the main entry area 30, then the overflow area 20 is used to send all valid instructions therein to the main entry area 30, and the overflow area 20 is used to send all valid instructions therein to the main entry area 30.

[0089] On the basis of the above, regarding the structure of the overflow area, the embodiment of the present invention also provides an optional implementation method, please continue to refer to Figure 2 .

[0090] The overflow area 20 includes a second selector, a first age matrix, and a plurality of secondary entries, wherein the number of secondary entries is greater than a target number K. In the drawings provided in the embodiments of the present invention, the number of secondary entries is 6 as an example, but this is not a limitation. The overflow area may include more or fewer secondary entries.

[0091] The kth input end of the second selector is connected to the output end of the kth cache entry in the write cache area 10, and each output end of the second selector is connected to the input end of the corresponding secondary entry. The output ends of multiple secondary entries are all connected to the first age matrix, and the output ends of the first age matrix are respectively connected to the first selector 40 and the main entry area 30.

[0092] Optionally, the first age matrix has a total of 2K output terminals, the kth output terminal of the first age matrix serves as the kth output terminal in the overflow area 20 , connected to the K+kth input terminal of the main entry area 30 , and the K+kth output terminal of the first age matrix is ​​connected to the first selector 40 .

[0093] Because the instruction ages of the instructions stored in the K cache entries increase sequentially, the second selector can ensure that instructions with older instruction ages are preferentially written into the secondary entries through its internal conduction relationship.

[0094] When it is necessary to store the valid instruction in the kth cache entry in the write cache area 10 into the overflow area 20, the second selector is used to connect its kth input terminal to the output terminal of any secondary entry in an idle state to store the instruction in the kth cache entry into the secondary entry.

[0095] The first age matrix is ​​used to obtain the overflow area write time and hazard check information of the valid instructions stored in the secondary entries. The overflow area write time corresponds to the instruction age. The earlier the overflow area write time, the older the corresponding instruction age. The hazard check information is used to indicate whether there is a hazard in the valid instruction.

[0096] It should be noted that in the embodiment of the present invention, the age matrix (including the first age matrix and the second age matrix described below) only needs to count the write time corresponding to each valid instruction (including the overflow area write time and the main entry area write time). Compared with counting the instruction age, the method of obtaining the write time is simpler and more conducive to convergence.

[0097] Optionally, when multiple instructions in the write cache area 10 need to be written to the overflow area 20, they are written to the overflow area 20 according to the instruction age (ie, the order of cache entries), so that the earlier the overflow area is written, the older the corresponding instruction age.

[0098] When the second direct sending condition is met, the first age matrix is ​​further used to send the corresponding first type of instructions in the overflow area 20 to the first selector 40 according to the overflow area writing time;

[0099] When valid instructions in the overflow area 20 need to be stored in the main entry area 30 , the first age matrix is ​​further used to send corresponding valid instructions in the overflow area 20 to the main entry area 30 according to the overflow area write time.

[0100] It should be understood that after the overflow area 20 completes the instruction outgoing work of the current clock cycle, the overflow area 20 marks the secondary entry corresponding to the outgoing instruction as idle. The outgoing instructions in the overflow area 20 include the instructions sent by the overflow area 20 to the first selector 40 and the instructions sent by the overflow area 20 to the main entry area 30.

[0101] Please continue to refer to Figure 1 Regarding the working logic of the main entry area, the embodiment of the present invention also provides an optional implementation method, please refer to the following.

[0102] In the current clock cycle, if the number of first-category instructions in the main entry area 30 is greater than or equal to the target number K, the main entry area 30 is used to send the first K first-category instructions sorted from largest to smallest according to instruction age to the first selector 40 as instructions to be issued.

[0103] If the number of the first category instructions in the main entry area 30 is less than the target number K, the main entry area 30 is used to send all the first category instructions therein to the first selector 40 as instructions to be issued.

[0104] Based on the above, regarding the structure of the main entry area, the embodiment of the present invention also provides an optional implementation method, please continue to refer to Figure 2 .

[0105] The main entry area 30 includes a third selector, a second age matrix, and multiple main entries, wherein the number of main entries is greater than a target number K. In the drawings provided in the embodiments of the present invention, the number of main entries is 8 as an example, but this is not a limitation. The main entry area may include more or fewer main entries.

[0106] The kth input terminal of the third selector is connected to the output terminal of the kth cache entry in the write cache area 10, the K+kth input terminal of the third selector is connected to the kth output terminal in the overflow area 20, each output terminal of the third selector is connected to the input terminal of the corresponding main entry, the output terminals of the multiple main entries are all connected to the second age matrix, and the output terminal of the second age matrix is ​​connected to the first selector 40.

[0107] When it is necessary to store the valid instruction in the kth cache entry in the write cache area 10 into the main entry area 30, the third selector is used to connect its kth input terminal to the output terminal of any main entry in an idle state to store the valid instruction in the kth cache entry into the main entry.

[0108] When the valid instructions in the overflow area 20 need to be stored in the main entry area 30, the third selector is used to connect the K+kth input terminal thereof to the output terminal connected to any idle main entry to store the valid instructions in the overflow area 20 in the main entry.

[0109] The second age matrix is ​​used to obtain the main entry area write time and hazard check information of the valid instructions stored in the main entry, wherein the earlier the main entry write time is, the older the corresponding instruction age is.

[0110] Optionally, it should be noted that when multiple instructions need to be written into the main entry area 30, they are written into the main entry area 30 according to the instruction age (i.e., the order of cache entries), so that the earlier the main entry area is written, the older the corresponding instruction age.

[0111] The second age matrix is ​​further used to send the corresponding first-category instructions in the main entry area 30 to the first selector 40 according to the writing time of the main entry area.

[0112] It should be understood that after the main entry area 30 completes the instruction outgoing work of the current clock cycle, the main entry area 30 marks the main entry corresponding to the outgoing instruction as idle. The outgoing instructions in the main entry area 30 include the instructions sent by the main entry area 30 to the first selector 40.

[0113] In an optional embodiment, the third selector may be composed of two cascaded selection units, namely a first selection unit and a second selection unit, as shown in FIG. Figure 3As shown, Figure 3 A schematic structural diagram of a third selector provided in an embodiment of the present invention.

[0114] The kth input end of the first selection unit is connected to the output end of the kth cache entry in the write cache area 10, the K+kth input end of the first selection unit is connected to the kth output end in the overflow area 20, the kth output end of the first selection unit is connected to the kth input end of the second selection unit, and each output end of the second selection unit is connected to the input end of the corresponding main entry.

[0115] The first selection unit is used to switch the kth input terminal and the kth output terminal of the first selection unit to be connected when the write cache area 10 sends an instruction to the main entry area 30, and to switch the K+kth input terminal and the kth output terminal of the first selection unit to be connected when the overflow area 20 sends an instruction to the main entry area 30.

[0116] In the out-of-order speculative execution issue queue provided by the present invention, write control is used to ensure that the age order of the three sub-areas is: all instructions in the main entry area are older than all instructions in the overflow area; all instructions in the overflow area are older than all instructions in the write buffer area; and instructions in the write buffer area are always the youngest. The final output of the entire issue queue is: if the main entry area outputs a valid output, the issue queue output is the main entry output; if the overflow area output is valid and the main entry area has no valid output at the time, the issue queue output is the overflow area output; if the write buffer output is valid and both the main entry area and the overflow area have no valid output at the time, the issue queue output is the write buffer output.

[0117] In an optional embodiment, the cache entries in the write cache area 10, the secondary entries in the overflow area 20, and the main entries in the main entry area 30 are all provided with static fields and dynamic fields;

[0118] The static field is used for fixed information corresponding to the instruction, including instruction encoding, instruction type, source register, destination register, and other information that will not change with the different stages of instruction execution.

[0119] The dynamic domain is used for information that changes with the execution of instructions, including risk check information, instruction execution stage information, result storage location information, and validity flag information, which changes as the instruction is executed.

[0120] By dividing the entries in each sub-region of the transmit queue into static and dynamic domains, and decoupling long-logic-depth and short-logic-depth storage cells, back-end physical implementation can more easily optimize circuit placement, facilitating transmit queue timing closure. Because the static domain's content does not change, the timing closure risk for this portion of the domain is lower. However, information in the dynamic domain is subject to changes in external logic, and much of this information has high logic depth and signal line delays. Therefore, the dynamic domain requires more detailed physical implementation optimization, which is facilitated by separating the dynamic and static domains.

[0121] An embodiment of the present invention further provides an electronic device, comprising: the above-mentioned out-of-order speculative execution transmit queue.

[0122] In summary, an embodiment of the present invention provides an out-of-order speculative execution emission queue and an electronic device, comprising a write cache, an overflow, a main entry, and a first selector; the write cache, the overflow, and the main entry are all connected to the first selector, the write cache and the overflow are both connected to the main entry, and the write cache is also connected to the overflow; in the current clock cycle, if the number of first-category instructions in the write cache is greater than the first gap number N1 and meets the first direct transmission condition, the write cache is used to send the first N1 first-category instructions sorted from largest to smallest according to instruction age to the first selector as instructions to be emitted; if the number of first-category instructions in the write cache is less than or equal to the first gap number N1, the write cache is used to send all first-category instructions therein to the first selector as instructions to be emitted; after providing the first-category instructions to the first selector, or if the first direct transmission condition is not met, if the number of remaining valid instructions in the write cache is greater than or equal to 1, the write cache is used to send the valid instructions therein to the overflow and / or main entry according to a preset priority rule. The transmit queue is divided into three areas: the write cache area, the overflow area, and the main entry area. Each area only needs to find the corresponding instruction as the output according to the instruction age, which greatly reduces the logical depth of the entire transmit queue age matrix, thereby reducing the difficulty of timing convergence of the transmit queue.

[0123] The foregoing description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Those skilled in the art will readily appreciate that various modifications and variations of the present invention are possible. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present invention are intended to be within the scope of protection of the present invention.

[0124] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above and that the invention can be embodied in other specific forms without departing from the spirit or essential characteristics of the invention. Therefore, the embodiments should be considered in all respects as illustrative and non-restrictive, and the scope of the invention is defined by the appended claims, not the foregoing description, and all variations within the meaning and range of equivalents of the claims are intended to be included therein. Any reference sign in a claim should not be construed as limiting the claim to which it relates.

Claims

1. An electronic device, characterized in that: The electronic device includes an out-of-order speculative execution transmit queue, the out-of-order speculative execution transmit queue including: a write buffer area, an overflow area, a main entry area, and a first selector; the write buffer area, the overflow area, and the main entry area are all connected to the first selector, the write buffer area and the overflow area are all connected to the main entry area, and the write buffer area is also connected to the overflow area; In the current clock cycle, if the number of first-category instructions in the write buffer is greater than the first gap number N1 and the first direct transmission condition is met, the write buffer is used to send the first N1 first-category instructions sorted in descending order of instruction age to the first selector as instructions to be transmitted; The first direct-fire condition indicates that the number of first-category instructions provided by the overflow area and the main entry area to the first selector is less than a target number K, the first-category instructions are valid instructions without any hazards, and the first gap number N1 is the difference between the target number K and the number of first-category instructions provided by the overflow area and the main entry area to the first selector in the current clock cycle. If the number of first-category instructions in the write cache is less than or equal to the first gap number N1, the write cache is used to send all first-category instructions therein to the first selector as instructions to be issued; After the write cache area provides the first type of instruction to the first selector, or when the first direct transmission condition is not satisfied, if the number of valid instructions remaining in the write cache area is greater than or equal to 1, the write cache area is configured to send the valid instructions therein to the overflow area and / or the main entry area according to a preset priority rule; The overflow region includes a second selector, a first age matrix, and a plurality of secondary entries; The kth input terminal of the second selector is connected to the output terminal of the kth cache entry in the write cache area, each output terminal of the second selector is connected to the input terminal of a corresponding secondary entry, the output terminals of the plurality of secondary entries are all connected to the first age matrix, and the output terminals of the first age matrix are respectively connected to the first selector and the main entry area; When it is necessary to store a valid instruction in the kth cache entry in the write cache area into the overflow area, the second selector is configured to connect the kth input terminal thereof to the output terminal connected to any secondary entry in an idle state; The first age matrix is ​​used to obtain the overflow area writing time and hazard check information of the valid instructions stored in the secondary entries. The overflow area writing time corresponds to the instruction age. The hazard check information is used to indicate whether the valid instructions have hazards.

2. The electronic device according to claim 1, wherein If all secondary entries in the overflow area are in an idle state, and the number M of idle main entries in the main entry area is greater than or equal to the number of valid instructions remaining in the write cache area, the write cache area is used to send all valid instructions therein to the main entry area; If all secondary entries in the overflow area are in an idle state, and the number M of idle main entries in the main entry area is less than the number of valid instructions remaining in the write cache area, the write cache area is used to send the first M valid instructions sorted in descending order of instruction age to the main entry area, and send the remaining valid instructions in the write cache area to the overflow area; If any secondary entry in the overflow area is in an occupied state, and the number L of idle secondary entries in the overflow area is greater than or equal to the number of valid instructions remaining in the write cache area, the write cache area is used to send all valid instructions therein to the overflow area; If the number L of idle secondary entries in the overflow area is less than the number of valid instructions remaining in the write cache area, the write cache area is used to send the first L valid instructions sorted in descending order of instruction age to the overflow area.

3. The electronic device according to claim 1, wherein The write cache area includes K cache entries, and the K cache entries are all connected to the first selector; The external module is used to write instructions into the write cache area according to a pre-configured write rule, wherein the write rule is that the instruction ages of the instructions stored in the K cache entries increase in sequence; After the write cache area completes the instruction outgoing work of the current clock cycle, if there are still valid instructions remaining in the write cache area, the write cache area is used to adjust the cache entries storing the remaining valid instructions according to the write rule.

4. The electronic device according to claim 1, wherein In the current clock cycle, if the number of first-category instructions in the overflow zone is greater than the second gap number N2 and the second direct-issuance condition is met, the overflow zone is used to send the first N2 first-category instructions sorted in descending order of instruction age to the first selector as instructions to be issued; The second direct-issue condition indicates that the number of first-category instructions provided by the main entry area to the first selector is less than the target number K, and the second gap number N2 is the difference between the target number K and the number of first-category instructions provided by the main entry area to the first selector in the current clock cycle; If the number of first-category instructions in the overflow area is less than or equal to the second gap number N2, the overflow area is used to send all first-category instructions therein to the first selector as instructions to be issued; After the overflow area provides the first type of instructions to the first selector, or when the second direct sending condition is not met, if the number of remaining valid instructions in the overflow area is greater than or equal to 1, the overflow area is used to send the valid instructions therein to the main entry area according to a preset priority rule.

5. The electronic device according to claim 4, wherein: If the number M of idle main entries in the main entry area is greater than or equal to the target number K, and the number of remaining valid instructions in the overflow area is greater than or equal to the target number K, the overflow area is used to send the first K valid instructions sorted in descending order of instruction age to the main entry area; If the number M of idle main entries in the main entry area is greater than or equal to the target number K, and the number of remaining valid instructions in the overflow area is less than the target number K, the overflow area is used to send all valid instructions therein to the main entry area; If the number M of idle main entries in the main entry area is less than the target number K, and the number of remaining valid instructions in the overflow area is greater than or equal to the number M of idle main entries in the main entry area, the overflow area is used to send the first M valid instructions sorted in descending order of instruction age to the main entry area; If the number M of idle main entries in the main entry area is less than the target number K, and the number of remaining valid instructions in the overflow area is less than the number M of idle main entries in the main entry area, the overflow area is used to send all valid instructions therein to the main entry area.

6. The electronic device according to claim 1, wherein When the second direct sending condition is met, the first age matrix is ​​further used to send the corresponding first type of instructions in the overflow area to the first selector according to the overflow area writing time; The second direct sending condition indicates that the number of first-category instructions provided by the main entry area to the first selector is less than the target number K; In the case where the valid instructions in the overflow area need to be stored in the main entry area, the first age matrix is ​​further used to send the corresponding valid instructions in the overflow area to the main entry area according to the overflow area write time.

7. The electronic device according to claim 1, wherein: In a current clock cycle, if the number of first-category instructions in the main entry area is greater than or equal to a target number K, the main entry area is used to send first K first-category instructions sorted in descending order of instruction age to the first selector as instructions to be issued; If the number of the first category instructions in the main entry area is less than the target number K, the main entry area is used to send all the first category instructions therein to the first selector as instructions to be issued.

8. The electronic device according to claim 1, wherein The main entry area includes a third selector, a second age matrix, and a plurality of main entries; The kth input terminal of the third selector is connected to the output terminal of the kth cache entry in the write cache area, the K+kth input terminal of the third selector is connected to the kth output terminal in the overflow area, each output terminal of the third selector is connected to the input terminal of a corresponding main entry, the output terminals of the plurality of main entries are all connected to the second age matrix, and the output terminal of the second age matrix is ​​connected to the first selector; When it is necessary to store a valid instruction in the kth cache entry in the write cache area into the main entry area, the kth input terminal of the third selector is connected to an output terminal connected to any main entry in an idle state; When it is necessary to store the valid instructions in the overflow area into the main entry area, the third selector is configured to connect the K+kth input terminal thereof to the output terminal connected to any main entry in an idle state; The second age matrix is ​​used to obtain the main entry area write time and hazard check information of the valid instructions stored in the main entry; The second age matrix is ​​further used to send the corresponding first-category instructions in the main entry area to the first selector according to the writing time of the main entry area.

9. The electronic device according to claim 1, wherein: The cache entries in the write cache area, the secondary entries in the overflow area, and the main entries in the main entry area are all provided with a static field and a dynamic field; The static field is used for fixed information corresponding to the instruction, including instruction code, instruction type, source register and destination register; The dynamic domain is used for the change information corresponding to the instruction, including risk check information, instruction execution stage information, result storage location information, and validity flag information.

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