Flip chip ball grid array heat sink structure and preparation method thereof

Abstract

The present application discloses a heat sink structure for a flip-chip ball grid array (BGA) and a method for making the same, relating to the field of semiconductor technology. The heat sink structure for the flip-chip BGA includes a substrate, a first chip, a heat sink cover, and a second chip. The substrate is provided with a solder pad. The first chip is flip-mounted on the substrate and electrically connected to the substrate. The heat sink cover is provided above the first chip. The second chip is mounted directly above the heat sink cover and electrically connected to the solder pad via wire bonding. The heat sink structure for the flip-chip BGA and the method for making the same can reduce package size, reduce the amount of substrate wiring, avoid parasitic effects and capacitance effects between substrate wiring layers, and ensure device performance.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a heat sink structure for a flip-chip ball grid array and a preparation method thereof. Background Art

[0002] With the rapid development of the semiconductor industry, flip chip-ball grid array (FC-BGA) packaging products are used in system-in-package (SIP). Flip chip bumps are usually used to provide a higher-density input / output (I / O) interface layout. This packaging technology reduces the area by 30% to 60% compared to traditional packaging. However, improving product performance requires integrating more chips and passive components, so its heat dissipation performance needs to be improved.

[0003] In conventional technology, heat dissipation is usually achieved by mounting a heat sink cover, and chips and passive components are arranged under the heat sink cover in a planar layout. However, as the number of integrated chips and passive components increases, the design size of the heat sink cover will inevitably increase and the number of substrate wiring layers will increase, which is not conducive to the miniaturization of the device. At the same time, it is easy to cause parasitic effects and capacitance effects between the substrate wiring layers, affecting the performance of the device. Summary of the Invention

[0004] The purpose of this application is to provide a heat sink structure for a flip-chip ball grid array and a preparation method thereof, which can reduce the package size, reduce the number of substrate wirings, avoid parasitic effects and capacitance effects between substrate wiring layers, and ensure device performance.

[0005] The embodiment of the present application is implemented as follows:

[0006] According to a first aspect of an embodiment of the present application, a heat sink structure for a flip-chip ball grid array is provided, comprising a substrate, a first chip, a heat dissipation cover, and a second chip. A solder pad is provided on the substrate, the first chip is flip-chip mounted on the substrate and electrically connected to the substrate, the heat dissipation cover is provided above the first chip, the second chip is mounted above the heat dissipation cover, and the second chip is electrically connected to the solder pad via bonding wires.

[0007] As an implementation method, the heat dissipation cover is provided on a surface of the first chip facing away from the substrate, and the second chip is mounted on a surface of the heat dissipation cover facing away from the first chip.

[0008] As an implementation method, a hollow structure is provided on the heat dissipation cover, and the hollow structure is sleeved on the first chip. The second chip is mounted on the surface of the first chip facing away from the substrate through a fixing adhesive layer.

[0009] As an implementation method, the number of the second chip is at least one. When the number of the second chip is multiple, the multiple second chips are distributed in the middle and edge of the heat dissipation cover.

[0010] As an implementation method, a plurality of heat dissipation fins are provided on the heat dissipation cover. When there are multiple second chips, the plurality of heat dissipation fins are distributed between two adjacent second chips.

[0011] As an implementation method, the plurality of heat dissipation fins are distributed along a surface of the heat dissipation cover close to the first chip and / or the plurality of heat dissipation fins are distributed along a surface of the heat dissipation cover away from the first chip.

[0012] As an embodiment, when there are multiple second chips and multiple heat sinks are distributed along the surface of the heat sink cover facing away from the first chip, the vertical distance between the end of at least one heat sink facing away from the heat sink cover and the surface of the substrate is greater than the vertical distance between the surface of the second chip facing away from the heat sink cover and the surface of the substrate.

[0013] As an implementation method, when the plurality of heat dissipation fins are distributed along the surface of the heat dissipation cover close to the first chip, ends of the plurality of heat dissipation fins facing away from the heat dissipation cover all extend toward a side close to the substrate.

[0014] As an implementation method, a first protective adhesive layer is provided on the bottom of the first chip, and an end portion of at least one of the heat dissipation fins facing away from the heat dissipation cover is in contact with the first protective adhesive layer.

[0015] As an implementation manner, an end portion of at least one of the heat dissipation fins facing away from the heat dissipation cover contacts the surface of the substrate.

[0016] As an implementation method, a third chip is further included, and the heat dissipation cover includes a cover body portion, a connecting portion and a support leg portion connected in sequence, and the angle between the cover body portion and the connecting portion and the angle between the support leg portion and the connecting portion are obtuse angles, and the third chip is arranged on the connecting portion.

[0017] As an implementation method, a conductive hole is provided on the connecting portion, the third chip is flip-chip mounted on a surface of the connecting portion close to the substrate, and the third chip is electrically connected to the second chip through the conductive hole.

[0018] As an implementation method, it further includes a fourth chip, which is flip-chip mounted on the surface of the heat dissipation cover close to the substrate, and the fourth chip is distributed on the edge of the heat dissipation cover, and the fourth chip is electrically connected to the substrate through bumps.

[0019] As an implementation method, the number of the bonding wires and the bumps is at least two, and at least one bonding wire is distributed between two adjacent bumps.

[0020] As an implementation method, a plastic package body is further included, and the plastic package body is arranged on the substrate and covers the first chip, the heat dissipation cover and the second chip.

[0021] According to a second aspect of the embodiments of the present application, a method for preparing a heat sink structure of a flip chip ball grid array is provided, which is used to prepare the heat sink structure of the flip chip ball grid array.

[0022] The beneficial effects of the embodiments of the present application include:

[0023] The flip-chip ball grid array heat sink structure includes a substrate, a first chip, a heat dissipation cover, and a second chip. The substrate is provided with solder pads. The first chip is flip-mounted on the substrate and electrically connected to the substrate. The heat dissipation cover is disposed above the first chip. The second chip is mounted upright on the heat dissipation cover and electrically connected to the solder pads via wire bonding. Compared to the prior art, the flip-chip ball grid array heat sink structure provided by the present application replaces the traditional planar layout method where all chips and passive components are located on the substrate surface by mounting the first chip on the substrate and the second chip on the heat dissipation cover. This three-dimensional layout effectively utilizes space, reduces the mounting area on the substrate surface, and makes the entire package more compact, thereby facilitating device miniaturization. Even if the number of integrated chips and passive components increases, the overall size does not increase significantly as in traditional methods. Furthermore, because the second chip is disposed above the heat dissipation cover, rather than on the substrate like the first chip, the flip-chip ball grid array heat sink structure provided by the present application reduces the number of chips that need to be connected on the substrate, thereby reducing the amount of wiring on the substrate. Reducing the number of wirings can reduce parasitic effects and capacitance effects between substrate wiring layers, which can reduce interference to signals during transmission, thereby improving device performance and enhancing its stability and reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without creative work.

[0025] Figure 1 A schematic structural diagram of a heat sink structure for a flip chip ball grid array provided in the first embodiment of the present application;

[0026] Figure 2 A schematic structural diagram of a heat sink structure for a flip chip ball grid array provided in a second embodiment of the present application;

[0027] Figure 3 A schematic structural diagram of a heat sink structure for a flip chip ball grid array provided in a third embodiment of the present application;

[0028] Figure 4 A schematic structural diagram of a heat sink structure for a flip chip ball grid array provided in a fourth embodiment of the present application;

[0029] Figure 5 A schematic structural diagram of a heat sink structure for a flip chip ball grid array provided in a fifth embodiment of the present application;

[0030] Figure 6 A schematic structural diagram of a heat sink structure for a flip chip ball grid array provided in a sixth embodiment of the present application;

[0031] Figure 7 A schematic flow chart of a method for preparing a heat sink structure for a flip chip ball grid array provided in the first embodiment of the present application;

[0032] Figure 8 This is a schematic diagram of a process for preparing a heat sink structure of a flip chip ball grid array provided in a sixth embodiment of the present application;

[0033] Figure 9 This is a second flow chart of a method for preparing a heat sink structure of a flip chip ball grid array provided in the sixth embodiment of the present application.

[0034] Icon: 100-heat sink structure of flip chip ball grid array; 110-substrate; 111-solder pad; 112-solder ball; 113-first protective adhesive layer; 120-first chip; 130-heat sink cover; 131-cover body; 132-connecting part; 1321-conductive hole; 133-support leg; 134-heat sink fin; 140-second chip; 141-wire bonding; 150-third chip; 160-fourth chip; 161-bump; 170-plastic package; 180-fixing adhesive layer; 190-second protective adhesive layer. DETAILED DESCRIPTION

[0035] The embodiments set forth below represent the information necessary to enable those skilled in the art to practice the embodiments and illustrate the best mode for practicing the embodiments. After reading the following description with reference to the accompanying drawings, those skilled in the art will understand the concepts of the present disclosure and will recognize applications of these concepts not specifically set forth herein. It should be understood that these concepts and applications fall within the scope of the present disclosure and the appended claims.

[0036] It should be understood that although the terms first, second, etc. can be used to describe various elements in this article, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, without departing from the scope of this disclosure, a first element can be referred to as a second element, and similarly, a second element can be referred to as a first element. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0037] It should be understood that when an element (such as a layer, region, or substrate) is referred to as being "on" or "extending onto" another element, it can be directly on or directly extended onto the other element, or intervening elements may be present. In contrast, when an element is referred to as being "directly on" or "extending directly onto" another element, there are no intervening elements. Similarly, it should be understood that when an element (such as a layer, region, or substrate) is referred to as being "on" or "extending onto" another element, it can be directly on or directly extended onto the other element, or there may be intervening elements. In contrast, when an element is referred to as being "directly on" or "extending directly onto" another element, there are no intervening elements. It should also be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or there may be intervening elements. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements.

[0038] Relative terms such as “below” or “above” or “upper” or “lower” or “horizontal” or “vertical” may be used herein to describe the relationship of one element, layer or region to another element, layer or region as illustrated in the figures.

[0039] The terms used herein are for the purpose of describing specific embodiments only and are not intended to limit the present disclosure. As used herein, unless the context clearly indicates otherwise, the singular forms "a," "an," and "the" are intended to include the plural forms as well. It should also be understood that when used herein, the term "comprising" indicates the presence of the recited features, integers, steps, operations, elements, and / or components, but does not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0040] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meanings as those commonly understood by those skilled in the art to which this disclosure belongs. It should also be understood that the terms used herein should be interpreted as having the same meanings as those in the context of this specification and the relevant art, and should not be interpreted in an idealized or overly formal sense, unless otherwise explicitly defined herein.

[0041] In traditional system-in-package (SIP) architectures, chips and passive components are laid flat on the substrate surface. This planar layout presents numerous drawbacks. When more chips and passive components need to be integrated to improve system performance, the mounting area inevitably expands as they occupy space on the substrate. The heatsink is designed to dissipate heat from these chips and components, so its size also increases. From a product design perspective, a larger heatsink hinders the miniaturization of the entire device, as miniaturization requires more functionality within a limited space, and an overly large heatsink takes up too much space. Furthermore, the large number of chips and passive components mounted on the substrate requires more wiring to connect them. This increased wiring increases the risk of parasitic effects and capacitance between wiring layers. These effects can interfere with signal transmission, impacting the performance of the entire device and reducing its stability and reliability.

[0042] To solve the above problems, please refer to Figures 1 to 9 The present application provides a flip-chip ball grid array heat sink structure 100 and a preparation method thereof, which can reduce the package size, reduce the number of wirings on the substrate 110, avoid parasitic effects and capacitance effects between wiring layers of the substrate 110, and ensure device performance.

[0043] Specifically, if Figures 1 to 6 As shown, in the first aspect of an embodiment of the present application, a heat sink structure 100 of a flip chip ball grid array is provided, comprising a substrate 110, a first chip 120, a heat dissipation cover 130 and a second chip 140, wherein a solder pad 111 is provided on the substrate 110, the first chip 120 is flipped on the substrate 110 and electrically connected to the substrate 110, the heat dissipation cover 130 is provided above the first chip 120, the second chip 140 is mounted upright above the heat dissipation cover 130, and the second chip 140 is electrically connected to the solder pad 111 via a bonding wire 141.

[0044] It should be noted that the heat sink structure 100 of the flip chip ball grid array includes a substrate 110, a first chip 120, a heat dissipation cover 130 and a second chip 140, wherein the substrate 110 is used as a basic supporting component and is provided with a pad 111 to realize the electrical connection between the chip and the substrate 110 through the pad 111; the first chip 120 is mounted on the substrate 110 in a flip-chip manner, and the bumps of the first chip 120 are connected to the pad 111 on the substrate 110, thereby realizing the electrical connection between the first chip 120 and the substrate 110. This flip-chip method is different from the traditional face-mounted method. , which can shorten the signal transmission path between the first chip 120 and the substrate 110 and improve the signal transmission efficiency; the heat dissipation cover 130 is arranged above the first chip 120. On the one hand, the heat dissipation cover 130 can dissipate heat for the first chip 120 and the entire packaging structure. On the other hand, the heat dissipation cover 130 can also serve as an installation platform for the second chip 140 and provide support for the second chip 140; the second chip 140 is installed above the heat dissipation cover 130 in a positive manner, and the second chip 140 is electrically connected to the pad 111 on the substrate 110 through the bonding wire 141.

[0045] Compared to the prior art, the flip-chip ball grid array heat sink structure 100 provided in this application replaces the traditional planar layout where all chips and passive components are located on the surface of substrate 110 by mounting the first chip 120 on substrate 110 and the second chip 140 on top of the heat dissipation cover 130. This three-dimensional layout effectively utilizes space, reduces the mounting area on the surface of substrate 110, and makes the entire package structure more compact, thereby facilitating device miniaturization. Even if the number of integrated chips and passive components increases, the overall size will not increase significantly as in traditional methods.

[0046] Furthermore, because the second chip 140 is disposed above the heat dissipation cover 130, rather than being disposed on the substrate 110 like the first chip 120, the flip-chip ball grid array heat sink structure 100 provided in this application reduces the number of chips that need to be connected to the substrate 110, thereby reducing the number of wirings on the substrate 110. The reduction in the number of wirings can reduce parasitic effects and capacitance effects between wiring layers on the substrate 110, thereby minimizing interference to signals during transmission, thereby improving device performance, stability, and reliability.

[0047] As an implementable method, Figure 1As shown in the first embodiment, the heat dissipation cover 130 is arranged on the surface of the first chip 120 facing away from the substrate 110, and the second chip 140 is mounted on the surface of the heat dissipation cover 130 facing away from the first chip 120. Therefore, the heat dissipation cover 130 can be used as a mounting platform for the second chip 140 to form a three-dimensional stacking structure of "substrate 110-first chip 120-heat dissipation cover 130-second chip 140", and the heat dissipation cover 130 can be used to achieve both heat dissipation and chip carrying functions; or, as shown in FIG. Figure 2 As shown, in the second embodiment, a hollow structure is provided on the heat dissipation cover 130, and the heat dissipation cover 130 is sleeved on the first chip 120 through the hollow structure. The second chip 140 is mounted on the surface of the first chip 120 facing away from the substrate 110 through the fixing adhesive layer 180. Therefore, the edge of the heat dissipation cover 130 at the hollow structure can be connected to the edge of the first chip 120, and the surface of the first chip 120 facing away from the substrate 110 can be exposed through the hollow structure, so that the second chip 140 can be directly stacked on top of the first chip 120, further compressing the package size in the vertical direction.

[0048] As an implementable method, Figures 1 to 6 As shown, the number of the second chip 140 is at least one. When the number of the second chip 140 is multiple, the multiple second chips 140 are distributed in the middle and edge of the heat dissipation cover 130 .

[0049] It should be noted that in the heat sink structure 100 of the flip-chip ball grid array, the number of second chips 140 can be one or more. When there are multiple second chips 140, they are not randomly distributed on the surface of the heat dissipation cover 130, but are arranged in the middle and edge positions of the heat dissipation cover 130. This can make the heat distribution on the surface of the heat dissipation cover 130 more uniform, avoid local overheating, and further optimize the heat dissipation performance of the entire packaging structure. Among them, the second chip 140 located in the middle position can transfer heat to the entire heat dissipation cover 130 structure more quickly with the help of the heat dissipation cover 130, while the second chip 140 located at the edge position can directly dissipate heat to the external environment. This distribution method forms a more efficient heat dissipation path, speeds up the heat dissipation rate, reduces the operating temperature of the second chip 140, helps to improve the performance and stability of the chip, and reduces the probability of performance degradation and failure due to overheating.

[0050] At the same time, the multiple second chips 140 are reasonably distributed in the middle and edges, with a relatively long distance between each other, which can effectively reduce electromagnetic interference and signal crosstalk between chips, ensure the independence and stability of signal transmission of each chip, and thus improve the electrical performance of the entire system. In addition, on the limited surface of the heat dissipation cover 130, the multiple second chips 140 are dispersed at different positions of the heat dissipation cover 130, avoiding mutual interference and spatial conflicts between chips, making full use of the effective area of ​​the heat dissipation cover 130, and realizing efficient use of space, which is particularly important for electronic devices that pursue miniaturization and high-density integration. This distribution method can also make the connection of the wire bonding 141 between the second chip 140 and the substrate 110 more orderly, reduce the crossing and entanglement between the wire bonding 141, reduce the complexity of wiring, facilitate the layout planning and production manufacturing process of the entire packaging structure, and improve production efficiency and product yield.

[0051] As an implementable method, Figures 1 to 6 As shown, a plurality of heat dissipation fins 134 are provided on the heat dissipation cover 130 . When there are multiple second chips 140 , the plurality of heat dissipation fins 134 are distributed between two adjacent second chips 140 .

[0052] It should be noted that in the heat sink structure 100 of the flip-chip ball grid array, the heat dissipation cover 130 plays a key role in dissipating heat from the chip. To enhance the heat dissipation effect, a plurality of heat dissipation fins 134 are provided on the heat dissipation cover 130. When there are multiple second chips 140, these heat dissipation fins 134 are arranged between two adjacent second chips 140. From a spatial layout perspective, the multiple second chips 140 are distributed on the surface of the heat dissipation cover 130, and the heat dissipation fins 134 are cleverly interspersed in the gaps between them. From a functional perspective, the second chips 140 generate heat during operation, and this heat is transferred to the heat dissipation cover 130. The presence of the heat dissipation fins 134 greatly increases the heat dissipation area of ​​the heat dissipation cover 130. The contact area between the heat dissipation fins 134 and the air is increased, and there are more paths for heat conduction. When the heat generated by the first chip 120 and the second chip 140 is transferred to the heat dissipation cover 130, it can be transferred to the surrounding air more quickly through the heat dissipation fins 134. Moreover, many air channels are formed between the heat dissipation fins 134. When the air flows through these channels, it will take away more heat, enhancing the effect of air convection heat dissipation, thereby significantly improving the overall heat dissipation efficiency, effectively reducing the operating temperature of the chip, and ensuring that the chip operates stably in a suitable temperature environment.

[0053] Placing the heat dissipation fins 134 between two adjacent chips fully utilizes the inter-chip space, improving heat dissipation performance without increasing additional space. This is crucial for electronic devices pursuing miniaturization and high-density integration, helping to achieve more functions within a limited space. Furthermore, the heat dissipation fins 134 can, to a certain extent, provide physical isolation, reducing electromagnetic interference between adjacent chips. Because the heat dissipation fins 134 can block the propagation of some electromagnetic waves, the electromagnetic environment of each chip is relatively independent, thereby ensuring the stability and accuracy of signal transmission between chips and improving the electrical performance of the entire system.

[0054] As an implementable method, Figures 1 to 6 As shown, the plurality of heat dissipation fins 134 are distributed along a surface of the heat dissipation cover 130 close to the first chip 120 and / or along a surface of the heat dissipation cover 130 away from the first chip 120 .

[0055] It should be noted that in some embodiments, the heat dissipation fins 134 are located on a side of the heat dissipation cover 130 that is close to the first chip 120. When the first chip 120 generates heat during operation, the heat is quickly transferred to the heat dissipation cover 130, which is in close contact with the first chip 120. The heat dissipation fins 134 close to the surface of the first chip 120 can then quickly receive the heat. Due to the large surface area of ​​the heat dissipation fins 134, the heat can be efficiently transferred to the surrounding air, thereby quickly dissipating the heat generated by the first chip 120.

[0056] In other embodiments, the heat dissipation fins 134 are located on the side of the heat dissipation cover 130 facing away from the first chip 120 (i.e., the side of the heat dissipation cover 130 that is closest to the second chip 140). When the second chip 140 generates heat during operation, the heat is quickly transferred to the heat dissipation cover 130, which is in close contact with it. The heat dissipation fins 134 near the surface of the second chip 140 can then quickly absorb the heat. Due to the large surface area of ​​the heat dissipation fins 134, they can efficiently transfer heat to the surrounding air, rapidly dissipating the heat generated by the second chip 140.

[0057] In other embodiments, multiple heat dissipation fins 134 are distributed along the surface of the heat dissipation cover 130 proximal to the first chip 120 and along the surface of the heat dissipation cover 130 distal from the first chip 120. In this case, the heat dissipation cover 130 dissipates heat from two directions, significantly increasing the heat transfer path and heat dissipation area, and more efficiently dissipating the heat generated by the first chip 120 and the second chip 140. For example, in electronic devices, this can effectively reduce the operating temperature of the chip, ensuring stable operation within an appropriate temperature range, avoiding performance degradation, operational lag, or even system crashes caused by overheating, and improving the overall performance and stability of the device.

[0058] As an implementable method, Figure 3 As shown, in the third embodiment, when the number of the second chips 140 is multiple and the multiple heat dissipation fins 134 are distributed along the surface of the heat dissipation cover 130 away from the first chip 120, the vertical distance between the end of at least one heat dissipation fin 134 away from the heat dissipation cover 130 (i.e., the top of the heat dissipation fin 134) and the surface of the substrate 110 is greater than the vertical distance between the surface of the second chip 140 away from the heat dissipation cover 130 (i.e., the top surface of the second chip 140) and the surface of the substrate 110.

[0059] This means that the top of the heat sink 134 is higher than the top surface of the second chip 140. This design prevents the second chip 140 from blocking the heat dissipation path of the heat sink 134 while also utilizing the height advantage of the heat sink 134 to enhance air convection. When the top of the heat sink 134 is higher than the top surface of the second chip 140, its top and side surfaces are directly exposed to the outside air, creating a larger heat dissipation surface area. Compared to a situation where the heat sink 134 is blocked by the second chip 140, the exposed heat sink 134 can dissipate heat more efficiently through heat conduction and convection, significantly improving the heat dissipation effect, especially in natural convection scenarios.

[0060] The design of the top of the heat dissipation fin 134 being higher than the top surface of the second chip 140 not only optimizes heat dissipation performance but also significantly enhances electromagnetic shielding. When the top of the heat dissipation fin 134 is higher than the top surface of the second chip 140, a three-dimensional metal barrier is formed around the second chip 140, effectively blocking the electromagnetic radiation generated by the second chip 140 during operation from spreading to the outside world, while also isolating the second chip 140 from the effects of external electromagnetic interference. When multiple heat dissipation fins 134 are distributed along the surface of the heat dissipation cover 130 facing away from the first chip 120, a fence structure is formed between adjacent heat dissipation fins 134, further enhancing the electromagnetic shielding effect. This fence structure can confine electromagnetic waves to the area between the heat dissipation fins 134, reducing the propagation intensity of electromagnetic waves through multiple reflections and attenuation.

[0061] As an implementable method, Figures 1 to 6 As shown, in other embodiments, when the plurality of heat dissipation fins 134 are distributed along the surface of the heat dissipation cover 130 close to the first chip 120 , the ends of the plurality of heat dissipation fins 134 facing away from the heat dissipation cover 130 (i.e., the bottom ends of the heat dissipation fins 134 ) all extend toward a side close to the substrate 110 .

[0062] This means that the heat dissipation fins 134 protrude downward (i.e., toward the substrate 110) from the surface of the heat dissipation cover 130 near the first chip 120, forming a structure similar to "rooting down." This design differs from the aforementioned "upward extension" (i.e., the ends of the multiple heat dissipation fins 134 facing away from the heat dissipation cover 130 extend toward the side away from the substrate 110). Instead, by extending the heat dissipation fins 134 toward the substrate 110, the air gap between the first chip 120 and the substrate 110 is utilized to enhance heat conduction, thereby further optimizing the heat dissipation path and structural layout. For example, the bottom ends of the heat dissipation fins 134 may maintain a certain gap with the substrate 110 (non-direct contact) or directly contact the surface of the substrate 110.

[0063] As an implementable method, Figure 4 As shown, in the fourth embodiment, a first protective adhesive layer 113 is provided at the bottom of the first chip 120, and the end of at least one heat dissipation fin 134 facing away from the heat dissipation cover 130 is in contact with the first protective adhesive layer 113. As a result, the heat dissipation fin 134 can be in contact with the first protective adhesive layer 113 to form a heat dissipation path of "first chip 120-heat dissipation cover 130-heat dissipation fin 134-first protective adhesive layer 113-substrate 110-external environment". The heat conduction capacity of the first protective adhesive layer 113 is utilized to simultaneously conduct heat from the top and bottom of the first chip 120, further improving the heat dissipation effect. At the same time, the heat dissipation fin 134 and the first protective adhesive layer 113 can be used to jointly support the first chip 120, reducing the risk of displacement of the first chip 120 due to vibration, impact or thermal expansion. In addition, an additional grounding channel can be formed to accelerate the discharge of electromagnetic interference and enhance the system's anti-interference capability.

[0064] Alternatively, as an implementation method, Figure 5 As shown, in the fifth embodiment, the end of at least one heat dissipation fin 134 facing away from the heat dissipation cover 130 contacts the surface of the substrate 110. Thus, the heat dissipation fin 134 can contact the substrate 110, forming a heat dissipation path of "first chip 120 - heat dissipation cover 130 - heat dissipation fin 134 - substrate 110 - external environment". Heat is rapidly diffused through the large metal layer of the substrate 110, significantly improving heat conduction efficiency. At the same time, the heat dissipation fin 134 can be used to securely connect the heat dissipation cover 130 to the substrate 110, significantly improving the overall package's resistance to bending and impact. Furthermore, the heat dissipation fin 134 can also connect the heat dissipation cover 130 to the ground layer of the substrate 110, forming a complete metal shielding cavity that completely encloses the first chip 120 and effectively suppresses electromagnetic radiation leakage.

[0065] As an implementable method, Figure 6As shown, in the sixth embodiment, the heat sink structure 100 of the flip chip ball grid array further includes a third chip 150, and the heat dissipation cover 130 includes a cover body portion 131, a connecting portion 132 and a support leg portion 133 connected in sequence, and the angle between the cover body portion 131 and the connecting portion 132 and the angle between the support leg portion 133 and the connecting portion 132 are obtuse angles, and the third chip 150 is arranged on the connecting portion 132.

[0066] It should be noted that the heat dissipation cover 130 is composed of a cover portion 131, a connecting portion 132, and a support portion 133, which are connected in sequence. The angles between the cover portion 131 and the connecting portion 132, as well as between the support portion 133 and the connecting portion 132, are both obtuse. The cover portion 131 primarily covers the first chip 120, directly collecting and conducting heat from the first chip 120. The connecting portion 132 serves as an intermediate transition portion, changing the extension direction of the heat dissipation cover 130 according to actual needs. The support portion 133 is used to support the heat dissipation cover 130, maintaining an appropriate distance from the underlying substrate 110, while also providing additional space for mounting other chips (such as the second chip 140).

[0067] The flip-chip BGA heat sink structure 100 also includes a third chip 150, which is disposed on the connecting portion 132. Due to the unique location and shape of the connecting portion 132, installing the third chip 150 there fully utilizes the space within the heatsink cover 130, achieving a more compact chip layout. This layout further increases the flexibility of chip integration, allowing for the integration of more functional chips within a limited space. It also helps reduce electromagnetic interference between chips, improving the stability and reliability of the entire system.

[0068] As an implementable method, Figure 6 As shown, conductive vias 1321 are provided on the connection portion 132. The third chip 150 is flip-chip mounted on the surface of the connection portion 132 near the substrate 110. The third chip 150 is electrically connected to the second chip 140 through the conductive vias 1321. For example, the second chip 140 can be a memory chip, and the third chip 150 can be a component, a logic chip, or a radio frequency chip. When the second chip 140 is a memory chip and the third chip 150 is a logic chip, electrically connecting the third chip 150 to the second chip 140 through the conductive vias 1321 can improve reading efficiency.

[0069] It should be noted that conductive holes 1321 are provided on the connecting portion 132. These conductive holes 1321 are important channels for achieving electrical connection between the third chip 150 and the second chip 140. The third chip 150 is mounted on the surface of the connecting portion 132 close to the substrate 110 in a flip-chip manner. This mounting method can shorten the signal transmission path and improve transmission efficiency. The bumps of the third chip 150 are connected to the conductive holes 1321 on the connecting portion 132. The second chip 140 is mounted on the surface of the heat dissipation cover 130 away from the first chip 120 in a face-up manner and is electrically connected to the pads 111 on the substrate 110 via bonding wires 141. At the same time, the second chip 140 can also be connected to the conductive holes 1321 on the connecting portion 132 via bonding wires 141, thereby achieving electrical connection with the flip-chip third chip 150. In this way, current can be smoothly conducted between the second chip 140 and the third chip 150, completing signal transmission and interaction.

[0070] The flip-chip third chip 150 is directly electrically connected to the second chip 140 via conductive vias 1321, significantly shortening the signal transmission path compared to traditional long-distance wiring connections. This shortened signal transmission path reduces resistance and inductance, lowering transmission losses and latency, enabling faster and more accurate signal transmission, improving the overall system's electrical performance and ensuring stable high-speed data transmission.

[0071] The bonding wires 141 between the second chip 140 and the conductive vias 1321 may generate electromagnetic coupling interference due to their close spacing. Therefore, the present application utilizes the heat dissipation fins 134 on the heat dissipation cover 130 as metal barriers, inserted between two adjacent bonding wires 141. This allows the heat dissipation fins 134 to isolate signal interference between the bonding wires, blocking the electromagnetic wave propagation path and reducing parasitic capacitance and mutual inductance between the bonding wires.

[0072] Different arcs may generate potential differences due to different transmission signal types (such as power, ground, and high-frequency signals), leading to the risk of charge accumulation or discharge. To address this, the present application also utilizes heat dissipation fins 134 to form an equipotential surface by connecting to the ground (connecting to the first protective adhesive layer 113 or the ground layer of the substrate 110), clamping the potential difference between the arcs to zero, thereby preventing electrostatic discharge or arc discharge.

[0073] Furthermore, complex wiring on substrate 110 to connect second chip 140 and third chip 150 is avoided, simplifying the overall wiring design. This reduces the number of wiring layers and the design and manufacturing costs of substrate 110, and also reduces the risk of short circuits, open circuits, and other problems that may arise during the wiring process, thereby improving production efficiency and product yield.

[0074] As an implementable method, Figure 6As shown, in the sixth embodiment, the heat sink structure 100 of the flip chip ball grid array also includes a fourth chip 160, which is flipped on the surface of the heat dissipation cover 130 close to the substrate 110, and the fourth chip 160 is distributed on the edge of the heat dissipation cover 130, and the fourth chip 160 is electrically connected to the substrate 110 through the bump 161.

[0075] It should be noted that in addition to the aforementioned first chip 120, second chip 140, and third chip 150, the flip-chip BGA heat sink structure 100 also incorporates a fourth chip 160. This fourth chip 160 is flip-chip mounted on the surface of the heat dissipation cover 130 near the substrate 110 and is located at the edge of the heat dissipation cover 130. The fourth chip 160 is electrically connected to the substrate 110 via bumps 161, providing a stable electrical path between the fourth chip 160 and the substrate 110, enabling signal transmission and data exchange between the fourth chip 160 and other chips and the entire system. Mounting the fourth chip 160 in this location fully utilizes the space within the heat dissipation cover 130, achieving a more compact chip layout and rapidly dissipating heat generated by the operation of the fourth chip 160 through the heat dissipation cover 130. This layout further increases the flexibility of chip integration, allowing for the integration of more functional chips within a limited space. It also helps reduce electromagnetic interference between chips, improving the stability and reliability of the entire system.

[0076] As an implementable method, Figure 6 As shown, the number of bonding wires 141 and bumps 161 is at least two to achieve electrical connection between the chip and the substrate 110. At least one bonding wire 141 is distributed between two adjacent bumps 161, thereby utilizing the arc of the bonding wire 141 to enhance the capillary action between the bumps 161 and enhance the filling and bonding strength of the bottom of the bump 161 of the fourth chip 160.

[0077] As an implementable method, Figures 1 to 6As shown, the flip-chip BGA heat sink structure 100 further includes a plastic encapsulation body 170, which is disposed on the substrate 110 and covers the first chip 120, the heat dissipation cover 130, and the second chip 140. When the flip-chip BGA heat sink structure 100 further includes a third chip 150 and a fourth chip 160, the plastic encapsulation body 170 covers the first chip 120, the heat dissipation cover 130, the second chip 140, the third chip 150, and the fourth chip 160. Thus, the plastic encapsulation body 170 provides physical protection for the chips and the heat dissipation cover 130, protecting them from external factors such as dust, moisture, and mechanical shock. For example, in a humid environment, the plastic encapsulation body 170 can prevent moisture from entering, preventing problems such as rusting and short circuiting of chip pins. In the event of vibration or collision, the plastic encapsulation body 170 can buffer external forces, reducing damage to the chips and the heat dissipation cover 130, thereby improving the reliability and stability of the entire structure.

[0078] like Figure 7 As shown, in a second aspect of an embodiment of the present application, a method for preparing a heat sink structure 100 of a flip chip ball grid array is provided, and the method is used to prepare the heat sink structure 100 of the flip chip ball grid array. The method comprises:

[0079] S01 . Provide a substrate 110 , wherein a pad 111 is provided on the substrate 110 .

[0080] S02. A first chip 120 is mounted on the substrate 110 using a flip-chip method, and the bumps of the first chip 120 are electrically connected to the pads 111 of the substrate 110. For example, the bumps of the first chip 120 are soldered to the pads 111 of the substrate 110 using reflow soldering, and a first protective adhesive layer 113 is disposed on the bottom of the first chip 120 using a dispensing method to protect the bumps of the first chip 120.

[0081] S03. Mount the heat dissipation cover 130 on the surface of the first chip 120 facing away from the substrate 110. For example, the heat dissipation cover 130 can be bent into a desired shape (e.g., a pot shape as shown) using a bending machine in advance, so that the second chip 140 can be placed on the leg portion 133 at the edge of the heat dissipation cover 130 and on the surface facing away from the first chip 120 in subsequent operations.

[0082] S04: Mount the second chip 140 on the surface of the heat dissipation cover 130 facing away from the first chip 120 in a top-mounted manner, and electrically connect the second chip 140 to the pads 111 of the substrate 110 via bonding wires 141. For example, the second chip 140 is mounted via a fixing adhesive layer 180.

[0083] S05 , forming a plastic package 170 on the substrate 110 . For example, the plastic package 170 is formed by a plastic packaging process, such as pressure injection molding, and is used to protect the substrate 110 , the chip, and the heat dissipation cover 130 .

[0084] S06: Planting balls on the surface of the substrate 110 facing away from the first chip 120 to form solder balls 112, and then cutting and separating them to form individual products. The process is completed.

[0085] like Figure 9 As shown, in a third aspect of an embodiment of the present application, a method for preparing a heat sink structure 100 of a flip chip ball grid array is provided, and the method is used to prepare the heat sink structure 100 of the flip chip ball grid array. The method comprises:

[0086] S11 , providing a substrate 110 , wherein a pad 111 is provided on the substrate 110 .

[0087] S12: Mount the first chip 120 on the substrate 110 using a flip-chip method, and electrically connect the bumps of the first chip 120 to the pads 111 of the substrate 110. For example, the bumps of the first chip 120 are soldered to the pads 111 of the substrate 110 using reflow soldering, and a first protective adhesive layer 113 is disposed on the bottom of the first chip 120 using a dispensing method to protect the bumps of the first chip 120.

[0088] S13, attaching a heat dissipation cover 130 to the surface of the first chip 120 facing away from the substrate 110. For example, Figure 8 As shown, the third chip 150 can be pre-mounted on the connection portion 132 of the heat dissipation cover 130, and the bumps of the third chip 150 can be soldered to the conductive holes 1321 of the connection portion 132. The heat dissipation cover 130 can then be bent into a desired shape (e.g., the pot shape shown in the figure) using a bending machine. The fourth chip 160 can then be flip-chip mounted on the support portion 133 at the edge of the heat dissipation cover 130, close to the surface of the substrate 110. This facilitates subsequent placement of the second chip 140 on the support portion 133 at the edge of the heat dissipation cover 130, facing away from the first chip 120. For example, the fourth chip 160 is mounted via a fixing adhesive layer 180.

[0089] S14. Mount the second chip 140 on the surface of the heat dissipation cover 130 facing away from the first chip 120 in a face-up manner. Furthermore, the second chip 140 is electrically connected to the pad 111 of the substrate 110 via the bonding wire 141, and / or the second chip 140 is electrically connected to the conductive via 1321 of the connection portion 132 via the bonding wire 141. Furthermore, the fourth chip 160 is electrically connected to the pad 111 of the substrate 110 via the bump 161. For example, the second chip 140 is mounted via the fixing adhesive layer 180.

[0090] S15 , disposing a second protective adhesive layer 190 on the bottom of the fourth chip 160 by dispensing.

[0091] S16 , forming a plastic package 170 on the substrate 110 . For example, the plastic package 170 is formed by a plastic packaging process, such as pressure injection molding, and is used to protect the substrate 110 , the chip, and the heat dissipation cover 130 .

[0092] S17 , planting balls on the surface of the substrate 110 away from the first chip 120 to form solder balls 112 , and then cutting and separating them to form individual products. The process is completed.

[0093] It should be noted that the method for preparing the heat sink structure 100 for a flip-chip ball grid array provided in this embodiment has the same specific structure as the heat sink structure 100 for a flip-chip ball grid array described above. A person skilled in the art can infer the method for preparing the heat sink structure 100 for a flip-chip ball grid array based on the description of the specific structure of the heat sink structure 100 for a flip-chip ball grid array described above, and this application will not repeat the description. Since the method for preparing the heat sink structure 100 for a flip-chip ball grid array provided in this embodiment is used to prepare the heat sink structure 100 for a flip-chip ball grid array described above, the method for preparing the heat sink structure 100 for a flip-chip ball grid array provided in this embodiment has the same beneficial effects as the heat sink structure 100 for a flip-chip ball grid array described above, and will not be repeated here.

[0094] The above description is merely an optional embodiment of the present application and is not intended to limit the present application. Various modifications and variations are possible for those skilled in the art. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application shall be included within the scope of protection of the present application.

[0095] It should also be noted that the various specific technical features described in the above specific embodiments can be combined in any appropriate manner unless there is any contradiction. In order to avoid unnecessary repetition, this application will not further describe various possible combinations.

Claims

1. A heat sink structure for a flip chip ball grid array, characterized in that: The device comprises a substrate, a first chip, a heat dissipation cover, and a second chip. The substrate is provided with a solder pad. The first chip is flip-chip mounted on the substrate and electrically connected to the substrate. The heat dissipation cover is provided above the first chip. The second chip is mounted on the heat dissipation cover and electrically connected to the solder pad via wire bonding. There are multiple second chips, and the multiple second chips are distributed in the middle and edges of the heat dissipation cover. The heat dissipation cover is provided with a hollow structure, which is sleeved on the first chip. The edge of the heat dissipation cover at the hollow structure is connected to the edge of the first chip, and the surface of the first chip facing away from the substrate is exposed through the hollow structure. The second chip is mounted on the surface of the first chip facing away from the substrate through a fixed adhesive layer; the heat dissipation cover includes a cover body, a connecting portion and a supporting leg portion connected in sequence, and the second chip is mounted on the supporting leg portion.

2. The heat sink structure of flip chip ball grid array according to claim 1, characterized in that: The heat dissipation cover is provided with a plurality of heat dissipation fins. When there are multiple second chips, the plurality of heat dissipation fins are distributed between two adjacent second chips.

3. The heat sink structure of the flip chip ball grid array according to claim 2, characterized in that: The plurality of heat dissipation fins are distributed along a surface of the heat dissipation cover close to the first chip and / or along a surface of the heat dissipation cover away from the first chip.

4. The heat sink structure of flip chip ball grid array according to claim 3, characterized in that: When there are multiple second chips and multiple heat sink fins are distributed along the surface of the heat sink cover facing away from the first chip, the vertical distance between the end of at least one heat sink facing away from the heat sink cover and the surface of the substrate is greater than the vertical distance between the surface of the second chip facing away from the heat sink cover and the surface of the substrate.

5. The heat sink structure of flip chip ball grid array according to claim 3, characterized in that: When the plurality of heat dissipation fins are distributed along the surface of the heat dissipation cover close to the first chip, the ends of the plurality of heat dissipation fins facing away from the heat dissipation cover all extend toward a side close to the substrate.

6. The heat sink structure of flip chip ball grid array according to claim 5, characterized in that: A first protective adhesive layer is provided on the bottom of the first chip, and an end portion of at least one of the heat dissipation fins facing away from the heat dissipation cover is in contact with the first protective adhesive layer.

7. The heat sink structure of flip chip ball grid array according to claim 5, characterized in that: An end portion of at least one of the heat dissipation fins facing away from the heat dissipation cover contacts the surface of the substrate.

8. The heat sink structure of flip chip ball grid array according to claim 1, characterized in that: It also includes a third chip, the angle between the cover portion and the connecting portion and the angle between the support leg portion and the connecting portion are obtuse angles, and the third chip is arranged on the connecting portion.

9. The heat sink structure of flip chip ball grid array according to claim 8, characterized in that: The connecting portion is provided with a conductive hole, the third chip is flip-mounted on a surface of the connecting portion close to the substrate, and the third chip is electrically connected to the second chip through the conductive hole.

10. The heat sink structure of flip chip ball grid array according to claim 1, characterized in that: The device further comprises a fourth chip, which is flip-mounted on the surface of the heat dissipation cover close to the substrate and distributed on the edge of the heat dissipation cover. The fourth chip is electrically connected to the substrate via bumps.

11. The heat sink structure of flip chip ball grid array according to claim 10, characterized in that: The number of the bonding wires and the bumps is at least two, and at least one bonding wire is distributed between two adjacent bumps.

12. The heat sink structure of flip chip ball grid array according to claim 1, characterized in that: It also includes a plastic package, which is arranged on the substrate and covers the first chip, the heat dissipation cover and the second chip.

13. A method for preparing a heat sink structure of a flip chip ball grid array, characterized in that: A heat sink structure for preparing the flip chip ball grid array according to any one of claims 1 to 12.

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