A method for generating a dynamic modulation signal within a pulse

Abstract

The present invention proposes a method for generating a dynamic modulation signal within a pulse, which belongs to the technical field of pulse broadband modulation signal sources. The method comprises: setting the pulse repetition interval and pulse width of a pulse signal generation module; the pulse signal generation module generates a pulse switching signal; the pulse switching signal is transmitted to a pulse segmentation module, and the pulse segmentation module generates a modulation time label; setting a modulation mapping table of a logic control unit, arranging and combining the phase offset control word or the phase increment control word of the bit data to be transmitted, and storing the combination in a double buffer register group; transmitting the modulation time label to a finite state machine, and when the finite state machine detects the modulation time label within the pulse, triggering an interrupt service program to read the phase offset control word or the phase increment control word and write it into a DDS signal generator, and the DDS signal generator generates a continuous waveform based on the phase offset control word or the phase increment control word. The present invention can make the time-frequency characteristics of the signal more complex and difficult to predict, and improve the anti-interference ability.

Description

Technical Field

[0001] The present invention belongs to the technical field of pulse broadband modulation signal sources, and in particular relates to a method for generating a pulse intra-pulse dynamic modulation signal. Background Art

[0002] With the rise of emerging technologies such as 5G, millimeter-wave radar, and quantum communications, the demand for high-performance pulse signal sources has increased significantly in radar, communications, navigation, sensing, and other fields. Traditional fixed-frequency signal sources can no longer meet the diverse signal needs in complex electromagnetic environments. Modulated pulse signal sources, with their flexible modulation capabilities and high-precision output characteristics, have become an indispensable module in electronic systems.

[0003] Modern electronic systems are increasingly moving toward multifunctional integration, with emerging trends such as the integration of radar and communications, and the combination of navigation and detection, becoming key trends. These integrated systems place increasingly complex demands on pulse signal sources for output frequency, modulation format, and dynamic response. The development of many emerging technologies relies on high-performance pulse signal sources. Traditional modulation sources typically use a fixed modulation scheme, meaning only one (or more) carrier frequency or phase change occurs within a single pulse. While this fixed modulation scheme can meet general application requirements, it has limitations in terms of interference immunity and adaptability to complex signal environments. Summary of the Invention

[0004] The purpose of this invention is to design a method for generating intra-pulse dynamic modulation signals, enabling multiple carrier frequency or phase changes within a single pulse. This method makes the signal's time-frequency characteristics more complex and unpredictable, making it difficult to detect and suppress with traditional reconnaissance and jamming methods. This method is suitable for high-security applications such as frequency-hopping communication systems, addressing the technical issues of existing technologies that limit carrier frequency or phase changes to just one (or more) per pulse, resulting in limited anti-interference capabilities and adaptability to complex signal environments.

[0005] In order to solve the above technical problems, the specific technical solutions of the present invention are as follows:

[0006] A method for generating a pulse intra-pulse dynamic modulation signal, the method comprising the following steps:

[0007] Step S1: Setting the pulse repetition interval PRI and pulse width PW of the pulse signal generating module. The pulse signal generating module generates a pulse switching signal.

[0008] Step S2: The pulse switch signal is transmitted to the pulse segmentation module, and the modulation state number of the pulse segmentation module is set. The pulse segmentation module divides the pulse width into the number of modulation states. Divided equally symbol periods and generates M modulation time labels.

[0009] Step S3: Set the modulation mapping table of the logic control unit, calculate the phase offset control word or phase increment control word combination corresponding to the bit data to be sent according to the PSK / FSK symbol mapping table in the modulation mapping table, and store it in the double buffer register group.

[0010] Step S4: The modulation time label is transmitted to the finite state machine. When the finite state machine detects the modulation time label in the pulse, it triggers the interrupt service program to read the phase offset control word or the phase increment control word and write it into the DDS signal generator. The DDS signal generator generates a continuous waveform based on the phase offset control word or the phase increment control word. After all the modulation time labels in the pulse arrive, the DDS signal generator generates a continuous modulation signal with multiple carrier frequency or phase transitions in a single pulse.

[0011] Furthermore, in step S3, the modulation mapping table includes the modulation type, the number of bits to be sent, the PSK / FSK symbol mapping table and the bit data to be sent; the modulation type determines whether the output pulse is PSK or FSK; the PSK / FSK symbol mapping table stores the phase offset control word or the phase increment control word of various bit combinations; if it is PSK modulation, the symbol mapping table stores the phase offset control word, and if it is FSK modulation, the symbol mapping table stores the phase increment control word; the bit data to be sent stores the binary data to be modulated by the system; during modulation, the logic control unit arranges the bit data to be sent into multiple bit combinations according to the PSK / FSK symbol mapping table, and queries the phase offset control word or phase increment control word in the PSK / FSK symbol mapping table according to the bit combination to obtain the phase offset control word or phase increment control word arrangement and combination corresponding to the bit data to be sent.

[0012] Furthermore, the phase shift control word and phase increment control word Calculated by the following formula:

[0013]

[0014] Where N is the phase accumulator bit width of the DDS signal generator; is the DAC sampling rate; is the output signal frequency, is the starting phase of the output signal.

[0015] Furthermore, in step S3, the double-buffer register group includes a foreground buffer and a background buffer; the foreground buffer is used to store a phase offset control word or a phase increment control word to be modulated; the background buffer is used to store a permutation and combination of phase offset control words or phase increment control words corresponding to the bit data to be sent; when each modulation time label arrives, the foreground buffer is updated, and the foreground buffer reads a phase offset control word or a phase increment control word to be modulated from the background buffer.

[0016] Further, in step S4, at the pulse start time, the finite state machine is in an idle state waiting for the rising edge of the threshold signal; when the first Modulation time label When the interrupt service routine is triggered, the phase offset control word or phase increment control word corresponding to the current encoding is read from the foreground buffer of the double buffer register group, and written into the DDS signal generator to update the carrier frequency or phase; the DDS signal generator generates a continuous waveform based on the updated phase offset control word or phase increment control word until the next modulation moment label When all modulation time tags in the pulse are executed, a continuous modulation signal with multiple carrier frequency or phase transitions in a single pulse is generated.

[0017] Compared with the prior art, the present invention has the following beneficial technical effects:

[0018] Compared with traditional intra-pulse fixed modulation, the present invention designs an intra-pulse dynamic modulation scheme that can be used for FPGA logic implementation. Users can adjust the output signal of the DDS signal generator by setting the pulse repetition interval PRI, pulse width PW, modulation state number M and modulation mapping table.

[0019] The present invention can perform multiple carrier frequency or phase changes within a single pulse. In this way, the time-frequency characteristics of the signal become more complex and unpredictable, improving the anti-interference ability and being suitable for high-security application scenarios such as frequency-hopping communication systems. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0021] Figure 1 This is a schematic diagram of the logic scheme for generating an intra-pulse continuous modulation signal according to the present invention.

[0022] Figure 2This is a schematic diagram of the carrier situation in a single conventional pulse of the present invention.

[0023] Figure 3 Schematic diagram of the four-pulse continuous FSK modulation waveform of the present invention. DETAILED DESCRIPTION

[0024] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0025] The present invention proposes a method for generating a pulse intra-pulse dynamic modulation signal, such as Figure 1 As shown, the method includes the following steps:

[0026] Step S1: setting the pulse repetition interval PRI and pulse width PW of the pulse signal generating module; the pulse signal generating module generates a pulse switch signal.

[0027] Specifically, the pulse signal generating module is a conventional pulse signal generating module, which is used to generate a pulse switching signal.

[0028] Step S2: The pulse switch signal is transmitted to the pulse segmentation module, and the modulation state number of the pulse segmentation module is set. The pulse segmentation module divides the pulse width into the number of modulation states. Divided equally symbol periods, and generates M modulation time labels ( ), Indicates the The modulation time label accurately marks the starting time point of each modulation, providing a clear timing node for subsequent parameter switching. It specifies how many times the carrier frequency or phase transitions need to be performed within a single pulse.

[0029] Step S3: Set the modulation mapping table of the logic control unit, calculate the phase offset control word or phase increment control word combination corresponding to the bit data to be sent according to the PSK / FSK symbol mapping table in the modulation mapping table, and store it in the double buffer register group.

[0030] As shown in Table 1, the modulation mapping table includes the modulation type, the number of bits to be sent, the PSK / FSK symbol mapping table, and the bit data to be sent. The modulation type determines whether the output pulse is PSK or FSK; the PSK / FSK symbol mapping table stores the phase offset control word for various bit combinations. Or phase increment control word ; If PSK modulation, the symbol mapping table stores the phase offset control word If it is FSK modulation, the symbol mapping table stores the phase increment control word The bit data to be sent stores the binary data to be modulated by the system. During modulation, the logic control unit arranges the bit data to be sent into multiple bit combinations according to the PSK / FSK symbol mapping table, and queries the phase offset control word in the PSK / FSK symbol mapping table according to the bit combination. Or phase increment control word Get the phase offset control word corresponding to the bit data to be sent Or phase increment control word Permutations and combinations.

[0031] Table 1 Modulation mapping table

[0032]

[0033] The double buffer register group includes the foreground buffer (Active Buffer) and the background buffer (ShadowBuffer). The foreground buffer is used to store a phase offset control word to be modulated. Or phase increment control word The background buffer is used to store the phase offset control word corresponding to the bit data to be sent. Or phase increment control word When each modulation time label arrives, the front buffer is updated, and the front buffer reads a phase offset control word to be modulated from the back buffer. Or phase increment control word By pre-reading the data from the background buffer and then outputting it to the front buffer, signal interruption during parameter update can be avoided.

[0034] Phase offset control word and phase increment control word Calculated by the following formula:

[0035]

[0036] Where N is the phase accumulator bit width of the DDS signal generator; is the DAC sampling rate; is the output signal frequency, is the starting phase of the output signal.

[0037] Step S4: The modulation time tag is transmitted to the finite state machine (FSM). When the finite state machine detects the modulation time tag in the pulse, it triggers the interrupt service routine to read the phase offset control word or the phase increment control word and write it into the DDS signal generator. The DDS signal generator is based on the phase offset control word. Or phase increment control word Generate a continuous waveform. After all modulation time tags arrive within the pulse, the DDS signal generator generates a continuous modulation signal with multiple carrier frequency or phase transitions within a single pulse.

[0038] Output signal frequency and the output signal starting phase Calculated by the following formula:

[0039]

[0040] The finite state machine monitors the modulation time label in real time. At the pulse start time, the finite state machine is in the idle state (Idle state) waiting for the rising edge of the threshold signal; when the first Modulation time label When the interrupt service routine (ISR) is triggered, the phase offset control word to be modulated is read from the foreground buffer of the double buffer register group. Or phase increment control word , write it to the DDS signal generator to update the carrier frequency or phase. The DDS signal generator is based on the updated phase offset control word Or phase increment control word Generates a continuous waveform until the next modulation moment label When all modulation time tags within a pulse are executed, a continuous modulation signal with multiple carrier frequency or phase transitions within a single pulse is generated.

[0041] The following describes a method for generating a dynamic modulation signal within a pulse according to the present invention using a specific embodiment.

[0042] Step S1: Set the pulse repetition interval PRI of the pulse signal generation module to 200us and the pulse width The duration is 100us, the number of modulation states is 4, and the pulse signal generation module generates a pulse switching signal.

[0043] Step S2: The pulse switch signal is transmitted to the pulse segmentation module, and the modulation state number of the pulse segmentation module is set. If the value is 4, the pulse division module divides the pulse width into the number of modulation states. The signal is divided into 4 symbol periods and 4 modulation time labels are generated (t1=0, t2=25us, t3=50us, t4=75us).

[0044] Step S3: Set the modulation mapping table of the logic control unit as shown in Table 2. The logic control unit arranges the bit data to be sent into 4 bit combinations according to the PSK / FSK symbol mapping table, and queries the phase increment control word in the PSK / FSK symbol mapping table according to the bit combination. Get the phase increment control word corresponding to the bit data to be sent Permutations and Combinations 、 、 、 , and stored in the double-buffered register bank. Set the phase accumulator bit width N to 30; bit data 00 outputs a 100 MHz signal with an initial phase of 0°; bit data 01 outputs a 200 MHz signal with an initial phase of 0°; bit data 11 outputs a 300 MHz signal with an initial phase of 0°; and bit data 10 outputs a 400 MHz signal with an initial phase of 0°.

[0045] Table 2 Modulation mapping table example

[0046]

[0047] Step S4: The modulation time label is transmitted to the finite state machine. When the finite state machine detects the modulation time label in the pulse, it triggers the interrupt service program to read the phase increment control word and write it into the DDS signal generator. The DDS signal generator generates a continuous waveform based on the phase increment control word.

[0048] The carrier situation within a single pulse achieved by this embodiment is as follows Figure 2 As shown in the figure, there are four parts of 100MHz, 200MHz, 300MHz and 400MHz in a pulse, which is an FSK modulation signal. The continuous FSK modulation waveform of the four pulses is as follows Figure 3 As shown, each pulse has Figure 2 shown.

[0049] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for generating a pulse intra-pulse dynamic modulation signal, characterized in that: The method comprises the following steps: Step S1: setting the pulse repetition interval PRI and pulse width PW of the pulse signal generating module; the pulse signal generating module generates a pulse switch signal; Step S2: The pulse switch signal is transmitted to the pulse segmentation module, and the modulation state number of the pulse segmentation module is set. The pulse segmentation module divides the pulse width into the number of modulation states. Divided equally symbol periods and generate M modulation time labels; Step S3: Setting the modulation mapping table of the logic control unit, calculating the phase offset control word or phase increment control word arrangement and combination corresponding to the bit data to be transmitted according to the PSK / FSK symbol mapping table in the modulation mapping table, and storing the combination in the double buffer register group; Step S4: The modulation time label is transmitted to the finite state machine. When the finite state machine detects the modulation time label in the pulse, it triggers the interrupt service program to read the phase offset control word and the phase increment control word and write them into the DDS signal generator. The DDS signal generator generates a continuous waveform based on the phase offset control word and the phase increment control word. After all the modulation time labels in the pulse arrive, the DDS signal generator generates a continuous modulation signal with multiple carrier frequency or phase transitions in a single pulse.

2. The method for generating a pulse intra-pulse dynamic modulation signal according to claim 1, wherein: In step S3, the modulation mapping table includes the modulation type, the number of bits to be transmitted, the PSK / FSK symbol mapping table, and the bit data to be transmitted; the modulation type determines whether the output pulse is PSK or FSK; the PSK / FSK symbol mapping table stores the phase offset control word or phase increment control word for various bit combinations; If it is PSK modulation, the symbol mapping table stores the phase offset control word; if it is FSK modulation, the symbol mapping table stores the phase increment control word; the bit data to be sent stores the binary data to be modulated by the system; during modulation, the logic control unit arranges the bit data to be sent into multiple bit combinations according to the PSK / FSK symbol mapping table, and queries the phase offset control word or phase increment control word in the PSK / FSK symbol mapping table according to the bit combination to obtain the phase offset control word or phase increment control word arrangement and combination corresponding to the bit data to be sent.

3. The method for generating a pulse intra-pulse dynamic modulation signal according to claim 2, wherein: Phase offset control word and phase increment control word Calculated by the following formula: Where N is the phase accumulator bit width of the DDS signal generator; is the DAC sampling rate; is the output signal frequency, is the starting phase of the output signal.

4. The method for generating a pulse intra-pulse dynamic modulation signal according to claim 1, wherein: In step S3, the double buffer register group includes a foreground buffer and a background buffer; the foreground buffer is used to store a phase offset control word or a phase increment control word to be modulated; The background buffer is used to store the phase offset control word or phase increment control word arrangement and combination corresponding to the bit data to be sent; When each modulation time label arrives, the front buffer is updated, and the front buffer reads a phase offset control word or a phase increment control word to be modulated from the back buffer.

5. The method for generating a pulse intra-pulse dynamic modulation signal according to claim 1, wherein: In step S4, at the pulse start time, the finite state machine is in an idle state waiting for the rising edge of the threshold signal; when the first Modulation time label When the interrupt service routine is triggered, the phase offset control word and phase increment control word corresponding to the current encoding are read from the foreground buffer of the double buffer register group, and written into the DDS signal generator to update the carrier frequency or phase; the DDS signal generator generates a continuous waveform based on the updated phase offset control word and phase increment control word until the next modulation moment label When all modulation time tags in the pulse are executed, a continuous modulation signal with multiple carrier frequency or phase transitions in a single pulse is generated.

Images