Semiconductor device and forming method thereof

Abstract

The invention provides a semiconductor device and a forming method thereof, and the method comprises the steps: carrying out the first ion implantation of an NMOS region of a Core device region and an NMOS region of an SRAM device region, so as to enable the threshold voltage of the NMOS region of the Core device region to be adjusted to a target value, and enabling the NMOS region of the SRAM device region to have a first threshold voltage value at the moment; determining a second threshold voltage value of a PMOS (P-channel Metal Oxide Semiconductor) region of the SRAM device region corresponding to the highest yield according to the first threshold voltage value and the relationship between the yield of the SRAM device and the threshold voltage; and performing second ion implantation on the PMOS region of the Core device region and the PMOS region of the SRAM device region to enable the threshold voltage of the PMOS region of the SRAM device region to reach a second threshold voltage value, and performing second threshold voltage adjustment on the PMOS region of the Core device region to enable the threshold voltage of the PMOS region of the Core device region to reach a target value. The method has the unexpected effects that the Core device region and the SRAM device region share the mask plate, so that the manufacturing cost is reduced, and meanwhile, the threshold voltage of the Core device region reaches the target value and the threshold voltage corresponding to the highest yield of the SRAM device region is ensured.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit technology, and particularly to a semiconductor device and a method for forming the same. Background Art

[0002] In integrated circuits, there are often various types of devices, such as Core (core) devices and SRAM (static random access memory) devices. When different devices share an ion implantation mask, the number of masks can be saved, thereby reducing the manufacturing cost of the integrated circuit. However, the doping doses required to adjust the threshold voltage for different devices are often different. When sharing an ion implantation mask, it is difficult to make the threshold voltages of different devices reach the optimal threshold voltage values simultaneously.

[0003] For the case where Core devices and SRAM devices share an ion implantation mask, the Core devices and SRAM devices manufactured by traditional processes have exactly the same doped ions. In this case, after the threshold voltage of the Core device is adjusted to the target value, since the yield of the SRAM device is closely related to the threshold voltage setting of the SRAM device, the threshold voltage of the SRAM device may be in the low-yield region, so that the Core device and the SRAM device cannot reach the optimal threshold voltage setting simultaneously. Summary of the Invention

[0004] The purpose of the present invention is to provide a semiconductor device and a method for forming the same to solve the problem that the Core device and the SRAM device cannot reach the optimal threshold voltage setting simultaneously.

[0005] To solve the above technical problems, the present invention provides a method for forming a semiconductor device, including: Providing a substrate, the substrate including a Core device region and an SRAM device region, the Core device region including a PMOS region and an NMOS region, and the SRAM device region including a PMOS region and an NMOS region; Performing a first ion implantation process to perform well doping and adjust the threshold voltage for the NMOS regions of the Core device region and the SRAM device region, so that the threshold voltage of the NMOS region of the Core device region is adjusted to the target value, and at this time, the NMOS region of the SRAM device region has a first threshold voltage value; Determining a second threshold voltage value of the PMOS region of the SRAM device region corresponding to the highest yield according to the first threshold voltage value of the NMOS region of the SRAM device region and the relationship between the yield of the SRAM device and the threshold voltage; Perform a second ion implantation process to perform well doping and threshold voltage adjustment on the PMOS regions of the Core device region and the SRAM device region, so that the threshold voltage of the PMOS region of the SRAM device region reaches a second threshold voltage value. At this time, the PMOS region of the Core device region has a third threshold voltage value; Perform a third ion implantation process to perform a second threshold voltage adjustment on the third threshold voltage value of the PMOS region of the Core device region, so that the threshold voltage of the PMOS region of the Core device region reaches the target value.

[0006] Optionally, in the third ion implantation process, calculate the ion type and ion implantation dose of the ion implantation according to the difference between the third threshold voltage value and the target value of the PMOS region of the Core device region.

[0007] Optionally, the implanted ion type in the third ion implantation process is P-type or N-type.

[0008] Optionally, after the second ion implantation process, if the third threshold voltage of the PMOS region of the Core device region is greater than the target value, P-type ions are implanted.

[0009] Optionally, after the second ion implantation process, if the third threshold voltage of the PMOS region of the Core device region is less than the target value, N-type ions are implanted.

[0010] Optionally, the third ion implantation process uses inclined angle ion implantation to inject only into the PMOS region of the Core device region.

[0011] Optionally, the distance between the peak of the implanted ion concentration in the third ion implantation process and the substrate surface is 20 nm to 50 nm.

[0012] Optionally, the PMOS region of the SRAM device region includes a pull-up transistor device region, the NMOS region of the SRAM device region includes a pull-down transistor device region and a transmission gate transistor device region, and the first threshold voltage value of the NMOS region of the SRAM device region is the threshold voltage of the pull-down transistor device region or the transmission gate transistor device region.

[0013] Optionally, the line width of the well doping ion implantation region of the PMOS region of the Core device region is much larger than the line width of the well doping ion implantation region of the pull-up transistor device region of the SRAM device region.

[0014] Based on the same inventive concept, the present invention also provides a semiconductor device prepared by using the formation method of the semiconductor device described in any one of the above.

[0015] In the method for forming a semiconductor device provided by the present invention, by performing a first ion implantation process, well doping and threshold voltage adjustment are carried out on the NMOS regions of the Core device region and the SRAM device region to adjust the threshold voltage of the NMOS region in the Core device region to a target value. At this time, the NMOS region in the SRAM device region has a first threshold voltage value; according to the first threshold voltage value of the NMOS region in the SRAM device region and the relationship between the yield of the SRAM device and the threshold voltage, the second threshold voltage value of the PMOS region in the SRAM device region corresponding to the highest yield is determined; a second ion implantation process is performed to carry out well doping and threshold voltage adjustment on the PMOS regions of the Core device region and the SRAM device region to make the threshold voltage of the PMOS region in the SRAM device region reach the second threshold voltage value. At this time, the PMOS region in the Core device region has a third threshold voltage value; a third ion implantation process is performed to perform a second threshold voltage adjustment on the third threshold voltage value of the PMOS region in the Core device region to make the threshold voltage of the PMOS region in the Core device region reach the target value. The unexpected effect of the present invention is that while sharing a mask between the Core device region and the SRAM device region to reduce the manufacturing cost, it is ensured that the threshold voltage of the Core device region reaches the target value and the threshold voltage corresponding to the highest yield of the SRAM device region is achieved. That is, under the condition of saving the mask and reducing the manufacturing cost, good Core device performance and SRAM yield are ensured. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Those of ordinary skill in the art will understand that the provided drawings are used to better understand the present invention and do not constitute any limitation to the scope of the present invention.

[0017] Figure 1 It is a flowchart of a method for forming a semiconductor device according to an embodiment of the present invention.

[0018] Figure 2 It is a partial top view schematic diagram of the Core device region according to an embodiment of the present invention.

[0019] Figure 3 It is a partial top view schematic diagram of the SRAM device region according to an embodiment of the present invention.

[0020] Figure 4 It is a schematic structural diagram of the Core device region and the SRAM device region when performing the first ion implantation process according to an embodiment of the present invention.

[0021] Figure 5 It is a relationship diagram between the SRAM device yield and the threshold voltage according to an embodiment of the present invention.

[0022] Figure 6It is a schematic structural diagram of the Core device area and the SRAM device area for performing the second ion implantation process according to an embodiment of the present invention.

[0023] Figure 7 It is a schematic structural diagram of the Core device area and the SRAM device area for performing the third ion implantation process according to an embodiment of the present invention.

[0024] In the accompanying drawings: 11 - Core device area; 11a - PMOS area of the Core device area; 11b - NMOS area of the Core device area; 12 - SRAM device area; 12a - Pull - up transistor device area; 12b - Transmission gate transistor device area; 12c - Pull - down transistor device area; 13 - Shallow trench isolation structure; 14 - Patterned first photoresist layer; 15 - Patterned second photoresist layer. Detailed implementation manners

[0025] To make the objectives, advantages and features of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that the accompanying drawings are all in very simplified forms and are not drawn to scale, only for the purpose of facilitating and clearly assisting in explaining the objectives of the embodiments of the present invention. In addition, the structures shown in the accompanying drawings are often part of the actual structures. In particular, the emphasis that each accompanying drawing needs to show is different, and sometimes different scales are used.

[0026] As used in the present invention, the singular forms "a", "an" and "the" include plural objects. The term "or" is generally used in the sense of including "and / or". The term "several" is generally used in the sense of including "at least one". The term "at least two" is generally used in the sense of including "two or more". In addition, the terms "first", "second", "third" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of the indicated technical features. Thus, the features defined with "first", "second", "third" may explicitly or implicitly include one or at least two of such features. In addition, as used in the present invention, when an element is disposed on another element, it generally only means that there is a connection, coupling, cooperation or transmission relationship between the two elements, and the two elements can be directly or indirectly connected, coupled, cooperated or transmitted through an intermediate element, rather than being understood as indicating or implying the spatial position relationship between the two elements, that is, an element can be in any position such as inside, outside, above, below or on one side of another element, unless otherwise explicitly stated in the content. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific situations.

[0027] Figure 1 It is a flowchart of a method for forming a semiconductor device according to an embodiment of the present invention. As Figure 1As shown in the figure, this embodiment provides a method for forming a semiconductor device, including: Step S10: Provide a substrate, the substrate includes a Core device region and an SRAM device region, the Core device region includes a PMOS region and an NMOS region, and the SRAM device region includes a PMOS region and an NMOS region; Step S20: Perform a first ion implantation process to perform well doping and threshold voltage adjustment on the NMOS regions of the Core device region and the SRAM device region, so as to adjust the threshold voltage of the NMOS region of the Core device region to a target value. At this time, the NMOS region of the SRAM device region has a first threshold voltage value; Step S30: According to the first threshold voltage value of the NMOS region of the SRAM device region and the relationship between the yield of the SRAM device and the threshold voltage, determine the second threshold voltage value of the PMOS region of the SRAM device region corresponding to the highest yield; Step S40: Perform a second ion implantation process to perform well doping and threshold voltage adjustment on the PMOS regions of the Core device region and the SRAM device region, so as to make the threshold voltage of the PMOS region of the SRAM device region reach the second threshold voltage value. At this time, the PMOS region of the Core device region has a third threshold voltage value; Step S50: Perform a third ion implantation process to perform a second threshold voltage adjustment on the third threshold voltage value of the PMOS region of the Core device region, so as to make the threshold voltage of the PMOS region of the Core device region reach the target value.

[0028] To make the above objects, features, and beneficial effects of the present invention more obvious and understandable, the following combines the accompanying Figures 2 to 7 description of the present invention will be described in detail with specific embodiments.

[0029] As Figure 2 and Figure 3 shown, Figure 2 is a partial top view schematic diagram of the Core device region of the embodiment of the present invention. Figure 3 is a partial top view schematic diagram of the SRAM device region of the embodiment of the present invention. Figure 2 and Figure 3This is the layout of a semiconductor device. The semiconductor device includes a Core device and an SRAM device, and the Core device and the SRAM device share the same ion implantation mask template, thus saving the number of mask templates and reducing the manufacturing cost. Correspondingly, the substrate includes a Core device region 11 and an SRAM device region 12. The Core device region 11 includes a PMOS region and an NMOS region, and the SRAM device region 12 also includes a PMOS region and an NMOS region. The device in the PMOS region of the SRAM device region 12 is a pull-up transistor (Pull-Up, PU) device region 12a. In terms of layout design, the line width CD1 of the well doping ion implantation region in the PMOS region 11a of the Core device region is much larger than the line width CD2 of the well doping ion implantation region in the pull-up transistor device region 12a of the SRAM device region.

[0030] As Figure 4 shown, a substrate is provided. The substrate can provide an operating platform for subsequent processes. It can be any substrate well-known to those skilled in the art for carrying semiconductor integrated circuit components, which can be a bare chip or a wafer processed by an epitaxial growth process. Specifically, the substrate is, for example, a silicon-on-insulator (SOI) substrate, a bulk silicon substrate, a germanium substrate, a germanium-silicon substrate, an indium phosphide (InP) substrate, a gallium arsenide (GaAs) substrate, or a germanium-on-insulator substrate, etc. In this embodiment, the substrate is a silicon substrate. The substrate includes a Core device region 11 and an SRAM device region 12. The Core device region 11 includes a PMOS region and an NMOS region, that is, the PMOS region 11a in the Core device region and the NMOS region 11b in the Core device region 11. The adjacent PMOS region 11a in the Core device region and the NMOS region 11b in the Core device region 11 are separated by a shallow trench isolation structure 13. The SRAM device region 12 includes a PMOS region and an NMOS region; the PMOS region of the SRAM device region includes a pull-up transistor (Pull-Up, PU) device region 12a, and the NMOS region of the SRAM device region includes a pass gate transistor (Pass Gate, PG) device region 12b and a pull-down transistor (Pull-Down, PD) device region 12c. And the pull-up transistor device region 12a is located between the pass gate transistor device region 12b and the pull-down transistor device region 12c, and the pull-up transistor device region 12a, the pass gate transistor device region 12b, and the pull-down transistor device region 12c are isolated by a shallow trench isolation structure 13.

[0031] Please continue to refer to Figure 4, the first ion implantation process is performed to perform well doping and threshold voltage adjustment on the NMOS region 11b in the Core device region and the NMOS region in the SRAM device region, so as to adjust the threshold voltage of the NMOS region 11b in the Core device region to the target value. At this time, the NMOS region in the SRAM device region has the first threshold voltage value. Specifically, a first photoresist layer is formed, the first photoresist layer covers the substrates in the Core device region and the SRAM device region, a lithography process is performed to form a patterned first photoresist layer 14, and the patterned first photoresist layer 14 exposes the NMOS region 11b in the Core device region and the NMOS region in the SRAM device region. The NMOS region in the SRAM device region is also the transmission gate transistor device region 12b and the pull-down transistor device region 12c. Using the patterned first photoresist layer 14 as a mask, the first ion implantation process is performed on the NMOS region 11b in the Core device region and the transmission gate transistor device region 12b and the pull-down transistor device region 12c in the SRAM device region. The first ion implantation process includes a well doping ion implantation process and an ion implantation process for adjusting the threshold voltage. The ion type of the first ion implantation process is P-type ions, so as to form a P well in the substrates of the NMOS region 11b in the Core device region and the transmission gate transistor device region 12b and the pull-down transistor device region 12c in the SRAM device region, and adjust the threshold voltage of the NMOS region 11b in the Core device region to the target value. At this time, the pull-down transistor device region 12c in the SRAM device region has the first threshold voltage value Vtlin_PD, and the transmission gate transistor device region 12b in the SRAM device region has the first threshold voltage value Vtlin_PG.

[0032] Figure 5 It is a graph showing the relationship between the yield of the SRAM device and the threshold voltage in the embodiment of the present invention. Figure 5 The abscissa in is the threshold voltage of PD, that is, the threshold voltage of the pull-down transistor in the SRAM device region. Figure 5 The ordinate in is the threshold voltage of PU, that is, the threshold voltage of the pull-up transistor in the SRAM device region. Pass ratio_32M refers to the yield of the SRAM device with a capacity of 32M. Different colors represent the size of the yield of the SRAM device. Blue represents a lower yield, and red represents a higher yield. According to the first threshold voltage value of the NMOS region in the SRAM device region, that is, the first threshold voltage value Vtlin_PD of the pull-down transistor device region 12c in the SRAM device region, or the first threshold voltage value Vtlin_PG of the transmission gate transistor device region 12b in the SRAM device region, and the relationship between the yield of the SRAM device and the threshold voltage, the second threshold voltage value of the PMOS region in the SRAM device region corresponding to the highest yield is determined. As Figure 5As shown, since the first threshold voltage value Vtlin_PD of the pull-down transistor device region 12c in the SRAM device region is the same as the first threshold voltage value Vtlin_PG of the transmission gate transistor device region 12b in the SRAM device region, in this embodiment, taking the first threshold voltage value Vtlin_PD of the pull-down transistor device region 12c in the SRAM device region as an example, the second threshold voltage value of the PMOS region in the SRAM device region corresponding to the highest yield is determined, that is, the second threshold voltage value Vtlin_PU of the pull-up transistor device region 12a in the SRAM device region.

[0033] As Figure 6 shown, perform a second ion implantation process to perform well doping and threshold voltage adjustment on the PMOS region 11a of the Core device region and the PMOS region of the SRAM device region, so that the threshold voltage of the PMOS region in the SRAM device region reaches the second threshold voltage value. At this time, the PMOS region of the Core device region has a third threshold voltage value. Specifically, form a second photoresist layer, the second photoresist layer covers the substrates of the Core device region 11 and the SRAM device region 12, perform a photolithography process to form a patterned second photoresist layer 15. The patterned second photoresist layer 15 exposes the PMOS region 11a of the Core device region and the PMOS region of the SRAM device region. The PMOS region of the SRAM device region is also the pull-up transistor device region 12a. Using the patterned second photoresist layer 15 as a mask, perform a second ion implantation process on the PMOS region 11a of the Core device region and the pull-up transistor device region 12a of the SRAM device region. The second ion implantation process includes a well doping ion implantation process and an ion implantation process for adjusting the threshold voltage. The ion type of the second ion implantation process is N-type ions to form an N well in the substrates of the PMOS region 11a of the Core device region and the pull-up transistor device region 12a of the SRAM device region, and make the threshold voltage of the pull-up transistor device region 12a in the SRAM device region reach the second threshold voltage value Vtlin_PU. At this time, the PMOS region 11a of the Core device region has a third threshold voltage value Vtlin_Core_PMOS. The third threshold voltage value Vtlin_Core_PMOS of the PMOS region 11a of the Core device region may be the target value of the PMOS region 11a of the Core device region, or may not reach the target value of the PMOS region 11a of the Core device region.

[0034] As Figure 7As shown, compare the difference between the third threshold voltage value Vtlin_Core_PMOS of the PMOS region 11a in the Core device region and the target value of the PMOS region 11a in the Core device region, and perform the third ion implantation process to perform a second threshold voltage adjustment on the third threshold voltage value of the PMOS region 11a in the Core device region, so that the threshold voltage of the PMOS region 11a in the Core device region reaches the target value. In the third ion implantation process, calculate the ion type and ion implantation dose of the ion implantation according to the difference between the third threshold voltage value and the target value of the PMOS region 11a in the Core device region. The implanted ions in the third ion implantation process are P-type or N-type. If the third threshold voltage Vtlin_Core_PMOS of the PMOS region 11a in the Core device region is greater than the target value, P-type ions are implanted to inversely consume the excess N-type ions. If the third threshold voltage Vtlin_Core_PMOS of the PMOS region 11a in the Core device region is less than the target value, N-type ions are implanted to increase the dose of N-type ions. The distance between the peak concentration of the implanted ions in the third ion implantation process and the surface of the substrate is 20 nm to 50 nm. If the ion implantation is too shallow, that is, too close to the surface of the substrate, it will affect the hole mobility on the substrate surface. If the ion implantation is too deep, it is not conducive to adjusting the threshold voltage. Since the threshold voltage of the pull-up transistor device region 12a in the SRAM device region has reached the threshold voltage corresponding to the highest yield of the SRAM device region, the third ion implantation process only implants the PMOS region 11a in the Core device region and cannot be implanted into the pull-up transistor device region 12a in the SRAM device region. The third ion implantation process uses angled ion implantation to only implant into the PMOS region 11a in the Core device region. Since the line width CD1 of the well doping ion implantation region of the PMOS region 11a in the Core device region is much larger than the line width CD2 of the well doping ion implantation region of the pull-up transistor device region 12a in the SRAM device region, according to the line width CD2 of the well doping ion implantation region of the pull-up transistor device region 12a in the SRAM device region and the thickness of the patterned second photoresist layer 15, the angle between the ion beam and the substrate is at least less than the first preset angle to avoid implanting into the pull-up transistor device region 12a in the SRAM device region. In other words, the angle between the ion beam and the vertical direction is at least greater than the second preset angle θ to avoid implanting into the pull-up transistor device region 12a in the SRAM device region. The first preset angle and the second preset angle are complementary, that is, the sum of the first preset angle and the second preset angle is 90°. In this embodiment, the second preset angle θ is, for example, 15° to 25°.Since the second photoresist layer 15 in the form of a pattern blocks the injection from reaching the pull-up transistor device region 12a in the SRAM device region, the third ion implantation process can increase or decrease the threshold voltage of the PMOS region 11a in the Core device region relative to the threshold voltage of the pull-up transistor device region 12a in the SRAM device region, so as to adjust the threshold voltage of the PMOS region 11a in the Core device region to reach the target value. It should be noted that the doping ions for adjusting the threshold voltage in the Core device region 11 and the SRAM device region 12 are uniformly distributed in the direction parallel to the channel surface, which can ensure good threshold voltage uniformity. Through the above method in this embodiment, while the threshold voltage of the Core device reaches the target value, the threshold voltage corresponding to the highest yield of the SRAM device is ensured, that is, good Core device performance and SRAM yield are ensured while saving the mask and reducing the manufacturing cost.

[0035] This embodiment also provides a semiconductor device, which is fabricated by using the formation method of the semiconductor device described in any one of the above. The semiconductor device includes a Core device and an SRAM device. The Core device and the SRAM device share a mask to reduce the manufacturing cost, and at the same time, ensure that the threshold voltage of the Core device reaches the target value and the threshold voltage corresponding to the highest yield of the SRAM device is ensured, that is, good Core device performance and SRAM yield are ensured while saving the mask and reducing the manufacturing cost.

[0036] In summary, in the method for forming a semiconductor device provided by the embodiment of the present invention, by performing a first ion implantation process, well doping and threshold voltage adjustment are performed on the NMOS regions of the Core device region and the SRAM device region, so that the threshold voltage of the NMOS region in the Core device region is adjusted to a target value. At this time, the NMOS region in the SRAM device region has a first threshold voltage value; according to the first threshold voltage value of the NMOS region in the SRAM device region and the relationship between the yield of the SRAM device and the threshold voltage, the second threshold voltage value of the PMOS region in the SRAM device region corresponding to the highest yield is determined; a second ion implantation process is performed to perform well doping and threshold voltage adjustment on the PMOS regions of the Core device region and the SRAM device region, so that the threshold voltage of the PMOS region in the SRAM device region reaches the second threshold voltage value. At this time, the PMOS region in the Core device region has a third threshold voltage value; a third ion implantation process is performed to perform a second threshold voltage adjustment on the third threshold voltage value of the PMOS region in the Core device region, so that the threshold voltage of the PMOS region in the Core device region reaches the target value. An unexpected effect of the present invention is that while sharing a mask for the Core device region and the SRAM device region to reduce the manufacturing cost, it is ensured that the threshold voltage of the Core device region reaches the target value and the threshold voltage corresponding to the highest yield of the SRAM device region is ensured. That is, under the condition of saving the mask and reducing the manufacturing cost, good Core device performance and SRAM yield are ensured.

[0037] It should be noted that the various embodiments in this specification are described in a progressive manner. Each embodiment focuses on the differences from other embodiments. The same or similar parts among the various embodiments can be referred to each other. In addition, the different parts among the various embodiments can also be combined and used with each other. The present invention does not limit this.

[0038] In addition, it should also be recognized that although the present invention has been disclosed above with preferred embodiments, the above embodiments are not intended to limit the present invention. For any person skilled in the art, without departing from the scope of the technical solution of the present invention, many possible changes and modifications can be made to the technical solution of the present invention by using the technical content disclosed above, or modified into equivalent embodiments with equivalent changes. Therefore, any simple modification, equivalent change and modification made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention still fall within the scope of the protection of the technical solution of the present invention.

Claims

1. A method for forming a semiconductor device, characterized in that, Comprising: Providing a substrate, the substrate including a Core device region and an SRAM device region, the Core device region including a PMOS region and an NMOS region, and the SRAM device region including a PMOS region and an NMOS region; Performing a first ion implantation process to perform well doping and threshold voltage adjustment on the NMOS regions of the Core device region and the SRAM device region, so as to adjust the threshold voltage of the NMOS region of the Core device region to a target value, and at this time, the NMOS region of the SRAM device region has a first threshold voltage value; According to the first threshold voltage value of the NMOS region of the SRAM device region and the relationship between the yield of the SRAM device and the threshold voltage, determining a second threshold voltage value of the PMOS region of the SRAM device region corresponding to the highest yield; Performing a second ion implantation process to perform well doping and threshold voltage adjustment on the PMOS regions of the Core device region and the SRAM device region, so as to make the threshold voltage of the PMOS region of the SRAM device region reach the second threshold voltage value, and at this time, the PMOS region of the Core device region has a third threshold voltage value; Performing a third ion implantation process to perform a second threshold voltage adjustment on the third threshold voltage value of the PMOS region of the Core device region, so as to make the threshold voltage of the PMOS region of the Core device region reach the target value.

2. The method for forming a semiconductor device according to claim 1, wherein In the third ion implantation process, calculating the ion type and ion implantation dose of the ion implantation according to the difference between the third threshold voltage value and the target value of the PMOS region of the Core device region.

3. The method for forming a semiconductor device according to claim 2, wherein, The implanted ion type in the third ion implantation process is P-type or N-type.

4. The method for forming a semiconductor device according to claim 3, wherein, After the second ion implantation process, if the third threshold voltage of the PMOS region of the Core device region is greater than the target value, then P-type ions are implanted.

5. The method for forming a semiconductor device according to claim 3, wherein, After the second ion implantation process, if the third threshold voltage of the PMOS region of the Core device region is less than the target value, then N-type ions are implanted.

6. The method for forming a semiconductor device according to claim 2, wherein, The third ion implantation process adopts inclined angle ion implantation to be implanted only into the PMOS region of the Core device region.

7. The method for forming a semiconductor device according to claim 6, wherein, The distance between the peak value of the implanted ion concentration in the third ion implantation process and the substrate surface is 20 nm to 50 nm.

8. The method for forming a semiconductor device according to claim 1, wherein, The PMOS region of the SRAM device region includes a pull-up transistor device region, the NMOS region of the SRAM device region includes a pull-down transistor device region and a transmission gate transistor device region, and the first threshold voltage value of the NMOS region of the SRAM device region is the threshold voltage of the pull-down transistor device region or the transmission gate transistor device region.

9. The method for forming a semiconductor device according to claim 8, wherein, The line width of the well doping ion implantation region of the PMOS region of the Core device region is much larger than the line width of the well doping ion implantation region of the pull-up transistor device region of the SRAM device region.

10. A semiconductor device, characterized in that, Prepared by using the method for forming a semiconductor device according to any one of claims 1 to 9.

Images