Semiconductor device having information structure

Abstract

A semiconductor device includes a lower structure having a conductive region and an information storage structure electrically connected to the conductive region. The information storage structure includes a lower electrode electrically connected to the conductive region, a dielectric layer on the lower electrode, and an upper electrode on the dielectric layer. The lower electrode comprises a first electrode material layer, a second electrode material layer and a third electrode material layer. The first electrode material layer extends over at least a portion of a side surface of the third electrode material layer and a bottom surface of the third electrode material layer. The second electrode material layer is between an upper portion of the first electrode material layer and the third electrode material layer.

Description

[0001] This application claims the benefit of priority to Korean Patent Application No. 10-2024-0005947, filed with the Korean Intellectual Property Office on January 15, 2024, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] The present inventive concept relates to a semiconductor device having an information storage structure. Background Art

[0003] As the demand for high performance, high speed, and / or multi-functionality of semiconductor devices increases, the integration degree of semiconductor devices has been increasing. When manufacturing a semiconductor device having a fine pattern corresponding to the trend of high integration of semiconductor devices, it may be necessary to implement a pattern having a relatively fine width or a fine separation distance. Summary of the Invention

[0004] According to an aspect of the present inventive concept, there is provided a semiconductor device including a lower structure having a conductive region and an information storage structure electrically connected to the conductive region. The information storage structure may include a lower electrode electrically connected to the conductive region, a dielectric layer on the lower electrode, and an upper electrode on the dielectric layer. The lower electrode may include a first electrode material layer, a second electrode material layer, and a third electrode material layer. The first electrode material layer may extend at least on a part of a side surface of the third electrode material layer and on a bottom surface of the third electrode material layer. The second electrode material layer may be between an inner surface of an upper portion of the first electrode material layer and the third electrode material layer.

[0005] According to another aspect of the present inventive concept, there is provided a semiconductor device including a lower structure having a conductive region and an information storage structure electrically connected to the conductive region. The information storage structure may include: a lower electrode electrically connected to the conductive region and extending away from the lower structure in a first direction; one or more support layers in contact with a side surface of the lower electrode, the one or more support layers extending in a second direction crossing the first direction; a dielectric layer on the lower electrode and the one or more support layers; and an upper electrode on the dielectric layer. The lower electrode may include a first structure and a second structure on the first structure. The first structure may include a first lower electrode layer and a third lower electrode layer. The second structure may include a first upper electrode layer integral or continuous with the first lower electrode layer, a third upper electrode layer integral or continuous with the third lower electrode layer, and an interlayer between the first upper electrode layer and the third upper electrode layer.

[0006] According to another aspect of the inventive concept, a semiconductor device is provided, which includes a lower structure having a conductive region and an information storage structure electrically connected to the conductive region. The information storage structure may include: a lower electrode electrically connected to the conductive region and extending away from the lower structure in a first direction; one or more support layers in contact with a side surface of the lower electrode, the one or more support layers extending in a second direction crossing the first direction; a dielectric layer on the lower electrode and the one or more support layers; and an upper electrode on the dielectric layer. The lower electrode may include a first electrode material layer having a cylindrical shape, a second electrode material layer on the first electrode material layer, and a third electrode material layer on the first electrode material layer and the second electrode material layer. The second electrode material layer may be on an inner surface within the cylindrical shape of an upper portion of the first electrode material layer. The third electrode material layer may include a lower portion, a middle portion, and an upper portion. The lower portion of the third electrode material layer may be surrounded by the first electrode material layer. The middle portion of the third electrode material layer may be surrounded by the second electrode material layer. The upper portion of the third electrode material layer may be surrounded by one of the one or more support layers. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The above and other aspects, features, and advantages of the inventive concept will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which: Figure 1 is a plan view of a semiconductor device according to an exemplary embodiment; Figure 2 is Figure 1 a vertical cross-sectional view of the semiconductor device shown in Figure 3 is Figure 2 an enlarged view of a part of the semiconductor device shown in Figure 4 and Figure 5 and Figure 6 are Figure 3 respectively cross-sectional views of the semiconductor device shown in Figure 7 and Figure 8 and Figure 9 and Figure 10 and Figure 11 are vertical cross-sectional views of a semiconductor device according to an exemplary embodiment; Figure 12A and Figure 12B are flowcharts illustrating a method of forming a semiconductor device according to an exemplary embodiment; Figure 13 and Figure 14 and Figure 15 and Figure 16 and Figure 17 andFigure 18 , Figure 19 , Figure 20 and Figure 21 are vertical cross-sectional views of sequential processes of a method of manufacturing a semiconductor device according to an exemplary embodiment; Figure 22 is a plan view of an integrated circuit device according to an exemplary embodiment; and Figure 23 is Figure 22 a vertical cross-sectional view of the integrated circuit device shown in DETAILED DESCRIPTION

[0008] Hereinafter, preferred exemplary embodiments of the inventive concept will be described with reference to the accompanying drawings. Terms such as "first", "second", etc. may be used herein only to distinguish one component, layer, direction, etc. from another component, layer, direction, etc. When used herein, the terms "comprising" and / or "including" indicate the presence of stated elements, but do not preclude the presence of additional elements. The term "and / or" includes any and all combinations of one or more of the related listed items. The term "connected" may be used herein to refer to a physical connection and / or an electrical connection. When a component or layer is referred to herein as being "directly" on, or "in direct contact with" or "directly connected to", there is no intervening component or layer.

[0009] Figure 1 is a plan view of a semiconductor device according to an exemplary embodiment. Figure 2 is Figure 1 a vertical cross-sectional view of the semiconductor device shown in

[0010] Referring to Figure 1 and Figure 2 , the semiconductor device 100 may include: a substrate 101 having an active region ACT, an isolation layer 110 defining the active region ACT in the substrate 101, a word line structure WLS buried and extending in the substrate 101, a bit line structure BLS extending on the substrate 101 to cross the word line structure WLS, and an information storage structure CAP on the bit line structure BLS. The word line structure WLS includes a word line WL, and the bit line structure BLS includes a bit line BL. The information storage structure CAP may store information and may be, for example, a capacitor structure of a DRAM. The semiconductor device 100 may further include a lower conductive pattern 150 on the active region ACT, an upper conductive pattern 160 on the lower conductive pattern 150, and an insulating pattern 165 passing through the upper conductive pattern 160.

[0011] The semiconductor device 100 may include a cell array such as a dynamic random access memory (DRAM). For example, a bit line BL may be connected to a first impurity region 105a of an active region ACT, and a second impurity region 105b of the active region ACT may be electrically connected to an information storage structure CAP on the upper conductive pattern 160 through a lower conductive pattern 150 and an upper conductive pattern 160.

[0012] The information storage structure CAP may be a capacitor capable of storing information in a memory such as a DRAM. The information storage structure CAP may be electrically connected to a conductive region (for example, the conductive region is included in a lower structure and corresponds to the lower conductive pattern 150 and the upper conductive pattern 160). Here, the lower structure may include a substrate 101, a word line structure WLS, and a bit line structure BLS.

[0013] The information storage structure CAP may include a lower electrode 170, a dielectric layer 180 on the lower electrode 170, and an upper electrode 190 on the dielectric layer 180. The information storage structure CAP may further include support layers SP1, SP2, and SP3.

[0014] The semiconductor device 100 may include a cell array region and a peripheral circuit region. A cell array is provided in the cell array region, and a peripheral circuit for driving memory cells provided in the cell array is provided in the peripheral circuit region. The peripheral circuit region may be provided to surround the cell array region.

[0015] The substrate 101 may include a semiconductor material (for example, a Group IV semiconductor, a Group III-V compound semiconductor, or a Group II-VI compound semiconductor). For example, the Group IV semiconductor may include silicon, germanium, or silicon germanium. The substrate 101 may further include impurities. The substrate 101 may be a silicon substrate, a silicon-on-insulator (SOI) substrate, a germanium substrate, a germanium-on-insulator (GOI) substrate, a silicon germanium substrate, or a substrate including an epitaxial layer.

[0016] The active region ACT may be defined in the substrate 101 through an isolation layer 110. In the substrate 101, the active region ACT may have a strip shape and may have an island shape extending in one direction. The extending direction of the active region ACT may be inclined or non-orthogonal to the extending directions of the word line WL and the bit line BL. The active regions ACT may be arranged parallel to each other, and an end portion of one active region ACT may be arranged adjacent to a central portion of another active region ACT adjacent to one active region ACT.

[0017] The active region ACT may have a first impurity region 105a and a second impurity region 105b, and the first impurity region 105a and the second impurity region 105b have a predetermined depth from the upper surface of the substrate 101. The first impurity region 105a and the second impurity region 105b may be spaced apart from each other. The first impurity region 105a and the second impurity region 105b may be used as the source region and the drain region of a transistor formed by the word line WL. The source region and the drain region formed by the first impurity region 105a and the second impurity region 105b caused by doping or ion implantation of substantially the same impurity may be interchangeably referred to according to the circuit configuration of the finally formed transistor. The impurity may include an impurity having a conductivity type opposite to that of the substrate 101. In an exemplary embodiment, in the source region and the drain region, the depths of the first impurity region 105a and the second impurity region 105b may be different from each other.

[0018] An isolation layer 110 may be formed using a shallow trench isolation (STI) process. The isolation layer 110 may electrically isolate the active regions ACT from each other while surrounding the active region ACT. The isolation layer 110 may be formed of an insulating material (e.g., silicon oxide, silicon nitride, or a combination thereof). The isolation layer 110 may have a plurality of regions, and the lower end depths of the plurality of regions vary according to the width of the trench in which the substrate 101 is etched.

[0019] A word line structure WLS may be disposed in a gate trench 115 extending in the substrate 101. Each of the word line structures WLS may include a gate dielectric layer 120, a word line WL, and a gate capping layer 125. As used herein, "gate (120, WL)" may be referred to as a structure including the gate dielectric layer 120 and the word line WL, and the word line WL may be referred to as the "gate electrode", and the word line structure WLS may be referred to as the "gate structure".

[0020] The word line WL may extend in a first direction X across the active region ACT. For example, a pair of word lines WL adjacent to each other may cross one active region ACT. The word line WL may form the gate of a buried channel array transistor (BCAT), but the inventive concept is not limited thereto. In an exemplary embodiment, the word line WL may be disposed on the upper portion of the substrate 101. The word line WL having a predetermined thickness may be disposed on the lower portion of the gate trench 115. The upper surface of the word line WL may be located at a height lower than the height of the upper surface of the substrate 101. As used herein, the term "height" may be defined based on or with respect to the substantially flat upper surface of the substrate 101.

[0021] The word line WL may include a conductive material (e.g., at least one of polysilicon (Si), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), and aluminum (Al)). As an example, the word line WL may include a lower pattern and an upper pattern formed of different materials. The lower pattern may include at least one of tungsten (W), titanium (Ti), tantalum (Ta), tungsten nitride (WN), titanium nitride (TiN), and tantalum nitride (TaN). The upper pattern may be a semiconductor pattern including polysilicon doped with P-type impurities or N-type impurities.

[0022] The gate dielectric layer 120 may be disposed on the bottom surface and the inner surface of the gate trench 115. The gate dielectric layer 120 may conformally cover the inner wall of the gate trench 115. The gate dielectric layer 120 may include at least one of silicon oxide, silicon nitride, and silicon oxynitride. The gate dielectric layer 120 may be, for example, an insulating film having a high dielectric constant or a silicon oxide film. In an exemplary embodiment, the gate dielectric layer 120 may be a layer formed by oxidizing the active region ACT or a layer formed by deposition.

[0023] The gate capping layer 125 may be disposed on the upper portion of the word line WL to fill the gate trench 115. The upper surface of the gate capping layer 125 may be at a height substantially the same as the upper surface of the substrate 101. The gate capping layer 125 may be formed of an insulating material (e.g., silicon nitride).

[0024] The bit line structure BLS may extend in a direction perpendicular to the word line WL (e.g., the second direction Y). The bit line structure BLS may include a bit line BL and a bit line capping pattern BC on the bit line BL.

[0025] The bit line BL may include a first conductive pattern 141, a second conductive pattern 142, and a third conductive pattern 143 stacked in sequence. The bit line capping pattern BC may be disposed on the third conductive pattern 143. A buffer insulating layer 128 may be disposed between the first conductive pattern 141 and the substrate 101, and a portion of the first conductive pattern 141 (hereinafter, the bit line contact pattern DC) may contact the first impurity region 105a of the active region ACT. The bit line BL may be electrically connected to the first impurity region 105a through the bit line contact pattern DC. The lower surface of the bit line contact pattern DC may be at a height lower than the upper surface of the substrate 101 and at a height higher than the upper surface of the word line WL. In one exemplary embodiment, the bit line contact pattern DC may be formed in the substrate 101 to be locally disposed in a bit line contact hole exposing the first impurity region 105a.

[0026] The first conductive pattern 141 may include a semiconductor material, such as polysilicon. The first conductive pattern 141 may be in direct contact with the first impurity region 105a. The second conductive pattern 142 may include a metal-semiconductor compound. The metal-semiconductor compound may be, for example, a layer obtained by siliciding a part of the first conductive pattern 141. For example, the metal-semiconductor compound may include cobalt silicide (CoSi), titanium silicide (TiSi), nickel silicide (NiSi), tungsten silicide (WSi), or other metal silicides. The third conductive pattern 143 may include a metal material, such as titanium (Ti), tantalum (Ta), tungsten (W), and aluminum (Al). In some example embodiments, the number, type of material, and / or stacking order of the conductive patterns forming the bit line BL may be changed in various ways.

[0027] The bit line covering pattern BC may include a first covering pattern 146, a second covering pattern 147, and a third covering pattern 148 sequentially stacked on the third conductive pattern 143. Each of the first to third covering patterns 146, 147, and 148 may include an insulating material (e.g., a silicon nitride film). The first to third covering patterns 146, 147, and 148 may be formed of different materials. Even when the first to third covering patterns 146, 147, and 148 include the same material, the first to third covering patterns 146, 147, and 148 may be distinguishable from each other by differences in physical properties. The thickness of the second covering pattern 147 may be respectively narrower than the thickness of the first covering pattern 146 and the thickness of the third covering pattern 148. In some example embodiments, the number of covering patterns and / or the type of material forming the bit line covering pattern BC may be changed in various ways.

[0028] The spacer structure SS may be disposed on opposite sidewalls of each of the bit line structures BLS to extend in a direction, for example, in the Y direction. The spacer structure SS may be disposed between the bit line structure BLS and the lower conductive pattern 150. The spacer structure SS may extend along the sidewalls of the bit line BL and the sidewalls of the bit line covering pattern BC. A pair of spacer structures SS disposed on opposite sides of one bit line structure BLS may have an asymmetric shape with respect to the bit line structure BLS. Each of the spacer structures SS may include a plurality of spacer layers, and in some example embodiments, each of the spacer structures SS may further include an air spacer.

[0029] The lower conductive pattern 150 may be connected to a region of the active region ACT (e.g., the second impurity region 105b). The lower conductive pattern 150 may be disposed between bit lines BL and between word lines WL. The lower conductive pattern 150 may pass through the buffer insulating layer 128 to be connected to the second impurity region 105b of the active region ACT. The lower conductive pattern 150 may be in direct contact with the second impurity region 105b. The lower surface of the lower conductive pattern 150 may be at a height lower than the height of the upper surface of the substrate 101 and may be at a height higher than the height of the lower surface of the bit line contact pattern DC. The lower conductive pattern 150 may be insulated from the bit line contact pattern DC by the spacer structure SS. The lower conductive pattern 150 may be formed of a conductive material. For example, the conductive material may include at least one of polysilicon (Si), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), and aluminum (Al). In an exemplary embodiment, the lower conductive pattern 150 may include multiple layers.

[0030] The metal-semiconductor compound layer 155 may be disposed between the lower conductive pattern 150 and the upper conductive pattern 160. When the lower conductive pattern 150 includes a semiconductor material, the metal-semiconductor compound layer 155 may be, for example, a layer obtained by siliciding a part of the lower conductive pattern 150. The metal-semiconductor compound layer 155 may include, for example, cobalt silicide (CoSi), titanium silicide (TiSi), nickel silicide (NiSi), tungsten silicide (WSi), or other metal silicides. In some exemplary embodiments, the metal-semiconductor compound layer 155 may be omitted.

[0031] The upper conductive pattern 160 may be disposed on the lower conductive pattern 150. The upper conductive pattern 160 may extend between the spacer structures SS to cover the upper surface of the metal-semiconductor compound layer 155. The upper conductive pattern 160 may include a barrier layer 162 and a conductive layer 164. The barrier layer 162 may cover the lower surface and the side surfaces of the conductive layer 164. The barrier layer 162 may include a metal nitride (e.g., at least one of titanium nitride (TiN), tantalum nitride (TaN), and tungsten nitride (WN)). The conductive layer 164 may include a conductive material (e.g., at least one of polysilicon (Si), titanium (Ti), tantalum (Ta), tungsten (W), ruthenium (Ru), copper (Cu), molybdenum (Mo), platinum (Pt), nickel (Ni), cobalt (Co), aluminum (Al), titanium nitride (TiN), tantalum nitride (TaN), and tungsten nitride (WN)).

[0032] The insulating pattern 165 may be disposed between the upper conductive patterns 160. The insulating pattern 165 may electrically insulate the upper conductive patterns 160 from each other. The insulating pattern 165 may include an insulating material (e.g., at least one of silicon oxide, silicon nitride, and silicon oxynitride).

[0033] The etch stop layer 168 may cover the insulating pattern 165 between the lower electrodes 170. The etch stop layer 168 may contact a lower region of the side surface of the lower electrode 170. The etch stop layer 168 may be disposed below the support layers SP1, SP2, and SP3. An upper surface of the etch stop layer 168 may include a portion that is in direct contact with the dielectric layer 180. The etch stop layer 168 may include at least one of, for example, silicon nitride, silicon oxynitride, and silicon carbonitride.

[0034] The lower electrode 170 may be disposed on the upper conductive pattern 160. The lower electrode 170 may have a columnar shape. The lower electrodes 170 may be spaced apart from each other in the X direction and the Y direction. In one exemplary embodiment, the lower electrodes 170 may be arranged to have a honeycomb structure. For example, as Figure 1 shown, the lower electrodes 170 may be respectively disposed at the vertices of a hexagonal pattern and at the center of the hexagonal pattern.

[0035] Figure 3 is Figure 2 an enlarged view of a portion of the semiconductor device shown in Figure 3 which may correspond to Figure 2 the region A shown in Figure 4 , Figure 5 and Figure 6 are respectively Figure 3 cross-sectional views of the semiconductor device taken along lines III-III', IV-IV', and V-V' shown in

[0036] Further referring to Figures 3 to 6 , each lower electrode 170 may include a first electrode material layer 172, a second electrode material layer 174, and a third electrode material layer 176. The first electrode material layer 172 may have a cylindrical shape that has an open upper end or an open upper surface. The first electrode material layer 172 may pass through the etch stop layer 168, and a lower surface of the first electrode material layer 172 may contact an upper surface of the upper conductive pattern 160. A height of the first electrode material layer 172 may be less than a height H1 of the lower electrode 170. The height may be measured along a direction extending away from the surface of the substrate 101 or the lower structure (e.g., a direction perpendicular to the surface of the substrate 101 or the lower structure). For example, an upper surface 173 of the first electrode material layer 172 may be disposed at a height lower than the height of the upper surface of the lower electrode 170. An outer surface of the first electrode material layer 172 may contact the support layers SP1, SP2, and SP3 and the dielectric layer 180. An inner surface of the first electrode material layer 172 (e.g., within the interior of the cylindrical shape) may contact the second electrode material layer 174 and the third electrode material layer 176. The first electrode material layer 172 may include at least one of titanium nitride (TiN), titanium oxide (TiO2), and titanium oxynitride (TiON).

[0037] The second electrode material layer 174 may be disposed on the inner surface of the first electrode material layer 172. Here, a part of the first electrode material layer 172 on which the second electrode material layer 174 is disposed may be referred to as an upper portion 172b, and a part of the first electrode material layer 172 disposed on the upper portion 172b (a part of the first electrode material layer 172 that does not have the second electrode material layer 174 thereon) may be referred to as a lower portion 172a. The second electrode material layer 174 may be disposed between the upper portion 172b of the first electrode material layer 172 and the third electrode material layer 176. For example, the second electrode material layer 174 may be disposed on the inner surface of the upper portion 172b of the first electrode material layer 172. In one exemplary embodiment, the second electrode material layer 174 may have a hollow cylindrical shape. For example, the second electrode material layer 174 may have a cylindrical shape having an open upper end and a lower end or an open upper surface and a lower surface.

[0038] In one exemplary embodiment, the upper end 175a of the second electrode material layer 174 may be disposed at the same height as the upper surface 173 of the first electrode material layer 172 (i.e., coplanar with the upper surface 173 of the first electrode material layer 172). The lower end 175b of the second electrode material layer 174 may be disposed at a height higher than the height of the lower surface of the first electrode material layer 172. In one exemplary embodiment, the distance or height H2 between the lower surface of the lower electrode 170 (that is, the lower surface of the first electrode material layer 172) and the lower end 175b of the second electrode material layer 174 may be about 0.4 times to about 0.6 times the distance or height H1 between the lower surface and the upper surface of the lower electrode 170. In one exemplary embodiment, the second electrode material layer 174 may have a constant or uniform thickness, but the inventive concept is not limited thereto. The thickness of the second electrode material layer 174 may be greater than 0 Å and less than about 20 Å.

[0039] The second electrode material layer 174 may include a material different from that of the first electrode material layer 172. In one exemplary embodiment, the second electrode material layer 174 may include a material having a dielectric constant higher than that of the dielectric layer 180. For example, the second electrode material layer 174 may include at least one of niobium nitride (NbN), niobium oxide (NbO x ), niobium oxynitride (NbON), tantalum nitride (TaN), tantalum oxide (TaO), lanthanum nitride (LaN), and lanthanum oxide (LaO). The second electrode material layer 174 may increase the capacitance of the information storage structure CAP.

[0040] The third electrode material layer 176 may be disposed on the first electrode material layer 172 and the second electrode material layer 174. A part of the third electrode material layer 176 may be surrounded by the first electrode material layer 172 and the second electrode material layer 174, and a part of the third electrode material layer 176 may be disposed at a height higher than the heights of the first electrode material layer 172 and the second electrode material layer 174. In other words, the first electrode material layer 172 may extend at least on a part of the side surface and the bottom surface of the third electrode material layer 176. Here, a part of the third electrode material layer 176 that contacts the inner surface of the first electrode material layer 172 (a part of the third electrode material layer 176 surrounded by the first electrode material layer 172) may be referred to as the lower part 176a. A part of the third electrode material layer 176 that contacts the inner surface of the second electrode material layer 174 (a part of the third electrode material layer 176 surrounded by the second electrode material layer 174) may be referred to as the middle part 176b. A part of the third electrode material layer 176 that is disposed at a height higher than the heights of the first electrode material layer 172 and the second electrode material layer 174 (a part of the third electrode material layer 176 surrounded by the support layer SP3) may be referred to as the upper part 176c. In one embodiment, the upper part 176c of the third electrode material layer 176 may be in direct contact with the first electrode material layer 172 and the second electrode material layer 174. As used herein, the term "surround" (or, "cover" or "fill") may not require completely surrounding (or, covering or filling) the described element or layer, but may, for example, refer to partially surrounding (or, covering or filling) the described element or layer.

[0041] The lower part 176a, the middle part 176b, and the upper part 176c of the third electrode material layer 176 have a first width W1, a second width W2, and a third width W3, respectively. The widths may be measured along a direction parallel to the surface of the substrate 101 or the underlying structure. The first width W1 may be greater than the second width W2 and may be less than the third width W3. The lower part 176a and the upper part 176c may be stacked with the second electrode material layer 174 in the vertical (e.g., Z) direction. When viewed along a line extending in a particular direction or in a plane perpendicular to the particular direction, the components or layers described as "stacked" in the particular direction may at least partially block each other. The third electrode material layer 176 may include a material having a strength or stiffness greater than the strength or stiffness of the first electrode material layer 172 and the second electrode material layer 174. In one exemplary embodiment, the third electrode material layer 176 may include titanium silicon nitride (TiSiN). The third electrode material layer 176 may prevent the lower electrode 170 from collapsing or bending.

[0042] As used herein, the lower portion 172a and the upper portion 172b of the first electrode material layer 172 may be referred to as the first lower electrode layer 172a and the first upper electrode layer 172b, respectively. The second electrode material layer 174 may be referred to as the insertion layer 174. The lower portion 176a of the third electrode material layer 176 may be referred to as the third lower electrode layer 176a, and the middle portion 176b and the upper portion 176c of the third electrode material layer 176 may also be referred to as the third upper electrode layers 176b and 176c.

[0043] The lower electrode 170 may include a first structure 170a and a second structure 170b. For example, the first lower electrode layer 172a of the first electrode material layer 172 and the third lower electrode layer 176a of the third electrode material layer 176 may form the first structure 170a of the lower electrode 170. The first upper electrode layer 172b of the first electrode material layer 172, the insertion layer 174, and the third upper electrode layers 176b and 176c may form the second structure 170b of the lower electrode 170. In one embodiment, the first upper electrode layer 172b may be integral or continuous with the first lower electrode layer 172a, and the third upper electrode layers 176b and 176c may be integral or continuous with the third lower electrode layer 176a.

[0044] According to an exemplary embodiment of the inventive concept, the second structure 170b of the lower electrode 170 may include the insertion layer 174, and the insertion layer 174 includes a material having a dielectric constant higher than that of the dielectric layer 180. Accordingly, the information storage structure CAP may have an increased or enlarged capacitance. The third lower electrode layer 176a of the third electrode material layer 176 included in the first structure 170a of the lower electrode 170 may have a first width W1, and the first width W1 may be greater than a second width W2 of the middle portion 176b of the third electrode material layer 176 disposed between the insertion layers 174 of the second structure 170b of the lower electrode 170. That is, in combination with the increased capacitance provided by the insertion layer 174 on the second (upper) structure 170b, the first (lower) structure 170a of the lower electrode 170 may not have the insertion layer 174 such that a greater first width W1 may be maintained. Accordingly, even when some of the support layers SP1, SP2, and SP3 do not directly contact the side surface of the first structure 170a and do not support the first structure 170a, bending of the first structure 170a of the lower electrode 170 may be prevented.

[0045] The dielectric layer 180 may cover side surfaces and upper surfaces of each of the lower electrodes 170 on the surface of the lower electrode 170. The dielectric layer 180 may be disposed between the lower electrode 170 and the upper electrode 190. The dielectric layer 180 may cover upper surfaces and lower surfaces of the support layers SP1, SP2, and SP3. The dielectric layer 180 may cover the upper surface of the etch stop layer 168.

[0046] The dielectric layer 180 may include a high-κ dielectric material, silicon oxide, silicon nitride, or a combination thereof. However, in some exemplary embodiments, the dielectric layer 180 may include: oxides, nitrides, silicides, oxynitrides, or silicon oxynitride including at least one or a combination of titanium (Ti), tantalum (Ta), hafnium (Hf), aluminum (Al), zirconium (Zr), and lanthanum (La) doped with fluorine (F).

[0047] The upper electrode 190 may cover the plurality of lower electrodes 170, the support layers SP1, SP2, and SP3, and the dielectric layer 180. The upper electrode 190 may fill the space between the plurality of lower electrodes 170 and the space between the support layers SP1, SP2, and SP3. The upper electrode 190 may be in direct contact with the dielectric layer 180.

[0048] In one exemplary embodiment, the upper electrode 190 may include a lower conductive layer 192 and an upper conductive layer 194 on the lower conductive layer 192. The lower conductive layer 192 may conformally cover the dielectric layer 180. The upper conductive layer 194 may fill the space between the plurality of lower electrodes 170 and the space between the support layers SP1, SP2, and SP3. The lower conductive layer 192 may include at least one of TiN, NbN, WN, VN, MoN, TaN, TiSiN, and TiCN. The upper conductive layer 194 may include a silicon material or a silicon germanium material.

[0049] The support layers SP1, SP2, and SP3 may include a first support layer SP1, a second support layer SP2 on the first support layer SP1, and a third support layer SP3 on the second support layer SP2. The support layers SP1, SP2, and SP3 may be spaced apart from the substrate 101 in a direction perpendicular to the upper surface of the substrate 101 (vertical direction). The support layers SP1, SP2, and SP3 may be in contact with the lower electrodes 170 and may extend in a direction parallel to the upper surface of the substrate 101 (horizontal direction).

[0050] The support layers SP1, SP2, and SP3 may be in direct contact with the lower electrodes 170 and the dielectric layer 180. The third support layer SP3 may have a thickness greater than the thicknesses of the first support layer SP1 and the second support layer SP2, but the inventive concept is not limited thereto. The support layers SP1, SP2, and SP3 may be layers for supporting the lower electrodes 170 having a high aspect ratio. The support layers SP1, SP2, and SP3 may each include, for example, at least one of silicon nitride and silicon oxynitride, or a material similar thereto. The number, thickness, and / or arrangement of the support layers SP1, SP2, and SP3 are not limited to those shown and may be changed in various ways in some exemplary embodiments.

[0051] The upper surface of the third support layer SP3 may be coplanar with the upper surface of the lower electrode 170. In one exemplary embodiment, the upper surface 173 of the first electrode material layer 172 and the upper end 175a of the second electrode material layer 174 may be disposed at the same height as the lower surface of the third support layer SP3 (i.e., coplanar with the height of the lower surface of the third support layer SP3), but the inventive concept is not limited thereto. In one exemplary embodiment, the upper portion 176c (e.g., the lower surface of the upper portion 176c) of the third electrode material layer 176 may be in direct contact with the upper surface 173 of the first electrode material layer 172 and the upper end 175a of the second electrode material layer 174. In one exemplary embodiment, the lower end 175b of the second electrode material layer 174 may be stacked with the first support layer SP1 in the horizontal direction, but the inventive concept is not limited thereto.

[0052] As Figure 1 shown, the support layers SP1, SP2, and SP3 may be disposed between the lower electrodes 170 and may support the lower electrodes 170. The support layers SP1, SP2, and SP3 may each include a support hole SH. In Figure 1 it, each support hole SH is shown to be disposed between four adjacent lower electrodes 170, but the inventive concept is not limited thereto. In some exemplary embodiments, the shape and arrangement of the support holes SH may be changed.

[0053] Figures 7 to 11 is a vertical cross-sectional view of a semiconductor device according to an exemplary embodiment.

[0054] Referring to Figure 7 it, the lower electrode 170 of the semiconductor device 100a may include a second electrode material layer 174 between the first electrode material layer 172 and the third electrode material layer 176. In one exemplary embodiment, the upper surface 173 of the first electrode material layer 172 and the upper end 175a of the second electrode material layer 174 may be disposed at a height different from the height of the lower surface of the third support layer SP3 (i.e., not coplanar with the height of the lower surface of the third support layer SP3) (e.g., at a height higher than the height of the lower surface of the third support layer SP3). The vertical height or thickness of the upper portion 176c of the third electrode material layer 176 may be less than the vertical height or thickness of the third support layer SP3.

[0055] Referring to Figure 8, the lower electrode 170 of the semiconductor device 100b may include a second electrode material layer 174 between the first electrode material layer 172 and the third electrode material layer 176. In one exemplary embodiment, the upper surface 173 of the first electrode material layer 172 and the upper end 175a of the second electrode material layer 174 may be disposed at a height different from the height of the lower surface of the third support layer SP3 (i.e., not coplanar with the height of the lower surface of the third support layer SP3) (e.g., at a height lower than the height of the lower surface of the third support layer SP3). The vertical height or thickness of the upper portion 176c of the third electrode material layer 176 may be greater than the vertical height or thickness of the third support layer SP3. The side surface of the upper portion 176c of the third electrode material layer 176 may be in contact with the dielectric layer 180.

[0056] Referring to Figure 9 , the lower electrode 170 of the semiconductor device 100c may include a second electrode material layer 174 between the first electrode material layer 172 and the third electrode material layer 176. In one exemplary embodiment, the second electrode material layer 174 may not have a constant thickness (i.e., may have a non-uniform thickness). For example, the thickness of the second electrode material layer 174 may decrease downward in the direction toward the substrate 101. The side surface of the second electrode material layer 174 may include a curved surface. The width of the middle portion 176b of the third electrode material layer 176 may decrease upward in the direction away from the substrate 101.

[0057] Referring to Figure 10 , the lower electrode 170 of the semiconductor device 100d may include a second electrode material layer 174 between the first electrode material layer 172 and the third electrode material layer 176. In one exemplary embodiment, the lower end 175b of the second electrode material layer 174 may be disposed at a height different from the height of the first support layer SP1 (e.g., at a height lower than the height of the first support layer SP1 with respect to the substrate 101). For example, the first structure 170a of the lower electrode 170 may be spaced apart from the support layers SP1, SP2, and SP3 and may not be in contact with the support layers SP1, SP2, and SP3 (e.g., the first structure 170a of the lower electrode 170 may be below the lowermost support layer SP1).

[0058] Referring to Figure 11, the lower electrode 170 of the semiconductor device 100e may include a second electrode material layer 174 between the first electrode material layer 172 and the third electrode material layer 176. In one exemplary embodiment, the lower end 175b of the second electrode material layer 174 may be disposed at a height different from that of the first support layer SP1 (e.g., at a height higher than that of the first support layer SP1). For example, the first structure 170a of the lower electrode 170 may be in contact with the first support layer SP1, and the second structure 170b of the lower electrode 170 may be spaced apart from the first support layer SP1 and may not be in contact with the first support layer SP1.

[0059] Figure 12A and Figure 12B is a flowchart of a method of forming a semiconductor device according to an exemplary embodiment.

[0060] Referring to Figure 12A , a method of manufacturing a semiconductor device according to an exemplary embodiment may include: forming a lower structure and a molding structure on a substrate (S10), forming a plurality of holes through the molding structure (S20), forming a lower electrode in the plurality of holes (S30), removing a part of the molding structure to form a support hole (S40), and forming a dielectric layer and an upper electrode (S50).

[0061] Further referring to Figure 12B , forming a lower electrode in the plurality of holes (S30) may include: depositing a first material layer in the plurality of holes (S31), depositing a second material layer on an upper portion of the first material layer (S32), etching the first material layer and the second material layer to form a first electrode material layer and a second electrode material layer (S33), and forming a third electrode material layer on the first electrode material layer and the second electrode material layer (S34).

[0062] Figures 13 to 21 is a vertical cross-sectional view of a sequential process of a method of manufacturing a semiconductor device according to an exemplary embodiment.

[0063] Referring to Figure 12A and Figure 13, a lower structure and a molding structure ST may be formed on a substrate (S10). An isolation layer 110 may be formed on the substrate 101 to define an active region ACT. Isolation trenches may be formed in the substrate 101, and the isolation layer 110 may fill the isolation trenches. In a plan view, the active region ACT may have an elongated strip shape extending in a direction inclined with respect to the extending direction of the word line WL. An impurity region may be formed on the upper portion of the active region ACT by performing an ion implantation process using the isolation layer 110 as an ion implantation mask. The active region ACT and the isolation layer 110 may be patterned to form gate trenches 115. A pair of gate trenches 115 may cross the active region ACT, but the inventive concept is not limited thereto. The impurity regions may also be isolated from each other through the gate trenches 115 to form a first impurity region 105a and a second impurity region 105b.

[0064] A gate dielectric layer 120 having a substantially conformal thickness may be formed on the inner surface of the gate trenches 115. Subsequently, the word line WL may be formed to at least fill a part of the gate trenches 115. The upper surface of the word line WL may be recessed below the upper surface of the active region ACT. A gate capping layer 125 may be formed on the word line WL by stacking an insulating layer on the substrate 101 to fill the gate trenches 115 and etching the insulating layer.

[0065] An insulating layer and a conductive layer may be sequentially formed on the front surface of the substrate 101 and patterned to form a buffer insulating layer 128 and a first conductive pattern 141 stacked in sequence. The buffer insulating layer 128 may be formed of at least one of silicon oxide, silicon nitride, and silicon oxynitride. A plurality of buffer insulating layers 128 may be formed to be spaced apart from each other. The first conductive pattern 141 may have a shape corresponding to the planar shape of the buffer insulating layer 128. The buffer insulating layer 128 may be formed to simultaneously cover the ends of two adjacent active regions ACT (i.e., adjacent second impurity regions 105b). Bit line contact holes may be formed by etching the upper portions of the isolation layer 110, the substrate 101, and the gate capping layer 125 using the buffer insulating layer 128 and the first conductive pattern 141 as etching masks. The bit line contact holes may expose the first impurity region 105a.

[0066] A bit line contact pattern DC capable of forming a bit line contact hole can be formed. Forming the bit line contact pattern DC may include: forming a conductive layer to fill the bit line contact hole, and performing a planarization process. As an example, the bit line contact pattern DC may be formed of polysilicon. The second conductive pattern 142, the third conductive pattern 143, and the first to third capping patterns 146, 147, and 148 may be sequentially formed on the first conductive pattern 141, and then the first to third conductive patterns 141, 142, and 143 may be sequentially etched using the first to third capping patterns 146, 147, and 148 as an etching mask. As a result, a bit line structure BLS including a bit line BL and a bit line capping pattern BC can be formed. The bit line BL includes the first to third conductive patterns 141, 142, and 143, and the bit line capping pattern includes the first to third capping patterns 146, 147, and 148.

[0067] The spacer structure SS can be formed on the side surface of the bit line structure BLS. The spacer structure SS can be formed of multiple layers. The fence insulating pattern 154 can be formed between the spacer structures SS. The fence insulating pattern 154 may include silicon nitride or silicon oxynitride. An opening exposing the second impurity region 105b can be formed by performing an anisotropic etching process using the fence insulating pattern 154 and the third capping pattern 148 as an etching mask.

[0068] The lower conductive pattern 150 can be formed on the lower part of the opening. The lower conductive pattern 150 can be formed of a semiconductor material (such as polysilicon). As an example, the lower conductive pattern 150 can be formed by forming a polysilicon layer to fill the opening and then performing an etch-back process.

[0069] The metal-semiconductor compound layer 155 can be formed on the lower conductive pattern 150. The formation of the metal-semiconductor compound layer 155 may include a metal layer deposition process and a heat treatment process.

[0070] The upper conductive pattern 160 can be formed on the upper part of the opening. Forming the upper conductive pattern 160 may include sequentially forming a barrier layer 162 and a conductive layer 164. Thereafter, a patterning process may be performed on the barrier layer 162 and the conductive layer 164 to form an insulating pattern 165 passing through the barrier layer 162 and the conductive layer 164. Accordingly, a lower structure including a substrate 101, a word line structure WLS, and a bit line structure BLS can be formed.

[0071] An etch stop layer 168 can be conformally formed on the lower structure, and a molding layer 118 and preliminary support layers SP1', SP2', and SP3' can be alternately stacked on the etch stop layer 168. The molding layer 118 and the preliminary support layers SP1', SP2', and SP3' can form a molding structure ST. The etch stop layer 168 can include an insulating material (e.g., at least one of silicon oxide, silicon nitride, silicon carbide, silicon carbon oxide, and silicon carbon nitride) having an etch selectivity under specific etching conditions. The molding layer 118 can be formed of silicon oxide, and the preliminary support layers SP1', SP2', and SP3' can be formed of silicon nitride.

[0072] Referring to Figure 12A and Figure 14 , a plurality of holes HL1 (S20) can be formed through the molding structure ST. An anisotropic etching process can be performed to form the plurality of holes HL1, and the etch stop layer 168 can be used as a stopper for stopping the etching process. The plurality of holes HL1 can pass through the etch stop layer 168 to expose the upper conductive pattern 160. The plurality of holes HL1 (the regions where the lower electrodes 170 are to be formed) can be spaced apart from each other at a predetermined interval in a plane, and thus can be formed in a regular arrangement as Figure 1 shown.

[0073] Thereafter, lower electrodes 170 (S30) can be formed in the plurality of holes HL1. Further referring to Figure 12B and Figure 15 , a first material layer 172p can be deposited in the plurality of holes HL1 (S31). The first material layer 172p can cover the inner walls of the plurality of holes HL1, the upper surface of the upper conductive pattern 160, and the upper surface of the preliminary support layer SP3'. The first material layer 172p can be conformally formed, and the first material layer 172p can have a constant thickness. The first material layer 172p can include titanium nitride (TiN).

[0074] Further referring to Figure 12B and Figure 16 , a second material layer 174p can be deposited on the upper portion of the first material layer 172p (S32). The second material layer 174p can be formed using a deposition method (such as a chemical vapor deposition (CVD) method or an atomic layer deposition method). In one exemplary embodiment, the second material layer 174p can be deposited to have a low step coverage. For example, the second material layer 174p can be deposited not on the lower portion of the first material layer 172p, but on the upper portion of the first material layer 172p and the upper surface of the preliminary support layer SP3'. That is, the second material layer 174p can extend along the upper portion of the first material layer 172p, but the lower portion of the first material layer 172p can be free of the second material layer 174p. The second material layer 174p can include at least one of niobium nitride (NbN), tantalum nitride (TaN), and lanthanum nitride (LaN).

[0075] Further referring to Figure 12B and Figure 17 , the first material layer 172p and the second material layer 174p can be etched to form the first electrode material layer 172 and the second electrode material layer 174 (S33). For example, an etch-back process can be performed to etch the upper portions of the first material layer 172p and the second material layer 174p, and the upper surface and side surfaces of the preliminary support layer SP3' can be exposed.

[0076] Further referring to Figure 12B , Figure 18 and Figure 19 , a third electrode material layer can be formed on the first electrode material layer 172 and the second electrode material layer 174 (S34). First, a third material layer 176p can be deposited on the first electrode material layer 172 and the second electrode material layer 174. The third material layer 176p can fill the plurality of holes HL1 and can cover the upper surface and side surfaces of the preliminary support layer SP3'.

[0077] Thereafter, the third material layer 176p can be etched to form the third electrode material layer 176. For example, an etch-back process can be performed to etch the upper portion of the third material layer 176p, and the upper surface of the preliminary support layer SP3' can be exposed. The upper surface of the third electrode material layer 176 can be coplanar with the upper surface of the preliminary support layer SP3'.

[0078] Referring to Figure 12A and Figure 20 , a support hole SH can be formed by removing a portion of the molding structure ST (S40). As Figure 20As shown, the support layers SP1, SP2, and SP3 having the support holes SH can be formed by etching the preliminary support layers SP1', SP2', and SP3'. In one exemplary embodiment, the support layers SP1, SP2, and SP3 may have support holes SH with the same pattern, but the inventive concept is not limited thereto. The molding layer 118 between the support layers SP1, SP2, and SP3 may be selectively removed to expose the lower electrode 170 including the first electrode material layer 172, the second electrode material layer 174, and the third electrode material layer 176. In the exemplary embodiment, the process of removing the molding layer 118 may be performed by a wet etching process using an etchant (e.g., a hydrogen fluoride (HF) solution). After removing the molding layer 118, an oxidation process may be performed. The oxidation process may be used to oxidize all or a part of the materials of the first electrode material layer 172 and the second electrode material layer 174. For example, the first electrode material layer 172 may include at least one of titanium nitride (TiN), titanium oxide (TiO2), and titanium oxynitride (TiON). The second electrode material layer 174 may include at least one of niobium nitride (NbN), niobium oxide (NbOx), niobium oxynitride (NbON), tantalum nitride (TaN), tantalum oxide (TaO), lanthanum nitride (LaN), and lanthanum oxide (LaO).

[0079] Referring to Figure 12A , Figure 21 and Figure 2 , a dielectric layer 180 and an upper electrode 190 may be formed (S50). The dielectric layer 180 may cover the side surfaces and the upper surfaces of each of the lower electrodes 170 and the upper surfaces and the lower surfaces of the support layers SP1, SP2, and SP3. The dielectric layer 180 may also cover the upper surface of the etch stop layer 168.

[0080] A lower conductive layer 192 may be conformally formed on the dielectric layer 180. Thereafter, an upper conductive layer 194 may be formed on the lower conductive layer 192 to form the upper electrode 190. The upper conductive layer 194 may fill the space between the lower electrodes 170 and may cover the lower electrodes 170 and the support layers SP1, SP2, and SP3.

[0081] Figure 22 is a plan view of an integrated circuit device according to an exemplary embodiment. Figure 23 is Figure 22 a vertical cross-sectional view of the integrated circuit device shown in

[0082] Referring to Figure 22 and Figure 23, the integrated circuit device 200 may include a substrate 210, a plurality of first wires 220, a channel layer 230, a gate electrode 240, a gate insulating layer 250, and an information storage structure 280. The integrated circuit device 200 may be a memory device including vertical channel transistors (VCTs). The vertical channel transistor may refer to a structure in which the channel length of the channel layer 230 extends in the vertical direction from the substrate 210.

[0083] An under-insulating layer 212 may be disposed on the substrate 210. On the under-insulating layer 212, a plurality of first wires 220 may be spaced apart from each other in a first direction (X direction) and may extend in a second direction (Y direction). A plurality of first insulating patterns 222 may be disposed on the under-insulating layer 212 to fill the spaces between the plurality of first wires 220. The plurality of first insulating patterns 222 may extend in the second direction (Y direction), and the upper surfaces of the plurality of first insulating patterns 222 may be disposed at the same height as the height of each of the upper surfaces of the plurality of first wires 220. The plurality of first wires 220 may serve as bit lines of the integrated circuit device 200.

[0084] In an exemplary embodiment, the plurality of first wires 220 may include doped polysilicon, metal, conductive metal nitride, conductive metal silicide, conductive metal oxide, or a combination thereof. For example, the plurality of first wires 220 may include doped polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrO x 、RuO x 、or a combination thereof, but the inventive concept is not limited thereto. The plurality of first wires 220 may include a single layer or multiple layers formed of the above materials. In an exemplary embodiment, the plurality of first wires 220 may include two-dimensional (2D) semiconductor materials. For example, the 2D semiconductor materials may include graphene, carbon nanotubes, or a combination thereof.

[0085] The channel layer 230 may be arranged in a matrix form spaced apart from each other in a first direction (X direction) and a second direction (Y direction) on a plurality of first wires 220. The channel layer 230 may have a first width in the first direction (X direction) and a first height in a third direction (Z direction), and the first height may be greater than the first width. For example, the first height may be about 2 to 10 times the first width, but the inventive concept is not limited thereto. The bottom of the channel layer 230 may serve as a first source / drain region (not shown), the upper portion of the channel layer 230 may serve as a second source / drain region (not shown), and a portion of the channel layer 230 between the first source / drain region and the second source / drain region may serve as a channel region (not shown). The first source / drain region and the second source / drain region may be vertically spaced apart from each other, and the channel region may be a vertical channel region.

[0086] In an exemplary embodiment, the channel layer 230 may include an oxide semiconductor. For example, the oxide semiconductor may include In x Ga y Zn z O, In x Ga y Si z O, In x Sn y Zn z O, In x Zn y O, Zn x O, Zn x Sn y O, Zn x O y N, Zr x Zn y Sn z O, Sn x O, Hf x In y Zn z O, Ga x Zn y Sn z O, Al x Zn y Sn z O, Yb x Ga y Zn z O, In x Ga yO or a combination thereof. The channel layer 230 may include a single layer or multiple layers of an oxide semiconductor. In some examples, the channel layer 230 may have a bandgap energy greater than that of silicon. For example, the channel layer 230 may have a bandgap energy of about 1.5 eV to about 5.6 eV. For example, when the channel layer 230 has a bandgap energy of about 2.0 eV to 4.0 eV, the channel layer 230 may have improved or optimal channel performance. For example, the channel layer 230 may be polycrystalline or amorphous, but the inventive concept is not limited thereto. In an exemplary embodiment, the channel layer 230 may include a 2D semiconductor material. For example, the 2D semiconductor material may include graphene, carbon nanotubes, or a combination thereof.

[0087] The gate electrode 240 may extend on opposite sidewalls of the channel layer 230 in a first direction (X direction). The gate electrode 240 may include a first sub-gate electrode 240P1 opposite to the first sidewall of the channel layer 230 and a second sub-gate electrode 240P2 opposite to the second sidewall of the channel layer 230, the second sidewall being opposite to the first sidewall. Since one channel layer 230 is disposed between the first sub-gate electrode 240P1 and the second sub-gate electrode 240P2, the integrated circuit device 200 may have a double-gate transistor structure. However, the inventive concept is not limited thereto, and the second sub-gate electrode 240P2 may be omitted, and only the first sub-gate electrode 240P1 opposite to the first sidewall of the channel layer 230 may be formed (and vice versa) to implement a single-gate transistor structure.

[0088] The gate electrode 240 may include doped polysilicon, metal, conductive metal nitride, conductive metal silicide, conductive metal oxide, or a combination thereof. For example, the gate electrode 240 may be formed of doped polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrO x 、RuO x or a combination thereof, but the inventive concept is not limited thereto.

[0089] The gate insulating layer 250 may surround the sidewalls of the channel layer 230 and may be disposed between the channel layer 230 and the gate electrode 240. For example, as Figure 23 shown, the entire sidewalls of the channel layer 230 may be surrounded by the gate insulating layer 250, and a part of the sidewalls of the gate electrode 240 may be in contact with the gate insulating layer 250. In other exemplary embodiments, the gate insulating layer 250 may extend in the extending direction of the gate electrode 240 (that is, the first direction (X direction)), and only two sidewalls of the sidewalls of the channel layer 230 opposite to the gate electrode 240 may be in contact with the gate insulating layer 250.

[0090] In an exemplary embodiment, the gate insulating layer 250 may be formed of a silicon oxide film, a silicon oxynitride film, a high-k dielectric film having a dielectric constant higher than that of the silicon oxide film, or a combination thereof. The high-k dielectric film may be formed of a metal oxide or a metal oxynitride. For example, the high-k dielectric film that may be used as the gate insulating layer 250 may be formed of HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, ZrO2, Al2O3, or a combination thereof, but the inventive concept is not limited thereto.

[0091] A plurality of second insulating patterns 232 may extend over the plurality of first insulating patterns 222 in a second direction (Y direction), and the channel layer 230 may be disposed between two adjacent second insulating patterns 232 among the plurality of second insulating patterns 232. In addition, between two adjacent second insulating patterns 232, a first buried layer 234 and a second buried layer 236 may be disposed in a space between two adjacent channel layers 230. The first buried layer 234 may be disposed on a bottom of the space between two adjacent channel layers 230, and the second buried layer 236 may be disposed on the first buried layer 234 to fill a remaining portion of the space between two adjacent channel layers 230. An upper surface of the second buried layer 236 may be disposed at a same height as an upper surface of the channel layer 230, and the second buried layer 236 may cover an upper surface of the gate electrode 240. Alternatively, the plurality of second insulating patterns 232 may be formed of a material layer continuous with the plurality of first insulating patterns 222, or the second buried layer 236 may be formed of a material layer continuous with the first buried layer 234.

[0092] The storage contact 260 may be disposed on the channel layer 230. The storage contact 260 may be vertically stacked with the channel layer 230 and may be arranged in a matrix form spaced apart from each other in a first direction (X direction) and a second direction (Y direction). The storage contact 260 may be formed of doped polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrO x 、RuO x or a combination thereof, but the inventive concept is not limited thereto. The upper insulating layer 262 may surround sidewalls of the storage contact 260 on the plurality of second insulating patterns 232 and the second buried layer 236.

[0093] The etch stop film 270 may be disposed on the upper insulating layer 262, and the information storage structure 280 may be disposed on the etch stop film 270. The information storage structure 280 may include a lower electrode 282, a dielectric layer 284, and an upper electrode 286.

[0094] The lower electrode 282 may pass through the etch stop film 270 to be electrically connected to the upper surface of the storage contact 260. The lower electrode 282 may be formed as a columnar electrode extending in the third direction (Z direction), but the inventive concept is not limited thereto. In an exemplary embodiment, the lower electrode 282 may be vertically stacked with the storage contact 260 and may be arranged in a matrix form spaced apart from each other in the first direction (X direction) and the second direction (Y direction). Optionally, a landing pad (not shown) may be further provided between the storage contact 260 and the lower electrode 282 such that the lower electrode 282 may be arranged to have a hexagonal shape.

[0095] In the integrated circuit device 200, the lower electrode 282 of the information storage structure 280 may include a first electrode material layer (corresponding to 172 in Figure 3 ), a second electrode material layer (corresponding to 174 in Figure 3 ), and a third electrode material layer (corresponding to 176 in Figure 3 ).

[0096] According to an exemplary embodiment of the inventive concept, the lower electrode of the information storage structure may include a second electrode material layer between the first electrode material layer and the third electrode material layer. The second electrode material layer may have a dielectric constant higher than that of the dielectric layer and may be provided on the inner surface of the upper portion of the first electrode material layer, thereby preventing bending of the lower electrode and increasing the capacitance of the information storage structure.

[0097] It will be understood that, unless otherwise indicated, spatial relative terms (such as "on", "above", "upper", "upper surface", "under", "below", "lower", "lower surface", "side surface", etc.) may be represented by reference numerals and referred to the accompanying drawings. It will be understood that such spatial relative terms are intended to cover different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is flipped, an element described as "under" or "below" other elements or features will be oriented "above" the other elements or features.

[0098] Although the exemplary embodiments have been shown and described above, it will be clear to those skilled in the art that modifications and variations can be made without departing from the scope of the inventive concept defined by the appended claims.

Claims

1. A semiconductor device, comprising: A lower structure having a conductive region; And An information storage structure electrically connected to the conductive region, Wherein the information storage structure includes: A lower electrode electrically connected to the conductive region; A dielectric layer on the lower electrode; and An upper electrode on the dielectric layer, Wherein the lower electrode includes a first electrode material layer, a second electrode material layer, and a third electrode material layer, Wherein the first electrode material layer extends at least on a part of the side surface and the bottom surface of the third electrode material layer, and Wherein the second electrode material layer is between the upper part of the first electrode material layer and the third electrode material layer.

2. The semiconductor device according to claim 1, wherein The first electrode material layer includes at least one of TiN and TiON, and the third electrode material layer includes TiSiN.

3. The semiconductor device according to claim 1, wherein, The second electrode material layer includes a material having a dielectric constant higher than that of the dielectric layer.

4. The semiconductor device according to claim 3, wherein, The second electrode material layer includes at least one of NbN, NbO, NbON, TaN, TaO, LaN, and LaO.

5. The semiconductor device according to claim 1, wherein, The thickness of the second electrode material layer is less than 20 Å.

6. The semiconductor device according to claim 1, wherein, The lower part of the first electrode material layer is in direct contact with the third electrode material layer.

7. The semiconductor device according to claim 1, wherein, The distance between the lower surface of the lower electrode and the lower end of the second electrode material layer is 0.4 to 0.6 times the height of the lower electrode measured between the lower surface and the upper surface of the lower electrode.

8. The semiconductor device according to claim 1, wherein, The third electrode material layer includes a lower part having a first width, an intermediate part on the lower part having a second width, and an upper part on the intermediate part having a third width, and wherein the first width is greater than the second width and less than the third width.

9. The semiconductor device according to claim 8, wherein, The lower part is in direct contact with the first electrode material layer, the intermediate part is in direct contact with the second electrode material layer, and the upper part is in direct contact with the first electrode material layer and the second electrode material layer.

10. The semiconductor device according to claim 8, wherein, The lower surface of the upper part is in direct contact with the upper surface of the first electrode material layer and the upper end of the second electrode material layer.

11. The semiconductor device according to claim 8, wherein, The width of the intermediate part decreases as the distance from the lower part increases.

12. The semiconductor device according to claim 1, wherein, The second electrode material layer has a cylindrical shape with an open upper end and a lower end.

13. The semiconductor device according to claim 1, wherein, The thickness of the second electrode material layer decreases as the distance from the bottom surface of the third electrode material layer decreases.

14. A semiconductor device, comprising: A lower structure having a conductive region; And An information storage structure electrically connected to the conductive region, Wherein the information storage structure includes: A lower electrode electrically connected to the conductive region, the lower electrode extending away from the lower structure in a first direction; One or more support layers on the side surface of the lower electrode, the one or more support layers extending in a second direction intersecting the first direction; A dielectric layer on the lower electrode and the one or more support layers; and An upper electrode on the dielectric layer, Wherein the lower electrode includes a first structure and a second structure on the first structure, Wherein the first structure includes a first lower electrode layer and a third lower electrode layer, and Wherein the second structure includes a first upper electrode layer continuous with the first lower electrode layer, a third upper electrode layer continuous with the third lower electrode layer, and an insertion layer between the first upper electrode layer and the third upper electrode layer.

15. The semiconductor device according to claim 14, wherein, The third upper electrode layer is in contact with the upper surface of the first upper electrode layer and the side surface of the insertion layer.

16. The semiconductor device according to claim 14, wherein, The one or more support layers include a lowermost support layer and an uppermost support layer, and wherein, the upper surface of the first upper electrode layer and the upper end of the insertion layer are lower than the upper surface of the uppermost support layer.

17. The semiconductor device according to claim 16, wherein, The lower end of the insertion layer is stacked with the lowermost support layer in a second direction.

18. The semiconductor device according to claim 16, wherein, The upper end of the insertion layer is non-coplanar with the lower surface of the uppermost support layer.

19. The semiconductor device according to claim 16, wherein, A part of the first structure of the lower electrode is lower than the lower surface of the lowermost support layer, and wherein, a part of the second structure of the lower electrode is higher than the lower surface of the uppermost support layer.

20. A semiconductor device, comprising: A lower structure having a conductive region; And An information storage structure electrically connected to the conductive region, wherein, the information storage structure includes: A lower electrode electrically connected to the conductive region, the lower electrode extending away from the lower structure in a first direction; One or more support layers on a side surface of the lower electrode, the one or more support layers extending in a second direction intersecting the first direction; A dielectric layer on the lower electrode and the one or more support layers; and An upper electrode on the dielectric layer, wherein, the lower electrode includes a first electrode material layer having a cylindrical shape, a second electrode material layer on the first electrode material layer, and a third electrode material layer on the first electrode material layer and the second electrode material layer, wherein, the second electrode material layer is on an inner surface of an upper portion of the first electrode material layer, wherein, the inner surface is within the cylindrical shape, wherein, the third electrode material layer includes a lower portion, a middle portion, and an upper portion, and wherein, the lower portion of the third electrode material layer is surrounded by the first electrode material layer, the middle portion of the third electrode material layer is surrounded by the second electrode material layer, and the upper portion of the third electrode material layer is surrounded by one of the one or more support layers.

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