Semiconductor device and method of manufacturing the same

Abstract

The invention relates to a semiconductor device and a manufacturing method thereof. An exemplary semiconductor device includes a conductive layer. The conductive layer includes a first conductive layer and a second conductive layer. The semiconductor device also includes an insulating structure over the first conductive layer and the second conductive layer. The insulating structure includes a first layer. The material of the first layer has a first etch rate that is less than an etch rate of the insulating material between the conductive layers. The semiconductor device also includes a first contact structure extending through a first portion of the first layer and connected to the first conductive layer. The semiconductor device also includes a second contact structure extending through a second portion of the first layer and connected to the second conductive layer.

Description

Technical Field

[0001] This disclosure relates to semiconductor devices and methods of manufacturing the same. Background Art

[0002] Semiconductor devices (e.g., memory devices) can have various structures to increase the density of memory cells and wires on a chip. For example, three-dimensional (3D) memory devices are attractive due to their ability to stack more layers within a similar footprint, thereby increasing array density. 3D memory devices typically include a memory array of memory cells and peripheral circuits for facilitating the operation of the memory array. Summary of the Invention

[0003] This disclosure describes methods, devices, systems, and techniques related to contact structures in semiconductor devices (e.g., 3D memory devices).

[0004] One aspect of this disclosure features a semiconductor device including a conductive layer, an insulating structure, a first contact structure, and a second contact structure. The conductive layer includes a first conductive layer and a second conductive layer. The insulating structure extends in a first direction over the first and second conductive layers. The insulating structure includes a first layer extending in the first direction. The material of the first layer has a first etch rate that is less than an etch rate of an insulating material located between the conductive layers. The first contact structure extends through a first portion of the first layer and is connected to the first conductive layer. The second contact structure extends through a second portion of the first layer and is connected to the second conductive layer. The first and second contact structures extend in a second direction perpendicular to the first direction. A length of the first contact structure in the second direction is less than a length of the second contact structure in the second direction. A thickness of the first portion of the first layer in the second direction is different from a thickness of the second portion of the first layer.

[0005] In some embodiments, the thickness of the first portion of the first layer is greater than the thickness of the second portion of the first layer.

[0006] In some embodiments, the first and second conductive layers extend different lengths in the first direction and form a stepped structure.

[0007] In some embodiments, the first layer has a stepped shape or a ramp shape.

[0008] In some embodiments, the insulating structure further includes a second layer including an insulating material, and the first and second contact structures extend through the first and second layers.

[0009] In some embodiments, the semiconductor device further includes a third conductive layer located above the first conductive layer and the second conductive layer, and a third contact structure extending through the second layer and connected to the third conductive layer, wherein the length of the third contact structure is greater than the length of the second contact structure.

[0010] In some embodiments, the semiconductor device includes a first stack and a second stack stacked along a second direction, the first stack includes a first conductive layer, and the second stack includes a second conductive layer.

[0011] In some embodiments, each of the first stack and the second stack includes alternating conductive layers and insulating layers along the second direction.

[0012] In some embodiments, the semiconductor device further includes a third contact structure connected to a third conductive layer included in the first stack. The length of the third contact structure is different from the length of the first contact structure. The first contact structure and the third contact structure extend through a first portion of the first layer.

[0013] In some embodiments, the semiconductor device further includes a fourth contact structure connected to a fourth conductive layer included in the first stack. The length of the fourth contact structure is different from the length of the second contact structure. The second contact structure and the fourth contact structure extend through a second portion of the first layer.

[0014] In some embodiments, the semiconductor device includes a plurality of contact structures extending through a first portion of the first layer along the second direction. Each of the plurality of contact structures has a corresponding length along the second direction and is connected to a corresponding one of the conductive layers included in the first stack. The number of the conductive layers included in the first stack is on the order of hundreds.

[0015] In some embodiments, the insulating structure further includes a third layer extending along a first direction. The third layer is located between the first layer and the first conductive layer. The material of the third layer has a second etching rate less than that of the material of the first layer.

[0016] In some embodiments, each of the first conductive layer and the second conductive layer has an edge portion that is thinner than an inner portion along the second direction.

[0017] In some embodiments, at the same position along the second direction, the first contact structure has a cross-sectional area different from that of the second contact structure.

[0018] In some embodiments, a semiconductor device includes a 3D NAND memory device that includes an array wafer. The array wafer includes an array region and a connection region. The semiconductor device includes a plurality of conductive layers extending through both the array region and the connection region. The plurality of conductive layers includes a first conductive layer and a second conductive layer. A first contact structure and a second contact structure extend through the connection region. The array region includes channel structures. The channel structures and the plurality of conductive layers form at least one memory cell array of the 3D NAND memory device.

[0019] In some embodiments, a semiconductor device includes a complementary metal oxide semiconductor (CMOS) wafer. The CMOS wafer includes a peripheral circuit of at least one memory cell array. The array wafer and the CMOS wafer are bonded together through a bonding interface.

[0020] In some embodiments, a semiconductor device includes a 3D dynamic random access memory (DRAM), and the first conductive layer and the second conductive layer include word lines of the 3D DRAM or bit lines of the 3D DRAM.

[0021] Another aspect of the present disclosure features a DRAM. The DRAM includes an array of DRAM memory cells, conductive layers, an insulating structure, a first contact structure, and a second contact structure. The conductive layers include a first conductive layer and a second conductive layer coupled to the array of DRAM memory cells. The insulating structure extends in a first direction over the first conductive layer and the second conductive layer. The insulating structure includes a first layer extending in the first direction. The material of the first layer has a first etching rate less than that of the insulating material located between the conductive layers. The first contact structure extends through a first portion of the first layer and is connected to the first conductive layer. The second contact structure extends through a second portion of the first layer and is connected to the second conductive layer. The first contact structure and the second contact structure extend in a second direction perpendicular to the first direction. The length of the first contact structure in the second direction is greater than the length of the second contact structure. The thickness of the first portion of the first layer is different from the thickness of the second portion of the first layer in the second direction. The first conductive layer is connected to at least a first semiconductor pillar extending in a third direction perpendicular to the first direction and the second direction. The second conductive layer is connected to at least a second semiconductor pillar extending in the third direction.

[0022] In some embodiments, the first conductive layer and the second conductive layer are word lines of the DRAM.

[0023] In some embodiments, the first conductive layer and the second conductive layer are bit lines of the DRAM.

[0024] Another aspect of the present disclosure features a method of manufacturing a semiconductor device, which includes: providing a semiconductor structure. The semiconductor structure includes a stack of conductive layers and first insulating layers that extend in a first direction and are alternately arranged with each other in a second direction perpendicular to the first direction. The conductive layers extend different lengths in the first direction and form a stepped structure of the stack. The method further includes: forming a second insulating layer extending in the first direction over the stack. The second insulating layer includes a first portion and a second portion. The thickness of the first portion of the second insulating layer is greater than the thickness of the second portion of the second insulating layer in the second direction. The material of the second insulating layer has a first etching rate less than that of the material of the first insulating layer. The method further includes: forming a contact structure extending in the second direction and connected to the stepped structure of the stack. The contact structure includes at least a first contact structure and a second contact structure. The length of the first contact structure in the second direction is less than the length of the second contact structure. The first contact structure extends through the first portion of the second insulating layer. The second contact structure extends through the second portion of the second insulating layer.

[0025] In some embodiments, forming the contact structure includes: forming contact holes extending in the second direction.

[0026] In some embodiments, forming the contact structure further includes: depositing bonding material on the inner surface of each of the contact holes and depositing conductive material into each of the contact holes.

[0027] In some embodiments, forming the second insulating layer includes: trimming and etching a portion of the second insulating layer into a stepped shape.

[0028] In some embodiments, the method further includes: depositing a third insulating layer on top of the second insulating layer. The third insulating layer includes a material having a second etching rate greater than that of the material of the second insulating layer. The contact holes extend through the third insulating layer.

[0029] In some embodiments, the method further includes: forming channel holes in an array region of the semiconductor structure, wherein the channel holes extend through the conductive layers. The method further includes: depositing a storage film in each of the channel holes to form a channel structure, wherein the channel structure and the conductive layers form at least one memory cell array.

[0030] Embodiments of the present disclosure may provide one or more of the following technical advantages and / or benefits. A 3D memory device may include multiple stacks, and each stack may include multiple conductive layers (e.g., word lines or bit lines of the 3D memory device) coupled to contact structures. As the number of stacks and conductive layers in the 3D memory device increases, the challenge of forming the contact structures also increases, and forming the contact structures may include an etching process followed by deposition of a conductive material. The techniques provided in the present disclosure enable the formation of contact structures for multiple stacks in one step instead of multiple steps (each step for one stack of the multiple stacks). The technique also uses an insulating structure to control the etching process such that consistent depressions are created at different depths in the conductive layers. Thus, without building complex landing structures in the conductive layers, the technique can prevent the contact structures from extending through the corresponding conductive layers, thereby improving the reliability and performance of the 3D memory device and reducing the manufacturing effort and cost.

[0031] The technique may be applied to various types of semiconductor devices, volatile memory devices (e.g., DRAM memory devices) or non-volatile memory (NVM) devices (e.g., NAND flash memory, NOR flash memory), resistive random access memory (RRAM), phase change memory (PCM) (e.g., phase change random access memory (PCRAM)), spin transfer torque (STT)-magnetoresistive random access memory (MRAM), and others. The technique may also be applied to charge trapping-based memory devices (e.g., silicon-oxide-nitride-oxide-silicon (SONOS) memory devices) and floating gate-based memory devices. The technique may be applied to three-dimensional (3D) memory devices. The technique may be applied to various memory types, such as single-level cell (SLC) devices, multi-level cell (MLC) devices (such as two-level cell devices), three-level cell (TLC) devices, four-level cell (QLC) devices, or five-level cell (PLC) devices. Additionally or alternatively, the technique may be applied to various types of devices and systems, such as secure digital (SD) cards, embedded multimedia cards (eMMC), or solid state drives (SSD), embedded systems, and others.

[0032] Details of one or more embodiments of the subject matter of the present disclosure are set forth in the accompanying drawings and the description below. Other features, aspects, and advantages of the subject matter will become apparent from the description, the drawings, and the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] The accompanying drawings, which are incorporated herein and form a part of this disclosure, illustrate aspects of the present disclosure and, together with the description, further serve to explain the principles of the present disclosure and enable a person of ordinary skill in the art to make and use the present disclosure.

[0034] Figures 1A - 1BA side view of an exemplary semiconductor structure is shown.

[0035] Figures 2A - 2B A side view of some other exemplary semiconductor structures is shown.

[0036] Figures 3A - 3B An exemplary three-dimensional (3D) dynamic random access memory (DRAM) device is shown.

[0037] Figures 4A - 4F A manufacturing process for forming an exemplary semiconductor structure is shown.

[0038] Figure 5 A flowchart of an exemplary process for forming a semiconductor structure is shown.

[0039] Figure 6 A block diagram of an exemplary system is shown.

[0040] Like reference numerals and names in the various figures indicate like elements. It should also be understood that the various exemplary embodiments shown in the figures are merely illustrative representations and are not necessarily drawn to scale. Detailed Description

[0041] Figure 1A A side view of a cross-section of an exemplary semiconductor structure 100a is shown. Figure 1B A side view of a cross-section of an exemplary semiconductor structure 100b is shown. The semiconductor structures 100a and 100b can be used to form a memory device, e.g., a 3D NAND memory device.

[0042] It should be noted that the X, Y, and Z axes (also referred to as the X, Y, and Z directions) are included Figures 1A - 1B to further illustrate the spatial relationships of the various components in the semiconductor device. The substrate of the semiconductor device includes two lateral surfaces that extend laterally in the X-Y plane: a top surface on the front side of the wafer on which components of the semiconductor device can be formed, and a bottom surface on the back side of the wafer opposite the front side. The Z direction is perpendicular to both the X direction and the Y direction. As used herein, when the substrate is in the lowest plane of the semiconductor device in the Z direction, whether a component (e.g., a layer or a device) is "on", "above", or "below" another component (e.g., a layer or a device) in the semiconductor device is determined in the Z direction (the vertical direction perpendicular to the X-Y plane, e.g., the thickness direction of the substrate) with respect to the substrate of the semiconductor device. The same concept for describing spatial relationships is applied throughout this disclosure.

[0043] As Figure 1AAs shown, the semiconductor structure 100a includes conductive layers 108a - 108j and an insulating structure 112 that electrically isolates the conductive layers 108a - 108j. Each of the conductive layers 108a - 108j may include one or more conductive materials, which include but are not limited to: tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), silicide, or any combination thereof. The insulating structure 112 may include one or more dielectric materials, which include but are not limited to: silicon oxide, silicon nitride, silicon oxynitride, low dielectric constant (low-k) dielectrics, or any combination thereof. The conductive layers 108a - 108j extend in a horizontal direction (e.g., the X direction) and may be included in a plurality of stacks (e.g., stacks 102, 104, and 106) stacked on top of each other in a vertical direction (e.g., the Z direction). The number of conductive layers in each stack may be the same or different. Each conductive layer includes a landing portion and a non-landing portion adjacent to each other in the X direction. For example, the conductive layer 108b located in stack 102 includes a landing portion 124 and a non-landing portion 122, and the conductive layer 108h located in stack 106 includes a landing portion 120 and a non-landing portion 118. The landing portion of each conductive layer is thicker than the non-landing portion of the conductive layer in the Z direction. The semiconductor structure 100a has two lateral surfaces 114 and 116. The semiconductor structure 100a further includes contact holes 110a - 110j. Each of the contact holes 110a - 110j extends from the surface 116 in the Z direction and extends into the landing portion of the corresponding conductive layer among the conductive layers 108a - 108j. The conductive layers 108a - 108j extend different lengths in the X direction to form a stepped structure. That is, the landing portions of the conductive layers 108a - 108j are located at different positions in the X direction. Thus, each of the contact holes 110a - 110j can extend into the corresponding conductive layer among the conductive layers 108a - 108j and bypass other conductive layers.

[0044] In some embodiments, contact holes 110a - 110j can be formed during a single etching process (e.g., dry etching). For example, a lithography process can be performed to pattern openings of contact holes 110a - 110j on surface 116 using an etching mask (e.g., a photoresist mask and / or a hard mask), and a dry etching process (e.g., reactive ion etching (RIE)) can be performed to etch the insulating structure 112 and the conductive layers 108a - 108j to form contact holes 110a - 110j. As the etching process proceeds, each of the contact holes 110a - 110j can start from surface 116, grow deeper and deeper, extend through the dielectric material located above the conductive layers 108a - 108j, and extend into the corresponding conductive layer. During the etching process, since the distances in the Z - direction between the conductive layers 108a - 108j and the surface 116 are different, and it may take longer to etch away the dielectric material located above the conductive layer farther from the surface 116, the contact holes 110a - 110j may reach the corresponding conductive layers at different times. Therefore, if a conductive layer is closer to the surface 116, the depression or space formed by the corresponding contact hole in the landing portion of the conductive layer has a larger size (or depth) in the Z - direction. For example, as Figure 1A shown, since the conductive layer 108h is closer to the surface 116, the depression in the landing portion 120 of the conductive layer 108h has a depth 126, and the depth 126 is greater than the depth 128 of the depression in the landing portion 124 of the conductive layer 108b. Having a thicker landing portion in the conductive layer can prevent the conductive layer from being penetrated by the corresponding contact hole. In other words, the thickness of the landing portion can serve as a buffer margin to accommodate depressions of various depths caused by the contact holes.

[0045] As Figure 1B shown, a semiconductor structure 100b can be formed from the semiconductor structure 100a by forming contact structures 130a - 130j in the contact holes 110a - 110j. Each of the contact structures 130a - 130j can include one or more conductive materials, which include but are not limited to: W, Co, Cu, Al, silicide, or any combination thereof. For example, the contact structures 130a - 130j can be formed by depositing the conductive material into the contact holes 110a - 110j. Since each of the contact holes 110a - 110j does not extend through the corresponding conductive layer (as described with respect to Figure 1AAs described, the contact structure formed in the contact hole does not extend through the corresponding conductive layer either. If the contact structure extends into the insulating structure 112 located below the conductive layer (e.g., closer to the surface 114) or even contacts another conductive layer, it may cause a short circuit, which may introduce leakage current or change the parasitic capacitance between the two conductive layers, thus affecting the electrical performance of the device formed by the semiconductor structure 100b.

[0046] Embodiments of the present disclosure provide techniques for forming a thicker landing portion for a conductive layer in a semiconductor structure, which can reduce the complexity and cost of the manufacturing process. As described in detail below, the techniques implemented herein can prevent the contact structure from extending through the corresponding conductive layer during manufacturing.

[0047] Figure 2A A side view showing a cross-section of an exemplary 3D memory device 200a is presented. In some embodiments, the 3D memory device 200a is a bonded chip that includes a first semiconductor structure 202 and a second semiconductor structure 204 stacked on top of the first semiconductor structure 202. According to some embodiments, the first semiconductor structure 202 and the second semiconductor structure 204 are joined at a bonding interface 206 therebetween. As Figure 2A shown, the first semiconductor structure 202 may include a substrate 201, which may include silicon (e.g., single-crystalline silicon (c-Si)), SiGe, GaAs, Ge, SOI, or any other suitable material.

[0048] The first semiconductor structure 202 of the 3D memory device 200a may include peripheral circuits 208 located on the substrate 201. In some embodiments, the peripheral circuits 208 are configured to control and sense the 3D memory device 200a. The peripheral circuits 208 may be any suitable digital, analog, and / or mixed-signal control and sensing circuits for facilitating the operation of the 3D memory device 200a, including but not limited to: page buffers, decoders (e.g., row decoders and column decoders), sense amplifiers, drivers (e.g., word line drivers), charge pumps, current or voltage references, or any active or passive components of such circuits (e.g., transistors, diodes, resistors, or capacitors).

[0049] As Figure 2AAs shown, the first semiconductor structure 202 of the 3D memory device 200a may further include a bonding layer 210 located at the bonding interface 206 and above the interconnect layer and the peripheral circuit 208. The bonding layer 210 may include a plurality of bonding contacts 211 and a dielectric that electrically isolates the bonding contacts 211. The bonding contacts 211 may include a conductive material, which includes but is not limited to: W, Co, Cu, Al, silicide, or any combination thereof. The remaining area of the bonding layer 210 may be formed of a dielectric, which includes but is not limited to: silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric, or any combination thereof. The bonding contacts 211 and the surrounding dielectric in the bonding layer 210 may be used for hybrid bonding.

[0050] Similarly, as Figure 2A shown, the second semiconductor structure 204 of the 3D memory device 200a may further include a bonding layer 212 located at the bonding interface 206 and above the bonding layer 210 of the first semiconductor structure 202. The bonding layer 212 may include a plurality of bonding contacts 213 and a dielectric that electrically isolates the bonding contacts 213. The bonding contacts 213 may include a conductive material, which includes but is not limited to: W, Co, Cu, Al, silicide, or any combination thereof. The remaining area of the bonding layer 212 may be formed of a dielectric, which includes but is not limited to: silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric, or any combination thereof. The bonding contacts 213 and the surrounding dielectric in the bonding layer 212 may be used for hybrid bonding. According to some embodiments, the bonding contacts 213 contact the bonding contacts 211 at the bonding interface 206.

[0051] As described in detail below, the second semiconductor structure 204 may be bonded on top of the first semiconductor structure 202 in a face-to-face manner at the bonding interface 206. In some embodiments, as a result of hybrid bonding (also referred to as "metal / dielectric hybrid bonding"), the bonding interface 206 is disposed between the bonding layers 210 and 212, which is a direct bonding technique (e.g., forming a bond between surfaces without using an intermediate layer such as solder or adhesive), and can obtain both metal-metal bonding and dielectric-dielectric bonding simultaneously. In some embodiments, the bonding interface 206 is where the bonding layers 212 and 210 meet and bond. In fact, the bonding interface 206 may be a layer with a specific thickness, which includes the top surface of the bonding layer 210 of the first semiconductor structure 202 and the bottom surface of the bonding layer 212 of the second semiconductor structure 204.

[0052] In some embodiments, the 3D memory device 200a is a NAND flash memory device, where the memory cells are provided in the form of an array of NAND memory strings. As Figure 2AAs shown, the second semiconductor structure 204 of the 3D memory device 200a may include an array of channel structures 224 that serves as an array of NAND memory strings. As Figure 2A shown, each channel structure 224 may extend vertically through a plurality of pairs, each of which includes a conductive layer 216 and an insulating layer 218. The interleaved conductive layers 216 and insulating layers 218 are part of the memory stack 214. The number of pairs of conductive layers 216 and insulating layers 218 in the memory stack 214 (e.g., 32, 64, 96, 128, 160, 192, 224, 256 or more) determines the number of memory cells in the 3D memory device 200a. It should be understood that in some embodiments, the memory stack 214 may have a multi-stack architecture (not shown in Figure 2A ) that includes a plurality of memory stacks stacked on top of each other. Examples of the multi-stack architecture will be described below with respect to Figure 2B . The number of pairs of conductive layers 216 and insulating layers 218 in each memory stack may be the same or different.

[0053] The memory stack 214 may include a plurality of interleaved conductive layers 216 and insulating layers 218. The conductive layers 216 and insulating layers 218 in the memory stack 214 may alternate in the vertical direction (e.g., the Z direction). In other words, except for the layers at the top or bottom of the memory stack 214, each conductive layer 216 may be adjacent to two insulating layers 218 on both sides, and each insulating layer 218 may be adjacent to two conductive layers 216 on both sides. The conductive layer 216 may include a conductive material, which includes but is not limited to: W, Co, Cu, Al, polysilicon, doped silicon, silicide, or any combination thereof. Each conductive layer 216 may include a gate electrode (gate line) surrounded by an adhesion layer and a gate dielectric layer. The gate electrode of the conductive layer 216 may extend laterally as a word line and terminate at one or more stepped structures of the memory stack 214. The insulating layer 218 may include a dielectric material, which includes but is not limited to: silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof.

[0054] As Figure 2A shown, the second semiconductor structure 204 of the 3D memory device 200a may further include a P-type doped semiconductor layer 220 located above the memory stack 214. The P-type doped semiconductor layer 220 may be an example of the "sidewall SEG" as described above. The P-type doped semiconductor layer 220 may include a semiconductor material, such as silicon. In some embodiments, the second semiconductor structure 204 of the 3D memory device 200a further includes an N well 221 located in the P-type doped semiconductor layer 220.

[0055] In some embodiments, each channel structure 224 includes a channel hole filled with a semiconductor layer (e.g., as the semiconductor channel 228) and a composite dielectric layer (e.g., as the storage film 226). In some embodiments, the semiconductor channel 228 includes silicon, such as amorphous silicon, polycrystalline silicon, or single-crystalline silicon. In some embodiments, the storage film 226 is a composite layer including a tunneling layer, a storage layer (also referred to as a “charge trapping layer”), and a blocking layer. The remaining space of the channel structure 224 may be partially or completely filled with a capping layer including a dielectric material (e.g., silicon oxide) and / or an air gap. The channel structure 224 may have a cylindrical shape (e.g., a columnar shape). According to some embodiments, the capping layer, the semiconductor channel 228, the tunneling layer, the storage layer, and the blocking layer of the storage film 226 are radially arranged from the center of the column to the outer surface in this order. The tunneling layer may include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer may include silicon nitride, silicon oxynitride, silicon, or any combination thereof. The blocking layer may include silicon oxide, silicon oxynitride, a high-k dielectric, or any combination thereof. In one example, the storage film 226 may include a composite layer of silicon oxide / silicon oxynitride / silicon oxide (ONO).

[0056] As Figure 2A shown, the second semiconductor structure 204 of the 3D memory device 200a may further include an insulating structure 230, and each insulating structure 230 vertically extends through the interleaved conductive layers 216 and insulating layers 218 of the memory stack 214. Each insulating structure 230 may also extend laterally to divide the channel structure 224 into a plurality of blocks. That is, the memory stack 214 may be divided into a plurality of memory blocks by the insulating structures 230, such that an array of the channel structures 224 can be divided into each memory block.

[0057] In some embodiments, as Figure 2A shown, the 3D memory device 200a may include a backside source contact 231 and a backside drain contact 232 located above the memory stack 214 and in contact with the N-well 221 and the P-type doped semiconductor layer 220, respectively.

[0058] As Figure 2A shown, the 3D memory device 200a may further include a BEOL (backend-of-line) interconnect layer 233, which is located above the source contacts 231 and 232 and electrically connected to the source contacts 231 and 232 for pad output, e.g., to transfer electrical signals between the 3D memory device 200a and an external circuit.

[0059] In some embodiments, the 3D memory device 200a further includes peripheral contacts, e.g., 246, 247, and 248, each of which extends vertically outside the memory stack 214. Each peripheral contact 246, 247, or 248 may have a depth greater than the depth of the memory stack 214 to extend vertically from the bonding layer 212 to the P-type doped semiconductor layer 220 in the peripheral region outside the memory stack 214.

[0060] As Figure 2A shown, the 3D memory device 200a further includes respective local contacts (also referred to as "C1") that are part of the interconnect structure and that directly contact structures in the memory stack 214. In some embodiments, the local contacts include channel local contacts 250, each of which is located below and in contact with the lower end of a corresponding channel structure 224. Each channel local contact 250 may be electrically connected to a bit line contact (not shown) for bit line fanout. In some embodiments, the local contacts further include contact structures 252a - 252d (also referred to as word line local contacts), each of the contact structures 252a - 252d being located below and in contact with a corresponding conductive layer 216 (including word lines) at the stepped structure of the memory stack 214 for word line fanout. The local contacts (e.g., channel local contacts 250 and word line local contacts 252a - 252d) may be electrically connected to the peripheral circuit 208 of the first semiconductor structure 202 at least through the bonding layers 212 and 210. Each of the local contacts (e.g., channel local contacts 250 and word line local contacts 252a - 252d) may include one or more conductive layers, such as a metal layer (e.g., W, Co, Cu, or Al) or a silicide layer surrounded by a bonding layer (e.g., TiN). The contact structures 252a - 252d have different lengths in the Z direction. For example, the length of the contact structure 252a is greater than the length of the contact structure 252d.

[0061] The 3D memory device 200a includes insulating structures 254 and 256. The insulating structure 254 may contact the stepped structure of the memory stack 214. In some embodiments, a protective layer 264 is located between the insulating structure 254 and the stepped structure of the memory stack 214. In some embodiments, the insulating structure 254 includes a dielectric material, which includes but is not limited to: silicon oxide, silicon nitride, silicon oxynitride, low dielectric constant (low-k) dielectrics, or any combination thereof. The insulating structures 254 and 256 are stacked along the Z direction. In some embodiments, an insulating structure 266 is located between the insulating structures 254 and 256. The insulating structure 256 may extend in the X direction. In some embodiments, the insulating structure 256 includes a layer 258 extending in the X direction. The layer 258 includes a material (e.g., a dielectric material) having an etching rate less than the etching rate of the dielectric material of the insulating structure 254. In some embodiments, the layer 258 includes a first portion 260 and a second portion 262 adjacent to each other in the X direction. The thickness (along the Y direction) of the first portion 260 is greater than the thickness (along the Y direction) of the second portion 262. The contact structures 252a - 252d extend through the layer 258. The longer contact structure (e.g., 252a) extends through the second portion 262, and the shorter contact structure (e.g., 252d) extends through the first portion 260.

[0062] Figure 2B A side view of a cross-section of an exemplary semiconductor structure 200b in accordance with some aspects of the present disclosure is shown. In some embodiments, the semiconductor structure 200b may be used to form a memory device (e.g., Figure 2Ain the semiconductor structure 204 of the 3D NAND memory device 200a). The stack 275 in the semiconductor structure 200b includes interleaved conductive layers 278a - 278j and insulating layers 280a - 280j. The stack 275 may include stacks 272, 274, and 276 stacked along a vertical direction (e.g., the Z direction). Each of the stacks 272, 274, and 276 includes alternating conductive layers and insulating layers along the Z direction (e.g., conductive layers 278a - 278d and insulating layers 280a - 280d in stack 272, conductive layers 278e - 278g and insulating layers 280e - 280g in stack 274, and conductive layers 278h - 278j and insulating layers 280h - 280j in stack 276). Each of the conductive layers 278a - 278j may include one or more conductive materials, which include but are not limited to: W, Co, Cu, Al, silicide, or any combination thereof. Each of the insulating layers 280a - 280j may include one or more dielectric materials, which include but are not limited to: silicon oxide, silicon nitride, silicon oxynitride, low - k dielectrics, or any combination thereof. The conductive layers 278a - 278j and the insulating layers 280a - 280j extend in a horizontal direction (e.g., the X direction). The number of conductive layers in each stack may be the same or different. In some embodiments, the stack 275 may be Figure 2A an example of the memory stack 214 of the 3D NAND memory device 200a in, and the conductive layers 278a - 278j may extend laterally as word lines of the 3D NAND memory device (e.g., Figure 2A the conductive layer 216 of the 3D NAND memory device 200a in). In some embodiments, each of the conductive layers 278a - 278j has an edge portion that is thinner than the inner portion along the Z direction. It should be understood that Figure 2B the number of the conductive layers 278a - 278j and the insulating layers 280a - 280j shown in is for illustration only, and any suitable number of conductive layers and insulating layers may be included in the stack 275.

[0063] The conductive layers 278a - 278j extend different lengths in the horizontal direction and form a "step structure" or "stepped cavity structure" in the stack 275. The terms "step structure", "stepped cavity structure" or similar terms refer to a structure having a stepped surface. In the present disclosure, a "stepped surface" refers to a set of surfaces that includes at least two horizontal surfaces (e.g., along the x - y plane) and at least two (e.g., first and second) vertical surfaces (e.g., along the z - axis), such that each horizontal surface is adjacent to a first vertical surface that extends upward from a first edge of the horizontal surface and is adjacent to a second vertical surface that extends downward from a second edge of the horizontal surface. A "step" or "step - up" refers to a vertical offset in the height of a set of adjacent surfaces. The semiconductor structure 200b has two lateral surfaces 271 and 273. The semiconductor structure 200b further includes contact structures 282a - 282j. The contact structures 282a - 282j extend in the Z - direction from the surface 273 and are connected to the respective conductive layers 278a - 278j. The stepped structure of the stack 275 enables each of the contact structures 282a - 282j to connect to one of the conductive layers 108a - 108j and bypass the other conductive layers. The contact structures 282a - 282j may have different lengths in the Z - direction.

[0064] The semiconductor structure 200b includes insulating structures 284 and 286. The insulating structure 284 may contact the stepped structure of the stack 275. In some embodiments (as Figure 2B shown), the insulating structure 284 and the insulating layers 280a - 280j of the stack 275 form a continuous structure. In some embodiments, the insulating structure 284 and the insulating layers 280a - 280j include the same dielectric material, which includes but is not limited to: silicon oxide, silicon nitride, silicon oxynitride, low - dielectric - constant (low - k) dielectrics, or any combination thereof. The insulating structures 284 and 286 are stacked in the Z - direction.

[0065] As Figure 2B shown, the insulating structure 286 extends in the X - direction. In some embodiments, the insulating structure 286 includes a first layer 290 that extends in the X - direction. The first layer 290 includes a material (e.g., a dielectric material) having an etch rate that is less than the etch rate of the dielectric material of the insulating structure 284. In some embodiments, the first layer 290 includes a first portion 294 and a second portion 296 that are adjacent to each other in the X - direction. The thickness (in the Z - direction) of the first portion 294 is greater than the thickness (in the Z - direction) of the second portion 296. In some embodiments, as Figure 2BAs shown, the first layer 290 has a stepped shape or a ladder shape. In some embodiments, the first layer 290 may have a ramp shape. The contact structures 282a - 282j extend through the insulating structure 286. Some of the contact structures among the contact structures 282a - 282j (e.g., the contact structures 282e - 282j) extend through the first layer 290. As Figure 2B shown, the longer contact structures (e.g., 282e - 282g) extend through the second portion 296, and the shorter contact structures (e.g., 282h - 282j) extend through the first portion 294.

[0066] In some embodiments, the insulating structure 286 includes a second layer 292 and a third layer 288. The second layer 292 shares the same surface 273 with the insulating structure 286 on one side, and contacts both the first layer 290 and the third layer 288 on the other side. The third layer 288 extends in the X direction and is adjacent to the insulating structure 284 and the first layer 290 on both sides. That is, the third layer 288 is located between the conductive layer 278j and the first layer 290. In some embodiments, the contact structures 282a - 282j extend through the second layer 292 and the third layer 288, and some of the contact structures among the contact structures 282a - 282j (e.g., 282a - 282d) bypass the first layer 290. In some embodiments, the second layer 292 and the insulating structure 284 include the same dielectric material. In some embodiments, the third layer 288 includes a material having an etching rate less than that of the material of the first layer 290.

[0067] In some embodiments, the contact structures 282a - 282j have different cross - sectional areas at the same position along the Z direction. For example, at the same position along the Z direction, the size of the cross - sectional area of the shorter contact structure (e.g., the contact structure 282h) is smaller than the size of the cross - sectional area of the longer contact structure (e.g., the contact structure 282a).

[0068] In some embodiments, the conductive layers located in the same stack are connected to the contact structures extending through the same portion of the first layer 290. For example, as Figure 2B shown, the conductive layers 278h, 278i, and 278j of the stack 276 are respectively connected to the contact structures 282h, 282i, and 282j, and the contact structures 282h, 282i, and 282j extend through the first portion 294 of the first layer 290. In some embodiments, the conductive layers located in the same stack are connected to the contact structures extending through different portions of the first layer 290. For example, the contact structures 282i and 282j may extend through the first portion 294 of the first layer 290, and the contact structure 282h may extend through the second portion 296 of the first layer 290 ( Figure 2Bnot shown).

[0069] It should be understood that although Figure 2B the first layer 290 in includes two parts, in some embodiments, the first layer 290 may include any suitable number of parts with different thicknesses (e.g., one part, two parts, or more than two parts). In some embodiments, the shorter contact structure and the longer contact structure of the semiconductor structure 200b may extend through the same part of the first layer 290. In some other embodiments, the thickness of the part through which the shorter contact structure of the first layer 290 extends is greater than the thickness of the part through which the longer contact structure of the first layer 290 extends.

[0070] In some embodiments, the insulating structure 286 may include a plurality of parts arranged along the X direction. The plurality of parts may have the same thickness along the Z direction. In some embodiments, the plurality of parts may be doped with different types of dopants, the same dopant with different doping concentrations, or a combination thereof. The plurality of parts may have different etching rates. In some embodiments, the shorter contact structure and the longer contact structure of the semiconductor structure 200b may extend through the same part of the insulating structure 286. In some other embodiments, the etching rate of the part through which the shorter contact structure of the insulating structure 286 extends is less than the etching rate of the part through which the longer contact structure of the insulating structure 286 extends.

[0071] In some embodiments, the semiconductor structure 200b is an array wafer of a 3D NAND memory device (e.g., Figure 2A the semiconductor structure 204 in). The array wafer may include an array region and a connection region. The conductive layers 278a - 278j may extend from the array region to the connection region along the X direction. The contact structures 282a - 282j extend through the connection region along the Z direction. In some embodiments, the array region includes channel structures. The channel structures and the conductive layers 278a - 278j form one or more memory cell arrays of the 3D NAND memory device. In some embodiments, the 3D NAND memory device further includes a complementary metal oxide semiconductor (CMOS) wafer (e.g., Figure 2A the semiconductor structure 202 in). The CMOS wafer may include peripheral circuits of one or more memory cell arrays. The array wafer and the CMOS wafer may be bonded together through a bonding interface (e.g., Figure 2A the bonding interface 206 in).

[0072] Figures 3A - 3B Exemplary 3D dynamic random access memory (DRAM) devices 300a and 300b are shown. As Figure 3AAs shown, the 3D DRAM device 300a includes word lines 302, word line extensions 304, semiconductor columns 306, cell storage capacitors 308, and bit lines 310. The word lines 302 extend in the Y direction. Each word line 302 is connected to a corresponding word line extension 304 that extends in the Z direction. Each word line 302 is connected to at least one semiconductor column 306 that extends in the X direction. Each semiconductor column 306 is connected to a corresponding cell storage capacitor 308. In some embodiments, each semiconductor column 306 is part of a vertical transistor. The 3D DRAM device 300a may include an array of DRAM memory cells. Each DRAM memory cell of the 3D DRAM device 300a may include one semiconductor column 306 and one cell storage capacitor 308 connected together. In some embodiments, Figure 2B the semiconductor structure 200b in may be a 3D DRAM device (e.g., Figure 3A the 3D DRAM device 300a in). Specifically, Figure 3A the word lines 302 in may be Figure 2B an example of the conductive layers 278a - 278j in, and Figure 3A the word line extensions 304 in may be Figure 2B an example of the contact structures 282a - 282j in.

[0073] As Figure 3B shown, the 3D DRAM device 300b includes word lines 312, bit lines 314, bit line extensions 316, semiconductor columns 318, and cell storage capacitors 320. The word lines 312 extend in the Z direction. The bit lines 314 extend in the Y direction. Each bit line 314 is connected to a corresponding bit line extension 316 that extends in the Z direction. Each bit line 314 is connected to at least one semiconductor column 318 that extends in the X direction. Each semiconductor column 318 is connected to a corresponding cell storage capacitor 320. In some embodiments, each semiconductor column 318 is part of a vertical transistor. The 3D DRAM device 300b may include an array of DRAM memory cells. Each DRAM memory cell of the 3D DRAM device 300b may include one semiconductor column 318 and one cell storage capacitor 320 connected together. In some embodiments, Figure 2B the semiconductor structure 200b in may be a 3D DRAM device (e.g., Figure 3B the 3D DRAM device 300b in). Specifically, Figure 3B the bit lines 314 in may be Figure 2B an example of the conductive layers 278a - 278j in, and Figure 3B the bit line extensions 316 in may be Figure 2B an example of the contact structures 282a - 282j in.

[0074] Figures 4A - 4F illustrates a manufacturing process for forming an exemplary semiconductor structure. Figures 4A - 4F Each structure shown in Figure 2A , 2B , 3A and 3B may be similar or identical to one of the semiconductor structures or devices 200a, 200b, 300a, and 300b or to a structure at an intermediate manufacturing process of the semiconductor structures or devices 200a, 200b, 300a, and 300b.

[0075] As Figure 4A shown, a stack 402 and an insulating structure 404 are formed. The stack 402 includes interleaved conductive layers 412a - 412j and insulating layers 414a - 414j extending in a horizontal direction (e.g., the X direction). The stack 402 may include stacks 406, 408, and 410 stacked in a vertical direction (e.g., the Z direction). Each of the stacks 406, 408, and 410 includes alternating conductive and insulating layers. Each of the conductive layers 412a - 412j may include one or more conductive materials, which include but are not limited to: W, Co, Cu, Al, silicide, or any combination thereof. Each of the insulating layers 414a - 414j may include one or more dielectric materials, which include but are not limited to: silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric, or any combination thereof. The number of conductive layers in each stack may be the same or different. In some embodiments, the stack 402 may be Figure 2A an example of the memory stack 214 of the 3D NAND memory device 200a in Figure 2B or an example of the stack 275 of the semiconductor structure 200b in Figure 2A , and the conductive layers 278a - 278j may be Figure 2B an example of the conductive layers 216 of the 3D NAND memory device 200a in Figure 4A or an example of the conductive layers 278a - 278j of the semiconductor structure 200b in

[0076] The insulating structure 404 contacts the stepped structure of the stack 402. As Figure 4AAs shown, the insulating structure 404 and the insulating layers 414a - 414j of the stack 402 can form a continuous structure. In some embodiments, there can be a protective layer (e.g., as shown in Figure 2A shown) between the insulating structure 404 and the stepped structure of the stack 402. In some embodiments, the insulating structure 404 and the insulating layers 414a - 414j include the same dielectric material, which includes but is not limited to: silicon oxide, silicon nitride, silicon oxynitride, low - dielectric - constant (low - k) dielectrics, or any combination thereof. In some embodiments, the insulating structure 404 can be formed by filling or depositing a dielectric material over the stack 402.

[0077] The insulating layer 416 extending in the horizontal direction can be deposited on top of the insulating structure 404 using one or more thin - film deposition processes (e.g., chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof). The insulating layer 416 can be an example of the third layer 288 of the insulating structure 286 in Figure 2B . The insulating layer 416 can include a material having an etch rate less than that of the dielectric material of the insulating structure 404.

[0078] As shown in Figure 4B shown, the insulating layer 418 extending in the horizontal direction is deposited on the insulating layer 416. One or more thin - film deposition processes (e.g., CVD, PVD, ALD, or any combination thereof) can be used to form the insulating layer 418. The insulating layer 418 can include a material having an etch rate less than that of the dielectric material of the insulating structure 404 but greater than that of the material of the insulating layer 416.

[0079] As shown in Figure 4C shown, a stepped shape or a stepped structure is formed on the insulating layer 418. In some embodiments, the stepped structure can be formed by performing a plurality of trimming and etching processes on the insulating layer 418. In some embodiments, the insulating layer 416 can prevent the insulating structure 404 from being etched away during the trimming and etching processes of the insulating layer 418. The stepped structure of the insulating layer 418 can include a plurality of portions having different thicknesses in the vertical direction. For example, the stepped structure of the insulating layer 418 can include both a portion 420 and a portion 422 in contact with the insulating layer 416. Portion 420 can be thicker than portion 422. In some embodiments, in the trimming and etching processes, a part of the insulating layer 418 in contact with the insulating layer 416 (such as Figure 4BAs shown, it can be etched away. In some embodiments, the ends of the conductive layers (e.g., 412e) located at a lower position in the vertical direction and the ends of the conductive layers (e.g., 412f) located at a higher position in the vertical direction are located under the same portion (e.g., 422) of the insulating layer 418. In some embodiments, the ends of the conductive layers (e.g., 412e) located at a lower position in the vertical direction are located under the thinner portion (e.g., 422) of the insulating layer 418, and the ends of the conductive layers (e.g., 412i) located at a higher position in the vertical direction are located under the thicker portion (e.g., 420) of the insulating layer 418.

[0080] As Figure 4D shown, an insulating layer 424 is formed over the insulating layer 416 and the insulating layer 418. The insulating layer 424 may include a material having an etching rate greater than that of the material of the insulating layer 418. The insulating layer 424 may be formed by depositing or filling a material on the tops of the insulating layer 416 and the insulating layer 418. In some embodiments, the insulating layer 424 and the insulating structure 404 may include the same material. In some embodiments, the insulating layer 424 includes a dielectric material, such as silicon oxide. In some embodiments, a planarization process (e.g., chemical mechanical polishing (CMP)) may then be performed to polish the top surface of the insulating layer 424.

[0081] As Figure 4E shown, contact holes 426a - 426j extending in the vertical direction are formed. The contact holes 426a - 426j may be formed during a single etching process. For example, a lithography process may be performed to pattern the openings of the contact holes 426a - 426j on the top surface of the insulating layer 424 using an etching mask (e.g., a photoresist mask and / or a hard mask), and a dry etching process (e.g., RIE) may be performed.

[0082] As the etching process proceeds, each of the contact holes 426a - 426j will start from the top surface of the insulating layer 424 and grow deeper and deeper, extending through the insulating layers 424, 418, and 416 (or only insulating layers 424 and 416) and the insulating structure 404, and extending into the corresponding conductive layers among the conductive layers 412a - 412j. Although some of the conductive layers are closer to the top surface of the insulating layer 424 (in the vertical direction), the insulating layer 418 can slow down the etching process of the contact holes that will reach these conductive layers. Specifically, before a contact hole (e.g., contact hole 426j) extends into a conductive structure (e.g., conductive structure 412j) closer to the top surface of the insulating layer 424, the contact hole must extend through a thicker portion (e.g., portion 420) of the insulating layer 418, which takes a longer time. Thus, the contact holes 426a - 426j can reach the corresponding conductive layers within an appropriate time period such that no contact hole extends through the corresponding conductive layer after the etching process.

[0083] As Figure 4F shown, a semiconductor structure 430 is formed including the stack 402, the insulating structure 404, the insulating layers 416, 418, and 424, and the contact structures 428a - 428j. The contact structures 428a - 428j can be formed by depositing a conductive material into each of the contact holes 426a - 426j. In some embodiments, a bonding and / or insulating material can be deposited on the inner surface of each of the contact holes 426a - 426j before depositing the conductive material.

[0084] In some embodiments, the semiconductor structure 430 is a 3D memory device and has an array region. The semiconductor structure 430 can include at least one memory cell array formed by channel structures (e.g., Figure 2A the channel structure 224 in

[0085] Figure 5 A flowchart of an exemplary process 500 for forming a semiconductor structure in accordance with some aspects of the present disclosure is shown. The semiconductor structure can be similar or identical to the semiconductor structure 204 in Figure 2A and the semiconductor structure 200b in Figure 2B or a part of the semiconductor structures 204 and 200b, or a structure at an intermediate manufacturing process of the semiconductor structures 204 and 200b. The process 500 can be described in view of Figures 4A - 4F The process 500 can include forming Figures 4A - 4FThe manufacturing process of the semiconductor structure in. It should be understood that the operations shown in process 500 are not exhaustive, and other operations can also be performed before, after, or between any of the operations shown. In addition, some of these operations can be performed simultaneously, or in a different order than that shown in Figure 5 shown in.

[0086] At operation 502, a semiconductor structure is provided. The semiconductor structure includes conductive layers (e.g., Figures 4A - 4F the conductive layers 412a - 412j in) that extend along a first direction (e.g., the horizontal direction) and are alternately arranged with respect to each other along a second direction (e.g., the vertical direction) perpendicular to the first direction, and a stack (e.g., Figures 4A - 4F the stack 402 in) of first insulating layers (e.g., Figures 4A - 4F the insulating layers 414a - 414j in). The conductive layers can extend different lengths along the first direction and form a stepped structure of the stack (e.g., the stepped structure of the stack 402). In some embodiments, the semiconductor structure further includes an insulating structure (e.g., Figure 4A the insulating structure 404 in) that contacts the stepped structure of the stack. The insulating structure and the first insulating layer can include the same dielectric material, which includes but is not limited to: silicon oxide, silicon nitride, silicon oxynitride, low dielectric constant (low-k) dielectrics, or any combination thereof. In some embodiments, the insulating structure can be formed by filling or depositing a dielectric material over the stack.

[0087] At operation 504, a second insulating layer (e.g., Figure 4D the insulating layer 418 in) that extends along the first direction is formed over the stack. The second insulating layer can include a first portion (e.g., Figure 4D the portion 420 in) and a second portion (e.g., Figure 4D the portion 422 in). The thickness of the first portion of the second insulating layer is greater than the thickness of the second portion of the second insulating layer along the second direction. The material of the second insulating layer has a first etching rate less than the material of the insulating structure. That is to say, if the insulating structure and the first insulating layer include the same material, the etching rate of the material of the second insulating layer is less than the etching rate of the material of the first insulating layer. In some embodiments, the second insulating layer can be formed by trimming and etching a portion of the second insulating layer into a stepped shape (e.g., as described with respect to Figure 4C ). In some embodiments, the semiconductor structure includes an additional insulating layer located between the second insulating layer and the insulating structure (e.g., Figure 4Cthe insulating layer 416). The additional insulating layer may include a material having an etching rate less than the etching rate of the dielectric material of the second insulating layer. Thus, the additional insulating layer can prevent the insulating structure from being etched away during the trimming and etching processes of the second insulating layer. In some embodiments, a third insulating layer (e.g., Figure 4D the insulating layer 424) may be deposited on top of the second insulating layer. The third insulating layer includes a material having a second etching rate greater than the material of the second insulating layer.

[0088] At operation 506, a contact structure (e.g., Figure 4F the contact structures 428a - 428j) extending in a second direction is formed. The contact structure is connected to the stepped structure of the stack. Specifically, each contact structure in the contact structure is connected to a corresponding conductive layer in the conductive layers located in the stepped structure of the stack. The contact structure includes at least a first contact structure (e.g., Figure 4F the contact structure 428h) and a second contact structure (e.g., Figure 4F the contact structure 428e). The length of the first contact structure in the second direction is less than the length of the second contact structure. The first contact structure extends through a first portion of the second insulating layer, and the second contact structure extends through a second portion of the second insulating layer.

[0089] In some embodiments, the contact structure is formed by forming contact holes (e.g., Figure 4E the contact holes 426a - 426j) extending in the second direction. Bonding material may be deposited on the inner surface of each of the contact holes. Then conductive material may be deposited into each of the contact holes.

[0090] In some embodiments, the semiconductor structure is a 3D memory device including an array region (e.g., Figure 2A the 3D NAND memory device 200a). Process 500 may include forming channel holes in the array region of the semiconductor structure. The channel holes may extend through the conductive layers. Process 500 may also include depositing a storage film (e.g., Figure 2A the storage film 226) in each of the channel holes to form a channel structure. The channel structure and the conductive layer may form at least one memory cell array of the 3D memory device.

[0091] Figure 6FIG. 600 is a block diagram of a system having one or more semiconductor devices (e.g., memory devices) in accordance with one or more embodiments of the present disclosure. The system 600 can be a mobile phone, a desktop computer, a laptop computer, a tablet computer, an in-vehicle computer, a game controller, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a storage device. As Figure 6 shown, the system 600 can include a host device 608 and a memory system 602 having one or more memory devices 604 and a memory controller 606. The host device 608 can include a processor (e.g., a central processing unit (CPU)) of the electronic device or a system-on-chip (SoC) (e.g., an application processor (AP)). The host device 608 can be configured to send data to or receive data from one or more memory devices 604.

[0092] The memory device 604 can be any memory device disclosed herein, such as a memory device based on Figures 2A - 2B , Figures 3A - 3B and Figures 4A - 4F semiconductor structures therein (e.g., a 3D memory device). In some embodiments, the memory device 604 includes a NAND flash memory. The memory controller 606 (also referred to as a controller circuit) is coupled to the memory device 604 and the host device 608. Consistent with embodiments of the present disclosure, the memory device 604 can include a plurality of conductive interconnects passing through a capping layer and contacting conductive pads located in a conductive pad layer, and the memory controller 606 can be coupled to the memory device 604 through at least one of the plurality of conductive interconnects. The memory controller 606 is configured to control the memory device 604. For example, the memory controller 606 can be configured to operate a plurality of channel structures via word lines. The memory controller 606 can manage data stored in the memory device 604 and communicate with the host device 608.

[0093] In some embodiments, the memory controller 606 is designed / configured to operate in a low duty cycle environment, such as a Secure Digital (SD) card, a Compact Flash (CF) card, a Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, mobile phones, etc. In some embodiments, the memory controller 606 is designed / configured to operate in a high duty cycle environment, such as a Solid State Drive (SSD) or an embedded multimedia card (eMMC), which is used as a data storage device for mobile devices such as smart phones, tablets, laptop computers, etc., and enterprise storage arrays. The memory controller 606 can be configured to control the operations of the memory device 604 (e.g., read operations, erase operations, and program (or write) operations). The memory controller 606 can also be configured to manage various functions regarding the data stored in or to be stored in the memory device 604, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some embodiments, the memory controller 606 is also configured to process error correction codes (ECCs) regarding the data read from or written to the memory device 604. The memory controller 606 can also perform any other appropriate functions, such as formatting the memory device 604.

[0094] The memory controller 606 can communicate with an external device (e.g., the host device 608) according to a specific communication protocol. For example, the memory controller 606 can communicate with the external device through at least one of various interface protocols, such as the USB protocol, the MMC protocol, the Peripheral Component Interconnect (PCI) protocol, the High-Speed PCI (PCI-E) protocol, the Advanced Technology Attachment (ATA) protocol, the Serial ATA protocol, the Parallel ATA protocol, the Small Computer System Interface (SCSI) protocol, the Enhanced Small Disk Interface (ESDI) protocol, the Integrated Drive Electronics (IDE) protocol, the FireWire protocol, etc.

[0095] The memory controller 606 and one or more memory devices 604 can be integrated into various types of storage devices, such as being included in the same package (e.g., a Universal Flash Storage (UFS) package or an eMMC package). That is to say, the memory system 602 can be implemented and packaged into different types of end-user electronic products. In Figure 6In one example shown, the memory controller 606 and the single memory device 604 may be integrated into the memory card 602. The memory card 602 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a Memory Stick, a Multimedia Card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), a UFS, etc.

[0096] Embodiments of the subject matter described in this disclosure, as well as the acts and operations, may be implemented in digital electronic circuitry, tangibly embodied computer software or firmware, computer hardware (including the structures disclosed in this disclosure and structural equivalents thereof), or in a combination of one or more of them. Embodiments of the subject matter described in this disclosure may be implemented as one or more computer programs, e.g., one or more modules of computer program instructions encoded on a computer program carrier for execution by, or to control the operation of, a data processing apparatus. The carrier may be a tangible non-transitory computer storage medium. Alternatively or additionally, the carrier may be an artificially generated propagated signal, e.g., a machine-generated electrical, optical, or electromagnetic signal, generated to encode information for transmission to an appropriate receiver apparatus for execution by the data processing apparatus. The computer storage medium may be a machine-readable storage device, a machine-readable storage substrate, a random or serial access memory device, or a combination of one or more of them, or a portion thereof. The computer storage medium is not a propagated signal.

[0097] It should be noted that references to "an embodiment", "embodiments", "exemplary embodiments", "some embodiments", etc. in this disclosure indicate that the described embodiments may include specific features, structures, or characteristics, but not every embodiment must include that specific feature, structure, or characteristic. Moreover, such phrases do not necessarily refer to the same embodiment. Additionally, when a specific feature, structure, or characteristic is described in connection with an embodiment, implementing such a feature, structure, or characteristic in connection with other embodiments is within the knowledge of those skilled in the relevant art, whether or not explicitly described.

[0098] Generally, terms can be understood, at least in part, from their usage in context. For example, depending at least in part on the context, the term "one or more" as used herein can be used to describe any feature, structure, or characteristic in a singular sense or can be used to describe a combination of features, structures, or characteristics in a plural sense. Similarly, depending at least in part on the context, terms such as "a" or "the" can also be understood to convey a singular usage or a plural usage. Additionally, again depending at least in part on the context, the term "based on" can be understood to not necessarily convey an exclusive set of factors but can allow for additional factors that are not necessarily explicitly described.

[0099] It should be readily understood that the meanings of "on", "above", and "over" in the present disclosure should be construed in the broadest manner such that "on" not only means "directly on something" but also includes the meaning of "on something" with intermediate features or layers therebetween. Further, "above" or "over" not only means "above something" or "over something" but can also include the meaning of "above something" or "over something" with no intermediate features or layers therebetween (i.e., directly on something).

[0100] In addition, for ease of description, spatial relative terms such as "under", "below", "lower", "above", "upper", etc. may be used herein to describe the relationship of one element or feature to another (or other) element or feature as shown in the figures. Except for the orientation depicted in the figures, the spatial relative terms are intended to encompass different orientations of the device during use or during a process step. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein may be interpreted accordingly.

[0101] As used herein, the term "substrate" refers to a material on which subsequent material layers are added. The substrate includes a "top" surface and a "bottom" surface. The top surface of the substrate is typically where a semiconductor device is formed, and thus, unless otherwise specified, the semiconductor device is formed on the top side of the substrate. The bottom surface is opposite the top surface, and thus, the bottom side of the substrate is opposite the top side of the substrate. The substrate itself can be patterned. The material added on top of the substrate can be patterned or can remain unpatterned. Additionally, the substrate can include various semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate can be made of a non-conductive material such as glass, plastic, or a sapphire wafer.

[0102] As used herein, the term "layer" refers to a portion of material that includes a region having a thickness. A layer has a top side and a bottom side, where the bottom side of the layer is relatively closer to the substrate and the top side is relatively farther from the substrate. A layer can extend over the entire underlying or overlying structure, or can have a scope that is less than the scope of the underlying or overlying structure. Additionally, a layer can be a region of a continuous structure that is uniform or non-uniform and has a thickness that is less than the thickness of the continuous structure. For example, a layer can be located between the top and bottom surfaces of the continuous structure or between any set of horizontal planes at the top and bottom surfaces. A layer can extend horizontally, vertically, and / or along a tapered surface. A substrate can be a layer, can include one or more layers therein, and / or can have one or more layers thereon, above it, and / or below it. A layer can include multiple layers. For example, an interconnect layer can include one or more conductive and contact layers (in which contacts, interconnect lines, and / or vertical interconnect access (VIA) are formed) and one or more dielectric layers.

[0103] As used herein, the term "nominal / nominally" refers to the expected or target value of a characteristic or parameter set for a component or process step during the design phase of a product or process, as well as a range of values above and / or below the expected value. As used herein, a range of values can be due to minor variations in the manufacturing process or tolerances. As used herein, the term "about" indicates a given amount of value that can vary based on a particular technology node associated with the subject semiconductor device. Based on a particular technology node, the term "about" can indicate a given amount of value that varies within, for example, 10 - 30% of that value (e.g., ±10%, ±20%, or ±30% of the value).

[0104] In the present disclosure, the terms "horizontal / horizontally / laterally / transversely" indicate nominally parallel to the lateral surface of the substrate, and the terms "vertical / vertically" indicate nominally perpendicular to the lateral surface of the substrate.

[0105] As used herein, the term "3D memory" refers to a three-dimensional (3D) semiconductor device having a string of memory cell transistors (referred to herein as a "memory string", such as a NAND string) with a vertical orientation on a laterally oriented substrate, such that the memory string extends in a vertical direction with respect to the substrate.

[0106] The present disclosure provides many different implementations or examples for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be restrictive. For example, in the following description, forming a first feature on or above a second feature may include embodiments in which the first feature and the second feature may be in direct contact, and may also include embodiments in which additional features may be formed between the first feature and the second feature such that the first feature and the second feature may not be in direct contact. Additionally, the present disclosure may repeat reference numerals and / or letters in the various examples. This repetition is for simplicity and clarity purposes and does not in itself indicate a relationship between the various embodiments and / or configurations being discussed.

[0107] The foregoing description of specific embodiments can be readily modified and / or adapted for various applications. Thus, such adaptations and modifications are intended to be within the meaning and scope of the equivalents of the disclosed embodiments based on the teachings and guidance presented herein.

[0108] Although the present disclosure contains many specific implementation details, these should not be construed as limitations on the scope of the claimed subject matter defined by the claims themselves, but rather as descriptions of features specific to particular embodiments of a particular invention. In the context of separate embodiments, certain features described in the present disclosure can also be implemented in combination in a single embodiment. Conversely, the various features described in the context of a single embodiment can also be implemented separately or in any suitable sub-combination in multiple embodiments. Additionally, although features may be described above as acting in certain combinations and even initially claimed as such, one or more features from the claimed combination can in some cases be deleted from the combination, and the claims can be directed to a sub-combination or a variation of the sub-combination.

[0109] Similarly, although operations are depicted in the figures in a particular order and recited in the claims, this should not be understood as requiring that such operations be performed in the particular order or sequence shown or that all of the illustrated operations be performed to achieve a desired result. In some cases, multitasking and parallel processing may be advantageous. Additionally, the separation of various system modules and components in the above embodiments should not be understood as required in all embodiments, and it should be understood that the described program components and systems can generally be integrated together in a single software product or packaged into multiple software products.

[0110] Specific embodiments of the subject matter have been described. Other embodiments are within the scope of the following claims. For example, the acts recited in the claims can be performed in a different order and still achieve the desired result. As one example, the processes depicted in the figures do not necessarily require the particular order or sequence shown to achieve the desired result. In some cases, multitasking and parallel processing may be advantageous.

[0111] The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.

Claims

1. A semiconductor device, comprising: A conductive layer, the conductive layer including a first conductive layer and a second conductive layer; An insulating structure, the insulating structure extending in a first direction over the first conductive layer and the second conductive layer, wherein the insulating structure includes a first layer extending in the first direction, and the material of the first layer has a first etching rate less than the etching rate of the insulating material between the conductive layers; A first contact structure, the first contact structure extending through a first portion of the first layer and connected to the first conductive layer; and A second contact structure, the second contact structure extending through a second portion of the first layer and connected to the second conductive layer, wherein the first contact structure and the second contact structure extend in a second direction perpendicular to the first direction, the length of the first contact structure in the second direction is less than the length of the second contact structure, wherein the thickness of the first portion of the first layer is different from the thickness of the second portion of the first layer in the second direction.

2. The semiconductor device according to claim 1, wherein, The thickness of the first portion of the first layer is greater than the thickness of the second portion of the first layer.

3. The semiconductor device according to claim 2, wherein, The insulating structure includes a second layer, the second layer including the insulating material, and the first contact structure and the second contact structure extend through the first layer and the second layer.

4. The semiconductor device according to claim 3, further comprising: A third conductive layer, the third conductive layer located over the first conductive layer and the second conductive layer; And A third contact structure, the third contact structure extending through the second layer and connected to the third conductive layer, Wherein the length of the third contact structure is greater than the length of the second contact structure.

5. The semiconductor device according to any one of claims 2 to 4, wherein, The semiconductor device includes a first stack and a second stack stacked in the second direction, the first stack including the first conductive layer, and the second stack including the second conductive layer.

6. The semiconductor device according to claim 5, wherein, The semiconductor device includes a third contact structure connected to a third conductive layer included in the first stack, and wherein the length of the third contact structure is different from the length of the first contact structure, and the first contact structure and the third contact structure extend through the first portion of the first layer.

7. The semiconductor device according to any one of claims 2 to 6, wherein, The insulating structure includes a third layer extending in the first direction, the third layer located between the first layer and the first conductive layer, and the material of the third layer has a second etching rate less than the material of the first layer.

8. The semiconductor device according to any one of claims 1 to 7, wherein, Each of the first conductive layer and the second conductive layer has an edge portion thinner than an inner portion in the second direction.

9. The semiconductor device according to any one of claims 1 to 8, wherein, At the same position in the second direction, the first contact structure has a cross-sectional area different from that of the second contact structure.

10. The semiconductor device according to any one of claims 1 to 9, wherein, The semiconductor device includes a three-dimensional (3D) NAND memory device, the three-dimensional (3D) NAND memory device including an array wafer, and the array wafer including an array region and a connection region, Among them, the semiconductor device includes a plurality of conductive layers extending through both the array region and the connection region, the plurality of conductive layers including the first conductive layer and the second conductive layer, and the first contact structure and the second contact structure extend through the connection region, and Among them, the array region includes a channel structure, and the channel structure and the plurality of conductive layers form at least one memory cell array of the 3D NAND memory device.

11. The semiconductor device according to claim 10, wherein, The semiconductor device includes a complementary metal oxide semiconductor (CMOS) wafer, the CMOS wafer includes a peripheral circuit of the at least one memory cell array, and the array wafer and the CMOS wafer are bonded together through a bonding interface.

12. The semiconductor device according to any one of claims 1 to 11, wherein, The semiconductor device includes a three-dimensional (3D) dynamic random access memory (DRAM), and Among them, the first conductive layer and the second conductive layer include word lines of the 3D DRAM or bit lines of the 3D DRAM.

13. A dynamic random access memory (DRAM) comprising: An array of DRAM memory cells; A conductive layer, the conductive layer including a first conductive layer and a second conductive layer coupled to the array of DRAM memory cells; An insulating structure, the insulating structure extending in a first direction over the first conductive layer and the second conductive layer, wherein the insulating structure includes a first layer extending in the first direction, and the material of the first layer has a first etching rate less than that of the insulating material located between the conductive layers; A first contact structure, the first contact structure extending through a first portion of the first layer and connected to the first conductive layer; and A second contact structure, the second contact structure extending through a second portion of the first layer and connected to the second conductive layer, wherein the first contact structure and the second contact structure extend in a second direction perpendicular to the first direction, the length of the first contact structure in the second direction is greater than the length of the second contact structure, the thickness of the first portion of the first layer is different from the thickness of the second portion of the first layer in the second direction, the first conductive layer is connected to at least a first semiconductor pillar extending in a third direction perpendicular to the first direction and the second direction, and the second conductive layer is connected to at least a second semiconductor pillar extending in the third direction.

14. The DRAM according to claim 13, wherein, The first conductive layer and the second conductive layer are word lines of the DRAM.

15. The DRAM according to claim 13, wherein, The first conductive layer and the second conductive layer are bit lines of the DRAM.

16. A method of manufacturing a semiconductor device, comprising: Providing a semiconductor structure, the semiconductor structure including a stack of conductive layers and first insulating layers extending in a first direction and alternating with each other in a second direction perpendicular to the first direction, wherein the conductive layers extend different lengths in the first direction and form a stepped structure of the stack. A second insulating layer extending in the first direction is formed over the stack, wherein the second insulating layer includes a first portion and a second portion, a thickness of the first portion of the second insulating layer is greater than a thickness of the second portion of the second insulating layer in the second direction, and a material of the second insulating layer has a first etching rate less than that of the material of the first insulating layer; and A contact structure extending in the second direction and connected to the stepped structure of the stack is formed, wherein the contact structure includes at least a first contact structure and a second contact structure, a length of the first contact structure in the second direction is less than a length of the second contact structure, the first contact structure extends through the first portion of the second insulating layer, and the second contact structure extends through the second portion of the second insulating layer.

17. The method according to claim 16, wherein, Forming the contact structure includes: forming contact holes extending in the second direction.

18. The method according to claim 17, wherein, Forming the contact structure further includes: Depositing bonding material on an inner surface of each of the contact holes; and Depositing conductive material into each of the contact holes.

19. The method according to any one of claims 16 to 18, wherein, Forming the second insulating layer includes: Trimming and etching a portion of the second insulating layer into a stepped shape.

20. The method according to any one of claims 17 to 19, further comprising: Depositing a third insulating layer on top of the second insulating layer, wherein the third insulating layer includes a material having a second etching rate greater than that of the material of the second insulating layer, and wherein the contact holes extend through the third insulating layer.

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