Semiconductor memory device

Abstract

The invention relates to a semiconductor memory device. The semiconductor memory device includes: a gate stack including interlayer insulating layers and word lines alternately stacked in a first direction; a channel pillar passing through the gate stack and tapering toward the first direction; a source selection line surrounding the channel pillar and extending to overlap the gate stack; and a source isolation insulating layer overlapping the gate stack between the source selection lines and tapering in a direction opposite to the first direction.

Description

[0001] This application is a divisional application of the invention patent application with the original application number 202110023270.4 (application date: January 8, 2021, invention title: Semiconductor Memory Device and Method of Manufacturing the Same). Technical Field

[0002] The present disclosure generally relates to a semiconductor memory device and a method of manufacturing the same, and more particularly, to a three-dimensional semiconductor memory device and a method of manufacturing the same. Background Art

[0003] A semiconductor memory device includes a plurality of memory cells capable of storing data. A three-dimensional semiconductor memory device may include memory cells arranged three-dimensionally. The memory cells may form a plurality of unit memory strings. The memory cell strings may be connected to word lines and selection lines. The selection lines may include a source selection line and a drain selection line. Summary of the Invention

[0004] A semiconductor memory device according to an embodiment of the present disclosure may include: a gate stack including an interlayer insulating layer and a word line alternately stacked in a first direction; a channel pillar passing through the gate stack and gradually narrowing toward the first direction; a source selection line surrounding the channel pillar and extending to overlap with the gate stack; and a source isolation insulating layer overlapping with the gate stack between the source selection lines and gradually narrowing toward a direction opposite to the first direction.

[0005] A method of manufacturing a semiconductor memory device according to an embodiment of the present disclosure may include the steps of: forming a preliminary structure including a channel pillar, an interlayer insulating layer, and a conductive pattern, each of the channel pillars gradually narrowing toward a first end facing the first direction, the interlayer insulating layer and the conductive pattern surrounding the channel pillar and alternately stacked in the first direction; forming a trench passing through a first conductive pattern of the conductive patterns and gradually narrowing toward a direction opposite to the first direction; and forming a source isolation insulating layer filling the trench. Brief Description of the Drawings

[0006] Figure 1 is a circuit diagram showing a memory block of a semiconductor memory device according to an embodiment of the present disclosure.

[0007] Figure 2 Shows a layout diagram of a gate stack, a channel pillar, and a bit line of a semiconductor memory device according to an embodiment of the present disclosure.

[0008] Figure 3A is along Figure 2 a cross-sectional view of the semiconductor memory device taken along line A-A' shown, and Figure 3BYes Figure 3A An enlarged cross-sectional view of the region R1 shown.

[0009] Figure 4A Is a cross-sectional view of a semiconductor memory device according to an embodiment of the present disclosure, and Figure 4B Is Figure 4A An enlarged cross-sectional view of the region R2 shown.

[0010] Figure 5 Is an enlarged cross-sectional view of a source selection line of a semiconductor memory device according to an embodiment of the present disclosure.

[0011] Figure 6A Is a cross-sectional view of a semiconductor memory device according to an embodiment of the present disclosure, and Figure 6B Is Figure 6A An enlarged cross-sectional view of the region R3 shown.

[0012] Figures 7A to 7H Is a cross-sectional view showing a method of manufacturing a semiconductor memory device according to an embodiment of the present disclosure.

[0013] Figures 8A to 8D Is showing after Figure 7H An enlarged cross-sectional view of the subsequent process after the process shown.

[0014] Figures 9A to 9C Is a cross-sectional view showing a method of manufacturing a semiconductor memory device according to an embodiment of the present disclosure.

[0015] Figures 10A to 10C Is showing after Figure 9C An enlarged cross-sectional view of the subsequent process after the process shown.

[0016] Figures 11A to 11D Is an enlarged cross-sectional view showing a method of manufacturing a semiconductor memory device according to an embodiment of the present disclosure.

[0017] Figures 12A to 12D Is a cross-sectional view showing a method of manufacturing a semiconductor memory device according to an embodiment of the present disclosure.

[0018] Figure 13A And Figure 13B Is showing after Figure 12D An enlarged cross-sectional view of the subsequent process after the process shown.

[0019] Figure 14 Is a block diagram showing the configuration of a memory system according to an embodiment of the present disclosure.

[0020] Figure 15 Is a block diagram showing the configuration of a computing system according to an embodiment of the present disclosure. Detailed Implementation Manner

[0021] The specific structural descriptions or functional descriptions disclosed herein are merely shown for the purpose of describing embodiments according to the concepts of the present disclosure. Embodiments according to the concepts of the present disclosure can be implemented in various forms, and they should not be construed as limited to the specific embodiments set forth herein.

[0022] Hereinafter, the terms "first" and "second" are used to distinguish one component from another component, and are not intended to imply a specific number or order of the components. These terms can be used to describe various components, but these components are not limited by these terms.

[0023] An embodiment of the present disclosure can provide a semiconductor memory device and a method of manufacturing the semiconductor memory device, the semiconductor memory device being capable of improving the alignment margin of a source isolation insulating layer that separates source selection lines from each other.

[0024] Figure 1 is a circuit diagram showing a memory block BLK of a semiconductor memory device according to an embodiment of the present disclosure.

[0025] Referring to Figure 1 , the semiconductor memory device may include a plurality of memory blocks BLK. Each memory block BLK may include a plurality of memory cell strings MS1, MS2, and MS3 connected to a common source layer CSL and bit lines BL.

[0026] Each of the memory cell strings MS1, MS2, and MS3 may include a plurality of memory cells MC connected in series, at least one source selection transistor SST, and at least one drain selection transistor DST. In one embodiment, each of the memory cell strings MS1, MS2, and MS3 may include one source selection transistor SST connected between the plurality of memory cells MC and the common source layer CSL. In one embodiment, each of the memory cell strings MS1, MS2, and MS3 may include two or more source selection transistors SST connected in series between the plurality of memory cells MC and the common source layer CSL. In one embodiment, each of the memory cell strings MS1, MS2, and MS3 may include one drain selection transistor DST connected between the plurality of memory cells MC and the bit line BL. In one embodiment, each of the memory cell strings MS1, MS2, and MS3 may include two or more drain selection transistors DST connected in series between the plurality of memory cells MC and the bit line BL.

[0027] The plurality of memory cells MC may be connected to the common source layer CSL via the source selection transistor SST. The plurality of memory cells MC may be connected to the bit line BL via the drain selection transistor DST.

[0028] The gates of source selection transistors SSTs provided at the same level may be connected to source selection lines SSL1, SSL2, and SSL3 separated from each other. The gates of drain selection transistors DSTs provided at the same level may be connected to drain selection lines DSL1, DSL2, and DSL3 separated from each other. The gates of multiple memory cells MC may be connected to multiple word lines WL. The word lines WL may be provided at different levels, and the gates of memory cells MC provided at the same level may be connected to a single word line WL.

[0029] Hereinafter, the present disclosure will be described based on an embodiment in which a memory block BLK includes a first source selection line SSL1, a second source selection line SSL2, and a third source selection line SSL3 separated from each other at the same level, and includes a first drain selection line DSL1, a second drain selection line DSL2, and a third drain selection line DSL3 separated from each other at the same level. The embodiment of the present disclosure is not limited thereto, and the memory block BLK may include two source selection lines separated from each other at the same level, or may include four or more source selection lines separated from each other at the same level. Similarly, the memory block BLK may include two drain selection lines separated from each other at the same level, or may include four or more drain selection lines separated from each other at the same level.

[0030] Multiple memory cell strings MS1, MS2, and MS3 may be connected to each of the word lines WL. The multiple memory cell strings MS1, MS2, and MS3 may include a first group, a second group, and a third group that can be individually selected by the first source selection line SSL1, the second source selection line SSL2, and the third source selection line SSL3. The first group may include a first memory cell string MS1, the second group may include a second memory cell string MS2, and the third group may include a third memory cell string MS3.

[0031] The first memory cell string MS1 may be connected to a bit line BL via a drain selection transistor DST connected to the first drain selection line DSL1, respectively. The second memory cell string MS2 may be connected to the bit line BL via a drain selection transistor DST connected to the second drain selection line DSL2, respectively. The third memory cell string MS3 may be connected to the bit line BL via a drain selection transistor DST connected to the third drain selection line DSL3, respectively. One of the first memory cell string MS1, one of the second memory cell string MS2, and one of the third memory cell string MS3 may be connected to a single bit line BL.

[0032] The first memory cell string MS1 can be connected to the common source layer CSL under the control of a source select transistor SST connected to the first source select line SSL1. The second memory cell string MS2 can be connected to the common source layer CSL under the control of a source select transistor SST connected to the second source select line SSL2, and the third memory cell string MS3 can be connected to the common source layer CSL under the control of a source select transistor SST connected to the third source select line SSL3. Thus, during a read operation or a verify operation, for each of the source select lines SSL1, SSL2, and SSL3, the multiple memory cell strings MS1, MS2, and MS3 can be divided into groups that can be individually selected simultaneously. In one embodiment, during a read operation or a verify operation, one of a first group of the first memory cell string MS1, a second group of the second memory cell string MS2, and a third group of the third memory cell string MS3 can be connected to the common source layer CSL by selecting one of the first source select line SSL1, the second source select line SSL2, and the third source select line SSL3. Thus, compared with the case where the first memory cell string MS1, the second memory cell string MS2, and the third memory cell string MS3 are simultaneously connected to the common source layer CSL during a read operation or a verify operation, embodiments of the present disclosure can reduce the channel resistance. Therefore, embodiments of the present disclosure can reduce read interference.

[0033] Figure 2 A layout diagram showing gate stacks G1, G2, and G3, channel pillars CH, and bit lines BL of a semiconductor memory device according to an embodiment of the present disclosure.

[0034] Referring to Figure 2 , the gate stacks G1, G2, and G3 can be separated from each other by a gate isolation insulating layer SG. The gate stacks G1, G2, and G3 can surround a channel pillar CH extending in a first direction D1.

[0035] The channel pillars CH can be arranged in multiple rows in a second direction D2 in a plane intersecting the channel pillars CH and multiple columns in a third direction D3 in a plane intersecting the channel pillars CH. In one embodiment, the multiple channel pillars CH respectively passing through the gate stacks G1, G2, and G3 can include a first channel pillar CH1, a second channel pillar CH2, and a third channel pillar CH3 arranged to be spaced apart from each other in the second direction D2.

[0036] Each of the gate stacks G1, G2, and G3 can include a word line WL and drain select lines DSL1, DSL2, and DSL3.

[0037] In one embodiment, each of the gate stacks G1, G2, and G3 may include a first drain select line DSL1 surrounding the first channel pillar CH1, a second drain select line DSL2 surrounding the second channel pillar CH2, and a third drain select line DSL3 surrounding the third channel pillar CH3. The first drain select line DSL1, the second drain select line DSL2, and the third drain select line DSL3 may be spaced apart from each other in the second direction D2 by a drain isolation insulating layer SD. The first drain select line DSL1, the second drain select line DSL2, the third drain select line DSL3, and the drain isolation insulating layer SD may extend in the third direction D3. The shape of the drain isolation insulating layer SD may be various, such as wavy or straight.

[0038] The word line WL may overlap with the drain select lines DSL1, DSL2, and DSL3. Each of the word lines WL may extend in the second direction D2 to surround the first channel pillar CH1, the second channel pillar CH2, and the third channel pillar CH3. Each of the word lines WL may overlap with the drain isolation insulating layer SD.

[0039] Each of the word lines WL may be penetrated by a dummy channel pillar DCH. The dummy channel pillar DCH may overlap with the drain isolation insulating layer SD. The dummy channel pillars DCH may be arranged in a row in the extending direction of the drain isolation insulating layer SD. Although not shown in the figure, the dummy channel pillars DCH may be omitted.

[0040] The bit line BL may extend in a direction intersecting with the drain select lines DSL1, DSL2, and DSL3. In one embodiment, the bit line BL may extend in the second direction D2. The bit line BL may be connected to the channel pillar CH through a contact plug CT. Each of the bit lines BL may be commonly connected to the channel pillars that can be controlled by different drain select lines DSL1, DSL2, and DSL3. In one embodiment, each of the bit lines BL may be commonly connected to the first channel pillar CH1 that can be controlled by the first drain select line DSL1, the second channel pillar CH2 that can be controlled by the second drain select line DSL2, and the third channel pillar CH3 that can be controlled by the third drain select line DSL3.

[0041] Figure 3A is along Figure 2 a cross-sectional view of a semiconductor memory device taken along the line A-A' shown, and Figure 3B is Figure 3A an enlarged cross-sectional view of the region R1 shown.

[0042] Figure 2 The line A-A' shown overlaps with the dummy channel pillar DCH between the first channel pillar CH1 and the second channel pillar CH2, but does not overlap with the dummy channel pillar DCH between the second channel pillar CH2 and the third channel pillar CH3.

[0043] Referring to Figure 3A , the semiconductor memory device may include a common source layer CSL overlapping with the bit line BL. Gate stacks G1 and G2 may be disposed between the common source layer CSL and the bit line BL. The semiconductor memory device may include a peripheral circuit structure 50. The bit line BL may be disposed between the gate stacks G1 and G2 and the peripheral circuit structure 50. The semiconductor memory device may include source select lines SSL1, SSL2, and SSL3 overlapping with each of the gate stacks G1 and G2. The source select lines SSL1, SSL2, and SSL3 may be disposed between each of the gate stacks G1 and G2 and the common source layer CSL.

[0044] The channel pillars CH may extend in a first direction D1 to pass through the gate stacks G1 and G2 and the source select lines SSL1, SSL2, and SSL3. The channel pillars CH may extend into the common source layer CSL. Each of the channel pillars CH may include a channel layer CL, a core insulating layer CO, and a capping pattern CAP. The core insulating layer CO and the capping pattern CAP may be disposed in a central region of the channel pillar CH. The core insulating layer CO may overlap with the capping pattern CAP. The capping pattern CAP may include a doped semiconductor layer. In one embodiment, the capping pattern CAP may include doped silicon containing n-type impurities. The channel layer CL may surround sidewalls of the capping pattern CAP and sidewalls of the core insulating layer CO. The channel layer CL may extend onto a surface of the core insulating layer CO facing the common source layer CSL. The channel layer CL may constitute a channel region of a memory cell string. The channel layer CL may include a semiconductor layer. In one embodiment, the channel layer CL may include silicon.

[0045] The common source layer CSL may include a doped semiconductor layer 181 and a metal layer 185 stacked in a first direction D1. The common source layer CSL may further include a first metal barrier layer 183. The doped semiconductor layer 181 may include at least one of n-type impurities and p-type impurities. In one embodiment, the doped semiconductor layer 181 may include silicon doped with n-type impurities. The common source layer CSL may be insulated from the source select lines SSL1, SSL2, and SSL3 by a first insulating layer 11. The first insulating layer 11 may extend between the common source layer CSL and each of the source select lines SSL1, SSL2, and SSL3.

[0046] The channel pillars CH may extend into the doped semiconductor layer 181 of the common source layer CSL. The channel layer CL of the channel pillar CH may be in contact with the doped semiconductor layer 181 of the common source layer CSL.

[0047] The source selection lines SSL1, SSL2, and SSL3 can be separated from each other by the source isolation insulating layer SS. In other words, the source isolation insulating layer SS can be disposed between the source selection lines SSL1, SSL2, and SSL3. The source isolation insulating layer SS can overlap with the drain isolation insulating layer SD. The source isolation insulating layer SS can extend parallel to the drain isolation insulating layer SD. In one embodiment, the source isolation insulating layer SS can extend in the third direction D3. The source isolation insulating layer SS can extend in the first direction D1 to pass through the first insulating layer 11.

[0048] The source isolation insulating layer SS can have a tapered shape opposite to that of each of the channel pillars CH. Each of the channel pillars CH can have a tapered shape that gradually narrows in the first direction D1. Accordingly, the distance between the protrusions of the channel pillars CH extending beyond the gate stack G1 in the first direction can be defined as greater than the distance between the portions of the channel pillars CH disposed inside the gate stack G1. Accordingly, according to one embodiment of the present disclosure, the margin space for aligning the source isolation insulating layer SS between the protrusions of the channel pillars CH can be increased.

[0049] The source isolation insulating layer SS can have a tapered shape that gradually narrows in a direction opposite to the first direction D1. Accordingly, the width of the upper end of the source isolation insulating layer SS facing the common source layer CSL can be formed wider than the width of the lower end of the source isolation insulating layer SS facing the gate stack G1.

[0050] Since the channel pillars CH can have a tapered shape that gradually narrows in the first direction D1, the space between the channel pillars CH can become wider as the channel pillars CH approach the common source layer CSL. Accordingly, the space between the channel pillars CH where the upper end of the source isolation insulating layer SS is disposed can be defined as wider than the space between the channel pillars CH where the lower end of the source isolation insulating layer SS is disposed. As a result, the margin space having a wider width for aligning the source isolation insulating layer SS between the channel pillars CH can be increased. Accordingly, according to one embodiment of the present disclosure, the alignment margin of the source isolation insulating layer SS can be improved.

[0051] Each of the gate stacks G1 and G2 can include an interlayer insulating layer 21 and a conductive pattern 23 that are alternately stacked in the first direction D1. Each of the gate stacks G1 and G2 can surround the channel pillars CH and the memory pattern ML is interposed between each of the channel pillars CH and the gate stacks G1 and G2. The memory pattern ML can extend along the sidewalls of the channel pillars CH. The memory pattern ML can extend between each of the source selection lines SSL1, SSL2, and SSL3 and the channel pillars CH.

[0052] The conductive pattern 23 may include the same conductive material. Each conductive pattern 23 may surround the channel pillar CH, and the first blocking insulating layer 25 is interposed between the channel pillar CH and each conductive pattern 23. The first blocking insulating layer 25 may be disposed between each conductive pattern 23 and the memory pattern ML. The first blocking insulating layer 25 may extend between each of the conductive patterns 23 and the interlayer insulating layer 21.

[0053] The conductive pattern 23 may be used as a word line WL and drain select lines DSL1, DSL2, and DSL3. At least one layer of the conductive pattern 23 adjacent to the bit line BL may be used as the drain select lines DSL1, DSL2, and DSL3, and the remaining layers may be used as the word line WL. In one embodiment, the drain select lines DSL1, DSL2, and DSL3 may include a two-layer first drain select line DSL1 to third drain select line DSL3 formed by a first-level conductive pattern 23A and a second-level conductive pattern 23B adjacent to the bit line BL. The drain select lines DSL1, DSL2, and DSL3 may be spaced apart from each other at the same level by a drain isolation insulating layer SD. The drain isolation insulating layer SD may have a tapered shape that gradually narrows in the first direction D1.

[0054] The source select lines SSL1, SSL2, and SSL3 may overlap with the drain select lines DSL1, DSL2, and DSL3, and the word line WL is interposed between the source select lines SSL1, SSL2, and SSL3 and the drain select lines DSL1, DSL2, and DSL3. In one embodiment, the source select lines SSL1, SSL2, and SSL3 may include a first source select line SSL1, a second source select line SSL2, and a third source select line SSL3 that extend parallel to the first drain select line DSL1, the second drain select line DSL2, and the third drain select line DSL3, respectively. The first source select line SSL1 may surround the first channel pillar CH1, the second source select line SSL2 may surround the second channel pillar CH2, and the third source select line SSL3 may surround the third channel pillar CH3.

[0055] The word line WL may be penetrated by a dummy channel pillar DCH. The dummy channel pillar DCH may be disposed between the source isolation insulating layer SS and the drain isolation insulating layer SD. The sidewall of the dummy channel pillar DCH may be surrounded by a dummy memory pattern DML. The dummy channel pillar DCH may include a dummy core insulating layer DCO and a dummy channel layer DCL. The dummy core insulating layer DCO may be disposed in the central region of the dummy channel pillar DCH, and the dummy channel layer DCL may be disposed between the dummy core insulating layer DCO and the dummy memory pattern DML.

[0056] The conductive materials of the source selection lines SSL1, SSL2, and SSL3 can be various. The manufacturing process of the semiconductor memory device can include a plurality of etching processes performed using various etching materials. The source selection lines SSL1, SSL2, and SSL3 can include materials that are resistant to etching with respect to some etching materials. In one embodiment, each of the source selection lines SSL1, SSL2, and SSL3 can include silicon.

[0057] The contact plug CT can pass through at least one insulating layer disposed between the bit line BL and the channel pillar CH. In one embodiment, the second insulating layer 133 and the third insulating layer 165 can be disposed between each of the gate stacks G1 and G2 and the bit line BL. The contact plug CT can contact the capping pattern CAP and can extend toward the bit line BL to pass through the second insulating layer 133 and the third insulating layer 165.

[0058] The semiconductor memory device can include a first insulating structure 171, a first interconnecting structure 173, and a first bonding metal pattern 175.

[0059] The first insulating structure 171 can be disposed between the peripheral circuit structure 50 and the bit line BL. The first insulating structure 171 can include two or more layers of insulating layers. The first interconnecting structure 173 and the first bonding metal pattern 175 can be buried in the first insulating structure 171. The first interconnecting structure 173 can include conductive patterns of various shapes. The first interconnecting structure 173 can be disposed between the bit line BL and the first bonding metal pattern 175. The bit line BL can be electrically connected to the first bonding metal pattern 175 via the first interconnecting structure 173. The first bonding metal pattern 175 can face the peripheral circuit structure 50.

[0060] The peripheral circuit structure 50 can include a substrate 101 having a transistor TR, a second insulating structure 121, a second interconnecting structure 123, and a second bonding metal pattern 125.

[0061] The transistor TR can be disposed in the active region of the substrate 101 separated by the element isolation layer 103. Each transistor TR can include a gate insulating layer disposed on the active region, a gate 115 disposed on the gate insulating layer 113, and junctions 111A and 111B formed in the active region on both sides of the gate insulating layer 113. Some of the transistors TR can constitute a page buffer circuit PB that controls the precharging operation and the discharging operation of the bit line BL. The page buffer circuit PB can be connected to the bit line BL via the second interconnecting structure 123 and the first interconnecting structure 173.

[0062] The second insulating structure 121 may be disposed between the first insulating structure 171 and the substrate 101. The second insulating structure 121 may include two or more insulating layers. The second insulating structure 121 may be bonded to the first insulating structure 171. The second interconnection structure 123 and the second bonding metal pattern 125 may be embedded in the second insulating structure 121. The second interconnection structure 123 may include conductive patterns of various shapes. The second interconnection structure 123 may be disposed between the transistor TR of the page buffer circuit PB and the second bonding metal pattern 125. The transistor TR of the page buffer circuit PB may be electrically connected to the second bonding metal pattern 125 via the second interconnection structure 123. The second bonding metal pattern 125 may face the first bonding metal pattern 175 and may be bonded to the first bonding metal pattern 175.

[0063] Referring to Figure 3B , the conductive pattern 23 may include a metal layer MT and a second metal barrier layer BM.

[0064] The channel pillar CH may protrude beyond the memory pattern ML into the doped semiconductor layer 181 of the common source layer. The channel layer CL of the channel pillar CH may extend between the doped semiconductor layer 181 and the core insulating layer CO.

[0065] The memory pattern ML may be disposed between the source select lines SSL2 or SSL3 and the channel pillar CH. The memory pattern ML may extend between the channel pillar CH and each of the interlayer insulating layer 21, the conductive pattern 23, and the first insulating layer 11. The memory pattern ML may include a tunneling insulating layer TI, a data storage layer DL extending along the outer wall of the tunneling insulating layer TI, and a second barrier insulating layer BI extending along the outer wall of the data storage layer DL. The data storage layer DL may be formed of a material layer capable of storing data. In one embodiment, the data storage layer DL may be formed of a material layer capable of storing data changed using the Fowler-Nordheim tunneling effect. The material layer may include a nitride layer capable of capturing charges. The second barrier insulating layer BI may include an oxide layer capable of blocking charges. The tunneling insulating layer TI may be formed of a silicon oxide layer capable of charge tunneling.

[0066] The first barrier insulating layer 25 may include a material layer having a dielectric constant higher than that of the second barrier insulating layer BI. In one embodiment, the first barrier insulating layer 25 may include an alumina layer. One of the first barrier insulating layer 25 and the second barrier insulating layer BI may be omitted.

[0067] The source isolation insulating layer SS may include a bottom surface facing the interlayer insulating layer 21 and an upper surface facing the doped semiconductor layer 181. According to one embodiment of the present disclosure, the bottom surface width W11 of the source isolation insulating layer SS may be narrower than the upper surface width W12 of the source isolation insulating layer SS through the tapered shape.

[0068] Figure 4A is a cross-sectional view of a semiconductor memory device according to one embodiment of the present disclosure, and Figure 4B yes Figure 4A An enlarged cross-sectional view of region R2 is shown.

[0069] Reference Figure 4A , the semiconductor memory device may include Figure 2 and Figure 3A The bit line BL, common source layer CSL, gate stacks G1 and G2, drain isolation insulating layer SD and contact plug CT have the same structure as the bit line BL', common source layer CSL', gate stacks G1' and G2', drain isolation insulating layer SD' and contact plug CT'. Figure 3A As described above, each of the gate stacks G1' and G2' may be penetrated by a channel pillar CH' and a dummy channel pillar DCH'. The channel pillar CH' and the dummy channel pillar DCH' may extend in the first direction D1. The sidewall of the channel pillar CH' may be surrounded by a memory pattern ML', and the sidewall of the dummy channel pillar DCH' may be surrounded by a dummy memory pattern DML'.

[0070] In addition, the semiconductor memory device may include Figure 3A The peripheral circuit structure 50, the first interconnect structure 173 and the first bonding metal pattern 175 are shown to have the same structure as the peripheral circuit structure 50', the first interconnect structure 173' and the first bonding metal pattern 175. In addition, the semiconductor memory device may include source selection lines SSL1', SSL2' and SSL3' disposed between the gate stacks G1' and G2' and the common source layer CSL'.

[0071] Each of the source selection lines SSL1', SSL2', and SSL3' may extend in the second direction D2 and the third direction D3 in a plane intersecting the channel pillar CH'. The source selection lines SSL1', SSL2', and SSL3' may be arranged to be spaced apart from each other in the second direction D2. The source selection lines SSL1', SSL2', and SSL3' may be insulated from the common source layer CSL' by the first insulating layer 11'.

[0072] The source selection lines SSL1’, SSL2’ and SSL3’ can be separated from each other by a first source isolation insulating layer SS1’ and a second source isolation insulating layer SS2’. Each of the first source isolation insulating layer SS1’ and the second source isolation insulating layer SS2’ can include a first portion disposed between the source selection lines SSL1’, SSL2’ and SSL3’ and a second portion passing through the first insulating layer 11’. The first portion of each of the first source isolation insulating layer SS1’ and the second source isolation insulating layer SS2’ can be formed in a tapered shape. The tapered shape of each of the first source isolation insulating layer SS1’ and the second source isolation insulating layer SS2’ can be the opposite shape of the tapered shape of the channel pillar CH’ as described with reference to Figure 3A Therefore, as described with reference to Figure 3A , embodiments of the present disclosure can improve the alignment margin of the first source isolation insulating layer SS1’ and the second source isolation insulating layer SS2’.

[0073] The first source isolation insulating layer SS1’ can overlap with the gate stack G1’. The first source isolation insulating layer SS1’ can extend parallel to the drain isolation insulating layer SD’. In one embodiment, the first source isolation insulating layer SS1’ and the drain isolation insulating layer SD’ can extend in a third direction D3.

[0074] The second source isolation insulating layer SS2’ can overlap with the gate isolation insulating layer SG’. The second source isolation insulating layer SS2’ can extend parallel to the gate isolation insulating layer SG’. In one embodiment, the second source isolation insulating layer SS2’ and the gate isolation insulating layer SG’ can extend in a third direction D3.

[0075] The source selection lines SSL1’, SSL2’ and SSL3’ can overlap with the drain selection lines DSL1’, DSL2’ and DSL3’ of the gate stack G1’. In one embodiment, each of the source selection lines SSL1’, SSL2’ and SSL3’ can include a silicon layer 13’ and a metal silicide layer 15’. Referring to Figure 4A , the silicon layer 13’ can be used as an etch stop layer in the manufacturing process of the semiconductor memory device. The metal silicide layer 15’ can be disposed between each of the first source isolation insulating layer SS1’ and the second source isolation insulating layer SS2’ and the silicon layer 13’. The metal silicide layer 15’ can be in contact with the silicon layer 13’. The metal silicide layer 15’ can reduce the resistance of the source selection lines SSL1’, SSL2’ and SSL3’.

[0076] The second insulating layer 133’ and the third insulating layer 165’ can be formed with the same structure as the second insulating layer 133 and the third insulating layer 165 shown in Figure 3A .

[0077] Reference Figure 4B , as in reference Figure 3B As described, the channel pillar CH' can protrude beyond the memory pattern ML' into the doped semiconductor layer 181' of the common source layer. The channel layer CL' and the core insulating layer CO' of the channel pillar CH' can extend into the doped semiconductor layer 181'.

[0078] As in reference Figure 3B As described, the memory pattern ML' can include a tunneling insulating layer TI', a data storage layer DL', and a blocking insulating layer BI'.

[0079] The first source isolation insulating layer SS1' can include a bottom surface facing the gate stack G1' and an upper surface facing the doped semiconductor layer 181'. According to an embodiment of the present disclosure, through a tapered shape, the bottom surface width W21 of the first source isolation insulating layer SS1' can be narrower than the upper surface width W22' of the first source isolation insulating layer SS1'.

[0080] Figure 5 is an enlarged cross-sectional view of a source selection line SSL of a semiconductor memory device according to an embodiment of the present disclosure.

[0081] Reference Figure 5 , the gate stack G1', the first insulating layer 11', the memory pattern ML', the tunneling insulating layer TI', the data storage layer DL', the blocking insulating layer BI', the channel pillar CH', the core insulating layer CO', the channel layer CL', and the doped semiconductor layer 181' of the common source layer can be formed in the structure described in Figure 4A and Figure 4B described.

[0082] The source selection lines SSL can be separated from each other by the source isolation insulating layer SS1" overlapping with the gate stack G1'. Each of the source selection lines SSL can include a silicon layer 13A and a sidewall conductive pattern 20. As in reference Figure 4A As described, the silicon layer 13A can be used as an etch stop layer in the manufacturing process of the semiconductor memory device. The sidewall conductive pattern 20 can be disposed between the source isolation insulating layer SS1" and the silicon layer 13A. The sidewall conductive pattern 20 can include a metal barrier layer 17 in contact with the silicon layer 13A and a metal layer 19 disposed between the metal barrier layer 17 and the source isolation insulating layer SS1". The metal layer 19 can reduce the resistance of the source selection line SSL. The metal barrier layer 17 can extend between the metal layer 19 and the first insulating layer 11'. The metal barrier layer 17 can extend between the metal layer 19 and the gate stack G1'.

[0083] Figure 6A is a cross-sectional view of a semiconductor memory device according to an embodiment of the present disclosure, and Figure 6BYes Figure 6A An enlarged cross-sectional view of the region R3 shown.

[0084] Referring to Figure 6A , the semiconductor memory device may include bit lines BL", common source layers CSL", gate stacks G1" and G2", drain isolation insulating layers SD", and contact plugs CT" that are the same as the bit lines BL, common source layer CSL, gate stacks G1 and G2, drain isolation insulating layer SD, and contact plugs CT shown. As described with reference to Figure 2 and Figure 3A . Each of the gate stacks G1" and G2" may be penetrated by channel pillars CH1" and dummy channel pillars DCH". The sidewalls of the channel pillars CH1" may be surrounded by memory patterns ML", and the sidewalls of the dummy channel pillars DCH" may be surrounded by dummy memory patterns DML". Figure 3A As described above, each of the gate stacks G1" and G2" may be penetrated by channel pillars CH1" and dummy channel pillars DCH". The sidewalls of the channel pillars CH1" may be surrounded by memory patterns ML", and the sidewalls of the dummy channel pillars DCH" may be surrounded by dummy memory patterns DML".

[0085] In addition, the semiconductor memory device may include a peripheral circuit structure 50", a first interconnect structure 173", and a first bonding metal pattern 175" that are the same as the peripheral circuit structure 50, the first interconnect structure 173, and the first bonding metal pattern 175 shown. In addition, the semiconductor memory device may include source selection lines SSL1", SSL2", and SSL3" disposed between the gate stacks G1" and G2" and the common source layer CSL". Figure 3A As shown. Each of the source selection lines SSL1", SSL2", and SSL3" may extend in a second direction D2 and a third direction D3 in a plane intersecting a first direction D1 that is the extending direction of the channel pillar CH". The source selection lines SSL1", SSL2", and SSL3" may include the same conductive material as the word line WL" of the gate stack G1". The source selection lines SSL1", SSL2", and SSL3" may overlap with the drain selection lines DSL1", DSL2", and DSL3". The source selection lines SSL1", SSL2", and SSL3" may be disposed on two or more layers spaced apart from each other along the first direction D1.

[0086] In one embodiment, the source selection lines SSL1", SSL2", and SSL3" may be formed by a selection stack 30 disposed between the word line WL" and the first insulating layer 11". The selection stack 30 may include a first conductive pattern 31A, an interlayer insulating layer 33, and a second conductive pattern 31B. The first conductive pattern 31A may be disposed between the interlayer insulating layer 33 and the first insulating layer 11", and the second conductive pattern 31B may be disposed between the interlayer insulating layer 33 and the gate stack G1".

[0087] In one embodiment, the source selection lines SSL1", SSL2", and SSL3" may be formed by a selection stack 30 disposed between the word line WL" and the first insulating layer 11". The selection stack 30 may include a first conductive pattern 31A, an interlayer insulating layer 33, and a second conductive pattern 31B. The first conductive pattern 31A may be disposed between the interlayer insulating layer 33 and the first insulating layer 11", and the second conductive pattern 31B may be disposed between the interlayer insulating layer 33 and the gate stack G1".

[0088] The selection stack 30 can be penetrated by the source isolation insulating layer SS” and the gate isolation insulating layer SG”. Each of the first conductive pattern 31A and the second conductive pattern 31B can be separated by the source isolation insulating layer SS” into source selection lines SSL1”, SSL2”, and SSL3”. In one embodiment, the source selection lines SSL1”, SSL2”, and SSL3” can include a two-layer first source selection line SSL1”, a two-layer second source selection line SSL2”, and a two-layer third source selection line SSL3”. The two-layer first source selection line SSL1” to the two-layer third source selection line SSL3” can be formed by the first conductive pattern 31A and the second conductive pattern 31B.

[0089] As referred to Figure 3A as described above, the source isolation insulating layer SS” can be formed in a shape opposite to the tapered shape of the channel pillar CH”. Thus, as referred to Figure 3A as described above, embodiments of the present disclosure can improve the alignment margin of the source isolation insulating layer SS”.

[0090] The source isolation insulating layer SS” can overlap with the gate stack G1”. The source isolation insulating layer SS” can extend parallel to the drain isolation insulating layer SD”. In one embodiment, the source isolation insulating layer SS” and the drain isolation insulating layer SD” can extend in the third direction D3.

[0091] The second insulating layer 133” and the third insulating layer 165” can be formed with the same structure as the Figure 3A second insulating layer 133 and the third insulating layer 165 shown.

[0092] Referring to Figure 6B , each of the first conductive pattern 31A and the second conductive pattern 31B of the selection stack 30 can include a metal layer MT” and a metal barrier layer BM”. The metal barrier layer BM” can be disposed between the metal layer MT” and the memory pattern ML”. The metal barrier layer BM” can extend between the metal layer MT” and the first insulating layer 11”. The metal barrier layer BM” can extend between the metal layer MT” and the interlayer insulating layer 33. The metal barrier layer BM” can extend between the metal layer MT” and the gate stack G1”.

[0093] As referred to Figure 3B as described above, the memory pattern ML” can include a tunneling insulating layer TI”, a data storage layer DL”, and a blocking insulating layer BI”. As referred to Figure 3B as described above, the channel pillar CH” can protrude beyond the memory pattern ML” into the doped semiconductor layer 181” of the common source layer. The channel layer CL” and the core insulating layer CO” of the channel pillar CH” can extend into the doped semiconductor layer 181”.

[0094] The source isolation insulating layer SS” may include a bottom surface facing the gate stack G1” and an upper surface facing the doped semiconductor layer 181”. According to one embodiment of the present disclosure, through a tapered shape, the bottom surface width W31 of the source isolation insulating layer SS” may be narrower than the upper surface width W32 of the source isolation insulating layer SS”.

[0095] Figures 7A to 7H is a cross-sectional view showing a method of manufacturing a semiconductor memory device according to one embodiment of the present disclosure.

[0096] Referring Figure 7A , a protective layer 603 may be formed on the sacrificial substrate 601. The protective layer 603 may include a material having an etching selectivity with respect to the sacrificial substrate 601. In one embodiment, the sacrificial substrate 601 may be a silicon substrate, and the protective layer 603 may include a silicon nitride layer.

[0097] Subsequently, a first insulating layer 605 and a first conductive pattern 607 may be stacked on the protective layer 603. Thereafter, an interlayer insulating layer 611 and a sacrificial layer 613 may be alternately stacked on the first conductive pattern 607.

[0098] The first insulating layer 605 may include a silicon oxide layer. The first conductive pattern 607 may include a conductive material having an etching selectivity with respect to the interlayer insulating layer 611 and the sacrificial layer 613. In one embodiment, the first conductive pattern 607 may include a silicon layer, the interlayer insulating layer 611 may include a silicon oxide layer, and the sacrificial layer 613 may include a silicon nitride layer.

[0099] Thereafter, a first mask pattern 615 may be formed on the stack of the interlayer insulating layer 611 and the sacrificial layer 613. Subsequently, a channel hole 619 may be formed through the interlayer insulating layer 611 and the sacrificial layer 613 and extending into the protective layer 603. A dummy hole 619D having the same shape as each channel hole 619 may be formed by using the process of forming the channel hole 619.

[0100] Each of the channel hole 619 and the dummy hole 619D may be formed by etching the interlayer insulating layer 611, the sacrificial layer 613, the first conductive pattern 607, and the first insulating layer 605 by an etching process using the first mask pattern 615 as an etching stop layer. During the etching process of forming the channel hole 619 and the dummy hole 619D, a part of the protective layer 603 may be etched, but the protective layer 603 may remain along the bottom surface of each of the channel hole 619 and the dummy hole 619D.

[0101] The etching process for forming the channel hole 619 and the dummy hole 619D can be performed by etching the interlayer insulating layer 611, the sacrificial layer 613, the first conductive pattern 607, and the first insulating layer 605 in sequence from the interlayer insulating layer 611 adjacent to the first mask pattern 615 toward the protective layer 603. Accordingly, each of the channel hole 619 and the dummy hole 619D may have a tapered shape that gradually narrows toward the sacrificial substrate 601 along the first direction D1.

[0102] Subsequently, a memory layer 621 and a dummy memory layer 621D may be formed on the surfaces of the channel hole 619 and the dummy hole 619D, respectively. Each of the memory layer 621 and the dummy memory layer 621D may include Figure 8A the first barrier insulating layer 621A, the data storage layer 621B, and the tunneling insulating layer 621C as shown.

[0103] Thereafter, a channel pillar 630 may be formed in the central region of the channel hole 619 opened by the memory layer 621. When forming the channel pillar 630, a dummy channel pillar 630D may be formed in the central region of the dummy hole 619D opened by the dummy memory layer 621D.

[0104] The steps of forming the channel pillar 630 and the dummy channel pillar 630D may include: forming a semiconductor layer along the surface of each of the channel hole 619 and the dummy hole 619D; forming a filling insulating layer on the semiconductor layer; removing a part of the filling insulating layer; filling the region where the filling insulating layer is removed with a doped semiconductor layer; and planarizing the doped semiconductor layer and the semiconductor layer so that the first mask pattern 615 is exposed. Through the above series of processes, the filling insulating layer may be retained as the core insulating layer 625 inside the channel hole 619, and may be retained as the dummy core insulating layer 625D inside the dummy hole 619D. In addition, the semiconductor layer may be retained as the channel layer 623 inside the channel hole 619, and may be retained as the dummy channel layer 623 inside the dummy hole 619D. In addition, the doped semiconductor layer may be retained as the capping pattern 627 inside the channel hole 619, and may be retained as the dummy capping pattern 627D inside the dummy hole 619D. The semiconductor layer may include a silicon layer, and the doped semiconductor layer may include a doped silicon layer containing n-type impurities.

[0105] Each of the channel pillars 630 may include a first end EP1A facing the first direction D1 and a second end EP2A facing a direction opposite to the first end EP1A. Each of the channel pillars 630 may have a tapered shape that gradually narrows as the channel pillar 630 approaches the first end EP1A.

[0106] After forming the channel pillar 630 and the dummy channel pillar 630D, the first mask pattern 615 may be removed.

[0107] Reference Figure 7B , a second insulating layer 635 covering the channel pillar 630 and the dummy channel pillar 630D can be formed. The second insulating layer 635 can extend to overlap with the interlayer insulating layer 611.

[0108] Subsequently, a first slit 637 can be formed to pass through the second insulating layer 635, Figure 7A the interlayer insulating layer 611 and the sacrificial layer 613 as shown. During the etching process of forming the first slit 637, the first conductive pattern 607 can be used as an etching stop layer.

[0109] Thereafter, by selectively removing the sacrificial layer 613 through the first slit 637, a horizontal space 639 can be opened between the interlayer insulating layers 611.

[0110] Reference Figure 7C , a second conductive pattern 649 can be formed inside the horizontal space 639 respectively through the first slit 637 as shown. Before forming the second conductive pattern 649, a second barrier insulating layer 641 can be formed on the surface of each horizontal space 639. Figure 7B The step of forming the second conductive pattern 649 can include: filling the horizontal space 639 opened by the second barrier insulating layer 641 with a conductive material, and removing the conductive material inside the first slit 637 so that the conductive material can be separated into the second conductive pattern 649. The conductive material of the second conductive pattern 649 can include

[0111] the metal barrier layer 643 and the metal layer 645 as shown. Figure 8A

[0112]

[0112] The preliminary structure 650 can be defined by the process described above with reference to Figures 7A to 7C . The preliminary structure 650 can include a channel pillar 630 having a tapered shape, a first conductive pattern 607 surrounding the channel pillar 630, and the interlayer insulating layer 611 and the second conductive pattern 649 that are alternately stacked on the first conductive pattern 607 and surround the channel pillar 630.

[0113] Thereafter, a second slit 651 can be formed by etching the first conductive pattern 607 exposed through the first slit 637. The second slit 651 can pass through the first conductive pattern 607 and can be connected to the first slit 637.

[0114] Reference Figure 7D , the first slit 637 and the second slit 651 as shown can be filled with the gate isolation insulating layer 653. Thereafter, a drain trench 657 can be formed. The drain trench 657 can pass through Figure 7C Figure 7C ​At least one layer of the second conductive pattern 649 shown. The second conductive pattern 649 penetrated by the drain trench 657 is adjacent to the second end EP2A of the channel pillar 630.

[0115] The drain trench 657 may extend in the third direction D3 between the channel pillars 630. Figure 7C The second conductive pattern 649 shown may be separated by the drain trench 657 into drain select lines 649D. The drain select lines 649D may extend in the second direction D2 and the third direction D3 in a plane intersecting the channel pillars 630 to surround the channel pillars 630.

[0116] During the etching process for forming the drain trench 657, a part of the dummy channel pillar 630D may be etched. It may be etched from the second insulating layer 635 towards Figure 7C The second insulating layer 635, the interlayer insulating layer 611, and Figure 7C At least one layer of the second conductive pattern 649 shown may be etched in sequence to perform the etching process for forming the drain trench 657. Therefore, the drain trench 657 may have a tapered shape that gradually narrows towards the first direction D1.

[0117] It is possible to Figure 7C Some of the second conductive pattern 649 shown may be defined as word lines 649W. The word lines 649W may not be penetrated by the drain trench 657 and may be disposed between the drain select lines 649D and the first conductive pattern 607.

[0118] Some regions of the drain trench 657 may overlap with the dummy channel pillar 630D, and other regions may overlap with some regions of the word lines 649W that are not penetrated by the dummy channel pillar 630D. Although not shown in the figure, Figure 7D The dummy channel pillar 630D shown may be adjacent to another dummy channel pillar in the third direction D3. Some regions of the word lines 649W that overlap with the drain trench 657 may be disposed between the dummy channel pillars adjacent in the third direction D3. The arrangement of the dummy channel pillars and the drain trench 657 is the same as Figure 2 The arrangement of the dummy channel pillars DCH and the drain isolation insulating layer SD shown.

[0119] Referring to Figure 7E , the drain trench 657 shown may be filled with the drain isolation insulating layer 659. The drain isolation insulating layer 659 may have the same tapered shape as Figure 7D The drain trench 657 shown. Figure 7D The drain trench 657 shown.

[0120] According to an embodiment of the present disclosure, when replacing with Figure 7C The second conductive pattern 649 shown Figure 7AAfter the sacrificial layer 613 shown is formed, a drain isolation insulating layer 659 is formed. Thus, when performing the process of replacing the sacrificial layer 613 shown with the second conductive pattern 649 shown, there will be no problem of the inflow of etching material or conductive material being blocked by the drain isolation insulating layer 659. Therefore, according to an embodiment of the present disclosure, since the layout of the drain isolation insulating layer 659 can be designed without design limitations on the inflow of etching material or conductive material, the design freedom of the drain isolation insulating layer 659 can be improved. Figure 7C the second conductive pattern 649 shown to replace Figure 7A the sacrificial layer 613 shown, there will be no problem of the inflow of etching material or conductive material being blocked by the drain isolation insulating layer 659. Therefore, according to an embodiment of the present disclosure, since the layout of the drain isolation insulating layer 659 can be designed without design limitations on the inflow of etching material or conductive material, the design freedom of the drain isolation insulating layer 659 can be improved.

[0121] Subsequently, a third insulating layer 661 can be formed on the second insulating layer 635. Thereafter, a contact plug 663 can be formed to cross the second insulating layer 635 and the third insulating layer 661 so as to overlap with the channel pillar 630. The contact plug 663 can contact the capping pattern 627 of the channel pillar 630.

[0122] Subsequently, a bit line 665 can be formed. The bit line 665 can face the second end EP2A of each channel pillar 630. The bit line 665 can be formed on the third insulating layer 661 and can contact the contact plug 663. The bit line 665 can extend in a direction crossing the drain isolation insulating layer 659. In this embodiment, the bit line 665 can extend in the second direction D2.

[0123] After the bit line 665 is formed, a first interconnect structure 668 and a first bonding metal pattern 669 can be formed. The first interconnect structure 668 and the first bonding metal pattern 669 can be buried in the first insulating structure 667. The first interconnect structure 668 can include conductive patterns of various shapes. The first bonding metal pattern 669 can be connected to the first interconnect structure 668. At least one of the first bonding metal patterns 669 can overlap with the bit line 665 and can be connected to the bit line 665 via the first interconnect structure 668.

[0124] Referring to Figure 7F , a peripheral circuit structure 670 can be provided. The peripheral circuit structure 670 can include a substrate 671 containing transistors 675, a second insulating structure 681 covering the substrate 671, and a second interconnect structure 682 and a second bonding metal pattern 683 buried in the second insulating structure 681.

[0125] The substrate 671 can be a semiconductor substrate such as a silicon substrate or a germanium substrate. The transistors 675 can be formed in the active regions of the substrate 671 separated by the element isolation layer 673. Each of the transistors 675 can be configured to be the same as the transistor TR described with reference to Figure 3A . Some of the transistors 675 can be included in the page buffer circuit 679.

[0126] The second interconnection structure 682 may include conductive patterns of various shapes. The second bonding metal pattern 683 may be connected to the second interconnection structure 682. At least one of the second bonding metal patterns 683 may overlap with the page buffer circuit 679 and may be connected to the page buffer circuit 679 via the second interconnection structure 682.

[0127] The sacrificial substrate 601 may be aligned with the peripheral circuit structure 670 such that the first bonding metal pattern 669 faces the second bonding metal pattern 683 of the peripheral circuit structure 670. Thereafter, the first bonding metal pattern 669 and the second bonding metal pattern 683 may be bonded to each other.

[0128] Referring Figure 7G , the sacrificial substrate 601 shown may be removed. When removing the sacrificial substrate 601, Figure 7F the protective layer 603 shown may protect the channel pillars 630 and the memory layer 621. Subsequently, the first insulating layer 605 may be exposed by selectively removing Figure 7F the protective layer 603 shown. Figure 7F The memory layer 621 may be retained to cover the surface of each of the channel pillars 630 protruding in the first direction beyond the first insulating layer 605, and the dummy memory layer 621D may be retained to cover the surface of the dummy channel pillars 630D protruding in the first direction beyond the first insulating layer 605.

[0129] The memory layer 621 may be retained to cover the surface of each of the channel pillars 630 protruding in the first direction beyond the first insulating layer 605, and the dummy memory layer 621D may be retained to cover the surface of the dummy channel pillars 630D protruding in the first direction beyond the first insulating layer 605.

[0130] Referring Figure 7H , a second mask pattern 685 may be formed on the first insulating layer 605. Subsequently, source trenches 687 may be formed through Figure 7G the first insulating layer 605 shown and Figure 7G the first conductive pattern 607 shown by an etching process using the second mask pattern 685 as an etch stop layer. Accordingly, Figure 7G the first conductive pattern 607 shown may be separated into source select lines 607S by the source trenches 687.

[0131] The source select lines 607S may extend in the second direction D2 and the third direction D3 to surround the channel pillars 630. The source trenches 687 may extend in the third direction D3 between the channel pillars 630. The source trenches 687 may overlap with the drain isolation insulating layer 659 and the word line 649W may be interposed between the source trenches 687 and the drain isolation insulating layer 659. The source trenches 687 may overlap with the dummy channel pillars 630D. During the etching process for forming the source trenches 687, a part of the dummy memory layer 621D and a part of the dummy channel pillars 630D may be etched.

[0132] Etching can be performed in a direction opposite to the first direction D1 to sequentially etch Figure 7G the first insulating layer 605 shown in Figure 7G and the first conductive pattern 607 shown in

[0133] Figures 8A to 8D to perform the etching process for forming the source trench 687. Therefore, the source trench 687 can have a tapered shape that gradually narrows in a direction opposite to the first direction D1. Figure 7H is an enlarged cross-sectional view of a subsequent process after the process shown in Figures 8A to 8D is Figure 7H an enlarged cross-sectional view of the region RA shown in

[0134] Referring to Figure 8A , the second mask pattern 685 shown in Figure 7H can be removed to expose the first insulating layer 605 and the memory layer 621. The memory layer 621 can include a first barrier insulating layer 621A, a data storage layer 621B, and a tunneling insulating layer 621C. The first barrier insulating layer 621A can include a silicon oxide layer, the data storage layer 621B can include a silicon nitride layer, and the tunneling insulating layer 621C can include a silicon oxide layer. The second barrier insulating layer 641 can include a material layer having a dielectric constant higher than that of the first barrier insulating layer 621A. In one embodiment, the second barrier insulating layer 641 can include an aluminum oxide layer.

[0135] Referring to Figure 8B , the source trench 687 shown in Figure 8A can be filled with a source isolation insulating layer 693. The source isolation insulating layer 693 can include an oxide layer.

[0136] Subsequently, a part of the first barrier insulating layer 621A can be removed to expose the data storage layer 621B. At this time, a part of the source isolation insulating layer 693 can be removed. A part of the first barrier insulating layer 621A and a part of the source isolation insulating layer 693 can be removed using an etch-back process.

[0137] Referring to Figure 8C , the memory pattern 621ML can be defined by sequentially performing an etching process for selectively etching the data storage layer 621B and an etching process for selectively etching the tunneling insulating layer 621C. The channel layer 623 and the core insulating layer 625 of the channel pillar 630 can protrude beyond the memory pattern 621ML, and the surface of the channel layer 623 can be exposed at the protrusion of the channel pillar 630.

[0138] When etching the data storage layer 621B and the tunneling insulating layer 621C, a part of the source isolation insulating layer 693 can be etched, but the first insulating layer 605 can be retained to surround the channel pillar 630.

[0139] Referring to Figure 8D , a doped semiconductor pattern 695 that contacts the exposed surface of the channel layer 623 can be formed. The doped semiconductor pattern 695 can constitute a common source layer. The doped semiconductor pattern 695 can extend to overlap with the source selection line 607S and the source isolation insulating layer 693. The doped semiconductor pattern 695 can be spaced apart from the source selection line 607S by the first insulating layer 605.

[0140] Figures 9A to 9C is a cross-sectional view illustrating a method of manufacturing a semiconductor memory device according to an embodiment of the present disclosure.

[0141] Referring to Figure 9A , a protective layer 703, a first insulating layer 705, and a preliminary structure 750 can be formed on the sacrificial substrate 701 by using the process described with reference to Figures 7A to 7C .

[0142] The first conductive pattern 707 of the preliminary structure 750 can include silicon. The interlayer insulating layer 711 and the second conductive pattern 749 of the preliminary structure 750 can be alternately stacked on the first conductive pattern 707. The conductive material of the second conductive pattern 749 can include a metal barrier layer 743 and a metal layer 745 as shown in Figure 10A .

[0143] Each of the channel pillars 730 of the preliminary structure 750 can have a tapered shape that gradually narrows in a first direction D1 facing the sacrificial substrate 701.

[0144] The interlayer insulating layer 711, the second conductive pattern 749, and the first conductive pattern 707 can be penetrated by dummy channel pillars 730D having a shape similar to the shape of the channel pillars 730. The channel pillars 730 and the dummy channel pillars 730D can pass through the first insulating layer 705 and extend into the protective layer 703.

[0145] As described with reference to Figure 7A , each of the channel pillars 730 can include a core insulating layer 725, a capping pattern 727, and a channel layer 723. Each of the channel pillars 730 can include a first end EP1B facing the first direction D1 and a second end EP2B facing a direction opposite to the first direction D1. The memory layer 721 can extend along the first end EP1B of the channel pillar 730 and the sidewalls of the channel pillar 730. As shown in Figure 10A , the memory layer 721 can include a first barrier insulating layer 721A, a data storage layer 721B, and a tunneling insulating layer 721C.

[0146] A second barrier insulating layer 741 can be formed along the surface of each of the second conductive patterns 749.

[0147] As described with reference to Figure 7A the dummy channel pillar 730D may be surrounded by a dummy memory layer 721D and may include a dummy channel layer 723D, a dummy core insulating layer 725D, and a dummy capping pattern 727D.

[0148] The second end EP2B of each of the channel pillars 730 and the dummy channel pillar 730D may be covered by a second insulating layer 735.

[0149] The gate isolation insulating layer 753 that separates the preliminary structure 750 may be disposed on the first conductive pattern 707 without penetrating the first conductive pattern 707.

[0150] With reference to Figure 9B , after the gate isolation insulating layer 753 is formed, a drain isolation insulating layer 759 having a tapered shape that gradually narrows in the first direction D1 may be formed by the processes described with reference to Figure 7D and Figure 7E . The drain isolation insulating layer 759 may divide at least one layer of the second conductive pattern 749 shown in Figure 9A into drain select lines 749D. The second conductive pattern divided into the drain select lines 749D is adjacent to the second end EP2B of the channel pillar 730. Among the second conductive patterns 749, the second conductive pattern between the drain isolation insulating layer 759 and the first conductive pattern 707 may be defined as a word line 749W.

[0151] Some regions of the drain isolation insulating layer 759 may overlap with the dummy channel pillar 730D, and other regions may overlap with some regions of the word line 749W not penetrated by the dummy channel pillar 730D.

[0152] With reference to Figure 9C , a third insulating layer 761, a contact plug 763, a bit line 765, a first interconnect structure 768, and a first bonding metal pattern 769 may be formed by the processes described with reference to Figure 7E . As described with reference to Figure 7E , the first interconnect structure 768 and the first bonding metal pattern 769 may be buried in the first insulating structure 767.

[0153] Subsequently, the second bonding metal pattern 783 of the peripheral circuit structure 770 may be bonded to the first bonding metal pattern 769 by the processes described with reference to Figure 7F . As described with reference to Figure 7F , the peripheral circuit structure 770 may include a substrate 771 having transistors 775, a second insulating structure 781 covering the substrate 771, and a second interconnect structure 782 and a second bonding metal pattern 783 buried in the second insulating structure 781.

[0154] Subsequently, the sacrificial substrate 701 and the protective layer 703 shown can be removed in sequence. Thus, the first insulating layer 705 can be exposed. Figure 9B The sacrificial substrate 701 and the protective layer 703 shown can be removed in sequence. Thus, the first insulating layer 705 can be exposed.

[0155] Thereafter, a mask pattern 785 can be formed on the first insulating layer 705. Subsequently, a source trench 787 passing through the first insulating layer 705 and the first conductive pattern 707 shown can be formed by an etching process using the mask pattern 785 as an etching stopper layer. As referred to Figure 9B The source trench 787 passing through the first insulating layer 705 and the first conductive pattern 707 shown can be formed by an etching process using the mask pattern 785 as an etching stopper layer. As referred to Figure 7H As described, the source trench 787 can have a tapered shape that gradually narrows in a direction opposite to the first direction D1.

[0156] Figure 9B The first conductive pattern 707 shown can be separated into preliminary selection lines 707A by the source trench 787. The preliminary selection lines 707A can extend in the second direction D2 and the third direction D3 in a plane intersecting the channel pillars 730. The source trench 787 can extend in the third direction D3 between the channel pillars 730. The source trench 787 can overlap with the dummy channel pillars 730D, the drain isolation insulating layer 759, and the gate isolation insulating layer 753.

[0157] Figures 10A to 10C is a magnified cross-sectional view showing subsequent processes after the process shown in Figure 9C is a magnified cross-sectional view showing subsequent processes after the process shown in Figures 10A to 10C is Figure 9C a magnified cross-sectional view of the region RB shown.

[0158] Referring to Figure 10A the mask pattern 785 shown can be removed to expose the first insulating layer 705 and the memory layer 721. Subsequently, a metal layer 789 can be formed on the sidewalls of the preliminary selection lines 707A exposed through the source trench 787. The metal layer 789 can extend along the surface of the source trench 787. The metal layer 789 can extend along the surface of the first insulating layer 705 and the surface of the memory layer 721. Figure 9C the mask pattern 785 shown can be removed to expose the first insulating layer 705 and the memory layer 721. Subsequently, a metal layer 789 can be formed on the sidewalls of the preliminary selection lines 707A exposed through the source trench 787. The metal layer 789 can extend along the surface of the source trench 787. The metal layer 789 can extend along the surface of the first insulating layer 705 and the surface of the memory layer 721.

[0159] The metal layer 789 can include a conductive material that can provide a metal silicide layer by reacting with the preliminary selection lines 707A via a silicidation process performed at a temperature of 450 °C or lower. In one embodiment, the metal layer 789 can include nickel.

[0160] Referring to Figure 10B By performing a silicidation process at a temperature of 450 °C or lower, Figure 10A a part of the preliminary selection lines 707A shown can be converted into a metal silicide layer. Thereafter, the remaining metal layer that has not reacted with the silicon layer can be removed. Figure 10ASome regions of the preliminary selection line 707A shown may not be converted into a metal silicide layer, but may remain as a silicon layer. The remaining silicon layer may form a first selection pattern 707B. In addition, the metal silicide layer may form a second selection pattern 791 extending along the sidewalls of the first selection pattern 707B.

[0161] The source selection line 790SSL including the first selection pattern 707B and the second selection pattern 791 may be defined by the above process. The second selection pattern 791 formed of the metal silicide layer may compensate for the resistance of the first selection pattern 707B formed of the silicon layer, thereby reducing the resistance of the source selection line 790SSL.

[0162] In a high-temperature process exceeding 450 °C, defects may occur in the Figure 9C first bonding metal pattern 769 and the second bonding metal pattern 783 shown. Since the silicidation process according to an embodiment of the present disclosure is performed at a low temperature of 450 °C or lower, according to this embodiment of the present disclosure, in the Figure 9C first bonding metal pattern 769 and the second bonding metal pattern 783 shown, the occurrence of defects due to high temperature can be reduced.

[0163] Referring to Figure 10C and Figure 8B the process described, the source isolation insulating layer 793 can be used to fill the Figure 10B source trench 787 shown.

[0164] Subsequently, as described with reference to Figure 8B and Figure 8C the memory pattern 721M can be defined by sequentially performing an etching process of the first barrier insulating layer 721A, an etching process of the data storage layer 721B, and an etching process of the tunneling insulating layer 721C. The channel layer 723 and the core insulating layer 725 of the channel pillar 730 may protrude beyond the memory pattern 721ML, and the surface of the channel layer 723 may be exposed at the protrusion of the channel pillar 730.

[0165] Thereafter, a doped semiconductor pattern 795 may be formed in contact with the surface of the exposed channel layer 723.

[0166] Figures 11A to 11D is an enlarged cross-sectional view showing a method of manufacturing a semiconductor memory device according to an embodiment of the present disclosure.

[0167] Before performing the Figures 11A to 11D process shown, the process described with reference to Figures 9A to 9C may be performed first. Thus, a preliminary selection line 707S' divided by the source trench 787' may be formed.

[0168] The preliminary selection line 707S’ can overlap with the stack of the conductive pattern 749’ and the interlayer insulating layer 711’. The conductive pattern 749’, the interlayer insulating layer 711’, and the preliminary selection line 707S’ can surround the channel pillar 730’. The channel pillar 730’ can have a tapered shape that gradually narrows toward the first direction D1. The channel pillar 730’ can include a core insulating layer 725’ and a channel layer 723’. The sidewalls of each of the channel pillars 730’ can be surrounded by the memory layer 721’.

[0169] The memory layer 721’ can extend to cover the first end EP1C facing the first direction D1 of each channel pillar 730’. The memory layer 721’ can include a first barrier insulating layer 721A’, a data storage layer 721B’, and a tunneling insulating layer 721C’.

[0170] The preliminary selection line 707S’ can be disposed closer to the first end EP1C of the channel pillar 730’ than the conductive pattern 749’. Each of the preliminary selection lines 707S’ can be formed of a silicon layer.

[0171] The conductive pattern 749’ can include a metal barrier layer 743’ and a metal layer 745’. A second barrier insulating layer 741’ can be disposed between the conductive pattern 749’ and the memory layer 721’. The second barrier insulating layer 741’ can extend between the conductive pattern 749’ and the interlayer insulating layer 711’.

[0172] The source trench 787’ can extend to penetrate the first insulating layer 705’. A portion of each of the preliminary selection lines 707’ can be etched through the source trench 787’. Thus, a groove 788’ can be defined between the first insulating layer 705’ and the interlayer insulating layer 711’.

[0173] The mask pattern 785’ can be used as an etch barrier layer during the etching process for forming the source trench 787’. The mask pattern 785’ can protect the memory layer 721’ and the channel pillar 730’ during the etching process for forming the groove 788’.

[0174] Referring to Figure 11B , the conductive layer 789’ can be utilized to fill Figure 11AThe groove 788’ shown in [the figure]. The conductive layer 789’ may include various conductive materials that can be deposited in a process at 450 °C or lower. In one embodiment, the conductive layer 789’ may include various conductive materials deposited by physical vapor deposition (PVD) or atomic layer deposition. The conductive layer 789’ may include a metal layer 789B and a metal barrier layer 789A located between the metal layer 789B and the preliminary selection line 707S’. The metal barrier layer 789A may be in contact with the sidewalls of the preliminary selection line 707S’. The metal layer 789B and the metal barrier layer 789A may compensate for the resistance of the preliminary selection line 707S’ formed of a silicon layer.

[0175] Because the conductive layer 789’ for compensating the resistance of the silicon layer is formed at a low temperature of 450 °C or lower, according to one embodiment of the present disclosure, in Figure 9C the first bonding metal pattern 769 and the second bonding metal pattern 783 shown, the occurrence of defects due to high temperature can be reduced.

[0176] Referring to Figure 11C , the metal layer 789B and the metal barrier layer 789A in the source trench 787’ can be removed by an etching process such as etch-back. Thus, a source selection line 790SSL’ including a sidewall conductive pattern 789P and a preliminary selection line 707S’ can be defined. The sidewall conductive pattern 789P can remain on the sidewalls of the preliminary selection line 707S’.

[0177] Referring to Figure 11D , by using the process described with reference to Figure 8B , the source trench 787’ shown in Figure 11C can be filled with the source isolation insulating layer 793’.

[0178] Subsequently, as described with reference to Figure 8B and Figure 8C , a memory pattern 721ML’ can be defined by sequentially performing an etching process of the first barrier insulating layer 721A’, an etching process of the data storage layer 721B’, and an etching process of the tunneling insulating layer 721C’. In addition, the channel layer 723’ and the core insulating layer 725’ of the channel pillar 730’ can protrude beyond the memory pattern 721ML’, and the surface of the channel layer 723’ can be exposed at the protrusion of the channel pillar 730’.

[0179] Thereafter, a doped semiconductor pattern 795’ in contact with the exposed surface of the channel layer 723’ can be formed.

[0180] Figures 12A to 12D is a cross-sectional view showing a method of manufacturing a semiconductor memory device according to one embodiment of the present disclosure.

[0181] Referring toFigure 12A After forming the first insulating layer 805 on the sacrificial substrate 801, the sacrificial layer 813 and the interlayer insulating layer 811 can be alternately laminated on the first insulating layer 805.

[0182] The first insulating layer 805 may include a silicon oxide layer. The sacrificial layer 813 may include a silicon nitride layer. The interlayer insulating layer 811 may include a silicon oxide layer.

[0183] The process described with reference to Figure 7A can be used to form the channel pillar 830. When forming the channel pillar 830, dummy channel pillars 830D can be formed. The channel pillar 830 and the dummy channel pillars 830D can extend into the sacrificial substrate 801.

[0184] Each of the channel pillars 830 may include a first end EP1D and a second end EP2D facing opposite directions. The first end EP1D may face the first direction D1. The sidewalls of the channel pillar 830 may be surrounded by the memory layer 821. The memory layer 821 may extend between the first end EP1D and the sacrificial substrate 801. The channel pillar 830 may include a channel layer 823, a core insulating layer 825, and a capping pattern 827. The channel pillar 830 may have a tapered shape that gradually narrows toward the first end EP1D. The memory layer 821 may include Figure 13A the first barrier insulating layer 821A, the data storage layer 821B, and the tunneling insulating layer 821C shown.

[0185] The dummy channel pillars 830D may be surrounded by a dummy memory layer 821D. The dummy channel pillars 830D may include a dummy channel layer 823D, a dummy core insulating layer 825D, and a dummy capping pattern 827D.

[0186] The channel pillar 830 and the dummy channel pillars 830D may be covered by a second insulating layer 835.

[0187] The second insulating layer 835, the interlayer insulating layer 811, the sacrificial layer 813, and the first insulating layer 805 may be penetrated by slits 837.

[0188] With reference to Figure 12B , the sacrificial layer 813 shown can be replaced with a conductive pattern 849 through the slit 837. The conductive pattern 849 may be formed of the same conductive material. As Figure 12A shown, each of the conductive patterns 849 may include a metal barrier layer 843 and a metal layer 845. Before forming the conductive pattern 849, a second barrier insulating layer 841 can be formed on the surface of each of the regions where the sacrificial layer 813 shown is removed. Figure 13A shown, each of the conductive patterns 849 may include a metal barrier layer 843 and a metal layer 845. Before forming the conductive pattern 849, a second barrier insulating layer 841 can be formed on the surface of each of the regions where the sacrificial layer 813 shown is removed. Figure 12A shown, each of the conductive patterns 849 may include a metal barrier layer 843 and a metal layer 845. Before forming the conductive pattern 849, a second barrier insulating layer 841 can be formed on the surface of each of the regions where the sacrificial layer 813 shown is removed.

[0189] Through the above reference to Figure 12A andFigure 12B The described process can form a preliminary structure 850, which includes a channel pillar 830 having a tapered shape, and conductive patterns 849 and interlayer insulating layers 811 that surround the channel pillar 830 and are alternately stacked on the first insulating layer 805.

[0190] Referring Figure 12C to, a gate isolation insulating layer 853 can be used to fill Figure 12B the slit 837 shown. Subsequently, a drain isolation insulating layer 859 can be formed through at least one layer of the conductive pattern 849 shown. The conductive pattern penetrated by the drain isolation insulating layer 859 is adjacent to the second end EP2D of the channel pillar 830. Figure 12B

[0191] The conductive pattern adjacent to the second end EP2D can be separated into a drain select line 849D by the drain isolation insulating layer 859. The drain select line 849D can extend in the second direction D2 and the third direction D3 in a plane intersecting the channel pillar 830 to surround the channel pillar 830. The drain isolation insulating layer 859 can extend in the third direction D3 between the channel pillars 830. The drain isolation insulating layer 859 can have a tapered shape that gradually narrows toward the first direction D1.

[0192] The drain isolation insulating layer 859 can include a region overlapping with the dummy channel pillar 830D and a region not overlapping with the dummy channel pillar 830D.

[0193] Referring Figure 12D to, a third insulating layer 861, contact plugs 863, bit lines 865, a first interconnect structure 868, and a first bonding metal pattern 869 can be formed using the process described in Figure 7E . As described in Figure 7E , the first interconnect structure 868 and the first bonding metal pattern 869 can be buried in the first insulating structure 867.

[0194] Subsequently, the second bonding metal pattern 883 of the peripheral circuit structure 870 can be bonded to the first bonding metal pattern 869 through the process described in Figure 7F . As described in Figure 7F , the peripheral circuit structure 870 can include a substrate 871 having transistors 875, a second insulating structure 881 covering the substrate 871, and a second interconnect structure 882 and a second bonding metal pattern 883 buried in the second insulating structure 881.

[0195] Subsequently, the sacrificial substrate 801 shown in Figure 12C can be removed. Thus, the first insulating layer 805 can be exposed.

[0196] ​Thereafter, a mask pattern 885 can be formed on the first insulating layer 805. Subsequently, a source trench 887 can be formed by an etching process using the mask pattern 885 as an etching stopper layer. The source trench 887 can penetrate through Figure 12C at least one layer of the conductive pattern 849 shown. The conductive pattern penetrated by the source trench 887 is adjacent to the first end EP1D of the channel pillar 830. As referred to Figure 7H above, the source trench 887 can have a tapered shape that gradually narrows in a direction opposite to the first direction D1.

[0197] The conductive pattern penetrated by the source trench 887 can be separated into source select lines 849S. The source select lines 849S can extend in the second direction D2 and the third direction D3 to surround the channel pillar 830. The source trench 887 can extend in the third direction D3 between the channel pillars 830. The source trench 887 can overlap with the drain isolation insulating layer 859.

[0198] Figure 13A and Figure 13B are enlarged cross-sectional views showing subsequent processes after the process shown in Figure 12D above. Figure 13A and Figure 13B are enlarged cross-sectional views of the region RC shown in Figure 12D above.

[0199] Referring to Figure 13A , the mask pattern 885 shown can be removed to expose the first insulating layer 805. Subsequently, the source trench 887 can be filled with a source isolation insulating layer 893. As referred to Figure 12D above, in the process for forming the source isolation insulating layer 893, the first barrier insulating layer 821A can be etched and the data storage layer 821B can be exposed. Figure 8B The source isolation insulating layer 893 can electrically insulate adjacent source select lines 849S at the same level. The source isolation insulating layer 893 can overlap with some regions of the word line 849W that overlap with the source trench 887.

[0200] Referring to

[0201] above, as referred to Figure 13B above, as referred to Figure 8C above, the memory pattern 821ML can be defined by sequentially performing an etching process of the data storage layer 821B and an etching process of the tunneling insulating layer 821C. The channel layer 823 and the core insulating layer 825 of the channel pillar 830 can protrude beyond the memory pattern 821ML, and the surface of the channel layer 823 can be exposed at the protrusion of the channel pillar 830.

[0202] Thereafter, a doped semiconductor pattern 895 may be formed in contact with the exposed surface of the channel layer 823.

[0203] The source isolation insulating layer 893 according to an embodiment of the present disclosure is formed after replacing Figure 12B the sacrificial layer 813 shown with Figure 12A the conductive pattern 849 shown. Therefore, embodiments of the present disclosure can design the layout of the source isolation insulating layer 893 without design limitations in terms of flowing in an etching material or a conductive material in order to replace Figure 12B the sacrificial layer 813 shown with Figure 12A the conductive pattern 849 shown. Therefore, according to an embodiment of the present disclosure, the design freedom of the source isolation insulating layer 893 can be increased.

[0204] Figure 14 FIG. is a block diagram showing a configuration of a memory system 1100 according to an embodiment of the present disclosure.

[0205] Referring to Figure 14 , the memory system 1100 may include a memory device 1120 and a memory controller 1110.

[0206] The memory device 1120 may include a channel pillar having a tapered shape, a source isolation insulating layer having a tapered shape opposite to the tapered shape of the channel pillar, and source selection lines surrounding the channel pillar and separated from each other at the same level. The source isolation insulating layer may be disposed between the source selection lines.

[0207] The memory device 1120 may be a multi-chip package composed of a plurality of flash memory chips.

[0208] The memory controller 1110 may be configured to control the memory device 1120. The memory controller 1110 may include a static random access memory (SRAM) 1111, a central processing unit (CPU) 1112, a host interface 1113, an error correction block 1114, and a memory interface 1115. The SRAM 1111 may be used as an operating memory of the CPU 1112. The CPU 1112 may execute an overall control operation for data exchange of the memory controller 1110, and the host interface 1113 may include a data exchange protocol for connecting to a host of the memory system 1100. In addition, the error correction block 1114 may detect and correct an error included in data read from the memory device 1120. The memory interface 1115 may perform an interface connection with the memory device 1120. In addition, the memory controller 1110 may further include a read-only memory (ROM) or the like for storing code data for interface connection with the host.

[0209] Figure 15is a block diagram showing the configuration of a computing system 1200 according to an embodiment of the present disclosure.

[0210] Referring to Figure 15 , the computing system 1200 may include a CPU 1220, a random access memory (RAM) 1230, a user interface 1240, a modem 1250, and a memory system 1210 electrically connected to a system bus 1260. The computing system 1200 may be a mobile device.

[0211] The memory system 1210 may include a memory device 1212 and a memory controller 1211. The memory device 1212 may include a channel pillar having a tapered shape, a source isolation insulating layer having a tapered shape opposite to the tapered shape of the channel pillar, and source selection lines surrounding the channel pillar and separated from each other at the same level. The source isolation insulating layer may be disposed between the source selection lines.

[0212] According to the present disclosure, since the source isolation insulating layer disposed between the channel pillars gradually narrows in a direction opposite to that of the channel pillars, the alignment margin of the source isolation insulating layer between the channel pillars can be improved.

[0213] Cross-reference to related applications

[0214] This application claims priority to Korean Patent Application No. 10-2020-0116060, filed with the Korean Intellectual Property Office on September 10, 2020, the entire contents of which are incorporated herein by reference.

Claims

1. A semiconductor memory device, the semiconductor memory device comprising: A gate stack including an interlayer insulating layer and a word line alternately stacked in a first direction; Channel pillars passing through the gate stack and tapering in the first direction, each channel pillar including a channel layer and a core insulating layer; A source isolation insulating layer disposed above a part of the gate stack; A source selection line surrounding the channel pillars, the source selection lines being spaced apart from each other by the source isolation insulating layer between the source selection lines; And A common source layer in contact with the channel layer.

2. The semiconductor memory device according to claim 1, Among them, The common source layer includes a doped semiconductor layer including at least one of an n-type impurity and a p-type impurity.

3. The semiconductor memory device according to claim 1, Among them, The common source layer includes a doped semiconductor layer and a metal layer stacked in the first direction.

4. The semiconductor memory device according to claim 3, Among them, The common source layer further includes a metal barrier layer disposed between the doped semiconductor layer and the metal layer.

5. The semiconductor memory device according to claim 1, the semiconductor memory device further comprising: A bit line connected to the channel layer; An outer circuit structure spaced apart from the bit line; And A first insulating structure located between the bit line and the outer circuit.

6. The semiconductor memory device according to claim 5, Among them, The first insulating structure includes two or more insulating layers.

7. The semiconductor memory device according to claim 5, the semiconductor memory device further comprising: A first bonding metal pattern and a first interconnect structure disposed in the first insulating structure.

8. The semiconductor memory device according to claim 7, Among them, The first bonding metal pattern faces the outer circuit, and Wherein, the first interconnect structure is disposed between the bit line and the first bonding metal pattern.

9. The semiconductor memory device according to claim 8, Among them, The first interconnect structure includes a conductive pattern electrically connecting the first bonding metal pattern to the bit line.

10. The semiconductor memory device according to claim 8, wherein, The outer circuit includes: A second insulating structure bonded to the first insulating structure; A second bonding metal pattern disposed in the second insulating structure and bonded to the first bonding metal pattern; A second interconnect structure disposed in the second insulating structure and connected to the second bonding metal pattern; and A transistor covered by the second insulating structure.

11. The semiconductor memory device according to claim 10, Among them, The second interconnect structure includes a conductive pattern electrically connecting the second bonding metal pattern to the transistor.

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