Fast recovery diode, semiconductor device, and method for manufacturing semiconductor device

Abstract

The invention discloses a fast recovery diode and a manufacturing method of a semiconductor device. The fast recovery diode comprises a substrate of a first conductivity type; the drift layer comprises a first concentration doping layer, a second concentration doping layer and a third concentration doping layer, the first concentration doping layer is arranged on the substrate, the second concentration doping layer is arranged on the side, away from the substrate, of the first concentration doping layer, and the third concentration doping layer is arranged on the side, away from the substrate, of the second concentration doping layer; the doping concentration of the second concentration doping layer is not greater than the doping concentration of the first concentration doping layer and is smaller than the doping concentration of the third concentration doping layer, and the doping concentration of the first concentration doping layer is gradually reduced in the direction away from the substrate; and the anode layer of the second conductivity type is arranged on one side, back to the substrate, of the third concentration doping layer.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular, to a fast recovery diode, a semiconductor device, and a manufacturing method of a semiconductor device. Background Art

[0002] Fast recovery diodes in related technologies generally include a substrate, a drift layer, and an anode layer. Moreover, the doping concentration of the drift layer greatly affects the breakdown voltage and the softness of reverse recovery of the fast recovery diode. However, due to the unreasonable structural setting of the fast recovery diode in related technologies, the doping concentration of the drift layer of some fast recovery diodes is too low. During the reverse recovery process, when the voltage across the fast recovery diode reaches the bus voltage, the width of the depletion region broadening is too large, resulting in few remaining carriers on the side of the drift layer close to the substrate, and current interruption is likely to occur. For some other fast recovery diodes, the doping concentration of the drift layer is too high, the width of the depletion region broadening is too small, and there are too many remaining carriers in the drift layer. The reverse current shows a soft recovery, but the electric field gradient becomes larger and the electric field peak becomes larger during reverse breakdown voltage, thereby causing a significant decrease in the reverse breakdown voltage of the fast recovery diode.

[0003] Disclosure Content

[0004] The present disclosure aims to solve at least one of the technical problems existing in the prior art. To this end, on the one hand, the present disclosure provides a fast recovery diode, which has advantages such as good breakdown voltage, small reverse recovery peak current, and high circuit stability.

[0005] The present disclosure also provides a semiconductor device.

[0006] The present disclosure also provides a manufacturing method of a semiconductor device.

[0007] According to the fast recovery diode of the present disclosure, the fast recovery diode includes: a substrate of a first conductivity type; a drift layer of a first conductivity type, the drift layer including a first concentration doping layer, a second concentration doping layer, and a third concentration doping layer, the first concentration doping layer being disposed on the substrate, the second concentration doping layer being disposed on a side of the first concentration doping layer away from the substrate, the third concentration doping layer being disposed on a side of the second concentration doping layer away from the substrate, the doping concentration of the second concentration doping layer being not greater than the doping concentration of the first concentration doping layer and less than the doping concentration of the third concentration doping layer, and the doping concentration of the first concentration doping layer gradually decreasing in a direction away from the substrate; an anode layer of a second conductivity type, the anode layer being disposed on a side of the third concentration doping layer facing away from the substrate.

[0008] The fast recovery diode according to the present disclosure has advantages such as good breakdown voltage, small reverse recovery peak current, and high circuit stability. Description of the Drawings

[0009] The above and / or additional aspects and advantages of the present disclosure will become apparent and be readily understood from the following description of embodiments in conjunction with the accompanying drawings, where:

[0010] Figure 1 is a schematic structural diagram of a fast recovery diode according to some embodiments of the present disclosure.

[0011] Figure 2 is a linear graph of the doping concentration of a fast recovery diode according to some embodiments of the present disclosure.

[0012] Figure 3 is a linear graph of the doping concentration of a fast recovery diode according to another embodiment of the present disclosure.

[0013] Figure 4 is a linear graph of the electric field strength of a fast recovery diode according to some embodiments of the present disclosure.

[0014] Figure 5 is a linear graph of the electric field strength of a fast recovery diode according to another embodiment of the present disclosure.

[0015] Figure 6 is a schematic structural diagram of a substrate and a drift layer during the processing of a fast recovery diode according to some embodiments of the present disclosure.

[0016] Figure 7 is a schematic structural diagram of a substrate, a drift layer, and an anode layer according to some embodiments of the present disclosure.

[0017] Figure 8 is a schematic structural diagram of a substrate, a drift layer, an anode layer, and an anode metal layer according to some embodiments of the present disclosure.

[0018] Fig. 9 is a schematic overall structural diagram of a fast recovery diode according to some embodiments of the present disclosure;

[0019] Fig.10 is a top view of a semiconductor device according to some embodiments of the present disclosure;

[0020] Fig.11 is a cross-sectional view of a semiconductor device according to some embodiments of the present disclosure;

[0021] Fig.12 is Fig.11 a schematic diagram of region A in

[0022] Fig.13 is Fig.11 another schematic diagram of region A in

[0023] Fig.14 is a schematic diagram of the breakdown voltage curve of a semiconductor device according to some embodiments of the present disclosure;

[0024] Fig.15 is a schematic diagram of the breakdown voltage curve of a semiconductor device according to a comparative example;

[0025] Fig.16 is a schematic diagram of a semiconductor device according to some embodiments of the present disclosure;

[0026] Fig.17 is a partial schematic diagram of a semiconductor device according to some embodiments of the present disclosure;

[0027] Fig.18 is a partial cross-sectional view of a semiconductor device according to some embodiments of the present disclosure;

[0028] Fig.19 is a partial schematic diagram of a semiconductor device according to some embodiments of the present disclosure;

[0029] Fig. 20 is a partial schematic diagram of a semiconductor device according to some embodiments of the present disclosure;

[0030] Fig.21 is a partial schematic diagram of a semiconductor device according to some embodiments of the present disclosure;

[0031] Fig. 22 is a partial schematic diagram of a semiconductor device according to some embodiments of the present disclosure;

[0032] Fig.23 is a schematic diagram of a semiconductor device according to some embodiments of the present disclosure;

[0033] Fig.24 is a schematic diagram of another perspective of a semiconductor device according to some embodiments of the present disclosure;

[0034] Fig.25 is a schematic diagram of another perspective of a semiconductor device according to some other embodiments of the present disclosure;

[0035] Fig.26 is a schematic diagram of another perspective of a semiconductor device according to some embodiments of the present disclosure;

[0036] Fig. 27 is the simulation result of the on-state voltage drop of the fast recovery diode device in the semiconductor device when the emitter layer on the back surface of the semiconductor device according to some embodiments of the present disclosure corresponds to the gate bus up and down;

[0037] Fig.28 is a schematic diagram of a semiconductor device according to some embodiments of the present disclosure;

[0038] Fig.29 is Fig. 27 a partial cross-sectional view in the A1 - A1 direction in;

[0039] Fig.30 For Fig. 27 Partial cross-sectional view of some other embodiments in the A1 - A1 direction;

[0040] Fig.31 For Fig. 27 Partial cross-sectional view of some more embodiments in the A1 - A1 direction;

[0041] Fig.32 Schematic diagram of a semiconductor device according to some other embodiments of the present disclosure;

[0042] Fig.33 Schematic diagram of a semiconductor device according to some more embodiments of the present disclosure;

[0043] Fig.34 Schematic diagram of a semiconductor device according to some more embodiments of the present disclosure;

[0044] Fig.35 For Fig.31 Partial cross-sectional view in the A2 - A2 direction or Fig.32 Partial cross-sectional view in the A3 - A3 direction in;

[0045] Fig.36 For Fig.32 Schematic diagram of the B1 region in;

[0046] Fig.37 For Fig.33 Schematic diagram of the B2 region or Fig.31 Schematic diagram of the B3 region in;

[0047] Fig.38 Schematic diagram of another perspective of a semiconductor device according to some embodiments of the present disclosure;

[0048] Fig.39 Flow chart of a method for manufacturing a semiconductor device according to some embodiments of the present disclosure;

[0049] Fig.40 Partial process diagram of a semiconductor device manufacturing process according to some embodiments of the present disclosure;

[0050] Fig.41 Partial process diagram of a semiconductor device manufacturing process according to some embodiments of the present disclosure;

[0051] Fig.42 Partial process diagram of a semiconductor device manufacturing process according to some embodiments of the present disclosure;

[0052] Fig.43 Partial process diagram of a semiconductor device manufacturing process according to some embodiments of the present disclosure;

[0053] Fig.44is a partial process diagram of a semiconductor device manufacturing process according to some embodiments of the present disclosure;

[0054] Fig.45 is a partial process diagram of a semiconductor device manufacturing process according to some embodiments of the present disclosure;

[0055] Fig.46 is a partial process diagram of a semiconductor device manufacturing process according to some embodiments of the present disclosure;

[0056] Fig.47 is a partial process diagram of a semiconductor device manufacturing process according to some embodiments of the present disclosure;

[0057] Fig.48 is a schematic diagram of a semiconductor device according to some embodiments of the present disclosure;

[0058] Fig.49 is a partial cross-sectional view of a semiconductor device along the A-A direction according to some embodiments of the present disclosure;

[0059] Fig.50 is a flowchart of a manufacturing method of a semiconductor device according to some embodiments of the present disclosure;

[0060] Fig.51 is a partial schematic diagram of a semiconductor device according to some embodiments of the present disclosure;

[0061] Fig.52 is a partial cross-sectional view of a semiconductor device according to some embodiments of the present disclosure;

[0062] Fig.53 is a partial cross-sectional view of a semiconductor device according to some embodiments of the present disclosure;

[0063] Fig.54 is a partial cross-sectional view of a semiconductor device according to some embodiments of the present disclosure;

[0064] Fig.55 is a partial cross-sectional view of a semiconductor device according to some embodiments of the present disclosure;

[0065] Fig.56 is a partial cross-sectional view of a semiconductor device according to some embodiments of the present disclosure;

[0066] Fig.57 is a partial cross-sectional view of a semiconductor device according to some embodiments of the present disclosure;

[0067] Fig.58 is a cross-sectional view of a semiconductor device according to some embodiments of the present disclosure;

[0068] Fig.59 is a partial sectional view of a semiconductor device according to some embodiments of the present disclosure;

[0069] Fig.60 A partial cross-sectional view of another location of a semiconductor device according to some embodiments of the present disclosure;

[0070] Fig.61 A partial cross-sectional view of a semiconductor device according to another embodiment of the present disclosure;

[0071] Fig.62 A partial schematic view of a polysilicon field plate according to some embodiments of the present disclosure;

[0072] Fig.63 A schematic view of a semiconductor device according to some embodiments of the present disclosure;

[0073] Fig.64 A layout design schematic view of a transition region according to some embodiments of the present disclosure;

[0074] Fig.65 A cross-sectional view of the transition region along the A-A direction according to some embodiments of the present disclosure;

[0075] Fig.66 A cross-sectional view of the transition region along the B-B direction according to some embodiments of the present disclosure;

[0076] Fig.67 A cross-sectional view of the transition region along the C-C direction according to some embodiments of the present disclosure;

[0077] Fig.68 A flowchart of a manufacturing method of a semiconductor device according to some embodiments of the present disclosure;

[0078] Fig.69 A flowchart of a manufacturing method of a semiconductor device according to another embodiment of the present disclosure;

[0079] Fig.70 A partial cross-sectional view of a semiconductor device according to some embodiments of the present disclosure;

[0080] Fig.71 A partial cross-sectional view of a semiconductor device according to some embodiments of the present disclosure;

[0081] Fig.72 A partial cross-sectional view of a semiconductor device according to some embodiments of the present disclosure;

[0082] Fig.73 A partial cross-sectional view of a semiconductor device according to some embodiments of the present disclosure;

[0083] Fig.74 A partial cross-sectional view of a semiconductor device according to some embodiments of the present disclosure;

[0084] Fig.75is a partial cross-sectional view of a semiconductor device according to some embodiments of the present disclosure;

[0085] Fig.76 is a partial cross-sectional view of a semiconductor device according to some embodiments of the present disclosure;

[0086] Fig.77 is a top view of a semiconductor device according to some embodiments of the present disclosure;

[0087] Fig.78 is Fig.76 a schematic diagram of region A in

[0088] Fig.79 is Fig.76 a schematic diagram of region B in

[0089] Fig.80 is a cross-sectional view of a semiconductor device according to some embodiments of the present disclosure along the A-A direction;

[0090] Fig.81 is a cross-sectional view of a semiconductor device according to some embodiments of the present disclosure along the B-B direction;

[0091] Fig.82 is a partial schematic diagram of a semiconductor device according to another embodiment of the present disclosure;

[0092] Fig.83 is a state diagram of the manufacturing process of a semiconductor device according to some embodiments of the present disclosure;

[0093] Fig.84 is a state diagram of the manufacturing process of a semiconductor device according to some embodiments of the present disclosure;

[0094] Fig.85 is a state diagram of the manufacturing process of a semiconductor device according to some embodiments of the present disclosure;

[0095] Fig.86 is a state diagram of the manufacturing process of a semiconductor device according to some embodiments of the present disclosure;

[0096] Fig.87 is a schematic diagram of a semiconductor device according to some embodiments of the present disclosure;

[0097] Fig.88 is a top view of a semiconductor device according to some embodiments of the present disclosure;

[0098] Fig.89 is a partial schematic diagram of a semiconductor device according to some embodiments of the present disclosure;

[0099] Fig.90 is a cross-sectional view of a semiconductor device according to some embodiments of the present disclosure along the A-A direction;

[0100] Fig.91 is a cross-sectional view of a semiconductor device along the B-B direction according to some embodiments of the present disclosure;

[0101] Fig.92 is a partial cross-sectional view of a semiconductor device according to some embodiments of the present disclosure;

[0102] Fig.93 is a partial cross-sectional view of a semiconductor device according to some embodiments of the present disclosure;

[0103] Fig.94 is a partial cross-sectional view of a semiconductor device according to some embodiments of the present disclosure;

[0104] Fig.95 is a partial cross-sectional view of a semiconductor device according to some embodiments of the present disclosure;

[0105] Fig.96 is a partial cross-sectional view of a semiconductor device according to some embodiments of the present disclosure;

[0106] Fig.97 is a partial cross-sectional view of a semiconductor device according to some embodiments of the present disclosure;

[0107] Fig.98 is a partial cross-sectional view of a semiconductor device according to some embodiments of the present disclosure;

[0108] Fig.99 is a partial schematic view of a semiconductor device according to some embodiments of the present disclosure;

[0109] Fig.100 is a partial schematic view of a semiconductor device according to some embodiments of the present disclosure;

[0110] Fig.101 is a cross-sectional view of a semiconductor device along the A-A direction according to some embodiments of the present disclosure;

[0111] Fig.102 is a partial schematic view of a semiconductor device according to another embodiment of the present disclosure;

[0112] Fig.103 is a partial schematic view of a semiconductor device according to another embodiment of the present disclosure;

[0113] Fig.104 is a partial cross-sectional view of a semiconductor device according to some embodiments of the present disclosure;

[0114] Fig.105 is a partial cross-sectional view of a semiconductor device according to some embodiments of the present disclosure;

[0115] Fig.106 is a partial cross-sectional view of a semiconductor device according to some embodiments of the present disclosure;

[0116] Fig.107 is a partial cross-sectional view of a semiconductor device according to some embodiments of the present disclosure;

[0117] Fig.108 is a partial cross-sectional view of a semiconductor device according to some embodiments of the present disclosure;

[0118] Fig.109 is a partial schematic view of a semiconductor device according to some embodiments of the present disclosure;

[0119] Fig.110 is a partial schematic view of a semiconductor device according to some embodiments of the present disclosure;

[0120] Fig.111 is a cross-sectional view of a semiconductor device according to some embodiments of the present disclosure along the A-A direction;

[0121] Fig.112 is a partial schematic view of a semiconductor device according to another embodiment of the present disclosure;

[0122] Fig.113 is a partial schematic view of a semiconductor device according to another embodiment of the present disclosure;

[0123] Fig.114 is a partial cross-sectional view of a semiconductor device according to some embodiments of the present disclosure;

[0124] Fig.115 is a partial cross-sectional view of a semiconductor device according to some embodiments of the present disclosure;

[0125] Fig.116 is a partial cross-sectional view of a semiconductor device according to some embodiments of the present disclosure;

[0126] Fig.117 is a partial cross-sectional view of a semiconductor device according to some embodiments of the present disclosure;

[0127] Fig.118 is a partial cross-sectional view of a semiconductor device according to some embodiments of the present disclosure.

[0128] Reference numerals:

[0129] 100. Semiconductor device; 101. Active region; 1011. First semiconductor device type region; 1012. Second semiconductor device type region; 1013. Gate region; 1014. dummy gate region; 1015. Insulated gate bipolar transistor region; 1016. Fast recovery diode main conduction region; 1017. Fast recovery diode transition region; 1018. Fast recovery diode region; 102. Transition region; 1021. Gate metal; 1022. Gate runner; 103. Terminal region; 104. Gate pad; 105. Emitter region; 106. Base region; 107. Ring layer; 108. Barrier metal layer; 109. Base layer; 110. Carrier storage layer; 111. Polycrystalline layer; 113. Third connection trench;

[0130] 300. Anode layer; 400. Anode metal layer; 500. Cathode metal layer; 600. Depletion region;

[0131] 1. Fast recovery diode; 2. Substrate; 3. Emitter layer; 4. Channel; 5. Metal electrode; 6. Emitter metal; 7. Terminal structure; 8. Polysilicon field plate; 9. Insulated gate bipolar transistor; 10. Drift layer; 1031. Second via; 1032. Third via; 11. Well layer; 1101. First contact hole; 1102. Second contact hole; 112. Short circuit region; 12. Second emitter layer; 13. Dielectric layer; 1301. Field oxide layer; 1302. Field cutoff ring; 1303. Field limiting ring; 1304. Interlayer dielectric layer; 1305. First dielectric layer; 1306. Second dielectric layer; 131. Sub-emitter part; 14. Emitter metal layer; 15. Field cutoff layer; 16. Collector layer; 17. First emitter layer; 171. Contact hole; 18. Collector metal layer; 19. Pad region;

[0132] 20. First trench; 201. Spacer trench; 2011. Sub-trench part; 21. Gate trench group; 211. Gate trench part; 212. Second sub-trench; 213. Main trench part; 214. Connection trench part; 22. dummy gate trench group; 221. dummy gate trench part; 2221. Gate trench; 223. dummy gate trench; 23. First spacer trench; 231. First sub-trench; 24. First main trench; 241. Third boundary trench; 242. Fourth boundary trench; 25. Voltage withstand ring; 26. Sub-concentration doped layer; 2110. Trench part; 210. First concentration doped layer; 220. Second concentration doped layer; 230. Third concentration doped layer;

[0133] 30. Second groove; 31. First perforation; 32. Second perforation; 341. Third contact hole; 35. Second spacer groove; 351. Third sub-groove; 352. Fourth sub-groove; 3521. Fifth boundary groove; 3522. Sixth boundary groove; 353. Fifth sub-groove; 36. Second main groove; 361. First boundary groove; 362. Second boundary groove;

[0134] 40. First connection groove; 41. First electrical connection protrusion; 42. Second electrical connection protrusion;

[0135] 50. Second connection groove; 501. Emission part;

[0136] 60. Field oxide layer; 61. Field oxide main body; 62. Convex nozzle; 63. Fourth via;

[0137] 70. Oxide insulating layer; 71. Polysilicon; 711. Trench-gate polysilicon; 712. Planar-gate polysilicon;

[0138] 80. Substrate; 801. First via; 81. First main surface; 82. Second main surface; 84. Gate bus; 85. Second polysilicon field plate; 810. Semiconductor substrate;

[0139] 90. Metal field plate; 91. First polysilicon field plate; 911. Main body part; 912. Covering part; 913. Extension part. Detailed implementation manners

[0140] The embodiments described with reference to the accompanying drawings are exemplary. The embodiments of the present disclosure will be described in detail below.

[0141] The fast recovery diode 1 according to some embodiments of the present disclosure will be described below with reference to the accompanying drawings.

[0142] As Figure 1-Figure 9 shown, the fast recovery diode 1 according to some embodiments of the present disclosure includes a substrate 2 of a first conductivity type, a drift layer 10 of a first conductivity type, and an anode layer 300 of a second conductivity type.

[0143] The drift layer 10 includes a first-concentration doping layer 210, a second-concentration doping layer 220, and a third-concentration doping layer 230. The first-concentration doping layer 210 is disposed on the substrate 2. The second-concentration doping layer 220 is disposed on a side of the first-concentration doping layer 210 away from the substrate 2. The third-concentration doping layer 230 is disposed on a side of the second-concentration doping layer 220 away from the substrate 2. The doping concentration of the second-concentration doping layer 220 is not greater than the doping concentration of the first-concentration doping layer 210 and less than the doping concentration of the third-concentration doping layer 230. The doping concentration of the first-concentration doping layer 210 gradually decreases in a direction away from the substrate 2. The anode layer 300 is disposed on a side of the third-concentration doping layer 230 facing away from the substrate 2.

[0144] Among them, the substrate 2 can be formed by arsenic doping, the drift layer 10 can be composed of a phosphorus-doped silicon epitaxial layer, and the anode layer 300 can be formed by boron ion implantation.

[0145] According to the fast recovery diode 1 of some embodiments of the present disclosure, by setting the drift layer 10 as the first concentration doping layer 210, the second concentration doping layer 220, and the third concentration doping layer 230, and the first concentration doping layer 210 is disposed on the substrate 2, the second concentration doping layer 220 is disposed on the side of the first concentration doping layer 210 away from the substrate 2, the third concentration doping layer 230 is disposed on the side of the second concentration doping layer 220 away from the substrate 2, the doping concentration of the second concentration doping layer 220 is not greater than the doping concentration of the first concentration doping layer 210 and less than the doping concentration of the third concentration doping layer 230, that is to say, the concentration of the third concentration doping layer 230 can be relatively large, that is, the doping concentration of the side of the drift layer 10 close to the anode layer 300 can be relatively large, so that the carrier concentration of the side of the drift layer 10 close to the anode layer 300 during forward conduction can be reduced, and thus the peak current of reverse recovery can be effectively reduced.

[0146] Moreover, the doping concentration of the second concentration doping layer 220 can be relatively low, that is, the doping concentration of the second concentration doping layer 220 can be less than the doping concentration of the first concentration doping layer 210 and the third concentration doping layer 230, or the doping concentration of the second concentration doping layer 220 can be equal to the doping concentration of the first concentration doping layer 210 and less than the doping concentration of the third concentration doping layer 230, so that the electric field gradient of the second concentration doping layer 220 can be reduced, which is beneficial to improving the reverse voltage withstand performance of the fast recovery diode 1.

[0147] In addition, the doping concentration of the first concentration doping layer 210 gradually decreases in a direction away from the substrate 2, and the anode layer 300 is disposed on a side of the third concentration doping layer 230 facing away from the substrate 2. That is to say, the side of the first concentration doping layer 210 away from the anode layer 300 is the location where the doping concentration of the first concentration doping layer 210 is the highest, and the side of the first concentration doping layer 210 close to the anode layer 300 is the location where the doping concentration of the first concentration doping layer 210 is the lowest. The doping concentration of the side of the first concentration doping layer 210 away from the anode layer 300 can be relatively large, and the doping concentration of the side of the first concentration doping layer 210 close to the anode layer 300 can be relatively low. This can cause the electric field gradient to gradually increase in a direction away from the anode layer 300, thereby making the width of the depletion region 600 during the reverse recovery process of the fast recovery diode 1 narrower under the same reverse breakdown voltage, avoiding the occurrence of current interruption. Moreover, the first concentration doping layer 210 can inject sufficient carriers, so that there can be more remaining carriers on the side of the first concentration doping layer 210 away from the anode layer 300, which is beneficial to increasing the reverse recovery softness factor of the fast recovery diode 1, that is, improving the reverse recovery softness, which is beneficial to improving the stability and reliability of the circuit. At the same time, it can also ensure that the reverse breakdown voltage of the fast recovery diode 11 is relatively high, avoiding circuit damage.

[0148] Thus, the fast recovery diode 11 according to some embodiments of the present disclosure has advantages such as good breakdown voltage resistance, small reverse recovery peak current, and high circuit stability.

[0149] In some specific embodiments of the present disclosure, such as Figure 2 and Figure 3 shown, the concentration of the first concentration doping layer 210 linearly decreases in a direction away from the substrate 2. In some embodiments, a plurality of sub-concentration doping layers 26 may be provided in the first concentration doping layer, and in a direction away from the substrate 2, the concentrations of the plurality of sub-concentration doping layers 26 gradually decrease, that is, the first concentration doping layer 210 is composed of multiple layers of doping concentration layers decreasing by epitaxy. Then, after the first concentration doping layer 210 undergoes a thermal process diffusion, a distribution with an approximately linearly decreasing doping concentration is obtained. This can cause the electric field gradient to gradually increase linearly in a direction away from the anode layer 300, thereby making the width of the depletion region 600 during the reverse recovery process of the fast recovery diode 1 narrower under the same reverse breakdown voltage, avoiding the occurrence of current interruption, and there can be more remaining carriers on the side of the first concentration doping layer 210 away from the anode layer 300, which is beneficial to increasing the reverse recovery softness factor of the fast recovery diode 1 to improve the stability and reliability of the circuit.

[0150] In some specific embodiments of the present disclosure, such as Figure 1-Figure 9As shown, the thickness of the first-concentration doping layer 210, the thickness of the second-concentration doping layer 220, and the thickness of the third-concentration doping layer 230 decrease in sequence. That is to say, the minimum thickness of the first-concentration doping layer 210 is not less than the maximum thickness of the second-concentration doping layer 220, and the minimum thickness of the second-concentration doping layer 220 is not less than the maximum thickness of the first-concentration doping layer 210. In this way, the thickness of the third-concentration doping layer 230 can be relatively thin, thereby ensuring a relatively large reverse breakdown voltage of the fast-recovery diode 1. At the same time, the thickness of the first-concentration doping layer 210 can be relatively thick to reduce the forward conduction voltage drop, and enable more carriers to be injected into the first-concentration doping layer 210 to ensure the soft recovery of the fast-recovery diode 1.

[0151] In some specific embodiments of the present disclosure, the thickness of the first-concentration doping layer 210 is 30um to 35um. For example, the thickness of the first-concentration doping layer 210 can be 30um, 31um, 32um, 33um, 34um, or 35um. On the one hand, this can avoid the thickness of the first-concentration doping layer 210 being too small, so that enough carriers can be injected into the first-concentration doping layer 210 to ensure the soft recovery of the fast-recovery diode 1. On the other hand, it can avoid the thickness of the first-concentration doping layer 210 being too large, and further avoid an increase in the forward conduction voltage drop of the fast-recovery diode 1.

[0152] In addition, the thickness of the second-concentration doping layer 220 is 20um to 25um. For example, the thickness of the second-concentration doping layer 220 can be 20um, 21um, 22um, 23um, 24um, or 25um. On the one hand, this can avoid the thickness of the second-concentration doping layer 220 being too small to make the voltage withstand performance of the fast-recovery diode 1 better. On the other hand, it can avoid the thickness of the second-concentration doping layer 220 being too large, and further avoid an increase in the forward conduction voltage drop of the fast-recovery diode 1.

[0153] Furthermore, the thickness of the third-concentration doping layer 230 is 8um to 12um. For example, the thickness of the third-concentration doping layer 230 can be 8um, 9um, 10um, 11um, or 12um. On the one hand, this can avoid the thickness of the third-concentration doping layer 230 being too small to effectively reduce the peak current of reverse recovery. On the other hand, it can avoid the thickness of the third-concentration doping layer 230 being too large, and further avoid a reduction in the reverse breakdown voltage of the fast-recovery diode 1.

[0154] In some specific embodiments of the present disclosure, the thickness of the drift layer 10 is 60 um to 80 um. Herein, the thickness of the drift layer 10 is also the sum of the thicknesses of the first concentration doping layer 210, the second concentration doping layer 220, and the third concentration doping layer 230. That is, the thickness of the drift layer 10, which is the sum of the thicknesses of the first concentration doping layer 210, the second concentration doping layer 220, and the third concentration doping layer 230, is 60 um to 80 um.

[0155] For example, the thickness of the drift layer 10 can be 60 um, 62 um, 64 um, 66 um, 68 um, 70 um, 72 um, 74 um, 76 um, 78 um, or 80 um. In this way, it can not only prevent the thickness of the drift layer 10 from being too small to ensure good breakdown voltage performance of the fast recovery diode 1, but also prevent the thickness of the drift layer 10 from being too large to avoid a significant increase in the forward conduction voltage drop of the fast recovery diode 1.

[0156] In addition, the junction depth of the anode layer 300 is 3 um to 5 um. That is to say, the junction depth of the anode layer 300 can be 3 um, 4 um, or 5 um. This can ensure that the overall thickness of the fast recovery diode 1 is appropriate.

[0157] In some specific embodiments of the present disclosure, as Figure 2 shown, the doping concentration of the second concentration doping layer 220 is a fixed value. Herein, the doping concentration of the second concentration doping layer 220 should not be greater than the minimum doping concentration of the first concentration doping layer 210, and the doping concentration of the second concentration doping layer 220 is less than the minimum doping concentration of the third concentration doping layer 230. This can reduce the electric field gradient of the second concentration doping layer 220, which is beneficial to improving the reverse breakdown voltage performance of the fast recovery diode 1, and thus conducive to achieving a compromise between the magnitude of the reverse recovery peak current and the breakdown voltage performance of the fast recovery diode 1.

[0158] In some other specific embodiments of the present disclosure, as Figure 3 shown, the doping concentration of the second concentration doping layer 220 gradually increases in the direction away from the substrate 2. In some embodiments, the doping concentration on the side of the second concentration doping layer 220 away from the substrate 2 is greater than the minimum doping concentration of the first concentration doping layer 210, and the doping concentration on the side of the second concentration doping layer 220 away from the substrate 2 is less than the minimum doping concentration of the third concentration doping layer 230. This can reduce the electric field gradient of the second concentration doping layer 220, which is beneficial to improving the reverse breakdown voltage performance of the fast recovery diode 1, and thus conducive to achieving a compromise between the magnitude of the reverse recovery peak current and the breakdown voltage performance of the fast recovery diode 1.

[0159] In some specific embodiments of the present disclosure, as Figure 2As shown, the doping concentration of the third-concentration doping layer 230 is a fixed value. Among them, the doping concentration of the third-concentration doping layer 230 needs to be greater than the maximum concentration of the second-concentration doping layer 220. In this way, when forward-conducting, the carrier concentration on the side of the drift layer 10 close to the anode layer 300 can be reduced, and thus the peak current of reverse recovery can be effectively reduced.

[0160] In some other specific embodiments of the present disclosure, as Figure 3 shown, the doping concentration of the third-concentration doping layer 230 gradually increases in the direction away from the substrate 2. Among them, the doping concentration of the side of the third-concentration doping layer 230 close to the substrate 2 needs to be greater than the maximum concentration of the second-concentration doping layer 220. In this way, when forward-conducting, the carrier concentration on the side of the drift layer 10 close to the anode layer 300 can be reduced, and thus the peak current of reverse recovery can be effectively reduced.

[0161] In some specific embodiments of the present disclosure, as Figure 2 shown, the doping concentration of the side of the first-concentration doping layer 210 close to the substrate 2 is greater than the doping concentration of the third-concentration doping layer 230. In this way, the doping concentration of the side of the first-concentration doping layer 210 close to the substrate 2 can be relatively large, so that the width of the depletion region 600 in the reverse recovery process of the fast-recovery diode 1 under the same reverse breakdown voltage can be narrower, and further prevent the depletion region 600 from expanding towards the side close to the substrate 2 during the reverse recovery process, ensuring that the cathode stores enough carriers and avoiding the occurrence of current interruption. In addition, the doping concentration of the side of the first-concentration doping layer 210 far from the substrate 2 is equal to the doping concentration of the side of the second-concentration doping layer 220 close to the substrate 2. In this way, it can be avoided that the doping concentration of the first-concentration doping layer 210 is too high, so that enough carriers can be injected into the first-concentration doping layer 210, and the remaining carriers on the side of the first-concentration doping layer 210 close to the substrate 2 can be more, which is beneficial to increasing the reverse recovery softness factor of the fast-recovery diode 1, that is, improving the reverse recovery softness.

[0162] In some specific embodiments of the present disclosure, the doping concentration of the side of the first-concentration doping layer 210 close to the substrate 2 is 8×1014 cm-3 to 10×1014 cm-3. On the one hand, this can avoid too low doping concentration of the first-concentration doping layer 210, so that the width of the depletion region 600 in the reverse recovery process of the fast-recovery diode 1 under the same reverse breakdown voltage is narrower, and avoid the occurrence of current interruption. On the other hand, it can avoid too high doping concentration of the first-concentration doping layer 210, so that enough carriers can be injected into the first-concentration doping layer 210, and the remaining carriers on the side of the first-concentration doping layer 210 close to the substrate 2 can be more, which is beneficial to increasing the reverse recovery softness factor of the fast-recovery diode 1, that is, improving the reverse recovery softness.

[0163] In addition, the doping concentration of the second concentration doping layer 220 is 1×1014 cm-3 to 1.5×1014 cm-3. In this way, on the one hand, it can avoid too low doping concentration of the second concentration doping layer 220 to make the breakdown voltage performance of the fast recovery diode 1 better. On the other hand, it can avoid too high doping concentration of the second concentration doping layer 220, and further avoid the increase of the forward conduction voltage drop of the fast recovery diode 1.

[0164] In addition, the doping concentration of the third concentration doping layer 230 is 5×1014 cm-3 to 6×1014 cm-3. In this way, on the one hand, it can avoid too low doping concentration of the third concentration doping layer 230 to effectively reduce the peak current of reverse recovery. On the other hand, it can avoid too high doping concentration of the third concentration doping layer 230, and further avoid the reduction of the reverse breakdown voltage of the fast recovery diode 1.

[0165] In some specific embodiments of the present disclosure, as Figure 7 shown, the fast recovery diode 1 further includes an anode metal layer 400 and a cathode metal layer 500.

[0166] The anode metal layer 400 is disposed on the side of the anode layer 300 facing away from the drift layer 10, and the cathode metal layer 500 is disposed on the side of the substrate 2 facing away from the drift layer 10. That is to say, along the anode metal layer 400 to the cathode metal layer 500, the third concentration doping layer 230, the second concentration doping layer 220, and the first concentration doping layer 210 are arranged in sequence, and the doping concentration of the first concentration doping layer 210 gradually increases in the direction from the anode metal layer 400 towards the cathode metal layer 500.

[0167] The following describes the manufacturing process of the fast recovery diode 1 according to some embodiments of the present disclosure with reference to the drawings:

[0168] First, as Figure 6 shown, the first concentration doping layer 210, the second concentration doping layer 220, and the third concentration doping layer 230 are sequentially grown epitaxially on the substrate 2;

[0169] Then, as Figure 7 shown, Pwell ions are implanted on the side of the third concentration doping layer 230 facing away from the substrate 2 to form a P-type region, that is, the anode layer 300 of the embodiment of the present disclosure;

[0170] Next, as Figure 8 shown, anode metal is deposited on the side of the anode layer 300 facing away from the substrate 2 to form the anode metal layer 400;

[0171] Finally, as Fig. 9 shown, the substrate 2 is thinned, and cathode metal is deposited on the side of the substrate 2 facing away from the anode metal layer 400 to form the cathode metal layer 500.

[0172] Refer to the following Figure 10-15 to describe the semiconductor device 100 according to some embodiments of the present disclosure. The semiconductor device 100 is, for example, an IGBT (Insulated Gate Bipolar Transistor). In the following description, N and P represent the conduction types of semiconductors. In the present disclosure, the first conduction type is set as the N type and the second conduction type is set as the P type for description.

[0173] Combined with Fig.11 as shown, the semiconductor device 100 according to the present disclosure may mainly include: a drift layer 10 of the first conduction type, a breakdown voltage ring 25 of the second conduction type, a dielectric layer 13, a metal field plate 90, and a first polysilicon field plate 91.

[0174] In some embodiments, a field stop layer 15 of the first conduction type is disposed below the drift layer 10 of the first conduction type, a collector layer 16 of the second conduction type is disposed below the field stop layer 15, and a collector metal layer 18 is disposed below the collector layer 16, so as to form the basic structure of the semiconductor device 100 and ensure the normal operation of the semiconductor device 100.

[0175] Considering that the transition region 102 of the semiconductor device 100 is located between the terminal region 103 and the active region 101, the structure of the transition region 102 is relatively complex and voltage breakdown is likely to occur there. By disposing the breakdown voltage ring 25 on the surface of the drift layer 10 corresponding to the transition region 102 of the semiconductor device 100, the breakdown voltage ring 25 can optimize the electric field distribution in the transition region 102 and improve the breakdown voltage withstand capacity of the transition region 102.

[0176] Combined with Fig.11 、 Fig.14 and Fig.15 as shown, the dielectric layer 13 is disposed on the upper surface of the breakdown voltage ring 25, the metal field plate 90 is disposed on the upper surface of the dielectric layer 13, the first polysilicon field plate 91 is disposed on the upper surface of the breakdown voltage ring 25, and the first polysilicon field plate 91 is located between the dielectric layer 13 and the breakdown voltage ring 25, and the metal field plate 90 is at least partially in contact with the first polysilicon field plate 91.

[0177] In some embodiments, by disposing the dielectric layer 13 on the upper surface of the breakdown voltage ring 25 and disposing the metal field plate 90 on the upper surface of the dielectric layer 13, a part of the metal field plate 90 can be in direct contact with the breakdown voltage ring 25 and another part can be in contact with the dielectric layer 13. When the semiconductor device 100 is subjected to a reverse bias voltage, the metal field plate 90 can cancel the influence of the positive charges in the dielectric layer 13 on the surface, repel the surface electrons, and widen the surface depletion region 600 at the interface, thereby increasing the breakdown voltage.

[0178] In some embodiments, considering that the contact area between the metal field plate 90 and the breakdown voltage ring 25 is small, the improvement of the breakdown voltage resistance of the semiconductor device 100 in the transition region 102 is limited. Compared with the comparative embodiment without the first polysilicon field plate 91, in the embodiments of the present disclosure, by disposing the first polysilicon field plate 91 between the dielectric layer 13 and the breakdown voltage ring 25, the first polysilicon field plate 91 can achieve a large-area direct contact with the breakdown voltage ring 25, and the metal field plate 90 can be at least partially in contact with the first polysilicon field plate 91, so that the first polysilicon field plate 91 and the metal field plate 90 are at the same potential.

[0179] Thus, when the semiconductor device 100 is subjected to a reverse bias voltage, both the metal field plate 90 and the first polysilicon field plate 91 can cancel the influence of the positive charges in the dielectric layer 13 on the surface, repel the surface electrons, widen the surface depletion region 600 at the interface, thereby significantly improving the surface charge and electric field distribution at the contact position between the first polysilicon field plate 91 and the breakdown voltage ring 25, effectively reducing the surface charge of the semiconductor device 100, and further significantly increasing the breakdown voltage of the semiconductor device 100, avoiding the breakdown and failure of the transition region 102 of the semiconductor device 100, and improving the breakdown voltage resistance and reliability of the semiconductor device 100.

[0180] Therefore, by disposing the first polysilicon field plate 91 on the upper surface of the breakdown voltage ring 25, the first polysilicon field plate 91 is located between the dielectric layer 13 and the breakdown voltage ring 25, and the metal field plate 90 is at least partially in contact with the first polysilicon field plate 91, so that the electric field distribution in the transition region 102 can be optimized, the breakdown voltage of the semiconductor device 100 can be significantly increased, and the breakdown voltage resistance and reliability of the semiconductor device 100 can be significantly improved.

[0181] Combined with Fig.11 As shown, the semiconductor device 100 may further include a field oxide layer 60. The field oxide layer 60 is disposed on the upper surface of the breakdown voltage ring 25, and the field oxide layer 60 is located between the first polysilicon field plate 91 and the breakdown voltage ring 25. In some embodiments, by disposing the field oxide layer 60 in the semiconductor device 100 such that the field oxide layer 60 is on the upper surface of the breakdown voltage ring 25, the field oxide layer 60 can be used for isolation to prevent the occurrence of parasitic transistors, and by locating the field oxide layer 60 between the first polysilicon field plate 91 and the breakdown voltage ring 25, the first polysilicon field plate 91 can be located above the field oxide layer 60, and the first polysilicon field plate 91 can modulate the electric field in the contact region between it and the field oxide layer 60 to make the electric field distribution more uniform, thereby improving the breakdown voltage resistance and reliability of the semiconductor device 100 in some embodiments.

[0182] In some embodiments, combined with Fig.12As shown, the field oxide layer 60 may mainly include a field oxide main body 61 and a protruding nozzle 62. The protruding nozzle 62 is disposed at one end of the field oxide main body 61, and at least a part of the first polysilicon field plate 91 covers the protruding nozzle 62.

[0183] In some embodiments, due to the growth process of the field oxide layer 60, the field oxide layer 60 includes a field oxide main body 61 and a protruding nozzle 62. The protruding nozzle 62 is located at one end of the field oxide main body 61. In the area of the protruding nozzle 62, the surface charge of the semiconductor device 100 is concentrated and the electric field distribution is relatively uneven, which is a weak area of the transition region 102. By making at least a part of the first polysilicon field plate 91 cover the protruding nozzle 62, the first polysilicon field plate 91 can improve the surface charge and electric field distribution in the area of the protruding nozzle 62, thereby increasing the breakdown voltage, enhancing the voltage withstand capacity of the semiconductor device 100, and enhancing the reliability of the semiconductor device 100.

[0184] Combined with Fig.12 As shown, the first polysilicon field plate 91 may include a main body portion 911, a covering portion 912, and an extending portion 913. The covering portion 912 is connected between the main body portion 911 and the extending portion 913. The main body portion 911 covers the upper surface of the field oxide main body 61, the covering portion 912 covers the upper surface of the protruding nozzle 62, and the extending portion 913 extends outside the protruding nozzle 62 and contacts the voltage withstand ring 25.

[0185] In some embodiments, by covering the main body portion 911 on the upper surface of the field oxide main body 61 and covering the covering portion 912 on the upper surface of the protruding nozzle 62, the first polysilicon field plate 91 can cover the field oxide layer 60, ensuring a uniform distribution of the electric field on the upper surface of the field oxide layer 60 in the transition region 102.

[0186] In some embodiments, by making the extending portion 913 cover the outside of the protruding nozzle 62, the extending portion 913 can modulate the electric field in the outside area of the protruding nozzle 62, ensuring a uniform distribution of the electric field in the outside area of the protruding nozzle 62.

[0187] In this way, in some embodiments, the structure and setting position of the first polysilicon field plate 91 can be optimized, the electric field modulation ability of the first polysilicon field plate 91 for the transition region 102 can be improved, electric field concentration can be avoided, the electric field distribution in the transition region 102 can be made more uniform, the voltage withstand capacity of the semiconductor device 100 can be increased in some embodiments, and the reliability of the semiconductor device 100 can be increased in some embodiments.

[0188] In some embodiments, combined with Fig.12As shown, the length of the extension portion 913 is L1, and L1 satisfies the relationship: L1 ≥ 2 μm. In some embodiments, by setting the length of the extension portion 913 within a reasonable range, that is, setting the length of the first polysilicon field plate 91 extending relative to the convex nozzle 62 to one side within a reasonable range, it is possible to optimize the electric field distribution in the area near the convex nozzle 62 for the first polysilicon field plate 91 in some embodiments, avoiding the situation where the length of the extension portion 913 is too short, resulting in local electric field concentration still existing on the side close to the convex nozzle 62 and far from the main body portion 911. Thus, the uniformity of the overall electric field distribution in the transition region 102 can be ensured in some embodiments, and the reliability of the transition region 102 and even the semiconductor device 100 can be improved in some embodiments.

[0189] Combined with Fig.13 As shown, a first through hole 31 is provided on the dielectric layer 13, and a first electrical connection protrusion 41 is provided on the metal field plate 90. The first electrical connection protrusion 41 penetrates through the first through hole 31 and is in contact with the first polysilicon field plate 91.

[0190] In some embodiments, the dielectric layer 13 is located between the first polysilicon field plate 91 and the metal field plate 90. By providing the first through hole 31 on the dielectric layer 13 and the first electrical connection protrusion 41 on the metal field plate 90, only by making the first electrical connection protrusion 41 penetrate through the first through hole 31 and making the first electrical connection protrusion 41 in contact with the first polysilicon field plate 91, it is possible to make the metal field plate 90 at least partially in contact with the first polysilicon field plate 91, making the connection between the metal field plate 90 and the first polysilicon field plate 91 simpler, more convenient, and stable and reliable.

[0191] Combined with Fig.13 As shown, the metal field plate 90 is at least partially in contact with the breakdown voltage ring 25, and the metal field plate 90 and the breakdown voltage ring 25 have the same electric potential.

[0192] In some embodiments, by making the metal field plate 90 at least partially in contact with the breakdown voltage ring 25, the metal field plate 90 and the breakdown voltage ring 25 can have the same electric potential. And since the metal field plate 90 is also at least partially in contact with the first polysilicon field plate 91 and the metal field plate 90 and the first polysilicon field plate 91 have the same electric potential, in this way, the breakdown voltage ring 25, the metal field plate 90, and the first polysilicon field plate 91 can be at the same electric potential, avoiding the appearance of floating electric fields in the transition region 102 and avoiding the problem that the floating electric fields are interfered by the outside world during the operation of the semiconductor device 100, resulting in uneven electric field distribution in the transition region 102 and causing a decrease in breakdown voltage and reliability. Thus, the breakdown voltage capacity of the semiconductor device 100 can be improved, and the reliability of the semiconductor device 100 can be improved.

[0193] In some embodiments, combined with Fig.13As shown, a second via 32 is provided on the dielectric layer 13, and a second electrical connection bump 42 is provided on the metal field plate 90. The second electrical connection bump 42 passes through the second via 32 and contacts the breakdown voltage ring 25, and the second electrical connection bump 42 is spaced apart from the first polysilicon field plate 91.

[0194] In some embodiments, in the region where the first polysilicon field plate 91 is not provided in the transition region 102, at least a part of the dielectric layer 13 is still located between the breakdown voltage ring 25 and the metal field plate 90. By providing the second via 32 on the dielectric layer 13 and providing the second electrical connection bump 42 on the metal field plate 90, and the second electrical connection bump 42 is spaced apart from the first polysilicon field plate 91, only by making the second electrical connection bump 42 pass through the second via 32 and making the second electrical connection bump 42 contact the breakdown voltage ring 25, the metal field plate 90 can be at least partially connected to the breakdown voltage ring 25, making the connection between the metal field plate 90 and the breakdown voltage ring 25 simpler and more convenient, and stable and reliable.

[0195] Combined Fig.10 and Fig.11 As shown, the semiconductor device 100 further has an active region 101 and a terminal region 103. The terminal region 103 is provided on the periphery of the active region 101, and the transition region 102 is connected between the active region 101 and the terminal region 103.

[0196] In some embodiments, the active region 101 can both carry most of the forward current during forward conduction and bear a high blocking voltage when a reverse voltage is applied. In some embodiments, by providing the terminal region 103 on the periphery of the active region 101 and connecting the transition region 102 between the active region 101 and the terminal region 103, when the semiconductor device 100 is applied with a reverse voltage, the terminal region 103 can relieve the electric field crowding at the edge of the active region 101, thereby achieving the purpose of increasing the reverse breakdown voltage of the semiconductor device 100.

[0197] Wherein, the active region 101 is provided with an emitter metal layer 14. The emitter metal layer 14 can be used as the emitter of the semiconductor device 100 and plays a role in conducting electricity and connecting. In addition, a gate bus 84 is provided in the transition region 102. The gates in parallel in the semiconductor device 100 are connected to the gate pad through the gate bus 84 and connected to an external gate drive circuit through the gate pad.

[0198] Combined Fig.10As shown, the metal field plate 90 is connected to the emitter metal layer 14 of the active region 101. In some embodiments, considering that the metal field plate 90 is in contact with the first polysilicon field plate 91, by connecting the metal field plate 90 to the emitter metal layer 14 of the active region 101, the metal field plate 90, the first polysilicon field plate 91, and the emitter metal layer 14 of the active region 101 can be made equipotential, and the electric field distribution in the transition region 102 can be made more uniform, thereby improving the breakdown voltage resistance of the transition region 102 and even the semiconductor device 100 in some embodiments.

[0199] Combined with Fig.11 As shown, the terminal region 103 is provided with a second polysilicon field plate 85, and the first polysilicon field plate 91 and the second polysilicon field plate 85 are made of the same material and are spaced apart.

[0200] In some embodiments, considering that the electric field intensity in the terminal region 103 is relatively strong and the voltage borne per unit length is relatively large, and voltage breakdown is more likely to occur at this location, by providing the second polysilicon field plate 85 in the terminal region 103, the second polysilicon field plate 85 can effectively broaden the main junction depletion region 600 outward, avoiding the phenomenon of electric field concentration, thereby increasing the breakdown voltage of the terminal region 103 and improving the breakdown voltage resistance of the terminal region 103 and even the semiconductor device 100.

[0201] In some embodiments, by making the first polysilicon field plate 91 and the second polysilicon field plate 85 of the same material and spacing them apart, in the manufacturing process of the semiconductor device 100, the first polysilicon field plate 91 and the second polysilicon field plate 85 can be synchronously fabricated and formed, and the manufacturing processes of the first polysilicon field plate 91 and the second polysilicon field plate 85 can be combined without adding extra processes, which can simplify the production process of the semiconductor device 100.

[0202] Next, refer to Figure 16-Figure 22 Describe the semiconductor device 100 according to some embodiments of the present disclosure. The semiconductor device 100 can be an RC-IGBT, the first semiconductor device type region 1011 can be an IGBT region, and the second semiconductor device type region 1012 can be an FRD region. In the following description, N and P represent the conductivity types of semiconductors. In the present disclosure, the first conductivity type is set as the N type and the second conductivity type is set as the P type for description.

[0203] Combined with Figure 16-Figure 18 As shown, the semiconductor device 100 according to the present disclosure mainly includes: a drift layer 10 of the first conductivity type, a field stop layer 15 of the first conductivity type, and a collector layer 16 of the second conductivity type.

[0204] In some embodiments, a well layer 11 of a second conductivity type is disposed on the upper surface of a drift layer 10 of a first conductivity type, a first emitter layer 17 of the first conductivity type located in the well layer 11, a dielectric layer 13 located above the first emitter layer 17, and an emitter metal layer 14 located above the dielectric layer 13. A field stop layer 15 of the first conductivity type is disposed on the lower surface of the drift layer 10 of the first conductivity type, a collector layer 16 of the second conductivity type disposed on the lower surface of the field stop layer 15, the first emitter layer 17 of the first conductivity type, and a collector metal layer 18 located at the bottommost.

[0205] Among them, the dielectric layer 13 can protect the well layer 11 and reduce the damage risk of the semiconductor device 100. By forming a contact hole 171 in the dielectric layer 13, the contact hole 171 is located above the well layer 11, and the contact hole 171 is located between two adjacent trench portions 2110, the contact hole 171 extends in a second direction, and the second emitter layer 12 is at least partially located below the contact hole 171, so that the emitter metal layer 14 can contact the second emitter layer 12 through the contact hole 171.

[0206] In some embodiments, the semiconductor device 100 includes an active region 101 and a terminal region 103 surrounding the outside of the active region 101. The first emitter layer 17 is disposed in the collector layer 16. The region corresponding to the collector layer 16 in the vertical direction is a first semiconductor device type region 1011, and the region corresponding to the first emitter layer 17 in the vertical direction is a second semiconductor device type region 1012, that is: the active region 101 of the semiconductor device 100 may include the first semiconductor device type region 1011 and the second semiconductor device type region 1012. The emitter metal layer 14 can not only serve as the emitter lead-out terminal of the first semiconductor device type region 1011, but also serve as the anode lead-out terminal of the second semiconductor device type region 1012. The collector metal layer 18 can not only serve as the collector lead-out terminal of the first semiconductor device type region 1011, but also serve as the cathode lead-out terminal of the second semiconductor device type region 1012. Thus, the first semiconductor device type region 1011 can achieve the forward conduction of the semiconductor device 100, and the second semiconductor device type region 1012 can achieve the reverse conduction of the semiconductor device 100, enabling the semiconductor device 100 to have both forward conduction and reverse conduction characteristics.

[0207] Combined Fig.17 and Fig.18As shown, the semiconductor device 100 may further include trench portions 2110 that extend downward from the upper surface of the drift layer 10. The trench portions 2110 extend in a first direction and are multiple. The multiple trench portions 2110 are spaced apart in a second direction and form a gate trench group 21 and a dummy gate trench group 22. The gate trench group 21 and the dummy gate trench group 22 are alternately arranged in the second direction.

[0208] In some embodiments, the gate trench group 21 includes at least one gate trench portion 211, and the dummy gate trench group 22 includes at least one dummy gate trench portion 221. Oxide insulating layers 70 are provided in both the gate trench portion 211 and the dummy gate trench portion 221, and polysilicon 71 is deposited. Among them, a gate may be formed at the gate trench portion 211, and second emitter layers 12 are provided on both sides of the gate trench portion 211 in the second direction. The gate trench portion 211 has a conductive channel 4 with current-carrying capacity to ensure the normal operation of the first semiconductor device type region 1011 and even the semiconductor device 100. However, second emitter layers 12 are not provided on both sides of the dummy gate trench portion 221 in the second direction. The dummy gate trench portion 221 does not have a conductive channel 4 and does not have current-carrying capacity. The dummy gate trench portion 221 may be connected to the emitter to reduce the Miller capacitance and lower the current density, thereby improving the short-circuit ability of the semiconductor device 100.

[0209] Moreover, by alternately arranging the gate trench group 21 and the dummy gate trench group 22 in the second direction, the uniformity of the circuit distribution of the semiconductor device 100 can be improved, the thermal distribution and anti-interference ability of the circuit can be improved, and the specific number of dummy gate trench portions 221 in the dummy gate trench group 22 and the specific number of gate trench portions 211 in the gate trench group 21 can be set according to the specific short-circuit requirements of the semiconductor device 100, and no specific limitation is made here.

[0210] In some embodiments, the first emitter layer 17 is vertically aligned with the dummy gate trench group 22. In some embodiments, the region corresponding to the dummy gate trench group 22 in the vertical direction is the dummy gate region 1014. Compared with the prior art in which the second semiconductor device type region and the dummy gate region are separately arranged, by vertically aligning the first emitter layer 17 with the dummy gate trench group 22, the area of the dummy gate region 1014 can be fully utilized, and there is no need to separately set the second semiconductor device type region 1012. Thus, on the premise of ensuring that the semiconductor device 100 has both forward conduction and reverse conduction characteristics and ensuring the short-circuit ability of the semiconductor device 100, the dummy gate region 1014 can also be used as the second semiconductor device type region 1012, which can reduce the area of the semiconductor device 100, improve the working performance of the semiconductor device 100, and reduce the production cost of the semiconductor device 100.

[0211] Thus, by making the first emitter layer 17 correspond to the dummy gate trench group 22 vertically, the dummy gate region 1014 can be fully utilized, eliminating the need to separately provide the second semiconductor device type region 1012. The dummy gate region 1014 can also be used as the second semiconductor device type region 1012, reducing the area of the semiconductor device 100, improving the working performance of the semiconductor device 100, and reducing the production cost of the semiconductor device 100.

[0212] Combined with Figure 16-Figure 18 As shown, there are multiple first emitter layers 17 and multiple dummy gate trench groups 22, and the multiple first emitter layers 17 are arranged in one-to-one correspondence with the multiple dummy gate trench groups 22. In some embodiments, by arranging the first emitter layers 17 in one-to-one correspondence with the multiple dummy gate trench groups 22, not only can the area of the dummy gate region 1014 be fully utilized, reducing the area of the semiconductor device 100 in some embodiments, but also the distribution of the multiple first emitter layers 17 in the semiconductor device 100 can be made more uniform, improving the working performance of the semiconductor device 100.

[0213] In some embodiments of the present disclosure, the first emitter layer 17 extends in the first direction. In some embodiments, by extending the first emitter layer 17 in the first direction, on the premise of ensuring the current specification of the second semiconductor device type region 1012, it is convenient to arrange the first emitter layer 17 in the semiconductor device 100, simplifying the working process of the second semiconductor device type region 1012 and even the semiconductor device 100, and improving the production efficiency.

[0214] In some other embodiments of the present disclosure, combined with Figure 16-Figure 18 As shown, the first emitter layer 17 includes multiple sub-emitter portions 131, and the multiple sub-emitter portions 131 are spaced apart in the first direction. In some embodiments, by making the first emitter layer 17 include multiple sub-emitter portions 131 and making the multiple sub-emitter portions 131 spaced apart in the first direction, the distribution of the multiple sub-emitter portions 131 in the semiconductor device 100 can be made more uniform and reasonable, thereby optimizing the working performance of the second semiconductor device type region 1012 and even the semiconductor device 100.

[0215] It should be noted that the lengths and spacings of the multiple sub-emitter portions 131 in the first direction are related to the current specifications of the second semiconductor device type region 1012. The larger its rated current, the larger the total area of the first emitter layer 17, that is: the longer the length of the sub-emitter portion 131, and the smaller the spacing between two adjacent sub-emitter portions 131. When the spacing between two adjacent sub-emitter portions 131 is zero, that is: the first emitter layer 17 extends in the first direction. In actual production and manufacturing, according to the actual application scenario, the first emitter layer 17 can be selectively extended in the first direction, or the first emitter layer 17 can include multiple sub-emitter portions 131 spaced apart in the first direction.

[0216] Combined with Figure 16-Figure 18 As shown, the projection of the dummy gate trench group 22 on the lower surface of the drift layer 10 covers the projection of the first emitter layer 17 on the lower surface of the drift layer 10. In some embodiments, the region corresponding to the gate trench group 21 in the up and down direction is the gate region 1013. To ensure the normal operation of the first semiconductor device type region 1011, the gate trench group 21 should correspond to the collector layer 16 in the up and down direction, rather than the first emitter layer 17, that is: the collector layer 16 should be located in the gate region 1013, and the first emitter layer 17 should be located in the dummy gate region 1014.

[0217] By making the projection of the dummy gate trench group 22 on the lower surface of the drift layer 10 cover the projection of the first emitter layer 17 on the lower surface of the drift layer 10, this can ensure that the first emitter layer 17 only corresponds to the dummy gate trench group 22 in the up and down direction, thereby avoiding the first emitter layer 17 entering the gate region 1013, avoiding affecting the first semiconductor device type region 1011, and further ensuring the working performance of the first semiconductor device type region 1011 and the normal operation of the semiconductor device 100.

[0218] Combined with Fig.17 As shown, the length of the first emitter layer 17 in the first direction is less than the length of the dummy gate trench group 22 in the first direction. In some embodiments, by setting the length of the first emitter layer 17 in the first direction to be less than the length of the dummy gate trench group 22 in the first direction, this can avoid the first emitter layer 17 protruding from both ends of the dummy gate trench group 22 in the first direction, resulting in the first emitter layer 17 entering the gate region 1013 in the first direction and affecting the first semiconductor device type region 1011, and can ensure the working performance of the first semiconductor device type region 1011 and the normal operation of the semiconductor device 100.

[0219] In some embodiments of the present disclosure, combined with Fig.17As shown, the width of the first emitter layer 17 in the second direction is equal to the width of the dummy gate trench group 22 in the second direction. In some embodiments, the width of the first emitter layer 17 in the second direction can be set to be equal to the width of the dummy gate trench group 22 in the second direction, so that the area of the dummy gate trench group 22 in the second direction can be fully utilized, thereby effectively utilizing the area of the semiconductor device 100, improving the performance of the semiconductor device 100, and reducing costs.

[0220] In some other embodiments of the present disclosure, the width of the first emitter layer 17 in the second direction is less than the width of the dummy gate trench group 22 in the second direction. In some embodiments, the width of the first emitter layer 17 in the second direction can be set to be less than the width of the dummy gate trench group 22 in the second direction, so as to more effectively prevent the first emitter layer 17 from protruding beyond the end of the dummy gate trench group 22 in the second direction and entering the gate region 1013 in the second direction, thereby avoiding affecting the first semiconductor device type region 1011 and ensuring the working performance of the first semiconductor device type region 1011 and the normal operation of the semiconductor device 100.

[0221] In some embodiments of the present disclosure, the dummy gate trench group 22 may include a single dummy gate trench portion 221, and the width of the first emitter layer 17 in the second direction is less than the width of the single dummy gate trench portion 221 in the second direction, or the width of the first emitter layer 17 in the second direction is equal to the width of the single dummy gate trench portion 221 in the second direction.

[0222] In some embodiments, when the dummy gate trench group 22 includes only a single dummy gate trench portion 221, the dummy gate trench portion 221 and the gate trench group 21 are spaced apart from each other, and the width of the dummy gate trench group 22 in the second direction is the width of a single gate trench portion 211 in the second direction. At this time, the width of the first emitter layer 17 in the second direction can be set to be less than the width of the single dummy gate trench portion 221 in the second direction, or the width of the first emitter layer 17 in the second direction can be set to be equal to the width of the single dummy gate trench portion 221 in the second direction, so that each first emitter layer 17 falls within the corresponding dummy gate region 1014 of each dummy gate trench portion 221, preventing the first emitter layer 17 from entering the gate region 1013 in the second direction and ensuring the respective performances of the second semiconductor device type region 1012 and the first semiconductor device type region 1011.

[0223] In some other embodiments of the present disclosure, in combination with Fig.17As shown, the dummy gate trench group 22 may include at least two dummy gate trench portions 221 spaced apart in the second direction. The width of the first emitter layer 17 in the second direction is D1, the sum of the widths of at least two dummy gate trench portions 221 in the second direction is D2, and the sum of the spacing distances of at least two dummy gate trench portions 221 in the second direction is D3. D1, D2, and D3 satisfy the relation: D1 ≤ D2 + D3.

[0224] In some embodiments, when the dummy gate trench group 22 includes at least two dummy gate trench portions 221 spaced apart in the second direction, the at least two dummy gate trench portions 221 are spaced apart from the gate trench group 21. The width of the dummy gate trench group 22 in the second direction can be understood as the sum of the widths of at least two dummy gate trench portions 221 in the second direction plus the sum of the spacing distances of at least two dummy gate trench portions 221 in the second direction. At this time, the width of the first emitter layer 17 in the second direction can be set to be not greater than the sum of the widths of at least two dummy gate trench portions 221 in the second direction and the sum of the spacing distances of at least two dummy gate trench portions 221 in the second direction. In this way, each first emitter layer 17 can fall within each dummy gate region 1014, avoiding the first emitter layer 17 entering the gate region 1013 in the second direction, ensuring the respective performances of the second semiconductor device type region 1012 and the first semiconductor device type region 1011, and ensuring the normal operation of the semiconductor device 100.

[0225] The following combines Figure 18-Figure 21 Describe the manufacturing method of the semiconductor device 100 by way of example. The semiconductor device 100 is an RC-IGBT and includes the following steps:

[0226] Step 1, as Fig.19 shown, provide the N-substrate 2 material as the drift layer 10. Form structure 1.

[0227] Step 2, as Fig. 20 shown, on the basis of structure 1, etch the trench portion 2110, and sequentially grow an oxide insulating layer 70 and deposit polysilicon 71 in the trench portion 2110, and then etch the polysilicon 71. Form structure 2.

[0228] Step 3, as Fig.21 shown, on the basis of structure 2, implant to form the P-well layer 11, implant the N+ second emitter layer 12 in the well layer 11 and anneal, and then deposit a dielectric layer 13 thereon. Form structure 3.

[0229] Step 4, as Fig. 22 shown, on the basis of structure 3, etch the contact hole 171, and perform metal sputtering to prepare the emitter metal layer 14. Form structure 4.

[0230] Step 5, as Fig.18As shown, on the basis of structure 4, N+ field stop layer 15 implantation, P+ collector layer 16 implantation, FRD region N+ first emitter layer 17 implantation, laser annealing, and metal sputtering are sequentially performed to prepare collector metal layer 18. Finally, semiconductor device 100 is formed.

[0231] The following refers to Figure 23-Figure 26 Describe semiconductor device 100 according to some embodiments of the present disclosure. The semiconductor device 100 is, for example, a reverse-conducting insulated gate bipolar transistor. In the following description, N and P represent the conduction types of semiconductors. In the present disclosure, the first conduction type is set as the N type and the second conduction type is set as the P type for description.

[0232] Combined with Fig.23 As shown, the semiconductor device 100 according to the present disclosure may mainly include: a drift layer 10 of the first conduction type, a well layer 11 of the second conduction type, a field stop layer 15, and a collector layer 16 of the second conduction type. Among them, the well layer 11 is disposed in a portion of the drift layer 10 corresponding to the transition region 102 of the semiconductor device 100, and the upper surface of the well layer 11 constitutes a part of the upper surface of the drift layer 10. The field stop layer 15 is disposed on the lower surface of the drift layer 10, and the collector layer 16 is disposed on the lower surface of the field stop layer 15.

[0233] In some embodiments, a drift layer 10 of the first conduction type, a well layer 11 of the second conduction type, a field stop layer 15, and a collector layer 16 of the second conduction type are provided in the semiconductor device 100. The field stop layer 15 is provided on the lower surface of the drift layer 10, and the collector layer 16 is provided on the lower surface of the field stop layer 15. In this way, the basic structure of the semiconductor structure can be formed to ensure the normal operation of the semiconductor device 100.

[0234] In some embodiments, an emitter layer 3 of the first conduction type is provided in the collector layer 16, and the emitter layer 3 is located in a portion of the collector layer 16 corresponding to the terminal region 103. In some embodiments, the conduction type of the collector layer 16 is the second conduction type, and the conduction type of the emitter layer 3 in the collector layer 16 is the first conduction type. The emitter layer 3 is provided in a portion of the collector layer 16 corresponding to the transition region 102. In this way, the emitter layer 3 of the first conduction type in the collector layer 16, the drift layer 10 of the first conduction type, and the well layer 11 of the second conduction type in the transition region 102 can form a reverse-conducting structure in the semiconductor device 100, and the reverse conduction of the semiconductor device 100 can be realized.

[0235] In the prior art, the insulated gate bipolar transistor and the fast recovery diode in the reverse-conducting insulated gate bipolar transistor are integrally disposed in the active region of the semiconductor device. When the semiconductor device conducts forward, under the drive of the gate voltage, the emitter layer of the first conductivity type in the insulated gate bipolar transistor device injects electrons into the drift region of the first conductivity type through the channel, and the collector region of the second conductivity type on the back surface of the semiconductor device injects holes upward, forming a conductive path from top to bottom. When conducting reversely, the fast recovery diode device integrated in the semiconductor device starts to work. The well layer 11 of the second conductivity type on the front surface serves as the anode of the fast recovery diode to inject holes into the drift region, and the emitter layer of the second conductivity type on the back surface serves as the cathode to inject electrons into the drift region, realizing the integration of the insulated gate bipolar transistor device and the fast recovery diode device in the same semiconductor device. However, the fast recovery diode device needs to occupy a part of the area of the active region of the semiconductor device. To achieve the on-state voltage drop of the insulated gate bipolar transistor, the area of the active region of the semiconductor device needs to be increased, which will increase the overall size of the semiconductor device. In addition, the increase in the area of the active region of the semiconductor device will cause an increase in the heat generated when the insulated gate bipolar transistor works, thereby reducing the reliability of the insulated gate bipolar transistor.

[0236] In some embodiments, in the embodiments of the present disclosure, the structure of the emitter layer 3 constituting the fast recovery diode 1 is disposed in the part of the semiconductor device 100 corresponding to the transition region 102 of the collector layer 16. In this way, the structure of the fast recovery diode 1 can be disposed in the transition region 102, which can not only achieve the reverse conduction of the semiconductor device 100, but also reduce the structure disposed in the active region 101 of the semiconductor device 100, so that the area of the active region 101 can be used as much as possible to dispose the structure of the insulated gate bipolar transistor 9, thereby improving the area utilization rate of the active region 101 and enhancing the area effectiveness of the semiconductor device 100.

[0237] In addition, on the premise that the theoretical performance of the insulated gate bipolar transistor 9 meets the requirements, the area of the active region 101 of the semiconductor device 100 can be reduced, so that the heat generated when the insulated gate bipolar transistor 9 works is reduced, the power consumption of the semiconductor device 100 is reduced, thereby reducing the overall area of the semiconductor device 100 and improving the reliability of the semiconductor device 100.

[0238] Therefore, by disposing the emitter layer 3 at the position corresponding to the transition region 102 of the collector layer 16, not only can the semiconductor device 100 conduct reversely, but also the area utilization rate of the semiconductor device 100 can be improved, and the increase in the overall area of the semiconductor device 100 can be prevented. Thus, while realizing the reverse conduction of the semiconductor device 100, the effective area of the semiconductor device 100 can be increased and the size of the semiconductor device 100 can be reduced.

[0239] Combined with Fig.23As shown, the well layer 11 and the emitter layer 3 correspond to each other in the up-down direction. In some embodiments, the well layer 11 with the second conductivity type corresponds to the emitter layer 3 with the first conductivity type in the up-down direction. A drift region with the first conductivity type is provided between the well layer 11 and the emitter layer 3, and the doping concentration of the well layer 11 and the doping concentration of the emitter layer 3 are both greater than the doping concentration of the drift layer 10. Therefore, the structure of the part where the well layer 11 is located in the semiconductor device 100 from top to bottom is successively a P+ well layer 11, an N- drift layer 10, and an N+ emitter layer 3, where the plus sign indicates that the impurity concentration in the P+ well layer 11 of the second conductivity type is heavily doped, N- indicates that the impurity concentration in the drift layer 10 of the first conductivity type is lightly doped, and N+ indicates that the impurity concentration in the emitter layer 3 of the first conductivity type is lightly doped. With such a setting, the well layer 11, the drift region, and the emitter layer 3 can form a P-I-N junction in the fast recovery diode 1 structure, achieving a large breakdown voltage, thereby facilitating the reverse conduction in the semiconductor device 100.

[0240] According to some embodiments of the present disclosure, in combination with Fig.23 and Fig.24 As shown, the emitter layer 3 is circumferentially disposed around the transition region 102. With such a setting, the occupied area of the emitter layer 3 in the transition region 102 can be increased, and the reverse conduction performance of the semiconductor device 100 can be adjusted. In the embodiments of the present disclosure, the area ratio of the transition region 102 in the semiconductor device 100 is relatively large and concentrated, and the area where the emitter layer 3 can be disposed in the transition region 102 is relatively large. In this way, the adjustability of the emitter layer 3 disposed in the transition region 102 can be increased. By adjusting the setting position and area of the emitter layer 3 in the transition region 102, the short-circuit performance of the semiconductor device 100 can be avoided, thereby ensuring the reliability of the semiconductor device 100.

[0241] In the embodiments of the present disclosure, in combination with Fig.24 As shown, the terminal region 103 of the semiconductor device 100 is circumferentially disposed around the outside of the active region 101 of the semiconductor device 100. The terminal region 103 is spaced apart from the active region 101. The transition region 102 is circumferentially disposed around the outside of the active region 101 and is located between the active region 101 and the terminal region 103. The emitter layer 3 is circumferentially disposed around the outside of the active region 101. In some embodiments, considering that the electric field intensity in the terminal region 103 of the semiconductor device 100 is relatively strong and the voltage borne per unit length is relatively large, voltage breakdown is relatively likely to occur at this location. By providing a terminal structure 7 in the terminal region 103, the electric field distribution in the terminal region 103 can be optimized, and the breakdown voltage capability of the terminal region 103 can be improved. The terminal region 103 being circumferentially disposed around the outside of the active region 101 of the semiconductor device 100 can ensure the breakdown voltage reliability of the terminal region 103 of the semiconductor device 100.

[0242] In some embodiments, the terminal region 103 and the active region 101 are spaced apart, such that the transition region 102 can be disposed between the terminal region 103 and the active region 101. The transition region 102 needs to connect the terminal region 103 and the active region 101. At the same time, for the insulated gate bipolar transistor 9 device, a gate electrical connection region will be designed in the transition region 102. Therefore, the width of the transition region 102 is generally relatively wide, which is beneficial to the setting of the emitter layer 3 of the fast recovery diode 1 in the embodiments of the present disclosure. In addition, the well layer 11 on the transition region 102 is connected to the main junction, which can ensure the breakdown voltage resistance of the transition region 102 to ensure the reliability of the semiconductor device 100.

[0243] In some embodiments, the transition region 102 is circumferentially disposed around the outside of the active region 101, which can ensure the transition reliability of the transition region 102 between the terminal region 103 and the active region 101, thereby ensuring the reliability of the semiconductor device 100. The emitter layer 3 is circumferentially disposed around the outside of the active region 101 to form a fast recovery diode 1 structure within the range of the transition region 102, realizing the reverse conduction of the semiconductor device 100. Compared with the active region 101, the transition region 102 provides a larger settable space for the emitter layer 3. In this way, not only can the space of the active region 101 be effectively utilized, which is beneficial to reducing the size of the semiconductor device 100, but also while increasing the adjustable space of the fast recovery diode 1 device, the electrical performance of the semiconductor device 100 can be ensured.

[0244] In the embodiments of the present disclosure, in combination with Fig.24 as shown, the emitter layer 3 and the active region 101 are spaced apart. In some embodiments, the insulated gate bipolar transistor 9 structure in the embodiments of the present disclosure is disposed in the active region 101. Spacing the emitter layer 3 and the active region 101 apart can enable the fast recovery diode 1 device and the insulated gate bipolar transistor 9 device to be integrated and spaced apart in the semiconductor device 100. In this way, in the semiconductor device 100, the on-state voltage drop of the fast recovery diode 1 device and the on-state voltage drop of the insulated gate bipolar transistor 9 device can be ensured, thereby ensuring the reliability of the semiconductor device 100.

[0245] In the embodiments of the present disclosure, in combination with Fig.23 as shown, the emitter layer 3 and the terminal region 103 are spaced apart. In some embodiments, a terminal structure 7 is disposed in the terminal region 103. The terminal structure 7 can improve the breakdown voltage resistance of the terminal region 103 in the semiconductor device 100 to prevent voltage breakdown of the terminal region 103 and improve the breakdown voltage resistance of the semiconductor device 100. Spacing the emitter layer 3 and the terminal region 103 apart can ensure the breakdown voltage resistance of the terminal region 103, and further ensure the breakdown voltage resistance of the semiconductor device 100.

[0246] According to some other embodiments of the present disclosure, in combination with Fig.23 and Fig.25 As shown, there are multiple emitter layers 3, and the multiple emitter layers 3 are arranged at intervals in the transition region 102. In some embodiments, in the embodiments of the present disclosure, a relatively large emitter layer 3 can be split into multiple relatively small emitter layers 3. The multiple emitter layers 3 can be arranged at intervals in the transition region 102. The transition region 102 occupies a relatively large area in the semiconductor device 100, which can provide a larger adjustment space for the emitter layer 3, so that the multiple emitter layers 3 can be set according to the specifications of the fast recovery diode 1 device. In addition, splitting a relatively large emitter layer 3 into multiple relatively small emitter layers 3 can disperse a relatively large fast recovery diode 1 device integrated in the semiconductor device 100 into multiple relatively small fast recovery diode 1 devices, which can prevent current concentration in the fast recovery diode 1 device in the semiconductor device 100 and affect the short-circuit performance of the semiconductor device 100, thereby ensuring the reliability of the semiconductor device 100.

[0247] Combined with Fig.25 As shown, the terminal region 103 of the semiconductor device 100 is circumferentially arranged around the outside of the active region 101 of the semiconductor device 100. The terminal region 103 is arranged at an interval from the active region 101. The transition region 102 is circumferentially arranged around the outside of the active region 101 and is located between the active region 101 and the terminal region 103. The multiple emitter layers 3 are circumferentially arranged at intervals in the transition region 102.

[0248] In some embodiments, considering that the electric field strength of the terminal region 103 of the semiconductor device 100 is relatively strong, the voltage borne per unit length is relatively large, and voltage breakdown is likely to occur there. By setting the terminal structure 7 in the terminal region 103, the electric field distribution in the terminal region 103 can be optimized, and the breakdown voltage resistance of the terminal region 103 can be improved. The terminal region 103 is circumferentially arranged around the outside of the active region 101 of the semiconductor device 100, which can ensure the breakdown voltage reliability of the terminal region 103 of the semiconductor device 100.

[0249] In some embodiments, the terminal region 103 and the active region 101 are arranged at an interval, which can enable the transition region 102 to be arranged between the terminal region 103 and the active region 101. The transition region 102 needs to connect the terminal region 103 and the active region 101. At the same time, for the insulated gate bipolar transistor 9 device, a gate electrical connection region will be designed in the transition region 102. Therefore, the width of the transition region 102 is generally relatively wide, which is beneficial to the setting of the emitter layer 3 of the fast recovery diode 1 in the embodiments of the present disclosure. In addition, the well layer 11 on the transition region 102 is connected to the main junction, which can ensure the breakdown voltage resistance of the transition region 102 to ensure the reliability of the semiconductor device 100.

[0250] In some embodiments, a plurality of emitter layers 3 are circumferentially spaced in the transition region 102, so that the fast recovery diode 1 structures in the semiconductor device 100 can be dispersed in the transition region 102, which can not only meet the specification requirements of the fast recovery diode 1 device, but also prevent current concentration on the fast recovery diode 1 structure, affecting the short-circuit performance of the semiconductor device 100, thereby ensuring the reliability of the semiconductor device 100.

[0251] In the embodiments of the present disclosure, as shown in Fig.25 the emitter layer 3 is spaced apart from the active region 101. In some embodiments, the insulated gate bipolar transistor 9 structure in the embodiments of the present disclosure is disposed in the active region 101. Spacing the emitter layer 3 from the active region 101 can enable the fast recovery diode 1 device and the insulated gate bipolar transistor 9 device to be integrated and spaced in the semiconductor device 100. In this way, in the semiconductor device 100, the on-state voltage drop of the fast recovery diode 1 device and the on-state voltage drop of the insulated gate bipolar transistor 9 device can be ensured, thereby ensuring the reliability of the semiconductor device 100.

[0252] In the embodiments of the present disclosure, as shown in Fig.25 the emitter layer 3 is spaced apart from the terminal region 103. In some embodiments, a terminal structure 7 is disposed in the terminal region 103, and the terminal structure 7 can improve the breakdown voltage of the terminal region 103 in the semiconductor device 100 to prevent voltage breakdown in the terminal region 103 and improve the breakdown voltage of the semiconductor device 100. Spacing the emitter layer 3 from the terminal region 103 can ensure the breakdown voltage of the terminal region 103, and further ensure the breakdown voltage of the semiconductor device 100.

[0253] According to the embodiments of the present disclosure, the doping concentration of the emitter layer 3 is greater than the doping concentration of the drift layer 10. In some embodiments, in the embodiments of the present disclosure, electrons need to be injected into the portion of the collector layer 16 corresponding to the well layer 11 to form the emitter layer 3. The electron concentration doped in the emitter layer 3 must be greater than the doping concentration of the drift layer 10, so that the emitter layer 3 can have enough electrons for current injection, enabling the emitter layer 3 to output a large enough current to ensure the normal operation of the semiconductor device 100.

[0254] According to the embodiments of the present disclosure, as shown in Fig.23 and Fig.26As shown, the transition region 102 is connected to the active region 101. There is a metal electrode 5 above the transition region 102, and the metal electrode 5 is connected to the emitter metal 6 disposed above the front surface of the active region 101, which can form the basic structure of the semiconductor structure and ensure the normal operation of the semiconductor device 100. An emitter layer 3 is disposed opposite below the well layer 11, which can not only form the fast recovery diode 1 device, but also ensure the normal electrical performance of the semiconductor device 100 without affecting the breakdown voltage and reliability of the semiconductor device 100.

[0255] In some embodiments, there is a gate bus 84 region in the transition region 102. The metal in this region is not connected to the emitter metal 6 of the active region 101. However, due to the fact that the area of the gate bus 84 region occupying the transition region 102 is small and the characteristics of the semiconductor device 100 itself, the carrier path does not exactly correspond to the position of the metal electrode 5 in the semiconductor device 100. Therefore, even if the emitter layer 3 on the back surface of the semiconductor device 100 partially corresponds to the gate bus 84 up and down, reverse conduction can be achieved in the semiconductor device 100. Through simulation experiments, the feasibility of reverse conduction of the semiconductor device 100 can be confirmed in the manner that the emitter layer 3 on the back surface of the semiconductor device 100 partially corresponds to the gate bus 84 up and down. Fig. 27 This is the simulation result of the conduction voltage drop of the fast recovery diode 1 device in the semiconductor device 100 when the emitter layer 3 on the back surface of the semiconductor device 100 partially corresponds to the gate bus 84 up and down.

[0256] Next, refer to Figure 28-Figure 47 Describe the semiconductor device 100 according to some embodiments of the present disclosure. The semiconductor device 100 is, for example, a reverse-conducting insulated gate bipolar transistor. In the following description, N and P represent the conduction types of semiconductors. In the present disclosure, the first conduction type is set as the N type and the second conduction type is set as the P type for description.

[0257] Combined with Fig.29 and Fig.35 As shown, the semiconductor device 100 according to the present disclosure mainly includes: a drift layer 10 of the first conduction type, a well layer 11 of the second conduction type, a dielectric layer 13, a gate pad 104, a field stop layer 15, and a collector layer 16 of the second conduction type. Among them, the drift layer 10 of the first conduction type, the well layer 11 of the second conduction type, the dielectric layer 13, the gate pad 104, the field stop layer 15, and the collector layer 16 of the second conduction type are provided in the semiconductor device 100. And the field stop layer 15 is disposed on the lower surface of the drift layer 10, the collector layer 16 is disposed on the lower surface of the field stop layer 15, and the gate pad 104 is disposed on the upper surface of the drift layer 10. In this way, the basic structure of the semiconductor structure can be formed to ensure the normal operation of the semiconductor device 100.

[0258] In some embodiments, the well layer 11 is disposed on the drift layer 10, and the upper surface forms at least a part of the upper surface of the drift layer 10. In some embodiments, a well layer 11 of a second conductivity type is disposed on at least a part of the upper surface of the drift layer 10, which can optimize the terminal electric field distribution of the main junction and is beneficial to improving the breakdown voltage of the semiconductor device 100. The well layer 11 is at least partially disposed on the upper surface of the drift layer 10 and is located below the gate pad 104, and can correspond to the emitter layer 3 in the structure of the fast recovery diode 1 to form a current flow path of the fast recovery diode 1.

[0259] In some embodiments, the dielectric layer 13 is disposed on the upper surface of the well layer 11, which can prevent the well layer 11 from being in electrical contact with the gate pad 104 and can ensure the reliability of the semiconductor device 100. The gate pad 104 is disposed on the upper surface of the dielectric layer 13, the field stop layer 15 is disposed on the lower surface of the drift layer 10, and the collector layer 16 is disposed on the lower surface of the drift layer 10. In this way, the basic structure of the semiconductor structure can be formed to ensure the normal operation of the semiconductor device 100.

[0260] In some embodiments, at least a part of the collector layer 16 is provided with an emitter layer 3. The collector layer 16 is located in the insulated gate bipolar transistor region 1015 of the semiconductor device 100, and the emitter layer 3 is located in the fast recovery diode region 1018 of the semiconductor device 100. The emitter layer 3 and the gate pad 104 are vertically corresponding. In some embodiments, the conductivity type of the collector layer 16 is the second conductivity type, and the conductivity type of the emitter layer 3 in the collector layer 16 is the first conductivity type. The emitter layer 3 is partially disposed below the gate pad 104 corresponding to the collector layer 16. The emitter layer 3 and a part of the well layer 11 corresponding to the lower part of the gate pad 104 can form a PN junction, and the well layer 11 corresponding to the upper part of the emitter layer 3 can be used as the collector of the fast recovery diode 1. In this way, the structure of the fast recovery diode 1 can be formed in the region of the semiconductor device 100 corresponding to the gate pad 104 to realize the reverse conduction of the semiconductor device 100.

[0261] In the prior art, the insulated gate bipolar transistor and the fast recovery diode in the reverse-conducting insulated gate bipolar transistor are integrally disposed in the active region of the semiconductor device. When the semiconductor device conducts forward, under the drive of the gate voltage, the emitter layer of the first conductivity type in the insulated gate bipolar transistor device injects electrons through the channel into the drift region of the first conductivity type, and the collector region of the second conductivity type on the back surface of the semiconductor device injects holes upward, forming a conductive path from top to bottom. When conducting reversely, the fast recovery diode region integrated in the semiconductor device starts to work. The well layer 11 of the second conductivity type on the front surface serves as the anode of the fast recovery diode and injects holes into the drift region, and the emitter layer of the second conductivity type on the back surface serves as the cathode and injects electrons into the drift region, realizing the integration of the insulated gate bipolar transistor region and the fast recovery diode region in the same semiconductor device. However, the fast recovery diode region needs to occupy a part of the area of the active region of the semiconductor device. On the premise that the ratio of the effective gate trenches in the insulated gate bipolar transistor region remains unchanged, the saturation current of the insulated gate bipolar transistor decreases, and the area of the active region of the semiconductor device needs to be supplemented, which will increase the overall size of the semiconductor device. In addition, the increase in the area of the active region of the semiconductor device will cause an increase in the heat generated when the insulated gate bipolar transistor works, thereby reducing the reliability of the insulated gate bipolar transistor.

[0262] In some embodiments, in the embodiments of the present disclosure, the structure of the emitter layer 3 constituting the fast recovery diode 1 is disposed in the portion of the collector layer 16 corresponding to the gate pad 104 in the semiconductor device 100. In this way, the structure of the fast recovery diode 1 can be disposed in the pad region 19, which can not only realize the reverse conduction of the semiconductor device 100, but also reduce the structure disposed in the active region 101 of the semiconductor device 100, and can reduce the area of the active region 101 of the semiconductor device 100, thereby improving the integration degree of the semiconductor device 100. It should be noted that a second contact hole 1102 can be provided on the upper surface of the gate pad 104, which can optimize the heat distribution on the gate metal 1021.

[0263] With such a setting, more semiconductor devices 100 can be produced on the same-size wafer, thereby improving the utilization rate of the wafer, which is beneficial to reducing the production cost of the semiconductor device 100. Taking the semiconductor device 100 with an A current specification as an example, by integrating the fast recovery diode 1 under the gate pad 104, about 27% of the area can be saved. Taking a wafer of [wafer size] inches as an example, the number of semiconductor devices 100 that can be produced on each wafer increases from [original number] pieces to [increased number] pieces, greatly improving the production efficiency of the semiconductor device 100 and the utilization rate of the wafer, and saving the production cost of the semiconductor device 100.

[0264] In addition, when ensuring that the theoretical performance of the insulated gate bipolar transistor 9 meets the requirements, reducing the area of the active region 101 of the semiconductor device 100 can further reduce the overall area of the semiconductor device 100. This can reduce the heat generated by the insulated gate bipolar transistor 9 during operation, thereby reducing the power consumption of the semiconductor device 100 and improving the reliability of the semiconductor device 100. The emitter layer 3 is disposed below the gate pad 104 of the semiconductor device 100. The emitter layer 3 and the well layer 11 below the gate pad 104 can form a PN junction. The well layer 11 corresponding to the upper part of the emitter layer 3 can serve as the collector of the fast recovery diode 1 to form the structure of the fast recovery diode 1. Except for the part of the well layer 11 corresponding to below the gate pad 104 above the drift layer 10, which can serve as the collector of the fast recovery diode 1, the other parts of the well layer 11 are used to optimize the terminal electric field distribution of the main junction. With such a setting, on the one hand, the breakdown voltage capability of the semiconductor device 100 is not affected, and on the other hand, the well layer 11 is integrated into the fast recovery diode region 1018, improving the chip integration degree, reducing the overall chip area, and thus reducing the cost.

[0265] Thus, by disposing the emitter layer 3 below the gate pad 104 corresponding to the collector layer 16, not only can the semiconductor device 100 be reverse-conducted, but also the integration degree of the semiconductor device 100 can be improved. Therefore, while realizing the reverse conduction of the semiconductor device 100, the saturation current of the insulated gate bipolar transistor 9 structure can be ensured without increasing the area of the active region 101. Compared with the reverse-conducted insulated gate bipolar transistor 9 devices of the same specification, the semiconductor device 100 of the present disclosure has an advantage in area size.

[0266] Combined with Figure 29-Figure 30 As shown, the width of the well layer 11 in the first direction is W1, and the width of the emitter layer 3 in the first direction is W2. W1 and W2 satisfy the relationship: W1 > W2. Setting the width of the well layer 11 in the first direction to be greater than the width of the emitter layer 3 in the first direction can ensure the reliability of the reverse current flow in the fast recovery diode 1 structure, and thus ensure the reliability of the reverse conduction of the semiconductor device 100. According to some other embodiments of the present disclosure, the width of the well layer 11 in the first direction is equal to the width of the emitter layer 3 in the first direction, and this can also achieve the reverse conduction of the semiconductor device 100. It should be noted that the width of the emitter layer 3 in the fast recovery diode region 1018 of the semiconductor device 100 needs to be set according to the specification of the fast recovery diode 1 in the reverse-conducted insulated gate bipolar transistor 9 device.

[0267] According to some embodiments of the present disclosure, combined with Fig.30As shown, the cross-section of the emitter layer 3 in the up-and-down direction is in the shape of a long strip continuous in the first direction. In some embodiments, the shape of the cross-section of the emitter layer 3 in the up-and-down direction on the first square is set as a continuous long strip, and the width of the well layer 11 in the first direction is sufficient to meet the setting of the emitter layer 3 of the fast recovery diode 1 structure in the part of the collector layer 16 corresponding to the gate pad 104, which can provide a sufficiently large setting space for the emitter layer 3 so that the fast recovery diode 1 structure meets the actual requirements and design objectives of the semiconductor device 100.

[0268] According to some other embodiments of the present disclosure, in combination with Fig.31 As shown, the cross-section of the emitter layer 3 in the up-and-down direction includes a plurality of emission portions 501. The plurality of emission portions 501 are spaced apart in the first direction, and the sum of the widths of the plurality of emission portions 501 in the first direction is W. In some embodiments, the emitter layer 3 of the fast recovery diode 1 in the semiconductor device 100 can also be jointly composed of a plurality of emission portions 501. The width of the well layer 11 in the first direction is sufficient to meet the setting of the emitter layer 3 of the fast recovery diode 1 structure in the part of the collector layer 16 corresponding to the gate pad 104, which can provide a sufficiently large setting space for the emitter layer 3 so that the fast recovery diode 1 structure meets the actual requirements and design objectives of the semiconductor device 100. It should be further noted that in the embodiments of the present disclosure, the sum of the widths of the cross-sections of the plurality of emission portions 501 in the up-and-down direction in the first direction does not exceed the width of the well layer 11 in the first direction to ensure that the plurality of emission portions 501 are vertically corresponding to the well layer 11.

[0269] According to some embodiments of the present disclosure, the widths of the plurality of emission portions 501 in the first direction are all the same. In this way, not only can the fast recovery diode 1 structure meet the actual requirements and design objectives of the semiconductor device 100, but also the manufacturing process of the fast recovery diode 1 structure can be simplified, and the production convenience of the semiconductor device 100 can be improved. According to some other embodiments of the present disclosure, the widths of the plurality of emission portions 501 in the first direction are not completely the same. Such a setting can improve the setting convenience of the emitter layer 3, which is of great significance for insulated gate bipolar transistors operating at high frequencies.

[0270] According to some embodiments of the present disclosure, when viewed from a top-down perspective, the emitter layer 3 is at least one of a square, a rounded rectangle, a circle, a small ellipse, and a hexagon. In some embodiments, setting the top-down shape of the emitter layer 3 as at least one of a square, a rounded rectangle, a circle, a small ellipse, and a hexagon can enable the emitter layer 3 in the fast recovery diode 1 to be set into different shapes according to the actual requirements and design objectives of the semiconductor device 100, so as to be applicable to semiconductor devices 100 of different specifications, which is beneficial to improving the reliability of the semiconductor device 100. It should be further noted that the top-down perspective is the perspective perpendicular to the plane direction in the figure.

[0271] According to some other embodiments of the present disclosure, when viewed from a top-down perspective, the emitter layer 3 is composed of at least two combinations of a plurality of small squares, small circles, small ellipses, and small rounded rectangles. In some embodiments, setting the top-down shape of the emitter layer 3 as at least two combinations of a plurality of small squares, small circles, small ellipses, and small rounded rectangles can enable the emitter layer 3 in the fast recovery diode 1 to be set into different shapes and sizes according to the actual requirements and design objectives of the semiconductor device 100, so as to be applicable to semiconductor devices 100 of different specifications, which is beneficial to improving the reliability of the semiconductor device 100. It should be further noted that the top-down perspective is the perspective perpendicular to the plane in the figure.

[0272] According to still some other embodiments of the present disclosure, when viewed from a top-down perspective, the emitter layer 3 is at least one of a square, a rounded rectangle, and a circle, and the emitter layer 3 is composed of at least two combinations of a plurality of small squares, small circles, small ellipses, and small rounded rectangles. In some embodiments, setting the top-down shape of the emitter layer 3 as at least one of a square, a rounded rectangle, and a circle, and at least two combinations of a plurality of small squares, small circles, small ellipses, and small rounded rectangles can enable the emitter layer 3 in the fast recovery diode 1 to be set into different shapes and sizes according to the actual requirements and design objectives of the semiconductor device 100, so as to be applicable to semiconductor devices 100 of different specifications, which is beneficial to improving the reliability of the semiconductor device 100. It should be further noted that the top-down perspective is the perspective perpendicular to the plane in the figure

[0273] Combined with Fig.30 and Fig.31 As shown, the drift layer 10 is provided with a plurality of trench portions 2110 spaced apart in a first direction corresponding to the active region 101 of the semiconductor device 100. The distance between two adjacent trench portions 2110 in the first direction is L2, and the distance from one of the plurality of trench portions 2110 adjacent to the well layer 11 to the well layer 11 in the first direction is W3. W3 and L2 satisfy the relationship: W3≥L2. In some embodiments, the drift layer 10 is provided with trench portions 2110 corresponding to the active region 101 of the semiconductor device 100. The trench portions 2110 are used to form the gate of the semiconductor device 100. There are a plurality of trench portions 2110, and the number of trench portions 2110 can be set according to the specifications of the semiconductor device 100. The plurality of trench portions 2110 are spaced apart in the first direction, which can ensure the mutual independence between the plurality of trench portions 2110 to ensure the reliability of the semiconductor device 100.

[0274] In an embodiment of the present disclosure, the area of the active region 101 of the semiconductor device 100 is only used to arrange the insulated-gate bipolar transistor structure, so that the area of the active region 101 can be reduced, the density of the effective trenches can be increased, and further the current density of the insulated-gate bipolar transistor can be increased, thereby reducing the on-state voltage drop of the semiconductor device 100 and being beneficial to reducing the switching loss of the semiconductor device 100.

[0275] In some embodiments, the spacing distance between two adjacent trench portions 2110 in the first direction is set not to exceed the distance from the trench portion 2110 closest to the well layer 11 in the first direction to the well layer 11. With such a setting, a setting space can be provided for the transition region 102 in the semiconductor device 100, so that the transition region 102 can transition between the active region 101 and the terminal region 103 of the semiconductor device 100, and the reliability of the semiconductor device 100 can be ensured.

[0276] According to some embodiments of the present disclosure, in combination with Fig.28 and Fig.32 As shown, the drift layer 10 is provided with trench portions 2110, the trench portions 2110 extend in the second direction, there are a plurality of trench portions 2110, and the plurality of trench portions 2110 are spaced apart in the first direction. In some embodiments, the plurality of trench portions 2110 provided in the drift layer 10 can extend in the second direction, and the plurality of trench portions 2110 can be spaced apart in the first direction to meet the structural settings of semiconductor devices 100 of different specifications, so that the fast recovery diode 1 structure can meet the actual requirements and design goals of the semiconductor device 100.

[0277] According to other embodiments of the present disclosure, in combination with Fig.33 and Fig.34 As shown, the trench portions 2110 extend in the first direction, there are a plurality of trench portions 2110, and the plurality of trench portions 2110 are spaced apart in the second direction. In some embodiments, the plurality of trench portions 2110 provided in the drift layer 10 can extend in the first direction, and the plurality of trench portions 2110 can be spaced apart in the second direction to meet the structural settings of semiconductor devices 100 of different specifications, so that the fast recovery diode 1 structure can meet the actual requirements and design goals of the semiconductor device 100.

[0278] According to some embodiments of the present disclosure, in combination with Fig.28 and Fig.33As shown, the gate pad 104 is located on one side of the drift layer 10 in the second direction, and the gate pad 104 is symmetrically arranged with respect to the center line extending in the second direction of the drift layer 10. In some embodiments, by arranging the gate pad 104 on one side of the drift layer 10 in the second direction and making the gate pad 104 symmetrically arranged with respect to the center line extending in the second direction of the drift layer 10, it is possible to meet the structural settings of semiconductor devices 100 of different specifications while ensuring the structural reliability and functional reliability of the semiconductor device 100. The structure of the fast recovery diode 1 can be freely arranged at the position corresponding to the gate pad 104 in the semiconductor device 100, so that the arrangement of the fast recovery diode 1 can meet the actual requirements and design goals of the semiconductor device 100.

[0279] According to some other embodiments of the present disclosure, in combination with Fig.32 and Fig.34 As shown, the gate pad 104 is located on one side of the drift layer 10 in the second direction, and the gate pad 104 is located at one end of the drift layer 10 in the first direction. Such an arrangement can save the area of the semiconductor device 100 while ensuring the structural reliability and functional reliability of the semiconductor device 100. This can meet the structural settings of semiconductor devices 100 of different specifications. The structure of the fast recovery diode 1 can be freely arranged at the position corresponding to the gate pad 104 in the semiconductor device 100, so that the arrangement of the fast recovery diode 1 can meet the actual requirements and design goals of the semiconductor device 100.

[0280] In combination with Fig.29 、 Fig.35 and Fig.38 As shown, an emitter metal 6 is further provided on the upper surface of the dielectric layer 13. A first contact hole 1101 is provided on the dielectric layer 13, and at least a part of the emitter metal 6 penetrates through the first contact hole 1101 and contacts the well layer 11. In some embodiments, the emitter metal 6 on the upper surface of the dielectric layer 13 can serve as the emitter of the insulated gate bipolar transistor region 1015, and the basic structure of the insulated gate bipolar transistor region 1015 in the semiconductor can be formed to ensure the normal operation of the semiconductor device 100. The first contact hole 1101 is formed on the dielectric layer 13 by etching. The first contact hole 1101 can be used for electrically connecting the emitter metal 6 and the well layer 11. When depositing metal to form the emitter metal 6, at least a part of the emitter metal 6 penetrates through the first contact hole 1101 for electrically connecting with the well layer 11, so as to realize the electrical conduction of the fast recovery diode 1 in the semiconductor device 100. At this time, a PN junction is formed between the emitter layer 3 of the fast recovery diode region 1018 and the corresponding part of the well layer 11 below the gate pad 104, and this part of the well layer 11 can serve as the collector in the fast recovery diode 1.

[0281] According to some embodiments of the present disclosure, the first contact hole 1101 is in a continuous strip shape, which can facilitate the electrical connection between the emitter metal 6 and the polysilicon field plate 8, increase the contact area between the emitter metal 6 and the polysilicon field plate 8, and thus ensure the circuit reliability of the semiconductor device 100.

[0282] According to some other embodiments of the present disclosure, in combination Fig.36 As shown, the first contact holes 1101 are rectangular and multiple, and the multiple first contact holes 1101 are spaced in the first direction. In some embodiments, the first contact holes 1101 can also be arranged in multiple rectangles, and the multiple rectangular first contact holes 1101 are spaced in the first direction, so that the emitter metal 6 is in electrical contact with the polysilicon field plate 8 at multiple spaced positions in the first direction, to be suitable for electrically conducting different specifications and sizes of fast recovery diodes 1, and thus ensure the reliability of the semiconductor device 100.

[0283] In combination Fig.29 、 Fig.35 、 Fig.36 and Fig.37 As shown, the trench portion 2110 includes a gate trench portion 211 and a dummy gate trench portion 221, and at least one dummy gate trench portion 221 is provided between two adjacent gate trench portions 211. In some embodiments, providing at least one dummy gate trench portion 221 between two adjacent gate trench portions 211 can not only ensure the structural reliability of the insulated gate bipolar transistor region in the semiconductor device 100, but also be used to control the short-circuit performance of the semiconductor device 100 and ensure the reliability of the semiconductor device 100. The first contact hole 1101 is located between two adjacent gate trench portions 211 and is spaced from the dummy gate trench portion 221 in the second direction; and / or, the first contact hole 1101 is spaced from the gate trench portion 211 in the second direction.

[0284] In combination Fig.37 As shown. According to some embodiments of the present disclosure, the first contact hole 1101 is located between two adjacent gate trench portions 211 and is spaced from the dummy gate trench portion 221 in the second direction. According to some other embodiments of the present disclosure, the first contact hole 1101 is spaced from the gate trench portion 211 in the first direction. According to still some other embodiments of the present disclosure, at least part of the first contact holes 1101 are located between two adjacent gate trench portions 211 and are spaced from the dummy gate trench portion 221 in the second direction, and at least part of the first contact holes 1101 are spaced from the gate trench portion 211 in the first direction. With such an arrangement, the first contact holes 1101 can be freely arranged on the semiconductor device 100 to meet the structural settings of different specifications of semiconductor devices 100, and the structure of the fast recovery diode 1 can meet the actual requirements and design goals of the semiconductor device 100.

[0285] Combined Fig.35 As shown, the structure of the insulated-gate bipolar transistor region in the semiconductor device 100 further includes: an emitter region 105 of a first conductivity type, a base region 106 of a second conductivity type, a carrier storage layer 110, a collector metal layer 18, a gate, an active region 101, a transition region 102, a pad region 19, and a terminal region 103. Among them, the terminal region 103 includes structures such as a field stop ring 1302, a field limiting ring 1303, a metal field plate 90, a polysilicon field plate 8, etc. These structures are arranged in sequence on the terminal region 103 at a certain interval distance to improve the breakdown voltage capability of the insulated-gate bipolar transistor and ensure the stability of the semiconductor device 100.

[0286] In some embodiments, the pad region 19 includes a gate metal 1021, which is used to connect to an external wire and serves as the focus of a gate runner 1022 to control the gate of the insulated-gate bipolar transistor device. A dummy gate trench portion 221 may or may not be provided in the transition region 102, and neither a first conductivity type emitter region 105 nor a second conductivity type contact layer is provided in the transition region 102.

[0287] Combined Figure 39-Figure 47 As shown, the following describes the manufacturing method of the semiconductor device 100 according to some embodiments of the present disclosure, including the following steps:

[0288] Step 1: Provide a semiconductor substrate of a first conductivity type, which is Structure 1;

[0289] Step 2: On the basis of Structure 1, after taking certain protection measures, implant a well layer 11 of a second conductivity type into the terminal region 103 to form Structure 2;

[0290] Step 3: On the basis of Structure 2, grow a field oxide layer 1301 to obtain Structure 3;

[0291] Step 4: On the basis of Structure 3, etch a trench portion 2110 and complete processes such as rounding of the trench portion 2110 and growth of a gate oxide layer to obtain Structure 4;

[0292] Step 5: On the basis of Structure 4, grow polysilicon 71 to obtain Structure 5;

[0293] Step 6: On the basis of Structure 5, implant structures such as an emitter region 105 of a first conductivity type, a carrier storage layer 110, and a contact layer of a second conductivity type to obtain Structure 6;

[0294] Step 7: On the basis of Structure 6, grow a dielectric layer 13 to obtain Structure 7;

[0295] Step 8, based on Structure Seven, etch the dielectric layer 13 to obtain Structure Eight;

[0296] Step 9, based on Structure Eight, deposit the emitter metal 6 to obtain Structure Nine;

[0297] Step 10, based on Structure Nine, form a field stop layer 15 and a collector layer 16 of the second conductivity type on the back surface of the semiconductor device 100 to obtain Structure Ten;

[0298] Step 11, based on Structure Ten, form an emitter layer 3 of the first conductivity type in the area of the collector layer 16 corresponding to the gate pad 104 to form Structure Eleven;

[0299] Step 12, based on Structure Eleven, deposit a collector metal layer 18 on the back surface of the semiconductor device 100 to finally form the structure of the insulated gate bipolar transistor device.

[0300] Next, with reference to Figure 48-Figure 57 Describe the semiconductor device 100 according to some embodiments of the present disclosure. The semiconductor device 100 may adopt the manufacturing method of the semiconductor device 100. The semiconductor device 100 may be an RC-IGBT. The first semiconductor device type region 1011 may be an IGBT region, and the second semiconductor device type region 1012 may be an FRD region. In the following description, N and P represent the conductivity types of semiconductors. In the present disclosure, the first conductivity type is set as the N type and the second conductivity type is set as the P type for description.

[0301] Combined with Fig.48 and Fig.49 As shown, the semiconductor device 100 according to the present disclosure may mainly include: a drift layer 10 of the first conductivity type, a field stop layer 15 of the first conductivity type, a collector layer 16 of the second conductivity type, a first emitter layer 17 of the first conductivity type, a ring layer 107 of the second conductivity type, and a well layer 11 of the second conductivity type.

[0302] In some embodiments, a ring layer 107 of a second conductivity type and a well layer 11 of the second conductivity type are disposed in a drift layer 10 of a first conductivity type. The upper surface of the ring layer 107 constitutes at least a part of the upper surface of the drift layer 10, and the upper surface of the well layer 11 constitutes at least a part of the upper surface of the drift layer 10. A well layer 11 of the second conductivity type, a first emitter layer 17 of the first conductivity type located in the well layer 11, a dielectric layer 13 located above the first emitter layer 17, and an emitter metal layer 14 located above the dielectric layer 13 are disposed on the upper surface of the drift layer 10 of the first conductivity type. A field stop layer 15 of the first conductivity type, a collector layer 16 of the second conductivity type disposed on the lower surface of the field stop layer 15, a first emitter layer 17 of the first conductivity type, and a collector metal layer 18 located at the lowermost part are disposed on the lower surface of the drift layer 10 of the first conductivity type.

[0303] In some embodiments, a semiconductor device 100 includes an active region 101 and a terminal region 103 surrounding the outside of the active region 101. The collector layer 16 is circumferentially disposed outside the first emitter layer 17. The region corresponding to the collector layer 16 in the up-down direction is a first semiconductor device type region 1011, and the region corresponding to the first emitter layer 17 in the up-down direction is a second semiconductor device type region 1012. That is, the active region 101 of the semiconductor device 100 may include a first semiconductor device type region 1011 and a second semiconductor device type region 1012. The emitter metal layer 14 can not only serve as an emitter lead-out terminal of the first semiconductor device type region 1011, but also serve as an anode lead-out terminal of the second semiconductor device type region 1012. The collector metal layer 18 can not only serve as a collector lead-out terminal of the first semiconductor device type region 1011, but also serve as a cathode lead-out terminal of the second semiconductor device type region 1012. In this way, the first semiconductor device type region 1011 can achieve forward conduction of the semiconductor device 100, and the second semiconductor device type region 1012 can achieve reverse conduction of the semiconductor device 100, enabling the semiconductor device 100 to have both forward conduction and reverse conduction characteristics.

[0304] Combined Fig.49 As shown, the ring layer 107 corresponds to the junction of the collector layer 16 and the first emitter layer 17. A plurality of trench portions 2110 are disposed in the ring layer 107. The well layer 11 is disposed on both sides of the ring layer 107 and at least partially corresponds to the collector layer 16 and the first emitter layer 17. A plurality of trench portions 2110 are disposed in the portion of the well layer 11 corresponding to the collector layer 16.

[0305] In some embodiments, the ring layer 107 corresponds to the junction of the collector layer 16 and the first emitter layer 17, that is, a ring layer 107 is provided at the junction of the first semiconductor device type region 1011 and the second semiconductor device type region 1012, and the well layer 11 is disposed on both sides of the ring layer 107. The well layer 11 at least partially corresponds to the collector layer 16 and the first emitter layer 17, that is, the well layer 11 is provided in both the first semiconductor device type region 1011 and the second semiconductor device type region 1012.

[0306] By providing a plurality of trench portions 2110 in the ring layer 107 and a plurality of trench portions 2110 in the portion of the well layer 11 corresponding to the collector layer 16, that is, the trench portions 2110 are provided in the first semiconductor device type region 1011, and no trench portions 2110 are provided in the second semiconductor device type region 1012. On the one hand, an oxide insulating layer 70 and a polysilicon 71 can be sequentially deposited in the trench portions 2110 to form a gate at the trench portions 2110 to ensure the normal operation of the first semiconductor device type region 1011. On the other hand, the trench portions 2110 at the second semiconductor device type region 1012 can be eliminated, so that the second semiconductor device type region 1012 is only a planar PN junction, thereby effectively increasing the effective area of the PN junction and reducing the forward conduction voltage drop of the second semiconductor device type region 1012. In this way, the working performance of the semiconductor device 100 can be improved.

[0307] In some embodiments, due to the elimination of the trench portion 2110 at the second semiconductor device type region 1012, the width of the dopant of the second semiconductor type to be implanted in the first semiconductor device type region 1011 is much larger than the width of the dopant of the second semiconductor type to be implanted in the second semiconductor device type region 1012. If the same implantation dose and annealing conditions are used, the junction depth and doping concentration at the junction of the first semiconductor device type region 1011 and the second semiconductor device type region 1012 will be smaller than the junction depth and doping concentration of the first semiconductor device type region 1011, resulting in a problem with the breakdown voltage of the semiconductor device 100. By separately providing the ring layer 107 and the well layer 11, the junction depth and doping concentration at the junction of the first semiconductor device type region 1011 and the second semiconductor device type region 1012 can be increased, ensuring that the junction depth and doping concentration of the first semiconductor device type region 1011 and the second semiconductor device type region 1012 are the same, ensuring that the breakdown voltages of the first semiconductor device type region 1011 and the second semiconductor device type region 1012 are the same, and ensuring the breakdown voltage capability of the semiconductor device 100.

[0308] Accordingly, by making the ring layer 107 correspond to the junction of the collector layer 16 and the first emitter layer 17, a plurality of trench portions 2110 are provided in the ring layer 107. The well layer 11 is disposed on both sides of the ring layer 107 and at least partially corresponds to the collector layer 16 and the first emitter layer 17. A plurality of trench portions 2110 are provided in the portion of the well layer 11 corresponding to the collector layer 16. In this way, on the premise of ensuring the breakdown voltage capability of the semiconductor device 100, the on-state voltage drop of the second semiconductor device type region 1012 can be increased, and the working performance of the semiconductor device 100 can be improved.

[0309] Combined with Fig.49 As shown, the depth of the well layer 11 in the vertical direction is less than the depth of the ring layer 107 in the vertical direction. In some embodiments, by setting the depth of the well layer 11 in the vertical direction to be less than the depth of the ring layer 107 in the vertical direction, the junction depth and doping concentration at the junction of the first semiconductor device type region 1011 and the second semiconductor device type region 1012 can be ensured to be the same as those of the first semiconductor device type region 1011 in some embodiments, thereby ensuring the breakdown voltage capability of the second semiconductor device type region 1012 and even the semiconductor device 100.

[0310] Combined with Fig.49 As shown, the depth of the trench portion 2110 in the vertical direction is greater than the depth of the well layer 11 in the vertical direction, and the depth of the trench portion 2110 in the vertical direction is less than the depth of the ring layer 107 in the vertical direction.

[0311] In some embodiments, by setting the depth of the trench portion 2110 in the vertical direction to be greater than the depth of the well layer 11 in the vertical direction, the trench portion 2110 of the first semiconductor device type region 1011 located in the well layer 11 can penetrate through the well layer 11 to reach the drift layer 10, thereby ensuring the normal operation of the first semiconductor device 100.

[0312] In some embodiments, the depth of the trench portion 2110 in the vertical direction is set to be less than the depth of the ring layer 107 in the vertical direction, so that the ring layer 107 can surround the trench portion 2110 at the junction of the first semiconductor device type region 1011 and the second semiconductor device type region 1012, thereby ensuring that the junction depth and doping concentration at the junction of the first semiconductor device type region 1011 and the second semiconductor device type region 1012 are the same as those of the first semiconductor device type region 1011, ensuring that the breakdown voltages of the first semiconductor device type region 1011 and the second semiconductor device type region 1012 are the same, and ensuring the working performance of the semiconductor device 100.

[0313] Combined with Fig.49As shown, the cross-section of the ring layer 107 in the up-down direction is arc-shaped, and the cross-section of the well layer 11 in the up-down direction is rectangular.

[0314] In some embodiments, by making the cross-section of the well layer 11 in the up-down direction rectangular, the lower surface of the well layer 11 is parallel to the upper surface of the drift layer 10. In this way, the well layer 11 in the second semiconductor device type region 1012 can be evenly distributed and have the same depth as that in the first semiconductor device type region 1011, which can ensure the working performance of the second semiconductor device type region 1012 and ensure that the junction depth and doping concentration in the middle of the first direction of the first semiconductor device type region 1011 and the middle of the first direction of the second semiconductor device type region 1012 are the same.

[0315] In some embodiments, by making the cross-section of the ring layer 107 in the up-down direction arc-shaped, the lower surface of the ring layer 107 is arc-shaped. In this way, the ring layer 107 can surround the trench portion 2110 at the junction of the first semiconductor device type region 1011 and the second semiconductor device type region 1012, so as to ensure that the junction depth and doping concentration at the junction of the first semiconductor device type region 1011 and the second semiconductor device type region 1012 are the same as those in the first semiconductor device type region 1011.

[0316] In this way, the breakdown voltages of the first semiconductor device type region 1011 and the second semiconductor device type region 1012 can be the same, ensuring the breakdown voltage capability of the semiconductor device 100 and the working performance of the semiconductor device 100.

[0317] Combined with Fig.49 As shown, the second emitter layers 12 are provided on both sides of the trench portion 2110. A dielectric layer 13 is provided on the upper surfaces of the ring layer 107 and the well layer 11. The dielectric layer 13 is provided with a first contact hole 1101 between two adjacent trench portions 2110. The dielectric layer 13 is provided with a second contact hole 1102 at the portion corresponding to the first emitter layer 17. An emitter metal layer 14 is provided on the upper surface of the dielectric layer 13. At least a part of the emitter metal layer 14 penetrates through the first contact hole 1101 and is electrically connected to the second emitter layer 12. At least a part of the emitter metal layer 14 penetrates through the second contact hole 1102 and is electrically connected to the portion of the well layer 11 located in the middle of the ring layer 107. The multiple trench portions 2110 are arranged at intervals in the first direction, and the length of the second contact hole 1102 in the first direction is greater than the length of the first contact hole 1101 in the first direction.

[0318] In some embodiments, by providing the dielectric layer 13 on the upper surfaces of the ring layer 107 and the well layer 11, the dielectric layer 13 can protect the well layer 11 and reduce the damage risk of the semiconductor device 100.

[0319] By providing a second emitter layer 12 on both sides of the trench portion 2110 and forming a first contact hole 1101 in the dielectric layer 13 corresponding to between two adjacent trench portions 2110, at least a part of the emitter metal layer 14 can pass through the first contact hole 1101 and be electrically connected to the second emitter layer 12, thereby ensuring the normal operation of the first semiconductor device type region 1011.

[0320] In some embodiments, by forming a second contact hole 1102 in the portion of the dielectric layer 13 corresponding to the first emitter layer 17, such that the length of the second contact hole 1102 in the first direction is greater than the length of the first contact hole 1101 in the first direction, and the second contact hole 1102 directly corresponds to the second semiconductor device type region 1012. Thus, different from arranging a plurality of first contact holes 1101 in the first semiconductor device type region 1011, only one second contact hole 1102 is arranged in the second semiconductor device type region 1012, such that at least a part of the emitter metal layer 14 passes through the second contact hole 1102 and is electrically connected to the portion of the well layer 11 located in the middle of the ring layer 107, that is: the emitter metal layer 14 is in contact with the well layer 11 of the second semiconductor device type region 1012, thereby ensuring the normal operation of the second semiconductor device type region 1012.

[0321] Combined Fig.49 As shown, a barrier metal layer 108 is provided on the surface of the dielectric layer 13, the barrier metal layer 108 is located between the dielectric layer 13 and the emitter metal layer 14, and a third contact hole 341 is formed in the portion of the barrier metal layer 108 corresponding to the second contact hole 1102, and at least a part of the emitter metal layer 14 passes through the third contact hole 341 and the second contact hole 1102 and is electrically connected to the portion of the well layer 11 located in the middle of the ring layer 107.

[0322] In some embodiments, considering that the width of the first contact hole 1101 on the dielectric layer 13 is small, for the convenience of arranging the emitter metal layer 14 and ensuring the contact between the emitter metal layer 14 and the second emitter layer 12, a barrier metal layer 108 can be provided on the surface of the dielectric layer 13, and then the emitter metal layer 14 is deposited. In this way, the barrier metal layer 108 is located between the dielectric layer 13 and the emitter metal layer 14, thereby ensuring the normal extraction of current and the normal operation of the first semiconductor device type region 1011 and even the semiconductor device 100.

[0323] In some embodiments, considering that the width of the second contact hole 1102 is relatively large, without affecting the electrical connection between the emitter metal layer 14 and the part of the well layer 11 located in the middle of the ring layer 107, by forming a third contact hole 341 in the part of the barrier metal layer 108 corresponding to the second contact hole 1102, the barrier metal layer 108 at the second semiconductor device type region 1012 can be eliminated, so that at least part of the emitter metal layer 14 can pass through the third contact hole 341 and the second contact hole 1102 and be directly electrically connected to the part of the well layer 11 located in the middle of the ring layer 107. Thereby, the contact resistance can be reduced, the forward conduction voltage drop of the second semiconductor device type region 1012 can be reduced, and the working performance of the second semiconductor device type region 1012 and even the semiconductor device 100 can be improved.

[0324] Combined Fig.50 As shown, the manufacturing method of the semiconductor device 100 according to the present disclosure may mainly include the following steps:

[0325] Step 1, preparing the drift layer 10;

[0326] Step 2, injecting the ring layer 107 of the second conductivity type into the drift layer 10 and annealing the ring layer 107;

[0327] Step 3, etching a trench portion 2110 in the drift layer 10 and providing an oxide insulating layer 70 on the upper surface of the drift layer 10;

[0328] Step 4, injecting the well layer 11 of the second conductivity type into the drift layer 10 and annealing the well layer 11, wherein the well layer 11 is located on both sides of the ring layer 107.

[0329] In some embodiments, when manufacturing the semiconductor device 100, to provide the drift layer 10 of the first conductivity type, the ring layer 107 of the second conductivity type can be first injected into the drift layer 10 and the ring layer 107 is annealed. The ring layer 107 is located at the junction of the first semiconductor device type region 1011 and the second semiconductor device type region 1012. Then, only the trench portion 2110 is etched in the drift layer 10 corresponding to the first semiconductor device type region 1011, and the oxide insulating layer 70 is provided on the upper surface of the drift layer 10. Then, the well layer 11 of the second conductivity type is injected into the drift layer 10 and the well layer 11 is annealed, so that the upper surfaces of the well layer 11 and the ring layer 107 together form the upper surface of the drift layer 10.

[0330] In this way, the setting of the trench portion 2110 at the second semiconductor device type region 1012 can be eliminated, the effective area of the PN junction of the second semiconductor device type region 1012 can be increased, and the forward conduction voltage drop of the second semiconductor device type region 1012 can be reduced.

[0331] Moreover, since the implantation dose and annealing time of the loop layer 107 are greater than those of the well layer 11, by adopting the method of implanting the loop layer 107 first and then the well layer 11, the junction depth and doping concentration of the first semiconductor device type region 1011 and the second semiconductor device type region 1012 can be ensured to be the same, the breakdown voltages of the first semiconductor device type region 1011 and the second semiconductor device type region 1012 can be ensured to be the same, and the breakdown voltage capability of the semiconductor device 100 can be ensured.

[0332] Combined with Fig.50 As shown, after the step of implanting the well layer 11 of the second conductivity type in the drift layer 10 and annealing the well layer 11, where the well layer 11 is located on both sides of the loop layer 107, the manufacturing method of the semiconductor device 100 may further include: implanting the second emitter layer 12 in the drift layer 10; disposing a dielectric layer 13 on the upper surface of the oxide insulating layer 70; opening a first contact hole 1101 in the dielectric layer 13 between two adjacent trench portions 2110, and opening a second contact hole 1102 in the portion of the dielectric layer 13 corresponding to the well layer 11 located in the middle of the loop layer 107, where the length of the second contact hole 1102 in the first direction is greater than the length of the first contact hole 1101 in the first direction.

[0333] In some embodiments, after implanting the well layer 11 of the second conductivity type in the drift layer 10 and annealing the well layer 11, the second emitter layer 12 may be implanted into both sides of the trench portion 2110 in the drift layer 10, and then the dielectric layer 13 is disposed on the surface of the oxide insulating layer 70, and the dielectric layer 13 covers the well layer 11, the loop layer 107, the second emitter layer 12, and the oxide insulating layer 70. Then, the first contact hole 1101 and the second contact hole 1102 are correspondingly opened on the dielectric layer 13, where the first contact hole 1101 corresponds to the region between two adjacent trench portions 2110, that is: the second emitter layer 12 may be exposed through the first contact hole 1101, and the second contact hole 1102 may correspond to the portion of the well layer 11 located in the middle of the loop layer 107, that is: the well layer 11 corresponding to the second semiconductor device type region 1012 may be exposed through the second contact hole 1102.

[0334] It can be understood that the width of the well layer 11 corresponding to the second semiconductor device type region 1012 is much larger than the width between two adjacent trench portions 2110. Therefore, the length of the second contact hole 1102 in the first direction is much larger than the length of the first contact hole 1101 in the first direction.

[0335] In some embodiments, combined with Fig.50As shown, after forming a first contact hole 1101 in the dielectric layer 13 between two adjacent trench portions 2110 and forming a second contact hole 1102 in the dielectric layer 13 corresponding to the portion of the well layer 11 located in the middle of the ring layer 107, where the length of the second contact hole 1102 in the first direction is greater than the length of the first contact hole 1101 in the first direction, the manufacturing method of the semiconductor device 100 may further include: disposing a barrier metal layer 108 on the upper surface of the dielectric layer 13, on the sidewalls of the dielectric layer 13 corresponding to the first contact hole 1101 and the second contact hole 1102, and on the upper surfaces of the ring layer 107 and the well layer 11; etching a portion of the opposite sidewalls of the barrier metal layer 108 corresponding to the second contact hole 1102 and the trench portions 2110 on both sides of the second contact hole 1102 to form a third contact hole 341.

[0336] In some embodiments, after forming a first contact hole 1101 in the dielectric layer 13 between two adjacent trench portions 2110 and forming a second contact hole 1102 in the dielectric layer 13 corresponding to the portion of the well layer 11 located in the middle of the ring layer 107, a barrier metal layer 108 may be disposed on the upper surface of the dielectric layer 13, on the sidewalls of the dielectric layer 13 corresponding to the first contact hole 1101 and the second contact hole 1102, and on the upper surfaces of the ring layer 107 and the well layer 11, and a portion of the opposite sidewalls of the second contact hole 1102 and the trench portions 2110 on both sides of the second contact hole 1102 may be etched to form a third contact hole 341.

[0337] On the one hand, the barrier metal layer 108 in the first semiconductor device type region 1011 remains, enabling the barrier metal layer 108 to contact the second emitter layer 12, facilitating the subsequent electrical connection between the emitter metal layer 14 and the second emitter layer 12 and ensuring the normal operation of the first semiconductor device type region 1011. On the other hand, the barrier metal layer 108 in the second semiconductor device type region 1012 can be removed, facilitating the direct electrical connection between the emitter metal layer 14 and the well layer 11 of the second semiconductor device type region 1012 and reducing the on-state voltage drop of the second semiconductor device type region 1012.

[0338] Combined with Fig.50As shown, after the step of etching portions of opposite sidewalls of the barrier metal layer 108 corresponding to the second contact hole 1102 and the trench portions 2110 on both sides of the second contact hole 1102 to etch out the third contact hole 341, the manufacturing method of the semiconductor device 100 may further include: disposing an emitter metal layer 14 on the upper surface of the barrier metal layer 108, at least a portion of the emitter metal layer 14 passing through the first contact hole 1101 and being electrically connected to the second emitter layer 12, and at least a portion of the emitter metal layer 14 passing through the third contact hole 341 and the second contact hole 1102 and being electrically connected to the portion of the well layer 11 located in the middle of the ring layer 107; disposing a field stop layer 15 on the lower surface of the drift layer 10; disposing a collector layer 16 of a second conductivity type on the lower surface of the field stop layer 15; disposing a first emitter layer 17 at a position corresponding to the middle of the ring layer 107 in the collector layer 16; and disposing a collector metal layer 18 on the lower surface of the collector layer 16.

[0339] In some embodiments, after etching portions of opposite sidewalls of the barrier metal layer 108 corresponding to the second contact hole 1102 and the trench portions 2110 on both sides of the second contact hole 1102 to etch out the third contact hole 341, an emitter metal layer 14 may be first disposed on the upper surface of the barrier metal layer 108, such that at least a portion of the emitter metal layer 14 passes through the first contact hole 1101 to contact the second emitter layer 12, and at least a portion of the emitter metal layer 14 may pass through the third contact hole 341 and the second contact hole 1102 to communicate with the well layer 11. Then, a field stop layer 15 is disposed on the lower surface of the drift layer 10, and in some embodiments, a collector layer 16 of a second conductivity type is disposed on the lower surface of the field stop layer 15. A first emitter layer 17 is disposed at a position corresponding to the middle of the ring layer 107 in the collector layer 16. Finally, a collector metal layer 18 is disposed on the lower surfaces of the collector layer 16 and the first emitter layer 17, and the collector metal layer 18 is electrically connected to both the collector layer 16 and the first emitter layer 17.

[0340] In this way, the semiconductor device 100 can be manufactured such that the semiconductor device 100 includes a first semiconductor device type region 1011 and a second semiconductor device type region 1012, and the semiconductor device 100 has a lower on-state voltage drop and a better breakdown voltage withstand capability.

[0341] Next, in conjunction with Fig.49 and Figure 51-Figure 57 the manufacturing method of the semiconductor device 100 will be described by way of example. The semiconductor device 100 is an RC-IGBT and includes the following steps:

[0342] Step 1, as Fig.51 shown, provide an N-substrate 2 material as the drift layer 10. Form structure 1.

[0343] Step 2, as Fig.52 As shown, based on Structure 1, P-type ring layer 107 is implanted and annealed to form Structure 2.

[0344] Step 3, as Fig.53 shown, based on Structure 2, trench portion 2110 is etched, and oxidation insulation layer 70 is sequentially grown and polysilicon 71 is deposited in trench portion 2110, and then polysilicon 71 is etched to form Structure 3.

[0345] Step 4, as Fig.54 shown, based on Structure 3, P-type well layer 11 is implanted and annealed to form Structure 4.

[0346] Step 5, as Fig.55 shown, based on Structure 4, N+ second emitter layer 12 is implanted and annealed, and then dielectric layer 13 is deposited thereon to form Structure 5.

[0347] Step 6, as Fig.56 shown, based on Structure 5, first contact hole 1101 and second contact hole 1102 are etched on dielectric layer 13, and then Ti or TiN barrier metal layer 108 is deposited on dielectric layer 13 to form Structure 6.

[0348] Step 7, as Fig.57 shown, based on Structure 6, third contact hole 341 is etched on barrier metal layer 108 to ensure that there is no barrier metal layer 108 in the FRD region to form Structure 7.

[0349] Step 8, as Fig.49 shown, based on Structure 7, emitter metal layer 14 is prepared by metal sputtering, and then N+ field stop layer 15 implantation, P+ collector layer 16 implantation, N+ first emitter layer 17 implantation in the FRD region, laser annealing, and collector metal layer 18 preparation by metal sputtering are successively carried out. Finally, semiconductor device 100 is formed.

[0350] Next, refer to Figure 58-Figure 62 to describe semiconductor device 100 according to some embodiments of the present disclosure. The semiconductor device 100 is, for example, an IGBT (Insulated Gate Bipolar Transistor). In the following description, N and P represent the conduction types of semiconductors. In the present disclosure, the first conduction type is set as N-type and the second conduction type is set as P-type for description.

[0351] Combined with Fig.58 shown, semiconductor device 100 according to the present disclosure may mainly include: drift layer 10 of the first conduction type, breakdown voltage ring 25 of the second conduction type, polysilicon field plate 8, first dielectric layer 1305, and metal field plate 90.

[0352] In some embodiments, a field stop layer 15 of a first conductivity type is disposed below a drift layer 10 of the first conductivity type, a collector layer 16 of a second conductivity type is disposed below the field stop layer 15, and a collector metal layer 18 is disposed below the collector layer 16, so as to form a basic structure of the semiconductor structure and ensure the normal operation of the semiconductor device 100.

[0353] Considering that the electric field intensity in the terminal region 103 of the semiconductor device 100 is relatively high, and the voltage borne per unit length is relatively large, it is relatively easy to have voltage breakdown at this location. By disposing a voltage withstand ring 25 on the surface of the drift layer 10 corresponding to the terminal region 103 of the semiconductor device 100, the voltage withstand ring 25 can optimize the electric field distribution in the terminal region 103 and improve the voltage withstand ability of the terminal region 103.

[0354] In some embodiments, in combination Fig.58 and Fig.60 as shown, a polysilicon field plate 8 is disposed above the surface of the voltage withstand ring 25 and is electrically connected corresponding to the voltage withstand ring 25. The polysilicon field plate 8 is provided with a first via 801. A first dielectric layer 1305 is disposed above the surface of the polysilicon field plate 8. The first dielectric layer 1305 is provided with a second via 1031 and a third via 1032. The second via 1031 corresponds to the first via 801, and the third via 1032 and the second via 1031 are spaced apart on the surface of the first dielectric layer 1305. The metal field plate 90 is provided with a first electrical connection protrusion 41 and a second electrical connection protrusion 42. The first electrical connection protrusion 41 sequentially passes through the second via 1031 and the first via 801 and is electrically connected to the voltage withstand ring 25. The second electrical connection protrusion 42 passes through the third via 1032 and is electrically connected to the polysilicon field plate 8.

[0355] In some embodiments, considering that there is usually a curved surface at the PN junction interface, and since the electric field at the curved surface junction is larger, the semiconductor device 100 is likely to break down at these locations. By disposing the polysilicon field plate 8 above the surface of the voltage withstand ring 25, disposing the first dielectric layer 1305 above the surface of the polysilicon field plate 8, and disposing the metal field plate 90 above the surface of the first dielectric layer 1305, the main junction depletion region 600 can be effectively widened outwards, the electric field concentration phenomenon can be avoided, the breakdown voltage can be increased, and thus the voltage withstand ability of the terminal region 103 and even the semiconductor device 100 can be improved in some embodiments.

[0356] In some embodiments, a first via 801 is formed in the polysilicon field plate 8, and a second via 1031 is formed in the first dielectric layer 1305. The first via 801 corresponds to the second via 1031. A first electrical connection protrusion 41 is provided on the metal field plate 90. In this way, the first electrical connection protrusion 41 can sequentially penetrate through the second via 1031 and the first via 801, and the first electrical connection protrusion 41 can be in contact electrical connection with the breakdown voltage ring 25, so that the electrical connection between the metal field plate 90 and the breakdown voltage ring 25 can be realized, and the metal field plate 90 and the breakdown voltage ring 25 are at the same potential.

[0357] In some embodiments, a third via 1032 is formed in the first dielectric layer 1305, and a second electrical connection protrusion 42 is correspondingly provided on the metal field plate 90. In this way, only by making the second electrical connection protrusion 42 penetrate through the third via 1032, the second electrical connection protrusion 42 can be in contact electrical connection with the polysilicon field plate 8, so that the electrical connection between the metal field plate 90 and the polysilicon field plate 8 can be realized, and the metal field plate 90 and the polysilicon field plate 8 are at the same potential.

[0358] Among them, the third via 1032 and the second via 1031 are spaced apart on the surface of the first dielectric layer 1305. In a specific embodiment of the present disclosure, the third via 1032 and the second via 1031 are spaced apart in the left-right direction of the first dielectric layer 1305. In this way, it is necessary to correspondingly extend the length of the polysilicon field plate 8 in the left-right direction, so that the polysilicon field plate 8 can correspond to the second via 1031 and the third via 1032. Furthermore, the area of the polysilicon field plate 8 can be increased, the electric field modulation ability of the polysilicon field plate 8 for the terminal region 103 can be improved, electric field concentration can be avoided, the electric field distribution in the terminal region 103 can be made more uniform, and thus in some embodiments, the breakdown voltage of the semiconductor device 100 can be increased, and the breakdown voltage resistance ability of the semiconductor device 100 can be improved.

[0359] In addition, the third via 1032 and the second via 1031 are spaced apart on the surface of the first dielectric layer 1305, and the first electrical connection protrusion 41 and the second electrical connection protrusion 42 are also correspondingly spaced apart on the metal field plate 90. In this way, it is not only convenient to form the second via 1031 and the first via 801 in the first dielectric layer 1305, and convenient to provide the first electrical connection protrusion 41 and the second electrical connection protrusion 42 on the metal field plate 90, which can reduce the manufacturing difficulty, but also the first electrical connection protrusion 41 can penetrate through the first via 801 and the second via 1031, and the second electrical connection protrusion 42 can penetrate through the third via 1032 simultaneously, which can improve the assembly efficiency.

[0360] In this way, equipotentiality among the voltage-resistant ring 25, the polysilicon field plate 8, and the metal field plate 90 can be achieved, thereby avoiding the occurrence of a floating electric field caused by non-interconnection of a certain structure among them, and avoiding the interference of the floating electric field by the outside world during the operation of the semiconductor device 100, which may lead to uneven distribution of the electric field in the terminal area 103 and cause problems such as reduced breakdown voltage and reliability. The breakdown voltage of the semiconductor device 100 can be improved, and the reliability of the semiconductor device 100 can be enhanced.

[0361] Therefore, by making the first electrical connection protrusion 41 sequentially penetrate through the second via hole 1031 and the first via hole 801 and be electrically connected to the voltage-resistant ring 25, and making the second electrical connection protrusion 42 penetrate through the third via hole 1032 and be electrically connected to the polysilicon field plate 8, equipotentiality among the voltage-resistant ring 25, the polysilicon field plate 8, and the metal field plate 90 is achieved, thereby improving the breakdown voltage and reliability of the semiconductor device 100.

[0362] Combined Figure 58-Figure 61 As shown, the second via hole 1031 and the first via hole 801 are arranged above the inner sides of the two side boundaries of the voltage-resistant ring 25, and both sides of the metal field plate 90 and the polysilicon field plate 8 extend out of the two side boundaries of the voltage-resistant ring 25.

[0363] In some embodiments, by arranging both the second via hole 1031 and the first via hole 801 above the inner sides of the two side boundaries of the voltage-resistant ring 25, when the first electrical connection protrusion 41 on the metal field plate 90 sequentially penetrates through the second via hole 1031 and the first via hole 801, it can directly contact and be electrically connected to the voltage-resistant ring 25, and it can be ensured that the end of the first electrical connection protrusion 41 is in complete contact with the voltage-resistant ring 25. Thus, not only can the realization of the electrical connection between the metal field plate 90 and the voltage-resistant ring 25 be made simpler, but also it can be ensured that there is sufficient contact area between the metal field plate 90 and the voltage-resistant ring 25, and the stability of the electrical connection between the metal field plate 90 and the voltage-resistant ring 25 can be ensured. Furthermore, the equipotentiality between the metal field plate 90 and the voltage-resistant ring 25 can be ensured more stably and reliably.

[0364] Furthermore, both sides of the metal field plate 90 and the polysilicon field plate 8 extend out of the two side boundaries of the voltage-resistant ring 25, so that the electric field modulation ability of the metal field plate 90 and the polysilicon field plate 8 on the terminal area 103 can be improved, electric field concentration can be avoided, and the electric field distribution in the terminal area 103 can be made more uniform. Thus, in some embodiments, the breakdown voltage of the semiconductor device 100 can be increased, and the breakdown voltage of the semiconductor device 100 can be improved.

[0365] Combined Fig.60 and Fig.61As shown, the aperture of the first via 801 is larger than that of the second via 1031. In some embodiments, the polysilicon field plate 8 is located below the first dielectric layer 1305. During the production process, the first via 801 can be formed in the polysilicon field plate 8 first, and then after the first dielectric layer 1305 is disposed on the polysilicon field plate 8, the second via 1031 is correspondingly formed in the first dielectric layer 1305. By setting the aperture of the first via 801 to be larger than that of the second via 1031, it is possible to avoid affecting the morphology and size of the first via 801 when forming the second via 1031, thereby ensuring the reliability of the polysilicon field plate 8 and even the semiconductor device 100.

[0366] In some embodiments, in combination with Fig.60 As shown, the first electrical connection protrusion 41 is circumferentially spaced from the inner wall of the first via 801 corresponding to the polysilicon field plate 8. In some embodiments, the first electrical connection protrusion 41 sequentially passes through the first through hole 31 and the second through hole 32. By circumferentially spacing the first electrical connection protrusion 41 from the inner wall of the first via 801 corresponding to the polysilicon 71, it is convenient for the first electrical connection protrusion 41 to pass through the first via 801 and can avoid damaging the inner wall of the first via 801 corresponding to the polysilicon field plate 8 during the process of the first electrical connection protrusion 41 passing through, thereby improving the reliability of the semiconductor device 100.

[0367] In combination with Fig.62 As shown, the first via 801 is at least one of a square, a rectangle, a circle, and a rhombus. In some embodiments, the designed shape of the first via 801 can be at least one of a square, a rectangle, a circle, and a rhombus. Correspondingly, the shape of the second via 1031 and the cross-sectional shape of the first electrical connection protrusion 41 can be designed. In this way, the shape of the first via 801 can be simple, facilitating the formation of the first via 801 and the second via 1031, as well as the manufacturing of the first electrical connection protrusion 41, and reducing the production difficulty of the semiconductor device 100.

[0368] In some embodiments, in combination with Fig.62 As shown, there are multiple first vias 801, and the multiple first vias 801 are spaced on the upper surface of the polysilicon field plate 8. There are multiple first electrical connection protrusions 41, and the multiple first electrical connection protrusions 41 correspond to the multiple first vias 801 one by one.

[0369] In some embodiments, a plurality of first vias 801 may be provided. Correspondingly, a plurality of first electrical connection protrusions 41 and second vias 1031 are also provided. By making the plurality of first electrical connection protrusions 41 correspond to the plurality of first vias 801 one by one, the plurality of first electrical connection protrusions 41 can pass through the first vias 801 and the second vias 1031 and be in electrical contact connection with the voltage withstand ring 25. Thus, there can be multiple electrical connections between the metal field plate 90 and the voltage withstand ring 25, and further, the stability and reliability of the electrical connection between the metal field plate 90 and the voltage withstand ring 25 can be improved, and the equipotential between the metal field plate 90 and the voltage withstand ring 25 can be ensured more stably and reliably.

[0370] It should be noted that the plurality of first vias 801 are arranged at intervals on the polysilicon field plate 8, so that it can be ensured that the polysilicon field plate 8 remains as a whole without being disconnected after being perforated.

[0371] Combined with Fig.61 As shown, the semiconductor device 100 may further include a field oxide layer 60. The field oxide layer 60 is provided above the surface of the voltage withstand ring 25 and at least partially located between the polysilicon field plate 8 and the voltage withstand ring 25. The field oxide layer 60 is provided with a fourth via 63, and the fourth via 63 corresponds to the first via 801 and the second via 1031. The first electrical connection protrusion 41 sequentially passes through the second via 1031, the first via 801, and the fourth via 63 and is electrically connected to the voltage withstand ring 25.

[0372] In some embodiments, there may be a field oxide layer 60 between the voltage withstand ring 25 and the polysilicon field plate 8. The field oxide layer 60 may isolate the voltage withstand ring 25 from the polysilicon field plate 8 and the first electrical connection protrusion 41 of the metal field plate 90, resulting in the failure of the electrical connection between the voltage withstand ring 25 and the metal field plate 90. By providing a fourth via 63 corresponding to the first via 801 and the second via 1031 in the field oxide layer 60, at least part of the field oxide between the polysilicon field plate 8 and the voltage withstand ring 25 can be removed. After the first electrical connection protrusion 41 can sequentially pass through the second via 1031, the first via 801, and the fourth via 63, the first electrical connection protrusion 41 can be electrically connected to the voltage withstand ring 25, that is: the contact electrical connection between the metal field plate 90 and the voltage withstand ring 25 can be achieved, thereby ensuring the equipotential between the voltage withstand ring 25 and the metal field plate 90.

[0373] In some embodiments, combined with Fig.61 As shown, the aperture of the fourth via 63 is equal to the aperture of the second via 1031. This not only ensures that the first electrical connection protrusion 41 can smoothly pass through the fourth via 63, facilitating the electrical connection between the metal field plate 90 and the voltage withstand ring 25, but also facilitates the synchronous formation of the fourth via 63 and the second via 1031, thereby improving the production efficiency of the semiconductor device 100.

[0374] Combined with Fig.58 As shown, the semiconductor device 100 includes an active region 101 and a transition region 102. The transition region 102 is disposed between the active region 101 and the terminal region 103. There are multiple breakdown voltage rings 25, and the multiple breakdown voltage rings 25 are arranged at intervals.

[0375] In some embodiments, the active region 101 can not only carry most of the forward current during forward conduction but also bear a high blocking voltage when a reverse voltage is applied. When a reverse voltage is applied to the semiconductor device 100, the terminal region 103 can relieve the electric field crowding at the edge of the active region 101, thereby achieving the purpose of increasing the reverse breakdown voltage of the semiconductor device 100.

[0376] Considering that the terminal region 103 bears a relatively large voltage, by arranging multiple breakdown voltage rings 25 in the terminal region 103 and spacing the multiple breakdown voltage rings 25 apart, the multiple breakdown voltage rings 25 can optimize the electric field distribution in the terminal region 103 in some embodiments, increase the breakdown voltage of the terminal region 103, and thus improve the voltage withstand capacity of the terminal region 103.

[0377] In some embodiments of the present disclosure, in combination Fig.58 As shown, a polysilicon field plate 8 and a metal field plate 90 are correspondingly disposed above one of the multiple breakdown voltage rings 25 that is far from the transition region 102. In some embodiments, the one of the multiple breakdown voltage rings 25 that is far from the transition region 102 bears the maximum voltage. By correspondingly disposing the polysilicon field plate 8 and the metal field plate 90 above it, the structure of the semiconductor device 100 can be simplified while improving the voltage withstand capacity and reliability of the terminal region 103, reducing the production difficulty and production cost of the semiconductor device 100.

[0378] In other embodiments of the present disclosure, a polysilicon field plate 8 and a metal field plate 90 are correspondingly disposed above at least one of the multiple breakdown voltage rings 25. In some embodiments, a polysilicon field plate 8 and a metal field plate 90 can also be correspondingly disposed above at least one of the multiple breakdown voltage rings 25, which can increase the number of the polysilicon field plate 8 and the metal field plate 90, thereby optimizing the electric field distribution in the terminal region 103 in some embodiments, increasing the voltage withstand capacity of the terminal region 103 and even the semiconductor device 100 in some embodiments, and improving the reliability of the semiconductor device 100.

[0379] Of course, whether a polysilicon field plate 8 and a metal field plate 90 are correspondingly disposed above one of the multiple breakdown voltage rings 25 that is far from the transition region 102 or above at least one of the multiple breakdown voltage rings 25, it is necessary to ensure the equipotential of the polysilicon field plate 8, the first dielectric layer 1305, and the metal field plate 90, which will not be elaborated here.

[0380] In some embodiments of the present disclosure, there are multiple polysilicon field plates 8, the multiple polysilicon field plates 8 are arranged at intervals, each of the multiple polysilicon field plates 8 is provided with a first via 801, a second dielectric layer 1306 is arranged between two adjacent polysilicon field plates 8, the first vias 801 on the multiple polysilicon field plates 8 correspond to each other, the second dielectric layer 1306 is provided with a fifth via, the fifth via corresponds to the first via 801, and the first electrical connection protrusion 41 penetrates through the fifth via, the first via 801 and the second via 1031 and is electrically connected to the withstand voltage ring 25.

[0381] In some embodiments, when the terminal region 103 includes multiple polysilicon field plates 8 arranged at intervals, and a second dielectric layer 1306 is arranged between the multiple polysilicon field plates 8, corresponding first vias 801 can be arranged on the multiple polysilicon field plates 8, and a fifth via corresponding to the first via 801 can be arranged on the second dielectric layer 1306, so that the first electrical connection protrusion 41 can penetrate through multiple fifth vias, multiple first vias 801 and the second via 1031 at the same time and be electrically connected to the withstand voltage ring 25, thereby realizing the electrical connection between the metal field plate 90 and the withstand voltage ring 25, and the multiple polysilicon field plates 8 can also be electrically connected to the metal field plate 90 by opening holes in the polysilicon field plate 8 and the second dielectric layer 1306 above it. In this way, even if there are multiple polysilicon field plates 8, the improvement of the electric field distribution in the terminal region 103 can be ensured, and the withstand voltage capacity and reliability of the semiconductor device 100 can be improved.

[0382] The following refers to Figure 63-Figure 76 Describe the semiconductor device 100 according to some embodiments of the present disclosure. The semiconductor device 100 can adopt the manufacturing method of the semiconductor device 100. The semiconductor device 100 can be an insulated gate bipolar transistor. In the following description, N and P represent the conduction types of semiconductors. In the present disclosure, the first conduction type is set as the N type and the second conduction type is set as the P type for description.

[0383] Combined with Figure 63-Figure 67 As shown, the semiconductor device 100 according to the present disclosure mainly includes: a substrate 80, a drift layer 10 of the first conduction type, a well layer 11 of the second conduction type, and a base layer 109 of the second conduction type.

[0384] In some embodiments, the substrate 80 has a first main surface 81 and a second main surface 82, the first main surface 81 and the second main surface 82 are spaced apart from each other in a first direction. By disposing the drift layer 10 within the substrate 80, the drift layer 10 is located between the first main surface 81 and the second main surface 82, and a well layer 11 is disposed at a portion corresponding to the transition region 102 of the semiconductor device 100 on a side of the drift layer 10 facing the first main surface 81. A side of the well layer 11 adjacent to the first main surface 81 forms a part of the first main surface 81. The length of the well layer 11 extends in a second direction, the depth of the well layer 11 extends in the first direction, and a base layer 109 is further disposed at a portion corresponding to the transition region 102 of the semiconductor device 100 on a side of the drift layer 10 facing the first main surface 81. A side of the base layer 109 adjacent to the first main surface 81 forms a part of the first main surface 81. The length of the base layer 109 extends in the second direction and extends from the active region 101 of the semiconductor device 100 to the transition region 102 of the semiconductor device 100. The depth of the base layer 109 extends in the first direction, such that the base layer 109 and the well layer 11 are arranged in the second direction, thereby forming the basic structure of the transition region 102 of the semiconductor device 100 and ensuring the normal operation of the semiconductor device 100.

[0385] Among them, considering that the transition region 102 of the semiconductor device 100 is located between the terminal region 103 and the active region 101, the structure of the transition region 102 is relatively complex and voltage breakdown is likely to occur there. By disposing the well layer 11, the depth of the well layer 11 is set to be greater than the depth of the base layer 109, and the doping concentration of the second conductivity type dopant in the well layer 11 is greater than the doping concentration of the second conductivity type dopant in the base layer 109, which can optimize the electric field distribution in the transition region 102 and improve the breakdown voltage withstand ability of the transition region 102.

[0386] Combined Fig.64 and Fig.65 As shown, the semiconductor device 100 may further include: a first trench 20, the first trench 20 is disposed in the transition region 102, the depth of the first trench 20 extends from the first main surface 81 in the first direction, the length of the first trench 20 extends in a third direction, the first trench 20 is located between the well layer 11 and the base layer 109 in the second direction, and two sides of the first trench 20 in the second direction are respectively in contact with the well layer 11 and the base layer 109, wherein the first direction, the second direction and the third direction are perpendicular to each other.

[0387] In some embodiments, considering that the base layer 109 is spaced apart from the well layer 11 in the second direction, and there is a difference in the doping concentration of the second conductivity type dopant in the base layer 109 and the well layer 11, the second conductivity type dopant in the well layer 11 will diffuse toward the base layer 109 in the second direction. And due to the difference in the depths of the base layer 109 and the well layer 11, a curved surface will be formed at the junction of the base layer 109 and the well layer 11. When the semiconductor device 100 withstands reverse voltage, electric field concentration will occur at this position, the electric field intensity is large, which may lead to a smaller safe operating area and a reduction in the reliability of the semiconductor device 100.

[0388] Define the direction perpendicular to both the first direction and the second direction as the third direction. By providing the second trench 30, an oxide insulating layer 70 can be grown and a polysilicon 71 can be deposited in the second trench 30, and the first trench 20 is located between the well layer 11 and the base layer 109 in the second direction. The first trench 20 has two sidewalls spaced apart in the second direction, and the two sidewalls of the first trench 20 extend in the first direction. By making the two sidewalls of the first trench 20 in the second direction contact the well layer 11 and the base layer 109 respectively, the first trench 20 can block between the well layer 11 and the base layer 109 in the second direction, so as to block the diffusion of the second conductivity type dopant in the well layer 11 toward the base layer 109, and further avoid the formation of a curved surface in the transition region 102. When the semiconductor device 100 withstands reverse voltage, the electric field concentration in the transition region 102 can be avoided, the reliability of the semiconductor device 100 can be improved, and the safe operating area of the semiconductor device 100 can be increased.

[0389] Therefore, by providing the first trench 20 and making the first trench 20 located between the well layer 11 and the base layer 109, the first trench 20 can block the diffusion of the second conductivity type dopant in the well layer 11 toward the base layer 109, avoid the formation of a curved surface in the transition region 102, optimize the electric field distribution in the transition region 102, avoid electric field concentration, thereby improving the reliability of the semiconductor device 100 and increasing the safe operating area of the semiconductor device 100.

[0390] Combined Fig.65 As shown, the depth of the first trench 20 is D4, and the depth of the base layer 109 is D5. D4 and D5 satisfy the relationship: D4≥D5. In some embodiments, by setting the depth of the first trench 20 to be not less than the depth of the base layer 109, it can be ensured that the first trench 20 completely blocks the base layer 109 in the first direction, so as to more reliably block the diffusion of the second conductivity type dopant in the well layer 11 into the base layer 109, avoid the generation of a curved surface at the junction of the well layer 11 and the base layer 109, and further improve the reliability of the semiconductor device 100 and increase the safe operating area of the semiconductor device 100 in some embodiments.

[0391] In some embodiments, in combination with Fig.65 As shown, the depth of the well layer 11 is D6, and D4 and D6 satisfy the relationship: D4 ≤ D6. In some embodiments, the first trench 20 is further provided with a bottom wall that connects the ends of the two side walls facing the second main surface 82. The position curvature of the bottom wall is small and electric field concentration is likely to occur. By setting the depth of the first trench 20 to be not greater than the depth of the well layer 11, it can be ensured that the well layer 11 wraps at least part of the bottom wall of the first trench 20, which can optimize the electric field near the bottom wall, avoid electric field concentration, and thus ensure the breakdown voltage capability of the semiconductor device 100 and the reliability of the semiconductor device 100.

[0392] In combination with Figure 64-Figure 67 As shown, the semiconductor device 100 may further include: a carrier storage layer 110 of a first conductivity type. The carrier storage layer 110 is disposed on a side of the drift layer 10 facing the first main surface 81. The carrier storage layer 110 is located between the drift layer 10 and the base layer 109. The length of the carrier storage layer 110 extends in the second direction and extends from the active region 101 of the semiconductor device 100 to the transition region 102 of the semiconductor device 100. The carrier storage layer 110 is located on a side of the first trench 20 facing the base layer 109 in the second direction. The depth of the carrier storage layer 110 extends in the first direction. The depth of the carrier storage layer 110 is D7, and D7, D5, and D4 satisfy the relationship: D7 + D5 ≤ D4.

[0393] In some embodiments, by providing the carrier storage layer 110 of the first conductivity type, the carrier storage layer 110 is disposed on a side of the drift layer 10 facing the first main surface 81, and the length of the carrier storage layer 110 extends in the second direction and extends from the active region 101 of the semiconductor device 100 to the transition region 102 of the semiconductor device 100, such that the carrier storage layer 110 is at least partially located between the drift layer 10 and the base layer 109, and the depth of the carrier storage layer 110 extends in the first direction. In this way, the carrier storage layer 110 functions to block holes, promote electron injection into the drift layer 10, enhance the conductance modulation effect, reduce the forward conduction voltage drop of the semiconductor device 100, and improve the normal operation of the semiconductor device 100.

[0394] In some embodiments, the carrier storage layer 110 is located on the side of the first trench 20 facing the base layer 109 in the second direction. By setting the sum of the depth of the carrier storage layer 110 and the depth of the base layer 109 to be less than the depth of the first trench 20, the first trench 20 can completely block the carrier storage layer 110 in the first direction, thereby blocking the first conductivity type dopant in the carrier storage layer 110 from diffusing into the well layer 11, avoiding the generation of a PN junction with a small curvature between the carrier storage layer 110 and the well layer 11 in the second direction, optimizing the electric field distribution in the transition region 102, avoiding electric field concentration, and further improving the reliability of the semiconductor device 100 and increasing the safe operating area of the semiconductor device 100 in some embodiments.

[0395] Combined Fig.64 with Fig.67 As shown, the semiconductor device 100 may further include a second trench 30. The depth of the second trench 30 extends from the first main surface 81 towards the first direction to the drift layer 10. The length of the second trench 30 extends in the second direction, and the second trench 30 extends from the active region 101 of the semiconductor device 100 to the transition region 102 of the semiconductor device 100 in the second direction. The second trench 30 is multiple, and the multiple second trenches 30 are spaced apart in the third direction.

[0396] In some embodiments, by providing the second trench 30 such that the second trench 30 extends from the first main surface 81 towards the first direction to the drift layer 10 and extends in the second direction, by growing an oxide insulating layer 70 in the second trench 30, depositing polysilicon 71, and providing an emitter layer 3 of the first conductivity type on both sides of the second trench 30, the second trench 30 can have a conductive channel 4 and have current-carrying capacity.

[0397] In some embodiments, the second trench 30 can be provided as multiple, and the multiple second trenches 30 are spaced apart in the third direction. When the second trench 30 extends in the second direction, it can extend from the active region 101 to the transition region 102. In this way, the multiple second trenches 30 can be connected to the gate pad 104 through the planar gate polysilicon 712 in the transition region 102, thereby leading out the current and ensuring the normal operation of the semiconductor device 100.

[0398] In some embodiments, the depth of the second trench 30 is the same as that of the first trench 20. In some embodiments, the depth of the first trench 20 can be set to be the same as that of the first trench 20, so that the first trench 20 and the second trench 30 can be etched synchronously, thereby simplifying the process flow of the semiconductor device 100.

[0399] The manufacturing method of the semiconductor device 100 according to the present disclosure can be used for the manufacturing of the above-mentioned semiconductor device 100.

[0400] In some embodiments of the present disclosure, in combination with Fig.68 As shown, the manufacturing method of the semiconductor device 100 may mainly include the following steps:

[0401] Step 1, injecting a dopant of the second conductivity type with a first doping concentration into a portion corresponding to the transition region 102 on the side of the drift layer 10 facing the first main surface 81 to form a well layer 11 with a first depth;

[0402] Step 2, injecting a dopant of the second conductivity type with a second doping concentration into the side of the drift layer 10 facing the first main surface 81 to form a base layer 109 with a second depth arranged in the second direction with the well layer 11, wherein the second doping concentration is less than the first doping concentration, and the second depth is less than the first depth;

[0403] Step 3, etching a first trench 20 extending from the first main surface 81 in the first direction between the well layer 11 and the base layer 109.

[0404] In some embodiments, when manufacturing the semiconductor device 100, a substrate 2 material may be first provided as the drift layer 10, and a dopant of the second conductivity type with a first doping concentration is injected into a portion corresponding to the transition region 102 on the side of the drift layer 10 facing the first main surface 81 to form a well layer 11 with a first depth, which can improve the breakdown voltage capability of the transition region 102, and then a dopant of the second conductivity type with a second doping concentration is injected into the side of the drift layer 10 facing the first main surface 81 to form a base layer 109 with a second depth. Wherein, the second doping concentration is less than the first doping concentration, and the second depth is less than the first depth, that is: the doping concentration of the dopant of the second conductivity type in the well layer 11 is greater than the doping concentration of the dopant of the second conductivity type in the base layer 109, and the depth of the well layer 11 in the first direction is greater than the depth of the base layer 109 in the first direction. In this way, on the premise of ensuring the breakdown voltage capability of the transition region 102, there will be a depth difference and a concentration difference between the well layer 11 and the base layer 109.

[0405] After that, a first trench 20 extending from the first main surface 81 in the first direction is etched between the well layer 11 and the base layer 109, so that the first trench 20 can block between the well layer 11 and the base layer 109, thereby blocking the diffusion of the dopant of the second conductivity type in the well layer 11 towards the base layer 109 and improving the reliability of the semiconductor device 100. Wherein, the first conductivity type dopant may be a phosphorus ion, and the second conductivity type dopant may be a boron ion, which is not specifically limited here.

[0406] In combination with Fig.64As shown, in the step of etching the first trench 20 extending in the first direction from the first main surface 81 between the well layer 11 and the base layer 109, it may include: spacing the side boundary of the first trench 20 and the ion implantation region of the well layer 11 facing the base layer 109 from each other in the second direction.

[0407] In some embodiments, after implanting a dopant of the second conductivity type into a portion of the drift layer 10 corresponding to the transition region 102 on the side facing the first main surface 81, the dopant of the second conductivity type will diffuse in the second direction, that is: the finally formed well layer 11 will extend beyond the ion implantation region of the well layer 11 in the second direction. By spacing the side boundary of the first trench 20 and the ion implantation region of the well layer 11 facing the base layer 109 from each other in the second direction in the step of etching the first trench 20 extending in the first direction from the first main surface 81 between the well layer 11 and the base layer 109, a distance can be reserved for the diffusion of the dopant of the second conductivity type in the well layer 11 in the second direction, ensuring that the first trench 20 can be located between the well layer 11 and the subsequent base layer 109, avoiding electric field concentration, and thus increasing the safe operating area of the semiconductor device 100.

[0408] In some embodiments, the spacing distance D8 between the side boundary of the first trench 20 and the ion implantation region of the well layer 11 facing the base layer 109 in the second direction satisfies the relation: 0.5um ≤ D8 ≤ 2.0um. In some embodiments, by setting the spacing distance between the side boundary of the first trench 20 and the ion implantation region of the well layer 11 facing the base layer 109 in the second direction within a reasonable range, not only can it be ensured that the first trench 20 is located between the well layer 11 and the subsequently formed base layer 109, avoiding the formation of a curved surface between the well layer 11 and the base layer 109, but also it can be ensured that the base layer 109 formed after the diffusion of the dopant of the second conductivity type in the second direction at least partially wraps the bottom wall of the first trench 20, avoiding electric field concentration in the first trench 20. Thus, the electric field distribution in the transition region 102 can be optimized, the safe operating area of the semiconductor device 100 can be increased, and the reliability of the semiconductor device 100 can be improved.

[0409] In some embodiments of the present disclosure, in combination with Fig.69As shown, after the step of implanting a dopant of the second conductivity type with a first doping concentration into a portion corresponding to the transition region 102 on the side of the drift layer 10 facing the first main surface 81 to form a well layer 11 with a first depth, and before the step of implanting a dopant of the second conductivity type with a second doping concentration into the side of the drift layer 10 facing the first main surface 81 to form a base layer 109 with a second depth arranged in a second direction with the well layer 11, where the second doping concentration is less than the first doping concentration and the second depth is less than the first depth, the manufacturing method of the semiconductor device 100 may further include: implanting a dopant of the first conductivity type into the side of the drift layer 10 facing the first main surface 81 to form a carrier storage layer 110.

[0410] In some embodiments, during the manufacturing process of the semiconductor device 100, after forming the well layer 11 and before forming the base layer 109, a dopant of the first conductivity type may also be implanted into the side of the drift layer 10 facing the first main surface 81, so that a carrier storage layer 110 can be formed in the semiconductor device 100, thereby improving the working performance of the semiconductor device 100.

[0411] In some embodiments, the carrier storage layer 110 is at least partially located between the drift layer 10 and the base layer 109, and the carrier storage layer 110 is spaced from the well layer 11 in the second direction. In this way, the well layer 11 and the carrier storage layer 110 can also be separated by the first trench 20, and the first trench 20 can block the diffusion of the dopant of the first conductivity type in the carrier storage layer 110 to the well layer 11, thereby preventing the formation of a PN junction with a small curvature and optimizing the electric field distribution.

[0412] In some embodiments, in combination with Fig.69 As shown, after the step of implanting a dopant of the first conductivity type into the side of the drift layer 10 facing the first main surface 81 to form a carrier storage layer 110, the manufacturing method of the semiconductor device 100 may further include: using a high-temperature gas at a first preset temperature to push the well at a high temperature for a first preset time. In this way, the rate and uniformity of the distribution and diffusion of the dopant of the first conductivity type in the substrate 2 can be improved, thereby optimizing the working performance of the carrier storage layer 110 and even the semiconductor device 100 and improving the reliability of the semiconductor device 100. Wherein, the high-temperature gas can be N2, the first preset temperature can be 1150 °C, and the first preset time can be 120 min, which are not specifically limited here.

[0413] In combination with Fig.68 and Fig.69As shown, after the step of implanting a dopant of a second conductivity type into a portion of the drift layer 10 corresponding to the transition region 102 on the side facing the first main surface 81 to form the well layer 11, the manufacturing method of the semiconductor device 100 may further include: high-temperature pushing the well for a second preset time using a high-temperature gas at a second preset temperature. In this way, the rate and uniformity of the distribution and diffusion of the dopant of the second conductivity type in the substrate 2 can be increased, so that the operating performance of the well layer 11 and even the semiconductor device 100 can be optimized, and the reliability of the semiconductor device 100 can be improved. Among them, the high-temperature gas may be N2, the second preset temperature may be 1150 °C, and the second preset time may be 80 min, which is not specifically limited here.

[0414] Combined with Fig.68 and Fig.69 As shown, after the step of implanting a dopant of a second conductivity type with a second doping concentration into the side of the drift layer 10 facing the first main surface 81 to form the base layer 109 with a second depth arranged in the second direction with the well layer 11, the manufacturing method of the semiconductor device 100 may further include: high-temperature pushing the well for a third preset time using a high-temperature gas at a third preset temperature. In this way, the rate and uniformity of the distribution and diffusion of the dopant of the second conductivity type in the substrate 2 can be increased, so that the operating performance of the base layer 109 and even the semiconductor device 100 can be optimized, and the reliability of the semiconductor device 100 can be improved. Among them, the high-temperature gas may be N2, the third preset temperature may be 1150 °C, and the third preset time may be 80 min, which is not specifically limited here.

[0415] Combined with Fig.68 and Fig.69 As shown, after the step of etching the first trench 20 extending from the first main surface 81 in the first direction between the well layer 11 and the carrier storage layer 110, the manufacturing method of the semiconductor device 100 may further include: growing an oxide insulating layer 70 on the surfaces of the well layer 11, the first trench 20, and the base layer 109; depositing polysilicon 71 on the surface of the oxide insulating layer 70 and etching the polysilicon 71; depositing a dielectric layer 13 on the surfaces of the polysilicon 71, the well layer 11, and the base layer 109.

[0416] In some embodiments, after etching a first trench 20 extending from the first main surface 81 in a first direction between the well layer 11 and the base layer 109, in some embodiments, an oxide insulating layer 70 may be grown on the surfaces of the well layer 11, the first trench 20, and the carrier storage layer 110, and then polysilicon 71 may be deposited on the surface of the oxide insulating layer 70. In this way, the polysilicon 71 may be located on the surface of the well layer 11, inside the first trench 20, and on the surface of the base layer 109. Then, the polysilicon 71 is etched, and the polysilicon 71 inside the first trench 20 is retained to form a trench gate polysilicon 711, and a part of the polysilicon 71 on the surface of the well layer 11 is retained to form a planar gate polysilicon 712. Then, a dielectric layer 13 is deposited on the surfaces of the polysilicon 71, the well layer 11, and the base layer 109. In this way, the dielectric layer 13 can protect the surfaces of the polysilicon 71, the well layer 11, and the base layer 109, thereby improving the structural reliability of the semiconductor device 100.

[0417] Combined with Fig.68 and Fig.69 As shown, while etching the first trench 20 extending from the first main surface 81 in a first direction between the well layer 11 and the base layer 109, the semiconductor device 100 may further include: etching a second trench 30 extending from the first main surface 81 in a first direction to the drift layer 10, wherein the second trench 30 extends in a second direction, the second trench 30 is multiple, and the multiple second trenches 30 are spaced in a third direction. The second trench 30 and the first trench 20 have the same depth. In this way, synchronous formation of the first trench 20 and the second trench 30 can be achieved, and in subsequent steps, an oxide insulating layer 70 can be grown and polysilicon 71 can be deposited inside the second trench 30 to connect the second trench 30 to the gate, thereby simplifying the manufacturing method of the semiconductor device 100 and ensuring the normal operation of the semiconductor device 100.

[0418] Next, combined with Fig.65 and Figure 70-Figure 75 , the manufacturing method of the semiconductor device 100 will be described by way of example, including the following steps:

[0419] Step 1, as Fig.70 shown, a substrate 2 material is provided, wherein the substrate 2 material may be a phosphorus-doped silicon substrate 2 with a resistivity of 25 ohm·cm. Structure 1 is formed.

[0420] Step 2, as Fig.71 shown, based on Structure 1, impurity boron ions are implanted with an energy of 60 kev and a dose of 5E13 cm−2, and high-temperature well pushing is performed. Among them, high-temperature well pushing uses gas N2 at a high temperature of 1150 °C for 80 min to form the well layer 11. Structure 2 is formed.

[0421] Step 3, as Fig.72As shown, based on Structure 2, impurity phosphorus ions are implanted with an energy of 200 kev and a dose of 5E12 cm-2, and high-temperature drive-in is performed. Among them, the high-temperature drive-in uses gas N2 at a high temperature of 1150 °C for 120 min to form the carrier storage layer 110. Structure 3 is formed.

[0422] Step 4, as Fig.73 shown, based on Structure 3, the first trench 20 is etched. Structure 4 is formed.

[0423] Step 5, as Fig.74 shown, based on Structure 4, gas O2 at 1100 °C is implanted to generate 0.12 um thick silicon dioxide as the insulating oxide layer 70. Structure 5 is formed.

[0424] Step 6, as Fig.75 shown, based on Structure 5, 0.8 um thick polysilicon 71 is deposited into the first trench 20 and on the plane, and the excess polysilicon 71 is etched off. Structure 6 is formed.

[0425] Step 7, as Fig.75 shown, based on Structure 6, impurity boron ions are implanted with an energy of 100 kev and a dose of 2E13 cm-2, and high-temperature drive-in is performed. Among them, the high-temperature drive-in uses gas N2 at a high temperature of 1150 °C for 80 min to form the base layer 109. Structure 7 is formed.

[0426] Step 8, as Fig.65 shown, based on Structure 7, 1 um thick silicon dioxide is deposited as the dielectric layer 13. The semiconductor device 100 is formed. It should be noted that here, the semiconductor device 100 provided with the carrier storage layer 110 is taken as an example. The specific manufacturing process of the semiconductor device 100 without the carrier storage layer 110 can be obtained in the same way and will not be elaborated here.

[0427] Next, refer to Figure 77-Figure 86 to describe the semiconductor device 100 according to some embodiments of the present disclosure. In the following description, N and P represent the conductivity types of semiconductors. In the present disclosure, the first conductivity type is set as the P type and the second conductivity type is set as the N type for description.

[0428] Combined with Figure 77-Figure 82As shown, the semiconductor device 100 according to the present disclosure may mainly include: a semiconductor substrate 810, a drift layer 10, a ring layer 107, and a main trench portion 213. Among them, the semiconductor substrate 810 has a first main surface 81 and a second main surface 82 opposite to the first main surface 81. The ring layer 107 is disposed on one side of the drift layer 10 facing the first main surface 81. The surface of the ring layer 107 away from the drift layer 10 constitutes a part of the first main surface 81. The main trench portion 213 is disposed in the ring layer 107 and extends in a first direction, where the first direction is perpendicular to the second direction.

[0429] In some embodiments, the semiconductor substrate 810 has a first main surface 81 and a second main surface 82. Both the ring layer 107 and the drift layer 10 are located between the first main surface 81 and the second main surface 82. And the ring layer 107 is disposed on one side of the drift layer 10 facing the first main surface 81. The surface of the ring layer 107 away from the drift layer 10 constitutes a part of the first main surface 81. Moreover, an oxide insulating layer 70, a polysilicon layer 111, and an interlayer dielectric layer 1304 are stacked on the ring layer 107. A field stop layer 15 and a collector layer 16 are also disposed under the drift layer 10.

[0430] Further, the main trench portion 213 is provided in the ring layer 107 and extends in the first direction. In this way, a gate can be formed at the main trench portion 213. And an emitter metal layer 14 is disposed on the interlayer dielectric layer 1304, and a collector metal layer 18 (not shown in the figure) is disposed under the collector layer 16, so that the basic structure of the semiconductor device 100 can be formed to ensure the normal operation of the semiconductor device 100.

[0431] Among them, the main trench portion 213 may mainly include a plurality of gate trench groups 21 and a plurality of dummy gate trench portions 221. The plurality of gate trench groups 21 are spaced apart in the second direction. At least one dummy gate trench portion 221 is disposed between two adjacent gate trench groups 21. The gate trench group 21 includes at least two gate trench portions 211 spaced apart in the second direction.

[0432] Specifically, oxide insulating layers 70 are provided in both the gate trench portions 211 and the dummy gate trench portions 221, and polysilicon 71 is deposited. However, a dopant of the first conductivity type is implanted into the gate trench portions 211, and a well layer 11 of the second conductivity type is provided. A gate can be formed at the gate trench portions 211, which has a conductive channel 4 and has current-carrying capacity to ensure the normal operation of the semiconductor device 100. While the first conductivity type dopant is not implanted into the dummy gate trench portions 221, and the well layer 11 of the second conductivity type is not provided. It does not have a conductive channel 4 and does not have current-carrying capacity. The dummy gate trench portions 221 can be connected to the emitter to reduce the Miller capacitance and lower the current density.

[0433] By forming at least two gate trench portions 211 into one gate trench group 21, forming at least one dummy gate trench portion 221 into one dummy gate trench group 22, and setting both the gate trench group 21 and the dummy gate trench group 22 to be multiple, the multiple gate trench groups 21 and the multiple dummy gate trench groups 22 are alternately arranged at intervals in the second direction in sequence. In this way, the arrangement of the multiple gate trench portions 211 and the multiple dummy gate trench portions 221 in the second direction can be made more reasonable, thereby improving the working performance of the semiconductor device 100 in some embodiments.

[0434] Combined Figure 77-Figure 78 with Fig.82 As shown, the semiconductor device 100 of the present disclosure may further include: a connection trench portion 214. The connection trench portion 214 is disposed in the loop layer 107 and extends in the second direction. The connection trench portion 214 is located at the edge of the active region 101 of the semiconductor device 100. The connection trench portion 214 connects at least one end of at least two gate trench portions 211 in each gate trench group 21, wherein the first direction is perpendicular to the second direction.

[0435] In some embodiments, at least two gate trench portions 211 in each gate trench group 21 are spaced apart in the second direction, that is, the ends of at least two gate trench portions 211 in each gate trench group 21 are also spaced apart in the second direction. Considering the region where the ends of the gate trench portions 211 are located, the electric field distribution is relatively concentrated, the distribution of the electric field is not uniform enough, electrostatic protection failure is likely to occur, and the insulation breakdown voltage withstand ability is also relatively low. By disposing the connection trench portion 214 in the loop layer 107, making the connection trench portion 214 extend in the second direction, and making the connection trench portion 214 located at the edge of the active region 101 of the semiconductor device 100, and making the connection trench portion 214 connect at least one end of at least two gate trench portions 211 in each gate trench group 21, in this way, within each gate trench group 21, the connection trench portion 214 can surround at least one end of at least two gate trench portions 211 thereof in the first direction, and make the connection trench portion 214 communicate with at least two gate trench portions 211 within each gate trench group 21.

[0436] On the one hand, the connection trench portion 214 surrounds the outside of the ends of at least two gate trench portions 211 within each gate trench group 21, which can optimize the electric field distribution at the ends of at least two gate trench portions 211 within each gate trench group 21, make the electric field distribution at the ends of at least two gate trench portions 211 within each gate trench group 21 more uniform, thereby effectively improving the electrostatic protection ability of the semiconductor device 100, avoiding electrostatic failure at the ends of the main trench portion 213 of the semiconductor device 100, and improving the insulation breakdown voltage withstand ability of the semiconductor device 100, and further improving the reliability of the semiconductor device 100.

[0437] On the other hand, the connecting groove portion 214 can serve as a gate path, thereby increasing the gate path, improving the turn-on speed of the semiconductor device 100, and reducing the turn-on loss.

[0438] Thus, by providing the connecting groove portion 214, arranging the connecting groove portion 214 in the ring layer 107 and extending it in the second direction, with the connecting groove portion 214 located at the edge of the active region 101 of the semiconductor device 100, and the connecting groove portion 214 connecting at least one end of at least two gate groove portions 211 in each gate groove group 21, not only can the electric field distribution of the semiconductor device 100 be optimized, improving the electrostatic protection ability and the insulation breakdown voltage withstand ability of the semiconductor device 100, but also the turn-on speed of the semiconductor device 100 can be increased, and the turn-on loss can be reduced.

[0439] Combined Fig.82 As shown, connecting groove portions 214 are provided at both ends of at least two gate groove portions 211 in each gate groove group 21. In some embodiments, the gate groove portion 211 has two ends in the first direction. By providing connecting groove portions 214 at both ends of at least two gate groove portions 211 in each gate groove group 21, the connecting groove portion 214 at one end can connect and communicate at least one end of at least two gate groove portions 211, and the connecting groove portion 214 at the other end can connect and communicate at least one end of at least two gate groove portions 211, so that all ends of each gate groove group 21 can be connected to the connecting groove portion 214, avoiding unconnected ends in each gate groove group 21, optimizing the electric field distribution of the semiconductor device 100 in some embodiments, improving the electrostatic protection ability and the insulation breakdown voltage withstand ability of the semiconductor device 100, and increasing the turn-on speed of the semiconductor device 100 in some embodiments.

[0440] It should be noted that the semiconductor device 100 is provided with a gate pad 104 for connecting to the gate and serving as a gate lead-out terminal. The gate groove portion 211 and the dummy gate groove portion 221 are disconnected at the gate pad 104. Therefore, a connecting groove portion 214 can also be provided at the end of the gate groove group 21 close to the gate pad 104, so that the connecting groove portion 214 connects and communicates the end of the gate groove group 21 close to the gate pad 104, thereby more reliably improving the electrostatic protection ability of the semiconductor device 100 and increasing the turn-on speed of the semiconductor device 100.

[0441] In some embodiments of the present disclosure, a dummy gate trench portion 221 is provided between at least two gate trench portions 211 in each gate trench group 21. In some embodiments, a dummy gate trench portion 221 may be provided between at least two gate trench portions 211 in each gate trench group 21, and the length of the dummy gate trench portion 221 in the first direction is not greater than the length of the gate trench portion 211, so as to prevent the setting of the dummy gate trench portion 221 from affecting the connection of at least one end of at least two gate trench portions 211 in each gate trench group 21 by the connection trench portion 214.

[0442] In a specific embodiment of the present disclosure, as shown in Fig.82 each gate trench group 21 may mainly include two gate trench portions 211, and the connection trench portion 214 connects at least one end of the two gate trench portions 211 in each gate trench group 21. In some embodiments, each gate trench group 21 may mainly include two gate trench portions 211, and the connection trench portion 214 connects at least one end of the two gate trench portions 211 in each gate trench group 21, so that the setting of the number of gate trench portions 211 in each gate trench group 21 can be made more reasonable, and it is also convenient for the setting of the connection trench portion 214.

[0443] As shown in Figure 77-Figure 79 the connection trench portion 214 connects at least one end of a plurality of gate trench groups 21.

[0444] In some embodiments, when considering that the connection trench portion 214 connects at least two gate trench portions 211 in each gate trench group 21, although the electric field distribution of the semiconductor device 100 can be optimized to a certain extent, and the electrostatic protection ability and insulation breakdown ability of the semiconductor device 100 can be improved, the plurality of gate trench groups 21 are still in a non-connected state, and there is still an end region in each gate trench group 21 in the second direction, and the electric field still concentrates here, and the electrostatic protection ability and insulation breakdown voltage ability of the semiconductor device 100 still need to be improved.

[0445] By making the connection trench portion 214 connect at least one end of a plurality of gate trench groups 21, it is convenient to connect the connection trench portion 214 with at least one end of all the gate trench portions 211 of the semiconductor device 100, so that the connection trench portion 214 can surround at least one end of all the gate trench portions 211 of the semiconductor device 100, and the connection trench portion 214 is connected to at least one end of all the gate trench portions 211 of the semiconductor device 100.

[0446] On the one hand, the connecting trench portion 214 surrounds the outside of the ends of all the gate trench portions 211. This can not only optimize the electric field distribution at the ends of all the gate trench portions 211, making the electric field distribution at the ends of all the gate trench portions 211 more uniform and avoiding electric field concentration at the ends of all the gate trench portions 211, but also increase the gate oxide thickness at the ends of all the gate trench portions 211. As a result, the electrostatic protection ability of the semiconductor device 100 can be effectively improved, electrostatic failure at the ends of the gate trench portions 211 of the semiconductor device 100 can be avoided, and the reliability of the semiconductor device 100 can be enhanced.

[0447] On the other hand, the connecting trench portion 214 can serve as a gate path, thereby increasing the gate path, improving the turn-on speed of the semiconductor device 100, reducing the turn-on loss, and enhancing the working performance of the semiconductor device 100.

[0448] On yet another hand, to ensure the normal extraction of current, contact holes 171 need to be provided in the semiconductor device 100. The contact holes 171 can connect the gate to other materials, thereby realizing the functions of the circuit. By providing the connecting trench portion 214, the connecting trench portion 214 is made to communicate with the ends of multiple gate trench portions 211. In this way, on the premise of ensuring the normal operation of the semiconductor device 100, the contact holes 171 can be directly provided in the connecting trench portion 214, which is convenient for the manufacturing of the contact holes 171 and reduces the manufacturing difficulty of the contact holes 171 and even the semiconductor device 100.

[0449] In this way, not only can the electric field distribution of the semiconductor device 100 be optimized and the electrostatic protection ability of the semiconductor device 100 be improved, but also the turn-on speed of the semiconductor device 100 can be increased, the turn-on loss can be reduced, and the manufacturing difficulty of the semiconductor device 100 can be decreased.

[0450] In some embodiments of the present disclosure, as shown in Figure 77-Figure 79 the length of the gate trench portion 211 in the first direction is greater than the length of the dummy gate trench portion 221 in the first direction. The two ends of the gate trench portion 211 in the first direction protrude from the two ends of the dummy gate trench portion 221 in the first direction. The connecting trench portion 214 is strip-shaped and spaced from the dummy gate trench portion 221.

[0451] In some embodiments, considering that the dummy gate trench portion 221 has no conductive ability, there will be no electrostatic failure at the ends of the dummy gate trench portion 221. When the length of the gate trench portion 211 in the first direction is greater than the length of the dummy gate trench portion 221 in the first direction, and the two ends of the gate trench portion 211 in the first direction protrude from the two ends of the dummy gate trench portion 221 in the first direction, it is only necessary to connect the connection trench portion 214 to each gate trench group 21, without connecting the multiple dummy gate trench groups 22. The connection trench portion 214 is strip-shaped and spaced from the dummy gate trench portion 221, which can improve the electrostatic protection ability of the semiconductor device 100 and the turn-on speed of the semiconductor device 100, thereby reducing the manufacturing cost of the semiconductor device 100.

[0452] In other embodiments of the present disclosure, the connection trench portion 214 connects at least one end of the multiple gate trench groups 21 and the multiple dummy gate trench portions 221. In some embodiments, it is also possible to connect at least one end of the multiple gate trench groups 21 and the multiple dummy gate trench portions 221 by the connection trench portion 214, that is, the connection trench portion 214 can connect at least one end of all the main trench portions 213. In this way, on the premise of optimizing the electric field distribution of the semiconductor device 100, it is convenient to open the connection trench portion 214 and reduce the manufacturing difficulty of the semiconductor device 100.

[0453] In some embodiments, the length of the dummy gate trench portion 221 in the first direction is equal to the length of the gate trench portion 211 in the first direction, and the two ends of the gate trench portion 211 in the first direction are flush with the two ends of the dummy gate trench portion 221 in the first direction. In some embodiments, when the length of the dummy gate trench portion 221 in the first direction of the semiconductor device 100 is equal to the length of the gate trench portion 211 in the first direction, and the two ends of the gate trench portion 211 in the first direction are flush with the two ends of the dummy gate trench portion 221 in the first direction, the connection trench portion 214 can be directly connected between the end of the gate trench portion 211 and the end of the dummy gate trench portion 221, so that the connection trench portion 214 penetrates the active region 101 of the semiconductor device 100 in the first direction, making the structure of the semiconductor device 100 simpler and more reliable.

[0454] In still some embodiments of the present disclosure, the connecting trench portion 214 connects at least one end of a plurality of dummy gate trench portions 221. In some embodiments, on the premise that the connecting trench portion 214 is provided to connect at least one end of a plurality of gate trench portions 211 in each gate trench group 21, the connecting trench portion 214 may also be additionally provided to connect at least one end of a plurality of dummy gate trench portions 221 between two adjacent gate trench groups 21. In this way, on the one hand, the connecting trench portion 214 can also optimize the electric field distribution at at least one end of the plurality of dummy gate trench portions 221, avoid electric field concentration, and improve the reliability of the semiconductor device 100. On the other hand, it is also convenient for the separate design of the connecting trench portion 214 and the dummy gate trench portion 221, and expands the application scenarios of the semiconductor device 100.

[0455] In some embodiments, the length of the dummy gate trench portion 221 in the first direction is greater than the length of the gate trench portion 211 in the first direction, and both ends of the dummy gate trench portion 221 in the first direction protrude beyond both ends of the gate trench portion 211 in the first direction. In some embodiments, when the length of the dummy gate trench portion 221 of the semiconductor device 100 in the first direction is greater than the length of the gate trench portion 211 in the first direction, and both ends of the dummy gate trench portion 221 in the first direction protrude beyond both ends of the gate trench portion 211 in the first direction, the connecting trench portion 214 may be separately provided within each gate trench group 21, and the connecting trench portion 214 may be separately provided between a plurality of dummy gate trench portions 221 between two adjacent gate trench groups 21, so as to prevent the two from affecting each other and ensure the electrostatic protection ability and insulation breakdown withstand voltage ability of the semiconductor device 100.

[0456] Combined Fig.80 and Fig.81 As shown, both the main trench portion 213 and the connecting trench portion 214 extend in the direction from the first main surface 81 towards the second main surface 82. In the direction from the first main surface 81 to the second main surface 82, the depth of the main trench portion 213 is L1, and the depth of the connecting trench portion 214 is L2, and L1 and L2 satisfy the relationship: L1 ≤ L2.

[0457] In some embodiments, by setting the depth of the connecting trench portion 214 to be not less than the depth of the main trench portion 213 in the direction from the first main surface 81 to the second main surface 82, in the direction from the first main surface 81 to the second main surface 82, the connecting trench portion 214 can completely connect the main trench portion 213, avoiding insufficient depth of the connecting trench portion 214 and the failure of the lower part of the main trench portion 213 to communicate with the connecting trench portion 214, resulting in uneven electric field distribution under the main trench portion 213 and the easy failure of the electrostatic protection of the semiconductor device 100. In this way, it is possible to ensure the optimization of the electric field at each position at the end of the main trench portion 213, and improve the electrostatic protection ability of the semiconductor device 100 in some embodiments.

[0458] Combined with Fig.80 and Fig.81 As shown, the width of the main groove portion 213 in the second direction is W1, and the width of the connecting groove portion 214 in the first direction is W2. W1 and W2 satisfy the relation: W1 ≤ W2.

[0459] In some embodiments, the width of the connecting groove portion 214 in the first direction can affect the passage size of the connecting groove portion 214. By setting the width of the connecting groove portion 214 in the first direction to be not less than the width of the main groove portion 213 in the second direction, on the premise of increasing the gate passage through the connecting groove portion 214, the passage capacity of the connecting groove portion 214 can be increased in some embodiments, so that the turn-on speed of the semiconductor device 100 can be increased in some embodiments, and the loss of the semiconductor device 100 can be reduced.

[0460] In some embodiments, in the direction from the first main surface 81 to the second main surface 82, the depth of the connecting groove portion 214 can be set to be the same as the depth of the main groove portion 213, and the width of the connecting groove portion 214 in the first direction can be set to be the same as the width of the main groove portion 213 in the second direction. In this way, on the premise of improving the electrostatic protection ability of the semiconductor device 100 and the switching speed of the semiconductor device 100, it is convenient to synchronously etch the main groove portion 213 and the connecting groove portion 214, and the structures are the same or almost the same, so that the processing complexity can be reduced and the production efficiency can be improved.

[0461] Combined with Fig.80 and Figure 81 As shown, both the main groove portion 213 and the connecting groove portion 214 are spaced apart from the drift layer 10. In some embodiments, the main groove portion 213 and the connecting groove portion 214 are etched and formed on the ring layer 107. By making both the main groove portion 213 and the connecting groove portion 214 spaced apart from the drift layer 10, that is, making the main groove portion 213 and the connecting groove portion 214 not penetrate the ring layer 107, and the main groove portion 213 and the connecting groove portion 214 are spaced apart from the drift layer 10, this can ensure that there is a field ring layer 107 between the main groove portion 213 and the connecting groove portion 214 and the drift layer 10, and the electrical performance of the semiconductor device 100 can be ensured.

[0462] Combined with Figure 77 and Figure 78 As shown, the semiconductor substrate 810 may include an active region 101 and a terminal region 103. The terminal region 103 is disposed around the outside of the active region 101. The main groove portion 213 is disposed in the active region 101, and the connecting groove portion 214 is located between the active region 101 and the terminal region 103.

[0463] In some embodiments, the active region 101 can bear most of the forward current during forward conduction and can also bear a high blocking voltage when a reverse voltage is applied. When a reverse voltage is applied to the semiconductor device 100, the terminal region 103 can relieve the electric field crowding at the edge of the active region 101, thereby achieving the purpose of increasing the reverse breakdown voltage of the semiconductor device 100.

[0464] In some embodiments, the main trench portion 213 is disposed in the active region 101. The end of the main trench portion 213 is located between the active region 101 and the terminal region 103. By disposing the connecting trench portion 214 between the active region 101 and the terminal region 103, the connecting trench portion 214 can block the diffusion of the electric field in the active region 101, and can more effectively and reliably avoid the failure of electrostatic protection in the region between the active region 101 and the terminal region 103, thereby improving the electrostatic protection ability of the semiconductor device 100.

[0465] The following combines Figures 83 - 86 The preparation method of the semiconductor device 100 will be described by way of example and includes the following steps:

[0466] Step 1, as Figure 83 shown, a substrate 2 is provided. The substrate 2 is an N-type drift layer 10, and a P-type dopant is implanted on the substrate 2 to form an N-type drift layer 10 and a P-type ring layer 107.

[0467] Step 2, as Figure 84 shown, a connecting trench portion 214 is etched in the ring layer 107, and an oxide insulating layer 70 is grown above the ring layer 107.

[0468] Step 3, as Figure 85 shown, polysilicon 71 is deposited and polysilicon is etched above the oxide insulating layer 70 to form a polysilicon layer 111.

[0469] Step 4, as Figure 86 shown, an interlayer dielectric is grown above the polysilicon layer 111 to form an interlayer dielectric layer 1304. Metal sputtering is performed above the interlayer dielectric layer 1304 to form an emitter metal layer 14, and a field stop layer 15, a collector layer 16, and a collector metal layer 18 are prepared below the drift layer 10, and finally the semiconductor device 100 is formed.

[0470] It should be noted that this preparation method only takes the preparation of the connecting trench portion 214 as an example. When the connecting trench portion 214 is etched on the ring layer 107, the main trench portion 213 can be etched synchronously, which will not be elaborated here. In addition, this preparation method only illustrates a part of the preparation process. The other compositions and operations of the semiconductor device 100 according to some embodiments of the present disclosure are known to those of ordinary skill in the art, and will not be described in detail here.

[0471] Reference is made below to Figures 87 - 98 Describe the semiconductor device 100 according to some embodiments of the present disclosure. The semiconductor device 100 may be an RC-IGBT. In the following description, N and P represent the conduction types of semiconductors. In the present disclosure, the first conduction type is set to N-type and the second conduction type is set to P-type for description.

[0472] Combined with Figures 87 - 91 As shown, the semiconductor device 100 according to the present disclosure may mainly include: a substrate 80, a drift layer 10 of the first conduction type, a first trench 20, and a second trench 30.

[0473] In some embodiments, the drift layer 10 of the first conduction type is disposed within the substrate 80 and between a first main surface 81 and a second main surface 82. A well layer 11 of the second conduction type is further disposed within the substrate 80. The well layer 11 is disposed on a side of the drift layer 10 close to the first main surface 81. An emitter layer 3 of the first conduction type is further disposed within the well layer 11. In addition, a field stop layer 15 of the first conduction type is disposed within the substrate 80. The field stop layer 15 is disposed on a side of the drift layer 10 close to the second main surface 82. A collector layer 16 of the second conduction type and a short-circuit region 112 of the first conduction type are disposed on a side of the field stop layer 15 close to the second main surface 82. Further, a dielectric layer 13 is disposed on the first main surface 81. An emitter metal layer 14 is disposed on a side of the dielectric layer 13 away from the first main surface 81. A collector metal layer 18 is further disposed on the side of the second main surface 82 of the substrate 80.

[0474] Among them, the semiconductor device 100 may include an active region 101 and a termination region 103 disposed outside the active region 101. Both the collector layer 16 and the short-circuit region 112 are located in the active region 101. The emitter metal layer 14 can not only be used as an emitter lead-out terminal for the region corresponding to the collector layer 16, but also be used as an anode lead-out terminal for the region corresponding to the short-circuit region 112. The collector metal layer 18 can not only be used as a collector lead-out terminal for the region corresponding to the collector layer 16, but also be used as a cathode lead-out terminal for the region corresponding to the short-circuit region 112. In this way, the region corresponding to the collector layer 16 can achieve forward conduction of the semiconductor device 100, and the region corresponding to the short-circuit region 112 can achieve reverse conduction of the semiconductor device 100, enabling the semiconductor device 100 to have both forward conduction and reverse conduction characteristics.

[0475] In some embodiments, the first trench 20 is located in the region corresponding to the collector layer 16. The first trench 20 extends from the first main surface 81 towards the second main surface 82 and reaches the drift layer 10, and the first trench 20 extends in the first direction. By setting the first trench 20 as multiple ones, the multiple first trenches 20 are spaced in the second direction, and an oxide insulating layer 70 and a polysilicon 71 are sequentially disposed in the first trench 20, so as to ensure the normal operation of the region corresponding to the collector layer 16 and even the semiconductor device 100.

[0476] Moreover, a part of the multiple first trenches 20 are first spacer trenches 23. The first spacer trenches 23 are multiple. The first spacer trenches 23 mainly include a first sub-trench 231 and a second sub-trench 212 that are spaced in the first direction. And the second trench 30 extends from the first main surface 81 towards the second main surface 82 and reaches the drift layer 10. The second trench 30 extends in the first direction, and the second trench 30 is at least partially located in the region corresponding to the short-circuit region 112.

[0477] Define the region where the multiple first trenches 20 are located as the insulated gate bipolar transistor region 1015, and the region where the multiple second trenches 30 are located as the fast recovery diode region 1018. By setting the second trenches 30 as multiple ones and corresponding to the multiple first spacer trenches 23 one by one, not only can the junction depth and doping concentration of the well layer 11 in the insulated gate bipolar transistor region 1015 and the fast recovery diode region 1018 be the same, ensuring the same breakdown voltage for the two regions, but also the process steps of the semiconductor device 100 can be simplified, and the manufacturing process of the semiconductor device 100 can be streamlined.

[0478] Moreover, by spacing the second trench 30 between the first sub-trench 231 and the second sub-trench 212, the insulated gate bipolar transistor region 1015 and the fast recovery diode region 1018 can be disconnected, thereby disconnecting the region corresponding to the short-circuit region 112 and the region corresponding to the collector layer 16, so as to ensure the performance of each of the two regions and the operating performance of the semiconductor device 100.

[0479] Combined with Figures 89 - 91 As shown, the semiconductor device 100 may further include a first connection trench 40. The first connection trench 40 extends from the first main surface 81 towards the second main surface 82 and reaches the drift layer 10. The first connection trench 40 extends in the second direction. There are two first connection trenches 40. One of the two first connection trenches 40 connects one end of the multiple second trenches 30, and the other connects the other end of the multiple second trenches 30.

[0480] In some embodiments, one ends of the plurality of second grooves 30 are flush with each other, and the other ends of the plurality of second grooves 30 are flush with each other. By providing the first connection groove 40, the first connection groove 40 extends from the first main surface 81 towards the second main surface 82 and reaches the drift layer 10. The first connection groove 40 is arranged to extend in the second direction, and two first connection grooves 40 are provided. In this way, while one of the two first connection grooves 40 extends in the second direction, it can connect one ends of the plurality of second grooves 30, and while the other of the two first connection grooves 40 extends in the second direction, it can connect the other ends of the plurality of second grooves 30. Thus, the two first connection grooves 40 can enclose the plurality of second grooves 30, that is, the two first connection grooves 40 can separate the insulated gate bipolar transistor region 1015 and the fast recovery diode region 1018, thereby preventing the insulated gate bipolar transistor region 1015 and the fast recovery diode region 1018 from interfering with each other in the manufacturing process, ensuring the respective performances of the two regions, ensuring the working performance of the semiconductor device 100, and improving the reliability of the semiconductor device 100.

[0481] Thus, by connecting one ends of the plurality of second grooves 30 with one of the two first connection grooves 40 and connecting the other ends of the plurality of second grooves 30 with the other of the two first connection grooves 40, the first connection groove 40 can enclose the plurality of second grooves 30, separate the insulated gate bipolar transistor region 1015 and the fast recovery diode region 1018, prevent the insulated gate bipolar transistor region 1015 and the fast recovery diode region 1018 from interfering with each other in the manufacturing process, ensure the respective performances of the two regions, and ensure the reliability of the semiconductor device 100.

[0482] In some embodiments, in combination with Figure 89 As shown, one of the plurality of second grooves 30 adjacent to the first groove 20 on one side in the second direction is defined as the first boundary groove 361, and one of the plurality of second grooves 30 adjacent to the first groove 20 on the other side in the second direction is defined as the second boundary groove 362. Thus, the region enclosed by the first boundary groove 361, the second boundary groove 362 and the two first connection grooves 40 is the fast recovery diode region 1018. The two first connection grooves 40 can serve as the boundaries of the fast recovery diode region 1018 in the first direction, thereby realizing the enclosure of the fast recovery diode region 1018, preventing the insulated gate bipolar transistor region 1015 and the fast recovery diode region 1018 from interfering with each other in the manufacturing process, ensuring the respective performances of the two regions, and ensuring the reliability of the semiconductor device 100.

[0483] In combination with Figure 87As shown, one of the two first connection grooves 40 corresponding to the first sub-groove 231 is arranged at an interval from the first sub-groove 231, and one of the two first connection grooves 40 corresponding to the second sub-groove 212 is arranged at an interval from the second sub-groove 212. With such an arrangement, the first connection groove 40 can be spaced apart from the insulated gate bipolar transistor region 1015, so that the insulated gate bipolar transistor region 1015 and the fast recovery diode region 1018 can be spaced apart. In some embodiments, it is ensured that the insulated gate bipolar transistor region 1015 and the fast recovery diode region 1018 can be separated, which can more reliably prevent the insulated gate bipolar transistor region 1015 and the fast recovery diode region 1018 from interfering with each other in the manufacturing process, ensure the performance of each of the two regions, and ensure the structural reliability of the semiconductor device 100.

[0484] Combined with Figure 89 and Figure 90 As shown, the semiconductor device 100 may further include a second connection groove 50. The second connection groove 50 extends from the first main surface 81 towards the second main surface 82 and reaches the drift layer 10, and is arranged to extend in the second direction. There are two second connection grooves 50. One of the two second connection grooves 50 connects one end of the plurality of first sub-grooves 231 adjacent to the second groove 30, and the other connects one end of the plurality of second sub-grooves 212 adjacent to the second groove 30.

[0485] In some embodiments, since the second groove 30 is arranged at an interval between the first sub-groove 231 and the second sub-groove 212, that is: one end of the first sub-groove 231 adjacent to the second groove 30 exists, one end of the second sub-groove 212 adjacent to the second groove 30 exists, and one ends of the plurality of first sub-grooves 231 adjacent to the second groove 30 are flush with each other, and one ends of the plurality of second sub-grooves 212 adjacent to the second groove 30 are flush with each other.

[0486] By providing two second connection grooves 50, the second connection grooves 50 extend from the surface of the drift layer 10 towards the inside of the drift layer 10, and the second connection grooves 50 are arranged to extend in the second direction. In this way, while one of the two second connection grooves 50 extends in the second direction, it can connect one ends of the plurality of first sub-grooves 231 adjacent to the second groove 30, and while the other of the two second connection grooves 50 extends in the second direction, it can connect one ends of the plurality of second sub-grooves 212 adjacent to the second groove 30, so that the first sub-grooves 231 of the insulated gate bipolar transistor region 1015 can be connected, and the second sub-grooves 212 of the insulated gate bipolar transistor region 1015 can be connected, and thus the normal operation of the insulated gate bipolar transistor region 1015 can be ensured.

[0487] Combined with Figure 88 and Figure 89As shown, a plurality of first trenches 20 may include a first main trench 24 and a plurality of first spaced trenches 23. The first main trenches 24 are multiple and are respectively located on both sides of the plurality of first spaced trenches 23 in the second direction. The two ends of the second connection trench 50 in the second direction are respectively connected to the first main trenches 24 on both sides.

[0488] In some embodiments, one of the plurality of first main trenches 24 adjacent to one side of the plurality of first spaced trenches 23 in the second direction is a third boundary trench 241, and one of the plurality of first main trenches 24 adjacent to the other side of the plurality of first spaced trenches 23 in the second direction is a fourth boundary trench 242. The region outside the area surrounded by the third boundary trench 241, the fourth boundary trench 242, and the two second connection trenches 50 is an insulated gate bipolar transistor region 1015, and the region inside the area surrounded by the third boundary trench 241, the fourth boundary trench 242, and the two second connection trenches 50 is a fast recovery diode region 1018.

[0489] Specifically, define one of the plurality of first main trenches 24 adjacent to one side of the plurality of first spaced trenches 23 in the second direction as the third boundary trench 241, and one of the plurality of first main trenches 24 adjacent to the other side of the plurality of first spaced trenches 23 in the second direction as the fourth boundary trench 242. By connecting the two ends of the second connection trench 50 in the second direction to the first main trenches 24 on both sides respectively, that is: connecting the two ends of the second connection trench 50 in the second direction to the third boundary trench 241 and the fourth boundary trench 242 respectively.

[0490] On the one hand, the plurality of first spaced trenches 23 and the first main trench 24 can be connected through the second connection trench 50, thereby ensuring the normal operation of the insulated gate bipolar transistor region 1015 and even the semiconductor device 100.

[0491] On the other hand, the region outside the area surrounded by the third boundary trench 241, the fourth boundary trench 242, and the two second connection trenches 50 is the insulated gate bipolar transistor region 1015. In this way, the two second connection trenches 50 can serve as the boundary of the insulated gate bipolar transistor region 1015 in the first direction, and can better separate the insulated gate bipolar transistor region 1015 and the fast recovery diode region 1018, thereby preventing the mutual interference between the insulated gate bipolar transistor region 1015 and the fast recovery diode region 1018 in the manufacturing process in some embodiments and improving the reliability of the semiconductor device 100.

[0492] Combined Figure 89As shown, a part of the second trench 30 is a second spacer trench 35. The second spacer trench 35 may mainly include a third sub-trench 351, a fourth sub-trench 352, and a fifth sub-trench 353. The third sub-trench 351 and the fifth sub-trench 353 are respectively disposed at two ends of the fourth sub-trench 352 in a first direction and are respectively spaced apart from the fourth sub-trench 352.

[0493] In some embodiments, by respectively disposing the third sub-trench 351 and the fifth sub-trench 353 at two ends of the fourth sub-trench 352 in the first direction and respectively spacing them from the fourth sub-trench 352, the fast recovery diode region 1018 can be divided. The fourth sub-trench 352 is located in the region corresponding to the short-circuit region 112. The region corresponding to the short-circuit region 112 is defined as the fast recovery diode main conduction region 1016, thereby avoiding mutual interference between the insulated gate bipolar transistor region 1015 and the fast recovery diode main conduction region 1016 during the manufacturing process and ensuring the respective performances of the insulated gate bipolar transistor region 1015 and the fast recovery diode main conduction region 1016.

[0494] Combined Figure 89 and Figure 90 As shown, the semiconductor device 100 may further include a third connection trench 113. The third connection trench 113 extends from the first main surface 81 towards the second main surface 82 and reaches the drift layer 10, and is disposed to extend in a second direction. There are two third connection trenches 113. One of the two third connection trenches 113 connects one end of a plurality of fourth sub-trenches 352, and the other connects the other end of the plurality of fourth sub-trenches 352.

[0495] In some embodiments, one ends of the plurality of fourth sub-trenches 352 are flush with each other, and the other ends of the plurality of fourth sub-trenches 352 are flush with each other. By providing the third connection trench 113, one of the two third connection trenches 113 can connect one ends of the plurality of fourth sub-trenches 352 while extending in the second direction, and the other of the two third connection trenches 113 can connect the other ends of the plurality of fourth sub-trenches 352 while extending in the second direction.

[0496] In this way, not only can multiple fourth sub-grooves 352 be connected to ensure the normal operation of the main conduction region 1016 of the fast recovery diode, but also multiple fourth sub-grooves 352 can be enclosed, that is, two third connection grooves 113 can enclose the main conduction region 1016 of the fast recovery diode. Thus, in some embodiments, the main conduction region 1016 of the fast recovery diode and the insulated gate bipolar transistor region 1015 can be separated, more effectively and reliably avoiding mutual interference between the main conduction region 1016 of the fast recovery diode and the insulated gate bipolar transistor region 1015 during the manufacturing process, ensuring the performance of each of the two regions, and ensuring the operating performance of the semiconductor device 100.

[0497] In some embodiments, as shown in Figure 88 and Figure 89 , one of the two third connection grooves 113 connects one end of multiple third sub-grooves 351 adjacent to the fourth sub-groove 352, and the other connects one end of multiple fifth sub-grooves 353 adjacent to the fourth sub-groove 352.

[0498] In some embodiments, since the third sub-groove 351, the fourth sub-groove 352, and the fifth sub-groove 353 are sequentially spaced in the first direction, one end of the third sub-groove 351 adjacent to the fourth sub-groove 352 exists, and one end of the fifth sub-groove 353 adjacent to the fourth sub-groove 352 exists. Moreover, one ends of multiple third sub-grooves 351 adjacent to the fourth sub-groove 352 are flush with each other, and one ends of multiple fifth sub-grooves 353 adjacent to the fourth sub-groove 352 are flush with each other.

[0499] By making one of the two third connection grooves 113 extend in the second direction while connecting one end of multiple third sub-grooves 351 adjacent to the fourth sub-groove 352, and making the other of the two third connection grooves 113 extend in the second direction while connecting one end of multiple fifth sub-grooves 353 adjacent to the fourth sub-groove 352, multiple third sub-grooves 351 can be connected and multiple fifth sub-grooves 353 can be connected, thereby avoiding interference between the manufacturing processes of the insulated gate bipolar transistor region 1015 and the main conduction region 1016 of the fast recovery diode.

[0500] In some embodiments, two of the fourth sub-grooves 352 defined on both sides of the second direction of the plurality of fourth sub-grooves 352 are respectively defined as a fifth boundary groove 3521 and a sixth boundary groove 3522. In this way, the fifth boundary groove 3521, the sixth boundary groove 3522, and the two third connection grooves 113 are all located within the fast recovery diode region 1018. The region enclosed by the fifth boundary groove 3521, the sixth boundary groove 3522, and the two third connection grooves 113 is the fast recovery diode main conduction region 1016. The part of the fast recovery diode region 1018 located outside the fast recovery diode main conduction region 1016 is the fast recovery diode transition region 1017.

[0501] As described above, the active region 101 of the semiconductor device 100 can include: an insulated gate bipolar transistor region 1015, a fast recovery diode main conduction region 1016, and a fast recovery diode transition region 1017. The first connection groove 40, the third connection groove 113, and the fast recovery diode transition region 1017 can jointly function to separate the insulated gate bipolar transistor region 1015 and the fast recovery diode main conduction region 1016, thereby more effectively and reliably avoiding mutual interference between the insulated gate bipolar transistor region 1015 and the fast recovery diode main conduction region 1016 during the manufacturing process, ensuring the performance of the insulated gate bipolar transistor region 1015 and the fast recovery diode main conduction region 1016, and further improving the reliability of the semiconductor device 100.

[0502] Combined Figure 91 As shown, the dielectric layer 13 can mainly include a first dielectric layer 1305 and a second dielectric layer 1306. The first dielectric layer 1305 corresponds to the insulated gate bipolar transistor region 1015 and the fast recovery diode main conduction region 1016. The second dielectric layer 1306 corresponds to the fast recovery diode transition region 1017. A plurality of spaced contact holes 171 are formed in the first dielectric layer 1305. The emitter metal layer 14 passes through the contact holes 171 and contacts the first main surface 81. The second dielectric layer 1306 is a continuous layer body and blocks between the emitter metal layer 14 and the first main surface 81.

[0503] In some embodiments, the dielectric layer 13 can protect the well layer 11, reducing the risk of damage to the semiconductor device 100. By making the first dielectric layer 1305 correspond to the insulated gate bipolar transistor region 1015 and the fast recovery diode main conduction region 1016, and forming a plurality of spaced contact holes 171 in the first dielectric layer 1305, the emitter metal layer 14 can pass through the contact holes 171 to contact the emitter metal layer 14 or the well layer 11 on the first main surface 81, ensuring the normal extraction of the current in the insulated gate bipolar transistor region 1015 and the fast recovery diode main conduction region 1016, and ensuring the normal operation of the insulated gate bipolar transistor region 1015 and the fast recovery diode main conduction region 1016.

[0504] In some embodiments, by making the second dielectric layer 1306 correspond to the fast recovery diode transition region 1017 and setting the second dielectric layer 1306 as a continuous layer body, the dielectric layer 13 can be blocked between the emitter metal layer 14 and the first main surface 81, so that the dielectric layer 13 can provide more reliable protection for the first main surface 81 of the transition region 102, improving the structural reliability of the fast recovery diode transition region 1017.

[0505] Combined Figure 89 As shown, at least a part of one of the two first connection trenches 40 connects one end of the third sub-trench 351 far from the fourth sub-trench 352, and at least a part of the other of the two first connection trenches 40 connects one end of the fifth sub-trench 353 far from the fourth sub-trench 352.

[0506] In some embodiments, the second trench 30 may mainly include: a second main trench 36 and a second spacer trench 35. There are a plurality of second main trenches 36, which are respectively located on both sides of the second direction of the plurality of second spacer trenches 35. One end of the plurality of second main trenches 36 is flush with one end of the third sub-trench 351 far from the fourth sub-trench 352, and the other end of the plurality of second main trenches 36 is flush with one end of the fifth sub-trench 353 far from the fourth sub-trench 352.

[0507] By connecting one of the two first connection grooves 40 to one end of the plurality of second grooves 30 and the other to the other end of the plurality of second grooves 30, that is: when one of the two first connection grooves 40 extends in the second direction, at least a part of it connects the ends of the plurality of third sub-grooves 351 away from the fourth sub-groove 352, and another part of it connects one end of the plurality of second main grooves 36; when the other of the two first connection grooves 40 extends in the second direction, at least a part of it connects the ends of the plurality of fifth sub-grooves 353 away from the fourth sub-groove 352, and another part of it connects the other end of the plurality of second main grooves 36. Thus, it can ensure the enclosure of the fast recovery diode main conduction region 1016 and the transition region 102 by the first connection groove 40, and ensure the working performance of the semiconductor device 100.

[0508] It should be noted that the processes in the first groove 20, the second groove 30, the first connection groove 40, the second connection groove 50 and the third connection groove 113 are the same. An oxide insulating layer 70 can be generated inside them and polysilicon 71 can be deposited, and the widths and depths of the first groove 20, the second groove 30, the first connection groove 40, the second connection groove 50 and the third connection groove 113 can be set to be the same, so that the first groove 20, the second groove 30, the first connection groove 40, the second connection groove 50 and the third connection groove 113 can be etched synchronously, which can simplify the process steps of the semiconductor device 100.

[0509] Combined with Figure 90 As shown, the spacing distance between the first connection groove 40 and the second connection groove 50 in the first direction is D9, and the spacing distance between the first connection groove 40 and the third connection groove 113 in the first direction is D10. D9 and D10 satisfy the relationship: D9 < D10.

[0510] In some embodiments, the second connection groove 50 is located between the insulated gate bipolar transistor region 1015 and the fast recovery diode transition region 1017, the third connection groove 113 is located between the fast recovery diode transition region 1017 and the fast recovery diode main conduction region 1016, and the first connection groove 40 is located in the fast recovery diode transition region 1017 and between the second connection groove 50 and the third connection groove 113.

[0511] By setting the spacing distance between the first connection trench 40 and the second connection trench 50 in the first direction to be the same as the spacing distance between the multiple first trenches 20 in the second direction, the manufacturing of the first connection trench 40 and the second connection trench 50 can be facilitated. And by setting the spacing distance between the first connection trench 40 and the second connection trench 50 in the first direction to be less than the spacing distance between the first connection trench 40 and the third connection trench 113 in the first direction, the area of the fast recovery diode transition region 1017 can be increased, and the separation effect on the insulated gate bipolar transistor region 1015 and the fast recovery diode main conduction region 1016 can be enhanced.

[0512] In some embodiments, D10 satisfies the relationship: D10≥30μm. In some embodiments, the spacing distance between the first connection trench 40 and the third connection trench 113 in the first direction is set to be not less than 30μm, so that the area of the fast recovery diode transition region 1017 can be set within a reasonable range, avoiding the area of the fast recovery diode transition region 1017 being too small, thereby more effectively and reliably separating the insulated gate bipolar transistor region 1015 and the fast recovery diode main conduction region 1016, avoiding mutual interference in the manufacturing processes of the two regions, ensuring the performance of each of the two regions, and enhancing the reliability of the semiconductor device 100.

[0513] It should be noted that the larger the spacing distance between the first connection trench 40 and the third connection trench 113 in the first direction, the better the separation effect on the insulated gate bipolar transistor region 1015 and the fast recovery diode main conduction region 1016. However, at the same time, it will also cause an increase in the overall area of the semiconductor device 100. Therefore, in actual production, the spacing distance between the first connection trench 40 and the third connection trench 113 in the first direction can be selected according to the actual application scenario and requirements to achieve a balance between the separation effect of the insulated gate bipolar transistor region 1015 and the fast recovery diode main conduction region 1016 and the overall area of the semiconductor device 100.

[0514] The following Figures 92 - 98 describes the manufacturing method of the semiconductor device 100 by way of example. The semiconductor device 100 is an RC-IGBT and includes the following steps:

[0515] Step 1, as Figure 92 shown, provide the N-substrate 2 material. Form structure 1.

[0516] Step 2, as Figure 93As shown, on the basis of Structure 1, the first trench 20, the second trench 30, the first connection trench 40, the second connection trench 50 and the third connection trench 113 are etched, and an oxide insulating layer 70 is grown in the first trench 20, the second trench 30, the first connection trench 40, the second connection trench 50 and the third connection trench 113. Structure 2 is formed.

[0517] Step 3, as Figure 94 shown, on the basis of Structure 2, polysilicon 71 is deposited. Structure 3 is formed.

[0518] Step 4, as Figure 95 shown, on the basis of Structure 3, the polysilicon 71 is etched to form Structure 4.

[0519] Step 5, as Figure 96 shown, on the basis of Structure 4, a P-well layer 11 and an N+ emitter layer 3 are sequentially implanted to form Structure 5.

[0520] Step 6, as Figure 97 shown, on the basis of Structure 5, a dielectric layer 13 is deposited, and a contact hole 171 is etched in the dielectric layer 13 to form Structure 6.

[0521] Step 7, as Figure 98 shown, on the basis of Structure 6, emitter metal layer 14 is prepared by sputtering a metal layer, and backside N+ field stop layer 15 implantation, backside P+ collector layer 16 implantation, backside FRD region N+ short circuit region 112 implantation, laser annealing, and backside metal sputtering to prepare collector metal layer 18 are sequentially performed. Finally, a semiconductor device 100 such as Structure 7 is formed.

[0522] Next, refer to Figures 99 - 108 to describe the semiconductor device 100 according to some embodiments of the present disclosure. The semiconductor device 100 may be an RC-IGBT. In the following description, N and P represent the conduction types of semiconductors. In the present disclosure, the first conduction type is set as N-type and the second conduction type is set as P-type for description.

[0523] Combined with Figures 99 - 101 shown, the semiconductor device 100 according to the present disclosure may mainly include: a substrate 80, a drift layer 10 of the first conduction type, a first trench 20 and a second trench 30.

[0524] In some embodiments, a drift layer 10 of a first conductivity type is disposed within a substrate 80 and is located between a first main surface 81 and a second main surface 82. A well layer 11 of a second conductivity type is also disposed within the substrate 80. The well layer 11 is disposed on a side of the drift layer 10 close to the first main surface 81. A second emitter layer 12 of the first conductivity type is further disposed within the well layer 11. In addition, a field stop layer 15 of the first conductivity type is disposed within the substrate 80. The field stop layer 15 is disposed on a side of the drift layer 10 close to the second main surface 82. A collector layer 16 of the second conductivity type and a first emitter layer 17 of the first conductivity type are disposed on a side of the field stop layer 15 close to the second main surface 82. Further, a dielectric layer 13 is disposed on the first main surface 81. An emitter metal layer 14 is disposed on a side of the dielectric layer 13 facing away from the first main surface 81. A collector metal layer 18 is further disposed on the second main surface 82 side of the substrate 80. Thus, a basic structure of the semiconductor device 100 can be formed.

[0525] Among them, the semiconductor device 100 may include an active region 101 and a terminal region 103 disposed outside the active region 101. The region corresponding to the collector layer 16 is an insulated gate bipolar transistor region 1015, and the region corresponding to the first emitter layer 17 is a fast recovery diode region 1018. That is, the active region 101 of the semiconductor device 100 may include an insulated gate bipolar transistor region 1015 and a fast recovery diode region 1018. The emitter metal layer 14 can not only serve as an emitter lead-out terminal of the insulated gate bipolar transistor region 1015, but also serve as an anode lead-out terminal of the fast recovery diode region 1018. The collector metal layer 18 can not only serve as a collector lead-out terminal of the insulated gate bipolar transistor region 1015, but also serve as a cathode lead-out terminal of the fast recovery diode region 1018. Thus, the insulated gate bipolar transistor region 1015 can achieve forward conduction of the semiconductor device 100, and the fast recovery diode region 1018 can achieve reverse conduction of the semiconductor device 100, enabling the semiconductor device 100 to have both forward conduction and reverse conduction characteristics.

[0526] In some embodiments, a first trench 20 extends from the first main surface 81 towards the second main surface 82 and reaches the drift layer 10, and the first trench 20 extends in a first direction. By setting the first trench 20 as a plurality of trenches, the plurality of first trenches 20 are spaced apart in a second direction. Among them, some of the plurality of first trenches 20 are spaced trenches 201. The spaced trench 201 may mainly include two sub-trench portions 2011 spaced apart in the first direction. The sub-trench portion 2011 may include a plurality of gate trench groups 21 and a plurality of dummy gate trenches 223. The plurality of gate trench groups 21 are spaced apart in the second direction. At least one dummy gate trench 223 is disposed between two adjacent gate trench groups 21. The gate trench group 21 includes at least two gate trenches 2221 spaced apart in the second direction.

[0527] Specifically, an oxide insulating layer 70 is provided in both the gate trench 2221 and the dummy gate trench 223, and polysilicon 71 is deposited. Among them, second emitter layers 12 are provided on both sides of the gate trench 2221 in the second direction. The gate trench 2221 has a conductive channel 4 with current-carrying capacity and can be electrically connected to the gate to ensure the normal operation of the insulated gate bipolar transistor region 1015 and even the semiconductor device 100. However, second emitter layers 12 are not provided on both sides of the dummy gate trench 223 in the second direction, and it does not have current-carrying capacity. The dummy gate trench 223 can be electrically connected to the emitter. On the premise of ensuring the breakdown voltage capability of the semiconductor device 100, the Miller capacitance can be reduced, and the current density can be decreased, thereby improving the short-circuit capability of the semiconductor device 100.

[0528] In some embodiments, the second trench 30 extends from the first main surface 81 towards the second main surface 82 and reaches the drift layer 10. The second trench 30 is arranged to extend in the first direction. By setting the second trench 30 as multiple ones and corresponding to the multiple first spacer trenches 23 one by one, not only can the junction depth and doping concentration of the well layer 11 in the insulated gate bipolar transistor region 1015 and the fast recovery diode region 1018 be the same, ensuring the same breakdown voltage for both regions, but also the process steps of the semiconductor device 100 can be simplified. And by arranging the second trench 30 at intervals in the first direction between the two sub-trench parts 2011, the insulated gate bipolar transistor region 1015 and the fast recovery diode region 1018 can be separated, thereby ensuring the respective performance of the two regions and the working performance of the semiconductor device 100.

[0529] Combined Figures 99 - 101 As shown, the semiconductor device 100 may further include: a first connection trench 40. The first connection trench 40 extends from the first main surface 81 towards the second main surface 82 and reaches the drift layer 10. The first connection trench 40 is arranged to extend in the second direction. There are two first connection trenches 40. One of the two first connection trenches 40 connects one end of the multiple second trenches 30 in the first direction, and the other connects the other end of the multiple second trenches 30 in the first direction.

[0530] In some embodiments, one end of the multiple second trenches 30 is flush with each other, and the other end of the multiple second trenches 30 is flush with each other. By providing the first connection trench 40, the first connection trench 40 extends from the first main surface 81 towards the second main surface 82 and reaches the drift layer 10. The first connection trench 40 is arranged to extend in the second direction, and the first connection trench 40 is provided as two. In this way, one of the two first connection trenches 40 can connect one end of the multiple second trenches 30 while extending in the second direction, and the other of the two first connection trenches 40 can connect the other end of the multiple second trenches 30 while extending in the second direction.

[0531] On the one hand, the two first connection grooves 40 can enclose the plurality of second grooves 30, that is, the two first connection grooves 40 can separate the insulated gate bipolar transistor region 1015 and the fast recovery diode region 1018, thereby preventing the insulated gate bipolar transistor region 1015 and the fast recovery diode region 1018 from interfering with each other in the manufacturing process and ensuring the performance of the two regions respectively. On the other hand, the two first connection grooves 40 can increase the current-carrying capacity of the fast recovery diode region 1018. In this way, the operating performance of the semiconductor device 100 can be improved, and the reliability of the semiconductor device 100 can be enhanced.

[0532] Combined Figure 99 and Figure 100 As shown in

[0533] In some embodiments, the ends of the gate trenches 2221 in each gate trench group 21 adjacent to the second trench 30 are flush. By providing the second connection trench 50, when the second connection trench 50 extends in the second direction, it can connect the ends of the gate trenches 2221 in the gate trench group 21 adjacent to the second trench 30. Moreover, the ends of the plurality of gate trenches 2221 in two adjacent gate trench groups 21 adjacent to the second trench 30 are flush. While the second connection trench 50 connects the ends of the gate trenches 2221 in the gate trench group 21 adjacent to the second trench 30, it can continue to extend to connect the ends of two adjacent gate trench groups 21 adjacent to the second trench 30.

[0534] That is, the second connection trench 50 can connect the ends of all the gate trenches 2221 in the sub-trench part 2011 adjacent to the second trench 30, and the second connection trench 50 can enclose all the gate trenches 2221 in the sub-trench part 2011. Thus, not only can the current-carrying capacity of the insulated gate bipolar transistor region 1015 and even the semiconductor device 100 be improved, but also the ends of the gate trenches 2221 in each gate trench group 21 adjacent to the second trench 30 can be enclosed, avoiding mutual interference between the gate trench group 21 and the second trench 30 in the manufacturing process, and preventing the insulated gate bipolar transistor region 1015 and the fast recovery diode region 1018 from interfering with each other in the manufacturing process, ensuring the performance of the two regions respectively.

[0535] Thus, by connecting one of the two first connection grooves 40 to one end of the plurality of second grooves 30 in the first direction and the other to the other end of the plurality of second grooves 30 in the first direction, and connecting the second connection groove 50 to one end of the gate grooves 2221 in the gate groove group 21 adjacent to the second groove 30 and to one end of the adjacent two gate groove groups 21 adjacent to the second groove 30, not only can the interference between the insulated gate bipolar transistor region 1015 and the fast recovery diode region 1018 in the manufacturing process be prevented, ensuring the performance of each of the two regions, but also the current-carrying capacity of the semiconductor device 100 can be improved, thereby improving the operating performance of the semiconductor device 100.

[0536] Combined Figure 99 and Figure 100 As shown, one end of the gate groove 2221 adjacent to the second groove 30 protrudes from one end of the dummy gate groove 223 adjacent to the second groove 30, and the dummy gate groove 223 and the second connection groove 50 are spaced apart from each other in the first direction.

[0537] In some embodiments, one end of the gate groove 2221 adjacent to the second groove 30 protrudes from one end of the dummy gate groove 223 adjacent to the second groove 30. By also spacing one end of the dummy gate groove 223 adjacent to the second groove 30 from the second connection groove 50 in the first direction, the second connection groove 50 can space the dummy gate groove 223 from the first connection groove 40 in the first direction, thereby avoiding interference between the dummy gate groove 223 and the first connection groove 40 or the second groove 30 in the manufacturing process and preventing interference between the insulated gate bipolar transistor region 1015 and the fast recovery diode region 1018 in the manufacturing process in some embodiments, ensuring the performance of each of the two regions.

[0538] In some embodiments, the semiconductor device 100 may further include: a third connection groove 113 that extends from the first main surface 81 toward the second main surface 82 and reaches the drift layer 10. The third connection groove 113 extends in the second direction. At least two dummy gate grooves 223 are provided between adjacent two gate groove groups 21, and the third connection groove 113 connects one end of the dummy gate grooves 223 between adjacent two gate groove groups 21 adjacent to the second groove 30.

[0539] In some embodiments, when at least two dummy gate trenches 223 are provided between two adjacent gate trench groups 21, one ends of the at least two dummy gate trenches 223 between two adjacent gate trench groups 21 adjacent to the second trench 30 are flush. By providing the third connection trench 113, the third connection trench 113 extends in the second direction and is spaced from the second connection trench 50 in the second direction. In this way, while the third connection trench 113 extends in the second direction, it can connect one ends of the dummy gate trenches 223 between two adjacent gate trench groups 21 adjacent to the second trench 30. Thus, not only can all the dummy gate trenches 223 between two adjacent gate trench groups 21 be connected and the third connection trench 113 can play a role in current conduction, thereby improving the current conduction ability of the semiconductor device 100, but also it can enclose one ends of the dummy gate trenches 223 between two adjacent gate trench groups 21 adjacent to the second trench 30. In some embodiments, this can prevent interference between the insulated gate bipolar transistor region 1015 and the fast recovery diode region 1018 during the manufacturing process and ensure the working performance of the semiconductor device 100.

[0540] As shown in combination with Figure 100 , the multiple second trenches 30 may include first sub-trenches 231 and second sub-trenches 212. The multiple first sub-trenches 231 and the multiple gate trenches 2221 are in one-to-one correspondence and are spaced from each other. The multiple second sub-trenches 212 and the multiple dummy gate trenches 223 are in one-to-one correspondence and are spaced from each other. In this way, on the premise of preventing interference between the insulated gate bipolar transistor region 1015 and the fast recovery diode region 1018 during the manufacturing process, not only can the circuit distribution of the semiconductor device 100 be made more uniform, the working performance of the semiconductor device 100 can be improved, but also the first sub-trenches 231 and the corresponding gate trenches 2221 can be etched synchronously, and the second sub-trenches 212 and the corresponding dummy gate trenches 223 can be etched synchronously, which can simplify the manufacturing process of the semiconductor device 100.

[0541] It should be noted that in some other embodiments of the present disclosure, in combination with Figure 102 and Figure 103As shown in the figure, when there is no dummy gate trench 223 between two adjacent gate trench groups 21, that is, when the dummy gate trench 223 is not provided in the insulated gate bipolar transistor region 1015 and there is only the gate trench 2221, the semiconductor device 100 does not need to provide the third connection trench 113. It only needs to connect one end of the plurality of gate trenches 2221 adjacent to the second trench 30 through the second connection trench 50, and connect one end of the plurality of second trenches 30 in the first direction through one of the two first connection trenches 40 and connect the other end of the plurality of second trenches 30 in the first direction through the other first connection trench 40. This can not only prevent the insulated gate bipolar transistor region 1015 and the fast recovery diode region 1018 from interfering with each other during the manufacturing process, ensuring the performance of each of the two regions, but also increase the current-carrying capacity of the two regions and improve the working performance of the semiconductor device 100.

[0542] As defined above, the two sides of the plurality of second trenches 30 in the second direction are respectively defined as the first boundary trench 361 and the second boundary trench 362. In this way, the region enclosed by the first boundary trench 361, the second boundary trench 362 and the two first connection trenches 40 is the fast recovery diode region 1018, and the region outside the region enclosed by the first boundary trench 361, the second boundary trench 362 and the two first connection trenches 40 is the insulated gate bipolar transistor region 1015.

[0543] Considering that the first connection trench 40 is located at the junction of the fast recovery diode region 1018 and the insulated gate bipolar transistor region 1015, by arranging the first connection trench 40 and the second connection trench 50 at intervals in the first direction, not only can the insulated gate bipolar transistor region 1015 and the fast recovery diode region 1018 be separated, effectively and reliably avoiding the mutual interference between the insulated gate bipolar transistor region 1015 and the fast recovery diode region 1018 during the manufacturing process and ensuring the performance of the insulated gate bipolar transistor region 1015 and the fast recovery diode region 1018, but also the current-carrying capacity of the semiconductor device 100 can be increased and the working performance of the semiconductor device 100 can be improved.

[0544] Combined Figure 100 and Figure 101 As shown in the figure, the interval distance D11 between the first connection trench 40 and the second connection trench 50 in the first direction, the interval distance D12 between two adjacent first trenches 20 in the second direction, and the interval distance D13 between two adjacent second trenches 30 in the second direction satisfy the relationship: D11 = D12 = D13.

[0545] In some embodiments, by setting the spacing distance between the first connection trench 40 and the second connection trench 50 in the first direction, the spacing distance between two adjacent first trenches 20 in the second direction, and the spacing distance between two adjacent second trenches 30 in the second direction to be equal, the distribution of the first connection trench 40 and the second connection trench 50 can be made more uniform, the uniformity of the circuit distribution of the semiconductor device 100 can be improved, and the working performance of the semiconductor device 100 can be enhanced.

[0546] In addition, the processes in the first trench 20, the second trench 30, the first connection trench 40, the second connection trench 50, and the third connection trench 113 are the same. An oxidation insulating layer 70 can be generated inside them and polysilicon 71 can be deposited. Moreover, the widths and depths of the first trench 20, the second trench 30, the first connection trench 40, the second connection trench 50, and the third connection trench 113 can be set to be the same, so that the first trench 20, the second trench 30, the first connection trench 40, the second connection trench 50, and the third connection trench 113 can be etched synchronously, which can simplify the process steps of the semiconductor device 100.

[0547] In some embodiments, D11 satisfies the relationship: 1.5 μm ≤ D11 ≤ 2 μm. In some embodiments, by setting the spacing distance between the first connection trench 40 and the second connection trench 50 in the first direction within a reasonable range, not only can it be avoided that the spacing distance between the first connection trench 40 and the second connection trench 50 in the first direction is too small, resulting in too small a spacing distance between the insulated gate bipolar transistor region 1015 and the fast recovery diode region 1018, and thus there is still mutual interference between the insulated gate bipolar transistor region 1015 and the fast recovery diode region 1018 during the manufacturing process, but also it can be avoided that the spacing distance between the first connection trench 40 and the second connection trench 50 in the first direction is too large, resulting in too large an overall area of the semiconductor device 100. In this way, the balance between the separation effect of the insulated gate bipolar transistor region 1015 and the fast recovery diode region 1018 and the overall area of the semiconductor device 100 can be achieved, and the structural design of the semiconductor device 100 can be optimized in some embodiments, and the working performance of the semiconductor device 100 can be enhanced.

[0548] In some embodiments, D11 satisfies the relationship: 1.5 μm ≤ D11 ≤ 2 μm, so that the spacing distance between the first connection trench 40 and the second connection trench 50 in the first direction can be set within a more optimal range. Thus, the balance between the separation effect of the insulated gate bipolar transistor region 1015 and the fast recovery diode region 1018 and the overall area of the semiconductor device 100 can be ensured in some embodiments, the structural design of the semiconductor device 100 can be optimized in some embodiments, and the working performance of the semiconductor device 100 can be enhanced.

[0549] The following will describe, with reference to Figure 101 and Figures 104 - 108 as an example, the manufacturing method of the semiconductor device 100, which is an RC-IGBT, and includes the following steps:

[0550] Step 1, as shown in Figure 104 , provide the N-substrate 2 material. Form Structure 1.

[0551] Step 2, as shown in Figure 105 , etch the first trench 20, the second trench 30, the first connection trench 40, the second connection trench 50, and the third connection trench 113 on the basis of Structure 1, and grow the oxide insulating layer 70. Form Structure 2.

[0552] Step 3, Step 1, as shown in Figure 106 , deposit polysilicon 71 on the basis of Structure 2 and etch it, and then inject the P-well layer 11 and the N+ second emitter layer 12 in sequence to form Structure 3.

[0553] Step 4, as shown in Figure 107 , deposit the dielectric layer 13 on the basis of Structure 3, and etch contact holes in the dielectric layer 13 to form Structure 4.

[0554] Step 5, as shown in Figure 107 , perform sputtering of the metal layer on the basis of Structure 4 to prepare the emitter metal layer 14 to form Structure 5.

[0555] Step 6, as shown in Figure 101 , perform implantation of the backside N+ field stop layer 15, implantation of the backside P+ collector layer 16, implantation of the backside FRD region N+ first emitter layer 17, laser annealing, and sputtering of the backside metal to prepare the collector metal layer 18 on the basis of Structure 5. Finally, the semiconductor device 100 is formed.

[0556] The following will describe, with reference to Figures 107 - 118 the semiconductor device 100 according to some embodiments of the present disclosure. The semiconductor device 100 may be an RC-IGBT. In the following description, N and P represent the conduction types of semiconductors. In the present disclosure, the first conduction type is set as the N type and the second conduction type is set as the P type for description.

[0557] With reference to Figure 109 Figure 115 as shown, the semiconductor device 100 according to the present disclosure may mainly include: a substrate 80, a drift layer 10 of the first conduction type, a first trench 20, and a second trench 30.

[0558] In some embodiments, a drift layer 10 of a first conductivity type is disposed within a substrate 80 and located between a first main surface 81 and a second main surface 82. A well layer 11 of a second conductivity type is also disposed within the substrate 80. The well layer 11 is disposed on a side of the drift layer 10 close to the first main surface 81. A second emitter layer 12 of the first conductivity type is further disposed within the well layer 11. Additionally, a field stop layer 15 of the first conductivity type is disposed within the substrate 80. The field stop layer 15 is disposed on a side of the drift layer 10 close to the second main surface 82. A collector layer 16 of the second conductivity type and a first emitter layer 17 of the first conductivity type are disposed on a side of the field stop layer 15 close to the second main surface 82. Further, a dielectric layer 13 is disposed on the first main surface 81, and an emitter metal layer 14 is disposed on a side of the dielectric layer 13 facing away from the first main surface 81. A collector metal layer 18 is further disposed on the second main surface 82 of the substrate 80. Thus, the basic structure of the semiconductor device 100 can be formed.

[0559] Among them, the semiconductor device 100 may include an active region 101 and a terminal region 103 disposed outside the active region 101. The region corresponding to the collector layer 16 is an insulated gate bipolar transistor region 1015, and the region corresponding to the first emitter layer 17 is a fast recovery diode region 1018. That is, the active region 101 of the semiconductor device 100 may include an insulated gate bipolar transistor region 1015 and a fast recovery diode region 1018. The emitter metal layer 14 can not only serve as the emitter lead-out terminal of the insulated gate bipolar transistor region 1015, but also serve as the anode lead-out terminal of the fast recovery diode region 1018. The collector metal layer 18 can not only serve as the collector lead-out terminal of the insulated gate bipolar transistor region 1015, but also serve as the cathode lead-out terminal of the fast recovery diode region 1018. Thus, the insulated gate bipolar transistor region 1015 can achieve the forward conduction of the semiconductor device 100,...

Claims

1. A fast recovery diode, characterized in that, Comprising: A substrate (2) of a first conductivity type; A drift layer (10) of a first conductivity type, the drift layer (10) comprising a first concentration doped layer (210), a second concentration doped layer (220) and a third concentration doped layer (230), the first concentration doped layer (210) being disposed on the substrate (2), the second concentration doped layer (220) being disposed on a side of the first concentration doped layer (210) away from the substrate (2), the third concentration doped layer (230) being disposed on a side of the second concentration doped layer (220) away from the substrate (2), the doping concentration of the second concentration doped layer (220) being not greater than the doping concentration of the first concentration doped layer (210) and less than the doping concentration of the third concentration doped layer (230), and the doping concentration of the first concentration doped layer (210) gradually decreasing in a direction away from the substrate (2); An anode layer (300) of a second conductivity type, the anode layer (300) being disposed on a side of the third concentration doped layer (230) facing away from the substrate (2).

2. A semiconductor device, characterized in that, Comprising: A drift layer (10) of a first conductivity type; A breakdown voltage ring (25) of a second conductivity type, the breakdown voltage ring (25) being disposed on an upper surface of the drift layer (10) and corresponding to a transition region (102) of the semiconductor device (100); A dielectric layer (13), the dielectric layer (13) being disposed on an upper surface of the breakdown voltage ring (25); A metal field plate (90), the metal field plate (90) being disposed on an upper surface of the dielectric layer (13); A first polysilicon field plate (91), the first polysilicon field plate (91) being disposed on an upper surface of the breakdown voltage ring (25) and located between the dielectric layer (13) and the breakdown voltage ring (25), and the metal field plate (90) being at least partially in contact with the first polysilicon field plate (91).

3. A semiconductor device, characterized in that, Comprising: A drift layer (10) of a first conductivity type; A trench portion (2110), the trench portion (2110) extending downward from an upper surface of the drift layer (10), the trench portion (2110) extending in a first direction and being multiple, the multiple trench portions (2110) being spaced apart in a second direction and forming a gate trench group (21) and a dummy gate trench group (22), and the gate trench group (21) and the dummy gate trench group (22) being alternately disposed in the second direction; A field stop layer (15) of a first conductivity type, the field stop layer (15) being disposed on a lower surface of the drift layer (10); A collector layer (16) of a second conductivity type, the collector layer (16) being disposed on a lower surface of the field stop layer (15), and a first emitter layer (17) of a first conductivity type being disposed in the collector layer (16), the first emitter layer (17) being vertically corresponding to the dummy gate trench group (22).

4. A semiconductor device, characterized in that, Comprising: A drift layer (10) of a first conductivity type; A well layer (11) of a second conductivity type, the well layer (11) being disposed in a portion of the drift layer (10) corresponding to the transition region (102) of the semiconductor device (100), and an upper surface of the well layer (11) constituting a part of the upper surface of the drift layer (10); A field stop layer (15), the field stop layer (15) being disposed on a lower surface of the drift layer (10); A collector layer (16) of a second conductivity type, the collector layer (16) being disposed on a lower surface of the field stop layer (15), and an emitter layer (3) of a first conductivity type being disposed in the collector layer (16), the emitter layer (3) being located in a portion of the collector layer (16) corresponding to the transition region (102).

5. A semiconductor device, characterized in that, Comprising: A drift layer (10) of a first conductivity type; A field stop layer (15) of a first conductivity type, the field stop layer (15) being disposed on a lower surface of the drift layer (10); A collector layer (16) of a second conductivity type, the collector layer (16) being disposed on a lower surface of the field stop layer (15); A first emitter layer (17) of a first conductivity type, the first emitter layer (17) being disposed on a lower surface of the field stop layer (15), and the collector layer (16) being circumferentially disposed around an outer side of the first emitter layer (17); A ring layer (107) of a second conductivity type, the ring layer (107) being disposed in the drift layer (10), an upper surface of the ring layer (107) constituting at least a part of the upper surface of the drift layer (10), the ring layer (107) corresponding to a junction of the collector layer (16) and the first emitter layer (17), and a plurality of trench portions (2110) being disposed in the ring layer (107); A well layer (11) of a second conductivity type, the well layer (11) being disposed in the drift layer (10), an upper surface of the well layer (11) constituting at least a part of the upper surface of the drift layer (10), the well layer (11) being disposed on both sides of the ring layer (107) and at least partially corresponding to the collector layer (16) and the first emitter layer (17), and a plurality of trench portions (2110) being disposed in a portion of the well layer (11) corresponding to the collector layer (16).

6. A method of manufacturing a semiconductor device for manufacturing the semiconductor device (100) described in claim 5, characterized in that, Comprising: Preparing the drift layer (10); Injecting a ring layer (107) of a second conductivity type into the drift layer (10) and annealing the ring layer (107); Etching trench portions (2110) in the drift layer (10) and disposing an oxide insulating layer (70) on an upper surface of the drift layer (10); Injecting a well layer (11) of a second conductivity type into the drift layer (10) and annealing the well layer (11), wherein the well layer (11) is located on both sides of the ring layer (107).

7. A semiconductor device, characterized in that, Comprising: A drift layer (10) of a first conductivity type; A voltage withstand ring (25) of a second conductivity type, the voltage withstand ring (25) being disposed in a portion of the drift layer (10) corresponding to the terminal region (103) of the semiconductor device (100); A polysilicon field plate (8), the polysilicon field plate (8) is disposed above the surface of the breakdown voltage ring (25), and the polysilicon field plate (8) is provided with a first via hole (801); A first dielectric layer (1305), the first dielectric layer (1305) is disposed above the surface of the polysilicon field plate (8), the first dielectric layer (1305) is provided with a second via hole (1031) and a third via hole (1032), the second via hole (1031) corresponds to the first via hole (801), and the third via hole (1032) and the second via hole (1031) are spaced apart on the surface of the first dielectric layer (1305); A metal field plate (90), the metal field plate (90) is disposed above the surface of the first dielectric layer (1305), the metal field plate (90) is provided with a first electrical connection protrusion (41) and a second electrical connection protrusion (42), the first electrical connection protrusion (41) sequentially passes through the second via hole (1031) and the first via hole (801) and is electrically connected to the breakdown voltage ring (25), and the second electrical connection protrusion (42) passes through the third via hole (1032) and is electrically connected to the polysilicon field plate (8).

8. A semiconductor device, characterized in that, Comprising: A substrate (80), the substrate (80) has a first main surface (81) and a second main surface (82), and the first main surface (81) and the second main surface (82) are spaced apart from each other in a first direction; A drift layer (10) of a first conductivity type, the drift layer (10) is disposed on the substrate (80) and is located between the first main surface (81) and the second main surface (82); A well layer (11) of a second conductivity type, the well layer (11) is disposed on a part of the drift layer (10) facing the first main surface (81) corresponding to the transition region (102) of the semiconductor device (100), and a side of the well layer (11) adjacent to the first main surface (81) constitutes a part of the first main surface (81), the length of the well layer (11) extends in a second direction and the depth extends in the first direction; A base layer (109) of a second conductivity type, the base layer (109) is disposed on a side of the drift layer (10) facing the first main surface (81), the length of the base layer (109) extends in the second direction and extends from the active region (101) of the semiconductor device (100) to the transition region (102) of the semiconductor device (100), a side of the base layer (109) adjacent to the first main surface (81) constitutes a part of the first main surface (81), the depth of the base layer (109) extends in the first direction, the base layer (109) and the well layer (11) are arranged in the second direction, and the depth of the well layer (11) is greater than the depth of the base layer (109); A first trench (20) is provided in the transition region (102). The depth of the first trench (20) extends in a first direction from the first major surface (81). The length of the first trench (20) extends in a third direction. The first trench (20) is located between the well layer (11) and the base layer (109) in a second direction. Both sides of the first trench (20) in the second direction are in contact with the well layer (11) and the base layer (109) respectively. Herein, the first direction, the second direction, and the third direction are perpendicular to each other.

9. A semiconductor device, characterized in that, Comprising: A semiconductor substrate (810) having a first major surface (81) and a second major surface (82) opposite to the first major surface (81); A drift layer (10) provided in the semiconductor substrate (810) and located between the first major surface (81) and the second major surface (82); A ring layer (107) provided on a side of the drift layer (10) facing the first major surface (81). A surface of the ring layer (107) away from the drift layer (10) constitutes a part of the first major surface (81); A main trench portion (213) provided in the ring layer (107) and extending in a first direction. The main trench portion (213) includes a plurality of gate trench groups (21) and a plurality of dummy gate trench portions (221). The plurality of gate trench groups (21) are spaced apart in a second direction. At least one of the dummy gate trench portions (221) is provided between two adjacent gate trench groups (21). Each gate trench group (21) includes at least two gate trench portions (211) spaced apart in the second direction; A connection trench portion (214) provided in the ring layer (107) and extending in a second direction. The connection trench portion (214) is located at an edge of the active region (101) of the semiconductor device (100). The connection trench portion (214) connects at least one end of at least two of the gate trench portions (211) in each gate trench group (21). Herein, the first direction is perpendicular to the second direction.

10. A semiconductor device, characterized in that, Comprising: A substrate (80) having a first major surface (81) and a second major surface (82) opposite to the first major surface (81); A drift layer (10) of a first conductivity type provided between the first major surface (81) and the second major surface (82); The first trench (20) extends from the first main surface (81) towards the second main surface (82) and reaches the drift layer (10). The first trench (20) extends in a first direction and there are a plurality of them. The plurality of first trenches (20) are spaced apart in a second direction. A part of the plurality of first trenches (20) is a first spaced trench (23). The first spaced trench (23) includes a plurality of first sub-trenches (231) and second sub-trenches (212) spaced apart in the first direction. The second trench (30) extends from the first main surface (81) towards the second main surface (82) and reaches the drift layer (10). The second trench (30) extends in a first direction and there are a plurality of them. The second trenches (30) are spaced apart in the first direction between the first sub-trench (231) and the second sub-trench (212). The first connection trench (40) extends from the first main surface (81) towards the second main surface (82) and reaches the drift layer (10). The first connection trench (40) extends in a second direction. There are two first connection trenches (40). One of the two first connection trenches (40) connects one end of the plurality of second trenches (30), and the other connects the other end of the plurality of second trenches (30).

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