Forming method of semiconductor device, semiconductor device and electronic device
By forming high-concentration Ge-enriched layers on FinFET channel regions through specific processing steps, the method enhances hole mobility and transistor performance in SiGe-based three-dimensional P-type field-effect transistors, overcoming limitations of increased Ge content in SiGe channel materials.
Patent Information
- Application Number
- CN202410039225.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-01-10
- Publication Date
- 2025-07-15
AI Technical Summary
Existing three-dimensional P-type field-effect transistors using SiGe materials for channel materials face limitations in enhancing performance due to constraints such as interface state density and channel stress, leading to reduced hole mobility and increased leakage current when Ge content is increased beyond a certain threshold.
A method involving the formation of high-concentration Ge-enriched layers on the channel regions of FinFETs by removing the pseudo-gate structure and applying a sequence of atomic layer processing and wet cleaning steps to enhance Ge concentration without altering the Si1-xGex composition, followed by forming a replacement gate structure.
This approach significantly boosts hole mobility and overall transistor performance by maintaining the Si1-xGex composition while increasing Ge concentration at the channel interface, thereby improving the device's operational efficiency.
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Abstract
Description
Technical Field
[0001] The present application relates to the field of semiconductor technology, and particularly relates to a method for forming a semiconductor device, a semiconductor device, and an electronic device. Background Art
[0002] With the continuous reduction of the size of semiconductor devices, in order to reduce the short-channel effect and improve the performance of semiconductor devices, three-dimensional field-effect transistors with fin structures have emerged, such as fin field-effect transistors (FinFETs, Fin Field-Effect Transistors) and gate-all-around field-effect transistors (GAAFETs, Gate-All-Around Field-Effect Transistors).
[0003] In related technologies, considering that the SiGe material has a higher hole mobility than the silicon material, the SiGe material is often introduced to replace the silicon material as the channel material of the three-dimensional P-type field-effect transistor to achieve the purpose of improving the performance of semiconductor devices. However, the performance of the above-mentioned three-dimensional P-type field-effect transistor devices in related technologies still needs to be further improved. Summary of the Invention
[0004] In order to solve the problems of the prior art, embodiments of the present application provide a method for forming a semiconductor device, a semiconductor device, and an electronic device. The technical solutions are as follows:
[0005] On the one hand, a method for forming a semiconductor device is provided, including:
[0006] Providing a semiconductor structure, the semiconductor structure including a semiconductor substrate, a semiconductor fin formed on the semiconductor substrate, and a dummy gate structure spanning the semiconductor fin, the semiconductor fin being formed of a semiconductor material containing germanium;
[0007] Forming source / drain regions on both sides of the dummy gate structure on the semiconductor fin;
[0008] Removing the dummy gate structure to expose the fin portion region covered by the dummy gate structure;
[0009] Forming a first germanium enrichment layer on the outer surface of the fin portion region;
[0010] Forming a gate structure spanning the semiconductor fin in the fin portion region, the gate structure covering the first germanium enrichment layer on the outer surface of the fin portion region.
[0011] In an exemplary embodiment, the forming a gate structure spanning the semiconductor fin in the fin portion region includes:
[0012] Form a passivation layer covering the fin region so that the passivation layer covers the first germanium-rich layer;
[0013] Form a gate dielectric layer on the passivation layer;
[0014] Form a gate electrode across the semiconductor fin on the gate dielectric layer; the gate structure includes the gate dielectric layer and the gate electrode.
[0015] In an exemplary embodiment, forming source / drain regions on both sides of the dummy gate structure on the semiconductor fin includes:
[0016] Etch the source region adjacent to the dummy gate structure on the semiconductor fin to form a first groove;
[0017] Deposit a seed layer in the first groove, and the forming material of the seed layer is a semiconductor material containing germanium;
[0018] Form a second germanium-rich layer on the outer surface of the seed layer;
[0019] Epitaxially grow a semiconductor material layer on the seed layer to obtain an epitaxial source region; the semiconductor material layer covers the second germanium-rich layer on the outer surface of the seed layer;
[0020] Form an epitaxial drain region in the drain region adjacent to the dummy gate structure on the semiconductor fin.
[0021] In an exemplary embodiment, epitaxially growing a semiconductor material layer on the seed layer to obtain an epitaxial source region includes:
[0022] Epitaxially grow a semiconductor material layer on the seed layer; the percentage of germanium atoms in the semiconductor material layer is less than the percentage of germanium atoms in the seed layer;
[0023] Form a third germanium-rich layer on the outer surface of the semiconductor material layer;
[0024] Form a blocking layer on the semiconductor material layer to obtain the epitaxial source region; the blocking layer covers the third germanium-rich layer on the outer surface of the semiconductor material layer.
[0025] In an exemplary embodiment, the method of forming a germanium-rich layer includes: performing atomic layer processing on a semiconductor material containing germanium.
[0026] In an exemplary embodiment, the atomic layer processing includes: performing ashing treatment and wet cleaning in sequence; wherein, the ashing treatment uses a hydrogen-containing mixed gas in plasma state.
[0027] In an exemplary embodiment, the ashing-treated hydrogen-containing mixed gas is a mixed gas of nitrogen and hydrogen, and the volume ratio of hydrogen in the hydrogen-containing mixed gas is greater than or equal to 4%.
[0028] In an exemplary embodiment, the processing technology of the ashing treatment further includes: the temperature is from room temperature to 300 °C, the pressure is from 1000 mTorr to 4000 mTorr, the power of the radio frequency power supply is from 800 W to 3500 W, and the time is from 10 s to 50 s.
[0029] In an exemplary embodiment, the wet cleaning includes: sequentially cleaning with deionized water and SCI solution.
[0030] In an exemplary embodiment, after the deionized water cleaning and before the SC1 solution cleaning, it further includes: cleaning with ozone deionized water.
[0031] In an exemplary embodiment, the thickness of the formed germanium-rich layer is less than or equal to 5 angstroms.
[0032] On the other hand, a semiconductor device is provided, which is formed by using the formation method of any of the foregoing semiconductor devices, and includes:
[0033] A semiconductor substrate;
[0034] A semiconductor fin located on the semiconductor substrate; the formation material of the semiconductor fin is a semiconductor material containing germanium;
[0035] A gate structure located on the semiconductor fin; wherein, a first germanium-rich layer is formed on the outer surface of the fin portion covered by the gate structure;
[0036] Source / drain regions located on both sides of the gate structure.
[0037] In an exemplary embodiment, the source region in the source / drain region includes:
[0038] A first groove located on the semiconductor fin; the first groove is located on one side of the gate structure;
[0039] A seed layer located in the first groove; the formation material of the seed layer is a semiconductor material containing germanium, and a second germanium-rich layer is formed on the outer surface of the seed layer;
[0040] A semiconductor material layer located on the seed layer; the semiconductor material layer covers the second germanium-rich layer on the outer surface of the seed layer, and the percentage of germanium atoms in the semiconductor material layer is less than the percentage of germanium atoms in the seed layer.
[0041] In an exemplary embodiment, a third germanium-rich layer is formed on the outer surface of the semiconductor material layer;
[0042] A barrier layer is further formed on the semiconductor material layer, and the barrier layer covers the third germanium-rich layer on the outer surface of the semiconductor material layer.
[0043] In an exemplary embodiment, the thickness of the germanium-rich layer in the semiconductor device is less than or equal to 5 angstroms.
[0044] On the other hand, an electronic device is provided, and the electronic device includes a semiconductor device formed by using the formation method of any one of the foregoing semiconductor devices.
[0045] In the embodiment of the present application, by providing a semiconductor structure, the semiconductor structure includes a semiconductor substrate, a semiconductor fin containing a germanium material formed on the semiconductor substrate, and a dummy gate structure formed on the semiconductor fin. Then, source / drain regions are formed on the semiconductor fin. After that, the dummy gate structure is removed to expose the fin region covered by it, and then a high-concentration germanium-rich layer is formed on the outer surface of the fin region before forming the replacement gate structure. Then, a gate structure spanning the semiconductor fin is formed in the fin region. Since a high-concentration germanium-rich layer is formed on the surface of the channel region of the semiconductor fin, that is, the fin region covered by the dummy gate structure, the carrier (hole) mobility is greatly enhanced, and the performance of the semiconductor device is improved. Description of the Drawings
[0046] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained according to these drawings.
[0047] Figure 1 is a schematic flowchart of the formation process of the semiconductor device provided by the embodiment of the present application;
[0048] Figure 2 is a cross-sectional view of the semiconductor structure in the embodiment of the present application;
[0049] Figure 3 is a cross-sectional view along the transverse direction of the semiconductor fin during the formation process of the semiconductor device provided by the embodiment of the present application;
[0050] Figure 4 is a schematic diagram of the principle of forming a Si separation layer by ashing treatment provided by the embodiment of the present application;
[0051] Figure 5It is another cross-sectional view along the transverse direction of the semiconductor fin during the formation of the semiconductor device provided by the embodiment of the present application;
[0052] Figure 6a It is a physical Ge concentration characterization diagram of the upper fin region of the semiconductor fin without being processed by step S107;
[0053] Figure 6b It is a physical Ge concentration characterization diagram of the upper fin region of the semiconductor fin after being processed by step S107;
[0054] Figure 7 It is another cross-sectional view along the transverse direction of the semiconductor fin during the formation of the semiconductor device provided by the embodiment of the present application;
[0055] Figures 8 to 10 They are some other cross-sectional views along the transverse direction of the semiconductor fin during the formation of the semiconductor device provided by the embodiment of the present application;
[0056] Figure 11 It is another process schematic diagram of the formation process of the semiconductor device provided by the embodiment of the present application;
[0057] Figures 12a to 12d They are some cross-sectional views along the longitudinal direction of the semiconductor fin during the formation of the semiconductor device provided by the embodiment of the present application;
[0058] Figure 13 It is another process schematic diagram of the formation process of the semiconductor device provided by the embodiment of the present application;
[0059] Figures 14a to 14b They are some other cross-sectional views along the longitudinal direction of the semiconductor fin during the formation of the semiconductor device provided by the embodiment of the present application. Detailed implementation manners
[0060] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present application without creative efforts shall fall within the protection scope of the present application.
[0061] It should be noted that in the description and claims of this application and the above-mentioned drawings, terms such as "first" and "second" are used to distinguish similar objects, and do not necessarily describe specific objects or the order of precedence. It should be understood that such data used can be interchanged under appropriate circumstances so that the embodiments of this application described here can be implemented in an order other than those illustrated or described here. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or server comprising a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products or devices.
[0062] It should be understood that when an element or layer is referred to as "on", "adjacent to", "connected to" or "coupled to" another element or layer, it can be directly on, adjacent to, connected or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as "directly on", "directly adjacent to", "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although terms such as first, second, third, etc. may be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of this application, the first element, component, region, layer or part discussed below may be represented as the second element, component, region, layer or part. And when discussing the second element, component, region, layer or part, it does not necessarily mean that there is a first element, component, region, layer or part in this application.
[0063] In the related art, considering that the SiGe material has a higher hole mobility than the silicon material, the SiGe material (Si 1-x Ge x ) is often introduced to replace the silicon material as the channel material of the three-dimensional P-type field-effect transistor to achieve the purpose of improving the performance of semiconductor devices, and increasing the Ge concentration in the SiGe channel is also an important direction for improving the performance of three-dimensional P-type field-effect transistor devices.
[0064] However, due to many limitations such as the interface state density (D it ) and channel stress, the content x of Ge in Si 1-x Ge x cannot be increased without limit. For example, when Si 1-x Ge xWhen the content x of Ge in Si is greater than 75%, leakage current and a decrease in channel stress will occur, leading to a decline in device performance. That is to say, by increasing the content x of Ge in Si 1-x Ge x one cannot enjoy the advantages of device performance improvement brought by a high concentration of Ge in the channel.
[0065] In view of this, an embodiment of the present application provides a method for forming a semiconductor device. The method includes providing a semiconductor structure, which includes a semiconductor substrate, a semiconductor fin containing a germanium material formed on the semiconductor substrate, and a dummy gate structure formed on the semiconductor fin. Then, source / drain regions are formed on the semiconductor fin. After that, the dummy gate structure is removed to expose the fin region covered by it, and then a high-concentration germanium enrichment layer is formed on the outer surface of the fin region before forming a replacement gate structure. Subsequently, a gate structure spanning the semiconductor fin is formed in the fin region, so that without changing the content x of Ge in Si 1-x Ge x a high-concentration germanium enrichment layer can be formed on the surface of the channel region of the semiconductor fin, that is, the fin region covered by the dummy gate structure, greatly enhancing the carrier (hole) mobility and improving the performance of the semiconductor device, and well enjoying the advantages of device performance improvement brought by a high concentration of Ge in the channel.
[0066] Please refer to Figure 1 which shows a schematic flow chart of a method for forming a semiconductor device provided by an embodiment of the present application. The following will describe in detail the method for forming a semiconductor device provided by an embodiment of the present application in conjunction with Figures 2 to 14b this flow chart.
[0067] Refer to Figure 1 In step S101: Provide a semiconductor structure, which includes a semiconductor substrate, a semiconductor fin formed on the semiconductor substrate, and a dummy gate structure spanning the semiconductor fin. The semiconductor fin is formed of a semiconductor material containing germanium.
[0068] As Figure 2The figure shows a cross-sectional view of a semiconductor structure. The semiconductor structure 200 includes a semiconductor substrate 210, which can be a bulk semiconductor or a silicon-on-insulator (SOI) substrate, etc. It can be doped (e.g., doped with p-type dopants or n-type dopants) or undoped. Among them, the SOI substrate is a semiconductor material layer formed on an insulator layer, and the insulator layer can be, for example, a buried oxide (BOX) layer or a silicon oxide layer, etc. The insulator layer is disposed on a silicon substrate or a glass substrate. In a specific implementation, the semiconductor material of the semiconductor substrate 210 can include one or a combination of more of: silicon, germanium, compound semiconductors, and alloy semiconductors. Among them, the compound semiconductor can be one or more of silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and indium antimonide, and the alloy semiconductor can be one or more of germanium silicon, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and gallium indium arsenide phosphide.
[0069] The semiconductor substrate 210 can include regions for forming P-type field-effect transistors. Of course, it can also include regions for forming N-type field-effect transistors.
[0070] A semiconductor fin 220 is formed on the semiconductor substrate 210. The forming material of the semiconductor fin 220 is a semiconductor material containing germanium. In the embodiments of the present application, the semiconductor material containing germanium is denoted as M 1-x Ge x ,The M 1-x Ge x in has different surface empty functions of M atoms and Ge atoms, and M atoms tend to be prone to the interface of the M 1-x Ge x layer, while Ge atoms tend to diffuse in a direction away from the interface of the M 1-x Ge x layer. Exemplarily, the M in M 1-x Ge x can be silicon Si, and then the semiconductor material containing germanium is germanium silicon Si 1-x Ge x 。
[0071] Among them, the molar ratio of Ge atoms in M 1-x Ge x can be less than 60% (x < 0.6). For example, the molar ratio of Ge atoms in M 1-x Ge x can be 40% - 50% (0.4 < x < 0.5).
[0072] It can be understood that the semiconductor fin 220 can be formed in the region of the semiconductor substrate 210 for forming P-type field effect transistors. Additionally, other semiconductor fins (not shown in the figure) can also be formed on the semiconductor substrate 210. The formation material of the other semiconductor fins does not contain germanium. For example, a semiconductor fin containing silicon can be formed, and the semiconductor fin containing silicon can be formed in the region of the semiconductor substrate 210 for forming N-type field effect transistors.
[0073] As Figure 2 shown, shallow trench isolation (STI) 230 is formed between adjacent semiconductor fins in the semiconductor substrate 210. The formation material of the shallow trench isolation 230 can be an oxide, such as silicon oxide, nitride, or a combination thereof, etc.
[0074] A dummy gate structure 240 is formed on the semiconductor fin 220. The dummy gate structure 240 is used to define the position and size of the subsequently formed gate structure. The dummy gate structure 240 straddles the semiconductor fin 220 and covers a part of the top surface and a part of the sidewall surface of the semiconductor fin 220.
[0075] In a specific implementation, the dummy gate structure 240 can include a dummy gate dielectric layer 241 and a dummy gate electrode 242. The formation material of the dummy gate dielectric layer 241 includes silicon oxide (SiO2), and the formation material of the dummy gate electrode 242 can include amorphous silicon, polysilicon, or doped polysilicon.
[0076] There are various ways to form the semiconductor fin 220 on the semiconductor substrate 210. For example, the silicon substrate can be etched to form silicon fins, and the remaining unetched part of the silicon substrate serves as the semiconductor substrate 210 in the above semiconductor structure 200. An STI region is formed between adjacent silicon fins, and then one or more silicon fins on the semiconductor substrate 210 are recessed, and an epitaxial structure containing a semiconductor material containing germanium (such as germanium silicon) is epitaxially grown at the recessed position to obtain the semiconductor fin 220 in the above semiconductor structure 200. Of course, a dielectric layer can also be formed on the upper surface of the semiconductor substrate 210, trenches passing through the dielectric layer are etched, an epitaxial structure is epitaxially grown in the trenches using a semiconductor material containing germanium, and the dielectric layer can be recessed so that the epitaxial structure protrudes from the dielectric layer to form the semiconductor fin 220 in the above semiconductor structure 200.
[0077] The formation of the dummy gate structure 240 on the semiconductor fin 220 may be as follows: a dielectric layer is conformally formed on the semiconductor substrate 210, covering the semiconductor fin 220 and the STI region, and the material of the dielectric layer may include silicon oxide; an electrode layer is covered on the dielectric layer, and the material of the electrode layer may include polysilicon; a patterned mask is formed on the electrode layer, and then one or more etching processes are performed using the patterned mask as an etching mask to form the dummy gate structure 240 surrounding the semiconductor fin 220; the patterned mask may be removed after etching.
[0078] Continue to refer to Figure 1 , in step S103, source / drain regions are formed on both sides of the dummy gate structure on the semiconductor fin.
[0079] Among them, forming the source / drain regions may be epitaxially growing a semiconductor layer to form source / drain components. For the epitaxial source region, the material of the epitaxially grown semiconductor layer includes germanium silicon or germanium silicon doped with boron, and for the epitaxial drain region, the material of the epitaxially grown semiconductor layer includes silicon doped with phosphorus. In a specific implementation, the semiconductor layer may be grown by molecular beam epitaxy, chemical vapor deposition, and / or other suitable epitaxial growth processes.
[0080] Continue to refer to Figure 1 , in step S105, the dummy gate structure is removed to expose the fin region covered by the dummy gate structure.
[0081] Specifically, removing the dummy gate structure 240 includes removing the dummy gate electrode 242 and the underlying dummy gate dielectric layer 241 to expose the part of the semiconductor fin 220 covered by the dummy gate structure 240, which is referred to as the fin region in the embodiments of the present application. As Figure 3 shown in, it can be understood that this fin region will be used as the channel region of the semiconductor device subsequently.
[0082] Among them, removing the dummy gate structure 240 may include one or more etching processes, such as wet etching, dry etching, or other etching techniques.
[0083] Continue to refer to Figure 1 , in step S107, a first germanium enrichment layer is formed on the outer surface of the fin region.
[0084] In some examples, the manner of forming the first germanium enrichment layer may include: performing atomic layer splitting on the fin region.
[0085] Among them, atomic layer splitting is used to separate the M atoms of the semiconductor material M 1-x Ge x containing germanium from the Ge atoms, and due to the different surface empty functions of the M atoms and the Ge atoms, the M atoms tend to move towards M 1-x Gex For the interface of the layer, Ge atoms tend to diffuse away from M 1-x Ge x towards the direction away from the layer interface, so that M in the exposed fin region 1-x Ge x forms an M separation layer on the surface. A high-concentration Ge enrichment layer is formed under the M separation layer. Then, the M separation layer formed on the surface is removed to expose the high-concentration Ge enrichment layer under the M separation layer. In the embodiment of the present application, it is called the first germanium enrichment layer, and this first germanium enrichment layer can provide an interface for the subsequent gate structure.
[0086] In some exemplary embodiments, the atomic layer treatment may include: ashing treatment and wet cleaning in sequence; wherein, the ashing treatment uses a plasma hydrogen-containing mixed gas.
[0087] Taking the semiconductor material M 1-x Ge x containing germanium as germanium-silicon as an example, when the semiconductor structure shown in Figure 3 is subjected to ashing treatment with a plasma hydrogen-containing mixed gas, the Si atoms and Ge atoms in the SiGe layer in the exposed fin region are separated under the action of hydrogen ions. Due to the different surface empty functions of Si atoms and Ge atoms, Si atoms tend to the interface of the SiGe layer, and Ge atoms tend to diffuse in the direction away from the SiGe layer interface, so that the SiGe layer in the exposed fin region forms an Si separation layer at the interface, and a Ge enrichment layer is formed under the Si separation layer. As shown in Figure 4 is a schematic diagram of the principle of forming an Si separation layer by ashing treatment of a SiGe material with a plasma hydrogen-containing mixed gas.
[0088] After the above ashing treatment, wet cleaning can remove the Si separation layer located at the interface, and then expose the Ge enrichment layer under the Si separation layer, forming a high-concentration first germanium enrichment layer on the outer surface of the fin region.
[0089] As shown in Figure 5 , after ashing treatment and wet cleaning in sequence, a first germanium enrichment layer 501 can be formed on the outer surface of the fin region of the semiconductor fin 220. Exemplarily, the thickness of the first germanium enrichment layer 501 is less than or equal to 5 angstroms.
[0090] In some examples, the hydrogen-containing mixed gas used in the above ashing treatment can be a mixed gas of nitrogen and hydrogen, wherein the volume ratio of hydrogen in the hydrogen-containing mixed gas is greater than or equal to 4%.
[0091] After removing the dummy gate structure in the embodiments of the present application, an ashing process using a hydrogen-containing mixed gas in a plasma state is adopted. Compared with the plasma dry etching process using pure hydrogen gas, it can avoid the adverse effects on the formation of the Ge-rich layer caused by a large etching amount and a large over-etching (OE) required in the pure hydrogen gas plasma dry etching process.
[0092] Considering that both the ion energy and the exposure time in the hydrogen plasma atmosphere will affect the etching selectivity of SiGe / Si, in the embodiments of the present application, the temperature of the ashing process is from room temperature to 300 °C, the pressure is from 1000 mTorr to 4000 mTorr, the power of the radio frequency power supply is from 800 W to 3500 W, and the time is from 10 s to 50 s. Thus, the ashing process control under different temperatures, different powers, and different gas flow rates can be realized for the formation of the first Ge-rich layer 501.
[0093] In some examples, the wet cleaning process can be sequentially cleaning with deionized water and SC1 solution.
[0094] Among them, the deionized water cleaning can be used to remove the ashing by-products that are relatively easy to be removed.
[0095] Among them, the SC1 solution cleaning is a mixed solution of an ammonia water solution and a hydrogen peroxide solution. The SC1 solution can oxidize the M separation layer (such as the Si separation layer) at the interface to form an oxide (such as silicon dioxide) to be removed, so as to expose the high-concentration Ge-rich layer, that is, the first Ge-rich layer, under the M separation layer to the outer surface of the fin region. Specifically, the hydrogen peroxide in the SC1 solution can oxidize the M component in the M separation layer to form an oxide, and this oxide can be corroded and dissolved in the SC1 solution by the ammonia water in the SC1 solution, so as to achieve the effect of removing the M separation layer at the interface and expose the high-concentration Ge-rich layer, that is, the first Ge-rich layer, under the M separation layer to the outer surface of the fin region.
[0096] In some exemplary embodiments, in order to improve the ability to remove the M separation layer at the interface, after the deionized water cleaning and before the SC1 solution cleaning, ozone deionized water cleaning can also be adopted. The oxidation ability of the ozone deionized water on the M separation layer at the interface is stronger than that of the SC1 solution on the M separation layer at the interface, so that the degree of oxidation of the M separation layer at the interface is higher, and thus the ability of the wet cleaning to remove the M separation layer at the interface can be improved.
[0097] As Figure 6a shown is the physical Ge concentration characterization diagram of the fin region on the semiconductor fin without undergoing step S107. Figure 6b The following is the physical Ge concentration characterization diagram of the fin region on the semiconductor fin after undergoing step S107. It can be seen that Figure 6bA high-concentration Ge-rich layer is formed on the outer surface of the fin portion region.
[0098] Continue to refer to Figure 1 , in step S109, a gate structure is formed across the semiconductor fin in the fin portion region, and the gate structure covers the first germanium-rich layer on the outer surface of the fin portion region.
[0099] As Figure 7 shown, the gate structure 710 may include a gate dielectric layer 711 and a gate electrode 712 formed on the gate dielectric layer 711. The gate dielectric layer 711 is formed on the fin portion region, and thus can cover the first germanium-rich layer 501 on the outer surface of the fin portion region.
[0100] In some exemplary embodiments, the gate dielectric layer 711 may include one or more dielectric materials, such as oxides, metal oxides, metal silicates, etc. or combinations thereof. For example, in some examples, the gate dielectric layer 711 may include an interface layer 711a and a high-k dielectric layer 711b above the interface layer 711a. The interface layer 711a may include silicon oxide, etc., and its formation method may adopt one method or a combination of methods such as thermal oxidation, ALD, CVD, etc. The high-k dielectric layer 711b may include high-k dielectric materials (for example, dielectric materials with a k value greater than about 7.0), such as metal oxides or silicates of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead and their combinations, and its formation method may adopt one method or a combination of methods such as molecular beam deposition (MBD), ALD, PECVD, etc.
[0101] The gate electrode 712 is deposited on the gate dielectric layer 711. The gate electrode 712 may include a liner layer, a work function adjustment layer, and a conductive material. The liner layer may include TiN, TiO, TaN, TaC, their combinations, or their multilayers, etc., and may be formed by PVD, CVD, ALD, or combinations thereof, etc. The work function layer may include TiN, WN, TaN, Ru, Co, their combinations, or their multilayers, etc., and may be formed using PVD, CVD, ALD, or combinations thereof, etc. The conductive filling material may include Co, Ru, Al, Ag, Au, W, Ni, Ti, Cu, Mn, Pd, Re, Ir, Pt, Zr, their alloys, their combinations, or their multilayers, etc., and may be formed by PVD, CVD, ALD, electroplating, or combinations thereof, etc.
[0102] In some exemplary embodiments, considering that if the high-concentration Ge-rich layer is directly connected to the metal, the interface state density D will be reduced it, which is not conducive to further improving the device performance. Based on this, in the above step S109, when forming the gate structure across the semiconductor fin in the fin region, the following Figures 8 to 10 steps shown in
[0103] can be adopted. Refer to Figure 8 to form a passivation layer 801 covering the fin region, so that the passivation layer 801 covers the first germanium-rich layer 501.
[0104] Specifically, a passivation layer 801 can be formed in the fin region. The formation material of the passivation layer 801 can include silicon and silicon dioxide (SiO2), and the passivation layer 801 can be epitaxially grown in the fin region by an epitaxial growth process.
[0105] Refer to Figure 9 to form a gate dielectric layer 901 on the passivation layer 801.
[0106] Specifically, an interfacial layer 901a can be formed on the passivation layer 801 by one or a combination of thermal oxidation, ALD, and CVD, and then a high-k dielectric layer 901b can be formed on the interfacial layer 901a by one or a combination of molecular beam deposition (MBD), ALD, and PECVD.
[0107] Refer to Figure 10 to form a gate electrode 1001 across the semiconductor fin on the gate dielectric layer 901.
[0108] Specifically, a liner layer 1001a can be formed on the high-k dielectric layer 901b by PVD, CVD, ALD, or a combination thereof, and then a work function adjustment layer 1001b can be formed on the liner layer 1001a by PVD, CVD, ALD, or a combination thereof, and then a conductive material 1001c can be formed on the work function adjustment layer 1001b by PVD, CVD, ALD, electroplating, or a combination thereof.
[0109] In the above embodiments, by forming a passivation layer on the first germanium-rich layer and then forming the final gate structure on the passivation layer, it is possible to well avoid the reduction of the interface state density caused by the direct connection of high-concentration Ge to the metal in the subsequent process, which is beneficial to improving the performance of the semiconductor device.
[0110] It can be seen that in the embodiment of the present application, during the formation process of the P-type field effect transistor device, for the semiconductor fin containing germanium material, after removing the dummy gate structure, ashing treatment and wet cleaning are performed in sequence first, and then a replacement gate structure is formed. Since the above ashing treatment and wet cleaning can form a high-concentration Ge enrichment layer on the outer surface of the fin region exposed and covered by the dummy gate structure, the Ge concentration in the channel region is increased, thereby greatly enhancing the carrier (hole) mobility and improving the performance of the semiconductor device.
[0111] In some exemplary embodiments, in order to further enhance the carrier (hole) mobility in the channel and improve the performance of the semiconductor device, in the foregoing step S103, when forming source / drain regions on both sides of the dummy gate structure on the semiconductor fin, it may be as Figure 11 shown, including the following steps S1101 to S1109.
[0112] In step S1101, the source region adjacent to the dummy gate structure on the semiconductor fin is etched to form a first groove.
[0113] On both sides of the semiconductor fin 220 adjacent to the dummy gate structure 240 are paired source / drain regions. Refer to Figure 12a , which is a cross-sectional schematic diagram along the extending direction of the semiconductor fin 220. The formation process of the first groove may be: forming a gate protection layer 1201 on the dummy gate structure 240 of the semiconductor fin 220. Generally, multiple dummy gate structures 240 may be formed on the semiconductor fin 220, and correspondingly multiple transistors may be formed. The formation material of the gate protection layer 1201 may be silicon oxide, and the gate protection layer 1201 only covers the surface of the dummy gate structure 240; forming a patterned mask layer 1202 on the semiconductor fin 220, and the patterned mask layer 1202 exposes the source region on one side of the dummy gate structure 240 on the semiconductor fin 220; etching with the patterned mask layer 1202 as an etching mask to form a first groove 1203 in the semiconductor fin 220, and then removing the patterned mask layer 1202. Among them, the etching process of the first groove 1203 may be a dry etching process, a wet etching process, or a combination of a dry etching process and a wet etching process.
[0114] In step S1103, a seed layer is deposited in the first groove, and the formation material of the seed layer is a semiconductor material containing germanium.
[0115] Among them, the semiconductor material containing germanium used to form the seed layer may be the aforementioned M 1- x Ge x in the implementation of the present application. For example, it may be germanium silicon Si 1-x Ge x .
[0116] See Figure 12b , a seed layer 1204 can be deposited on the inner sidewall of the first groove 1203 by, for example, a chemical vapor deposition process.
[0117] In step S1105, a second germanium-rich layer is formed on the outer surface of the seed layer.
[0118] In some examples, the manner of forming the second germanium-rich layer may include: performing an atomic layering process on the above-mentioned seed layer.
[0119] Wherein, the atomic layering process is used to separate M atoms from Ge atoms in the seed layer material M 1-x Ge x such that M atoms in M 1-x Ge x form an M separation layer on the surface, and a high-concentration Ge-rich layer is formed under the M separation layer, and then used to remove the M separation layer formed on the surface of the seed layer material M 1-x Ge x to expose the high-concentration Ge-rich layer under the M separation layer, which is called the second germanium-rich layer in the embodiments of the present application.
[0120] In some exemplary embodiments, the atomic layering process may include: sequentially performing ashing treatment and wet cleaning; wherein, the ashing treatment uses a hydrogen-containing mixed gas in a plasma state.
[0121] Taking a semiconductor material M 1-x Ge x containing germanium as germanium-silicon as an example, the aforementioned seed layer can be called a germanium-silicon seed layer. Then, as shown in the schematic principle diagram Figure 4 above, when performing ashing treatment with a hydrogen-containing mixed gas in a plasma state, under the action of hydrogen ions, Si atoms in the germanium-silicon seed layer are separated from Ge atoms. Since the surface empty functions of Si atoms and Ge atoms are different, Si atoms tend to be towards the interface of the germanium-silicon seed layer, and Ge atoms tend to diffuse away from the interface, so that a Si separation layer is formed at the interface of the germanium-silicon seed layer, and a Ge-rich layer is formed under the Si separation layer. After the above ashing treatment, wet cleaning can remove the Si separation layer located at the interface, and then expose the Ge-rich layer under the Si separation layer, and a high-concentration second germanium-rich layer is formed on the outer surface of the germanium-silicon seed layer.
[0122] As Figure 12c shown, sequentially passing through ashing treatment and wet cleaning can form a second germanium-rich layer 1205 on the outer surface of the germanium-silicon seed layer 1204. Exemplarily, the thickness of the second germanium-rich layer 1205 is less than or equal to 5 angstroms.
[0123] In some examples, the hydrogen-containing mixed gas used in the ashing process described above can be a mixed gas of nitrogen and hydrogen, where the volume ratio of hydrogen in the hydrogen-containing mixed gas is greater than or equal to 4%.
[0124] In some examples, the temperature of the ashing process in step S1105 is from room temperature to 300 °C, the pressure is from 1000 mTorr to 4000 mTorr, the power of the radio frequency power supply is from 800 W to 3500 W, and the time is from 10 s to 50 s. Thus, the ashing process control under different temperatures, different powers, and different gas flow rates can be achieved for the formation of the second germanium-rich layer 1205.
[0125] In some examples, the wet cleaning process in step S1105 can be sequentially cleaning with deionized water and cleaning with an SCI solution.
[0126] In other examples, the wet cleaning process in step S1105 can be sequentially deionized water cleaning, ozone deionized water cleaning, and SC1 solution cleaning.
[0127] In step S1107, a semiconductor material layer is epitaxially grown on the seed layer to obtain an epitaxial source region, where the semiconductor material layer covers the second germanium-rich layer on the outer surface of the seed layer.
[0128] Among them, the epitaxially grown semiconductor material layer is also formed of a semiconductor material containing germanium, and the percentage of germanium atoms in the semiconductor material layer is less than the percentage of germanium atoms in the seed layer. For example, the epitaxially grown semiconductor material layer can be the aforementioned M 1-x Ge x of the present application implementation, such as it can be germanium silicon Si 1-x Ge x .
[0129] See Figure 12d , when epitaxially growing the semiconductor material layer 1206 on the seed layer 1204, the semiconductor material layer 1206 starts to grow epitaxially with the second germanium-rich layer 1205 on the outer surface of the seed layer 1204. Thus, the semiconductor material layer 1206 covers the second germanium-rich layer 1205, and the semiconductor material layer 1206 at least fills the first groove 1203 to form an epitaxial source region.
[0130] Among them, the process of epitaxially growing the semiconductor material layer can be a molecular beam epitaxy process, a chemical vapor deposition process, and / or other suitable epitaxial growth processes.
[0131] In step S1109, an epitaxial drain region is formed in the drain region adjacent to the pseudo-gate structure on the semiconductor fin.
[0132] Specifically, after forming the epitaxial source region, an epitaxial drain region may be formed in the drain region corresponding to the respective pseudo-gate structure. The material used to form the epitaxial drain region is silicon or silicon doped with phosphorus.
[0133] In some examples, forming the epitaxial drain region may include: etching the drain region adjacent to the pseudo-gate structure on the semiconductor fin to form a second groove (not shown in the figure); depositing a SiP seed layer in the second groove; epitaxially growing a SiP layer on the SiP seed layer, and the SiP layer at least fills the second groove to form the epitaxial drain region (not shown in the figure).
[0134] In the above-mentioned embodiment, during the formation of the epitaxial source region, ashing treatment and wet cleaning are sequentially performed after depositing the seed layer. Since the above-mentioned ashing treatment and wet cleaning can form a high-concentration Ge enrichment layer on the outer surface of the seed layer, the Ge concentration in the epitaxial source region is increased, thereby enhancing the stress exerted by the epitaxial source / drain region on the channel region between the epitaxial source / drain regions, and further enhancing the carrier (hole) mobility and improving the performance of the semiconductor device.
[0135] In some exemplary embodiments, in order to further enhance the carrier (hole) mobility in the channel and improve the performance of the semiconductor device, in the aforementioned step S1107, when epitaxially growing a semiconductor material layer on the seed layer to obtain the epitaxial source region, it may be as Figure 13 shown and include the following steps S1301 to step S1305.
[0136] In step S1301, a semiconductor material layer is epitaxially grown on the seed layer.
[0137] Among them, the percentage of germanium atoms in the semiconductor material layer is less than the percentage of germanium atoms in the seed layer. The semiconductor material layer covers the second germanium enrichment layer on the outer surface of the seed layer.
[0138] For specific implementation, reference may be made to the foregoing Figure 12d shown.
[0139] In step S1303, a third germanium enrichment layer is formed on the outer surface of the semiconductor material layer.
[0140] In some examples, the method of forming the third germanium enrichment layer may include: performing atomic layering treatment on the above-mentioned semiconductor material layer.
[0141] Among them, the atomic layering treatment is used to separate the M atoms and Ge atoms in the semiconductor material layer material M 1-x Ge x such that the M 1-x Ge xForm an M separation layer on the surface, form a high-concentration Ge enrichment layer under the M separation layer, and then use it to process the semiconductor material layer material M 1-x Ge x Remove the M separation layer formed on the surface to expose the high-concentration Ge enrichment layer under the M separation layer. In the embodiments of the present application, this is called the third germanium enrichment layer.
[0142] In some exemplary embodiments, the atomic layer processing may include: performing ashing treatment and wet cleaning in sequence; wherein, the ashing treatment uses a plasma hydrogen-containing mixed gas.
[0143] Taking the semiconductor material M containing germanium 1-x Ge x as an example of germanium silicon, the aforementioned epitaxially grown semiconductor material layer may be called a germanium silicon layer. As shown in the schematic principle diagram above, when performing ashing treatment with a plasma hydrogen-containing mixed gas, under the action of hydrogen ions, Si atoms and Ge atoms in the germanium silicon layer are separated. Since the surface empty functions of Si atoms and Ge atoms are different, Si atoms tend to the interface of the germanium silicon layer, and Ge atoms tend to diffuse in the direction away from the interface, so that a Si separation layer is formed at the interface of the germanium silicon layer, and a Ge enrichment layer is formed under the Si separation layer. After the above ashing treatment, wet cleaning can remove the Si separation layer located at the interface, thereby exposing the Ge enrichment layer under the Si separation layer, and forming a high-concentration third germanium enrichment layer on the outer surface of the germanium silicon layer. Figure 4 As shown in the schematic principle diagram, after the above ashing treatment, wet cleaning can remove the Si separation layer located at the interface, thereby exposing the Ge enrichment layer under the Si separation layer, and forming a high-concentration third germanium enrichment layer on the outer surface of the germanium silicon layer.
[0144] See Figure 14a , After ashing treatment and wet cleaning in sequence, a third germanium enrichment layer 1401 can be formed on the outer surface of the germanium silicon layer 1204. Exemplarily, the thickness of the third germanium enrichment layer 1401 is less than or equal to 5 angstroms.
[0145] In some examples, the hydrogen-containing mixed gas used in the above ashing treatment may be a mixed gas of nitrogen and hydrogen, wherein the volume ratio of hydrogen in the hydrogen-containing mixed gas is greater than or equal to 4%.
[0146] In some examples, the temperature of the ashing treatment in step S1303 is room temperature to 300 °C, the pressure is 1000 mTorr to 4000 mTorr, the power of the radio frequency power supply is 800 W to 3500 W, and the time is 10 s to 50 s, so that the ashing treatment can be regulated under different temperatures, different powers and different gas flows for the formation of the third germanium enrichment layer 1401.
[0147] In some examples, the wet cleaning treatment in step S1303 may be to clean with deionized water and SCI solution in sequence.
[0148] In some other examples, the wet cleaning process in step S1303 may be sequentially deionized water cleaning, ozone deionized water cleaning, and SC1 solution cleaning.
[0149] In step S1305, a barrier layer is formed on the semiconductor material layer to obtain an epitaxial source region, and the barrier layer covers the third germanium-rich layer on the outer surface of the semiconductor material layer.
[0150] See Figure 14b , after ashing treatment and wet cleaning, a barrier layer 1402 is formed on the germanium-silicon layer 1204, so that the barrier layer 1402 can cover the third germanium-rich layer 1401 on the outer surface of the germanium-silicon layer 1204 to protect the high-concentration Ge-rich layer.
[0151] Among them, the forming material of the barrier layer 1402 may be silicon oxide, and the forming method of the barrier layer 1402 may include chemical vapor deposition, etc.
[0152] In the above embodiments, during the formation of the epitaxial source region, after the first deposition of the germanium-containing semiconductor material to form the seed layer, ashing treatment and wet cleaning are sequentially performed, and after the second epitaxial growth of the germanium-containing semiconductor material to form the semiconductor material layer, ashing treatment and wet cleaning are performed again, so as to form high-concentration Ge-rich layers on the outer surface of the seed layer and on the outer surface of the semiconductor material layer respectively, further increasing the Ge concentration in the epitaxial source region, and further enhancing the stress applied by the epitaxial source / drain region to the channel region between the epitaxial source / drain regions, enhancing the carrier (hole) mobility, and improving the performance of the semiconductor device.
[0153] The embodiment of the present application also provides a semiconductor device formed based on the foregoing forming method. The semiconductor device includes:
[0154] A semiconductor substrate;
[0155] A semiconductor fin located on the semiconductor substrate, and the forming material of the semiconductor fin is a germanium-containing semiconductor material;
[0156] A gate structure located on the semiconductor fin; wherein, a first germanium-rich layer is formed on the outer surface of the fin portion covered by the gate structure;
[0157] Source / drain regions located on both sides of the gate structure.
[0158] Among them, the semiconductor substrate may be a bulk semiconductor or a silicon-on-insulator semiconductor. The semiconductor substrate may include regions for forming P-type field effect transistors, and of course may also include regions for forming N-type field effect transistors. The semiconductor fin containing germanium silicide in the embodiment of the present application is formed in the region of the semiconductor substrate for forming P-type field effect transistors.
[0159] Among them, the germanium-containing semiconductor material used to form the semiconductor fin can be expressed as M 1-x Ge x , and the surface empty function of M atoms and Ge atoms in this M 1-x Ge x is different, and M atoms tend to be towards the interface of the M 1-x Ge x layer, while Ge atoms tend to diffuse away from the interface of the M 1-x Ge x layer. Exemplarily, M 1-x Ge x in can be silicon Si, and then the germanium-containing semiconductor material is silicon germanium Si 1-x Ge x .
[0160] Among them, the molar ratio of Ge atoms in M 1-x Ge x can be less than 60% (x < 0.6). For example, the molar ratio of Ge atoms in M 1-x Ge x can be 40% - 50% (0.4 < x < 0.5).
[0161] Among them, the source region can be an epitaxial structure grown by using a germanium-containing semiconductor material, that is, it can be an epitaxial source region, and the drain region can be an epitaxial structure grown by using SiP epitaxy, that is, it can be an epitaxial drain region.
[0162] In some exemplary embodiments, the above source region includes:
[0163] a first groove located on the semiconductor fin, and the first groove is located on one side of the gate structure;
[0164] a seed layer located in the first groove, and the formation material of the seed layer is a germanium-containing semiconductor material, and a second germanium-rich layer is formed on the outer surface of the seed layer;
[0165] a semiconductor material layer located on the seed layer, and the semiconductor material layer covers the second germanium-rich layer on the outer surface of the seed layer, and the percentage of germanium atoms in the semiconductor material layer is less than the percentage of germanium atoms in the seed layer. The semiconductor material layer at least fills the remaining space of the first groove.
[0166] In some exemplary embodiments, a third germanium-rich layer is formed on the outer surface of the semiconductor material layer; a barrier layer is also formed on the semiconductor material layer, and the barrier layer covers the third germanium-rich layer on the outer surface of the semiconductor material layer.
[0167] Exemplarily, the thickness of the germanium-rich layer in the semiconductor device is less than or equal to 5 angstroms, where the germanium-rich layer in the semiconductor device is any one of the aforementioned first germanium-rich layer, second germanium-rich layer, and third germanium-rich layer. Additionally, the thicknesses of the first germanium-rich layer, second germanium-rich layer, and third germanium-rich layer may be the same or different.
[0168] In the embodiments of the present application, a high-concentration Ge-rich layer is formed in the germanium-containing channel region of the semiconductor device, which increases the Ge concentration in the channel region, thereby greatly enhancing the carrier (hole) mobility and improving the performance of the semiconductor device.
[0169] Furthermore, in the embodiments of the present application, a high-concentration Ge-rich layer is formed in the epitaxial source region of the semiconductor device, which increases the Ge concentration in the epitaxial source region, thereby enhancing the stress exerted by the epitaxial source / drain region on the channel region between the epitaxial source / drain regions, and further enhancing the carrier (hole) mobility and improving the performance of the semiconductor device.
[0170] Correspondingly, the embodiments of the present application further provide an electronic device, and the electronic device includes any one of the semiconductor devices described above in the embodiments of the present application.
[0171] Since the semiconductor device has good working performance, and the electronic device uses the semiconductor device, this correspondingly improves the performance of the electronic device. Among them, the electronic device can be any electronic product or device such as a mobile phone, tablet computer, laptop computer, netbook, game console, television, VCD, DVD, navigator, camera, video camera, recording pen, MP3, MP4, PSP, etc., or it can also be an intermediate product having the semiconductor device, such as: a device main board having the semiconductor device, etc.
[0172] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be determined by the scope defined by the claims.
Claims
1. A method for forming a semiconductor device, characterized in that, Comprising: Providing a semiconductor structure, the semiconductor structure including a semiconductor substrate, semiconductor fins formed on the semiconductor substrate, and a dummy gate structure spanning the semiconductor fins, wherein the semiconductor fins are formed of a semiconductor material containing germanium; Forming source / drain regions on both sides of the dummy gate structure on the semiconductor fins; Removing the dummy gate structure to expose the fin region covered by the dummy gate structure; Forming a first germanium enrichment layer on the outer surface of the fin region; Forming a gate structure spanning the semiconductor fins in the fin region, the gate structure covering the first germanium enrichment layer on the outer surface of the fin region.
2. The forming method according to claim 1, wherein The forming of the gate structure spanning the semiconductor fins in the fin region includes: Forming a passivation layer covering the fin region such that the passivation layer covers the first germanium enrichment layer; Forming a gate dielectric layer on the passivation layer; Forming a gate electrode spanning the semiconductor fins on the gate dielectric layer; the gate structure includes the gate dielectric layer and the gate electrode.
3. The forming method according to claim 1, wherein The forming of the source / drain regions on both sides of the dummy gate structure on the semiconductor fins includes: Etching the source region adjacent to the dummy gate structure on the semiconductor fins to form a first groove; Depositing a seed layer in the first groove, the seed layer being formed of a semiconductor material containing germanium; Forming a second germanium enrichment layer on the outer surface of the seed layer; Epitaxially growing a semiconductor material layer on the seed layer to obtain an epitaxial source region; the semiconductor material layer covers the second germanium enrichment layer on the outer surface of the seed layer; Forming an epitaxial drain region in the drain region adjacent to the dummy gate structure on the semiconductor fins.
4. The forming method according to claim 3, wherein, The epitaxially growing a semiconductor material layer on the seed layer to obtain an epitaxial source region includes: Epitaxially growing a semiconductor material layer on the seed layer; the percentage of germanium atoms in the semiconductor material layer is less than the percentage of germanium atoms in the seed layer; Forming a third germanium enrichment layer on the outer surface of the semiconductor material layer; Forming a barrier layer on the semiconductor material layer to obtain the epitaxial source region; the barrier layer covers the third germanium enrichment layer on the outer surface of the semiconductor material layer.
5. The forming method according to any one of claims 1 to 4, characterized in that The method of forming the germanium enrichment layer includes: performing atomic layering treatment on a semiconductor material containing germanium.
6. The forming method according to claim 5, characterized in that, The atomic layering treatment includes: sequentially performing ashing treatment and wet cleaning; wherein, the ashing treatment uses a hydrogen-containing mixed gas in plasma state.
7. The forming method according to claim 6, wherein The hydrogen-containing mixed gas for the ashing treatment is a mixed gas of nitrogen and hydrogen, and the volume ratio of hydrogen in the hydrogen-containing mixed gas is greater than or equal to 4%.
8. The forming method according to claim 7, characterized in that, The processing technology of the ashing treatment further includes: the temperature is from room temperature to 300 °C, the pressure is from 1000 mTorr to 4000 mTorr, the power of the radio frequency power supply is from 800 W to 3500 W, and the time is from 10 s to 50 s.
9. The forming method according to claim 6, characterized in that, The wet cleaning includes: sequentially cleaning with deionized water and SC1 solution.
10. The forming method according to claim 9, wherein After the deionized water cleaning and before the SC1 solution cleaning, it further includes: cleaning with ozone deionized water.
11. The forming method according to any one of claims 1 to 4, characterized in that, The thickness of the formed germanium enrichment layer is less than or equal to 5 angstroms.
12. A semiconductor device, characterized in that, Comprising: Semiconductor substrate; A semiconductor fin located on the semiconductor substrate; The semiconductor fin is formed of a semiconductor material containing germanium; A gate structure located on the semiconductor fin; wherein, a first germanium-rich layer is formed on the outer surface of the fin portion covered by the gate structure; Source / drain regions located on both sides of the gate structure.
13. The semiconductor device according to claim 12, wherein The source region in the source / drain region includes: A first groove located on the semiconductor fin; the first groove is located on one side of the gate structure; A seed layer located in the first groove; the seed layer is formed of a semiconductor material containing germanium, and a second germanium-rich layer is formed on the outer surface of the seed layer; A semiconductor material layer located on the seed layer; the semiconductor material layer covers the second germanium-rich layer on the outer surface of the seed layer, and the percentage of germanium atoms in the semiconductor material layer is less than the percentage of germanium atoms in the seed layer.
14. The semiconductor device according to claim 13, wherein, A third germanium-rich layer is formed on the outer surface of the semiconductor material layer; A barrier layer is further formed on the semiconductor material layer, and the barrier layer covers the third germanium-rich layer on the outer surface of the semiconductor material layer.
15. The semiconductor device according to any one of claims 12 to 14, characterized in that, The thickness of the germanium-rich layer in the semiconductor device is less than or equal to 5 angstroms.
16. An electronic device, characterized in that, The electronic device includes a semiconductor device formed by using the forming method according to any one of claims 1 to 11.