Semiconductor device and forming method thereof
By implementing an interlayer wall structure with controlled aspect ratios in semiconductor devices, the method addresses the complexity and performance issues of stress-induced carrier mobility enhancements, resulting in improved electrical performance and reliability.
Patent Information
- Application Number
- CN202410038649.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-01-10
- Publication Date
- 2025-07-15
AI Technical Summary
In the prior art, in semiconductor devices, as the line width is reduced, the difficulty of manufacturing process control increases, which affects the electrical performance of the semiconductor device, and is particularly difficult to control the influence of current-intensive areas on both sides of the gate structure.
By providing a gap wall structure, especially the second gap wall, in the semiconductor device, the thickness of the cap structure relative to the distance of the gate structure is accurately controlled, so as to avoid the current-intensive areas on both sides of the gate structure being affected by the cap structure and epitaxial structure.
Effectively improve the overall electrical performance of the semiconductor device and improve the operation performance, especially in metal oxide semiconductor transistors and static random access memory devices.
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Figure CN120321983A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to a semiconductor device and a method for forming the same, and more particularly to a semiconductor device having an epitaxial structure and a method for forming the same. Background Art
[0002] In order to increase the carrier mobility of a semiconductor structure, compressive stress or tensile stress can be applied to the gate channel. For example, if compressive stress needs to be applied, the prior art often uses selective epitaxial growth (SEG) technology to form an epitaxial structure with the same lattice arrangement as the silicon substrate in the silicon substrate, such as a silicon germanium (SiGe) epitaxial structure. By utilizing the characteristic that the lattice constant of the silicon germanium epitaxial structure is greater than that of the silicon substrate lattice, compressive stress is generated in the channel region of the P-type metal oxide semiconductor transistor, increasing the carrier mobility in the channel region and being used to increase the speed of the metal oxide semiconductor transistor. Conversely, for an N-type semiconductor transistor, a silicon carbide (SiC) epitaxial structure can be formed in the silicon substrate to generate tensile stress in the gate channel region. However, although the foregoing methods can effectively improve the carrier mobility in the channel region, they greatly increase the difficulty of manufacturing process control in the trend of continuous reduction of the semiconductor device line width. In view of this, how to effectively improve the structure and manufacturing process of semiconductor devices remains an important issue today to obtain more reliable components. Summary of the Invention
[0003] An object of the present invention is to provide a semiconductor device and a method for forming the same, which accurately control the aspect ratio of the thickness of the cap structure to its distance from the gate structure through the setting of the spacer structure, avoiding affecting the overall electrical performance of the semiconductor device, and thereby improving the operating performance of the semiconductor structure.
[0004] To achieve the above object, a preferred embodiment of the present invention provides a semiconductor device, including a substrate, two gate structures, a spacer structure, an epitaxial structure, a cap structure, and a metal silicide layer. The two gate structures are disposed on the substrate. The spacer structure is disposed on the substrate and surrounds each of the gate structures. The epitaxial structure is disposed in the substrate and between the two gate structures. The cap structure is disposed on the epitaxial structure and between the two gate structures. The metal silicide layer is disposed on the cap structure. The spacer structure includes a first spacer, a second spacer, and a third spacer sequentially stacked on the sidewalls of the gate stack. The second spacer at least contacts a part of the sidewall of the cap structure.
[0005] To achieve the above object, a preferred embodiment of the present invention provides a method for forming a semiconductor device, including the following steps. Provide a substrate, and form two gate structures on the substrate. Form a first spacer and a dummy spacer that simultaneously surround the two gate structures on the substrate in sequence. Form an epitaxial structure in the substrate, located between the two gate structures. Form a capping structure on the epitaxial structure, located between the two gate structures, and the capping structure includes a first capping layer and a second capping layer stacked on the epitaxial structure in sequence. Form a metal silicide layer on the capping structure. Wherein, forming the capping structure further includes forming the first capping layer, forming a capping material layer on the first capping layer, oxidizing a part of the capping material layer, and removing the oxidized part of the capping material layer, and forming the second capping layer on the first capping layer.
[0006] Generally speaking, the semiconductor device of the present invention is provided with a second spacer that at least partially contacts the capping structure between the capping structure and / or the epitaxial structure and the gate structure, so as to precisely control the aspect ratio of the thickness of the capping structure relative to the distance between it and the gate structure, avoid the regions with relatively dense current on both sides of the gate structure from being affected by the capping structure and / or the epitaxial structure, improve the overall electrical performance of the semiconductor device, and further improve the operating performance of the semiconductor structure. Accordingly, the semiconductor device of the present invention can be further applied to various functional semiconductor devices including epitaxial structures, such as metal oxide semiconductor transistor devices, or static random access memory devices (static random access memory device), etc., but not limited thereto. BRIEF DESCRIPTION OF THE DRAWINGS
[0007] Figure 1 is a cross-sectional schematic diagram of the semiconductor device in the first embodiment of the present invention;
[0008] Figure 2 is a top view schematic diagram of the semiconductor device in the preferred embodiment of the present invention;
[0009] Figures 3 to 6 is a schematic diagram of the method for forming the semiconductor device in the first embodiment of the present invention, wherein:
[0010] Figure 3 is a cross-sectional schematic diagram of the semiconductor device after forming the capping structure;
[0011] Figure 4 is a cross-sectional schematic diagram of the semiconductor device after performing the thermal oxidation manufacturing process;
[0012] Figure 5 is a cross-sectional schematic diagram of the semiconductor device after forming the second spacer; and
[0013] Figure 6 is a cross-sectional schematic diagram of the semiconductor device after forming the spacer structure.
[0014] Figures 7 to 8 Schematic diagram of the method for forming a semiconductor device in the second embodiment of the present invention, wherein:
[0015] Figure 7 is a cross-sectional schematic diagram of the semiconductor device after forming the second spacer; and
[0016] Figure 8 is a cross-sectional schematic diagram of the semiconductor device after forming the metal silicide layer;
[0017] Figures 9 to 10 Schematic diagram of the method for forming a semiconductor device in the third embodiment of the present invention, wherein:
[0018] Figure 9 is a cross-sectional schematic diagram of the semiconductor device after removing the dummy spacer; and
[0019] Figure 10 is a cross-sectional schematic diagram of the semiconductor device after forming the metal silicide layer.
[0020] Description of main element symbols
[0021] 10, 30, 50 Semiconductor device
[0022] 20 Static random access memory device
[0023] 100 Substrate
[0024] 110 Gate structure
[0025] 112 Gate dielectric layer
[0026] 114 Gate layer
[0027] 120 Epitaxial structure
[0028] 122 Doped region
[0029] 130, 330, 530 Spacer structure
[0030] 132 First spacer
[0031] 134, 334 Second spacer
[0032] 134a Vertical portion
[0033] 134b Horizontal portion
[0034] 136 Third spacer
[0035] 140 Capping structure
[0036] 142 First capping layer
[0037] 144 Second capping layer
[0038] 150 Metal silicide layer
[0039] 202 Static random access memory cell
[0040] 204 First inverter
[0041] 204a First pull-up transistor
[0042] 204b First pull-down transistor
[0043] 206 Second inverter
[0044] 206a Second pull-up transistor
[0045] 206b Second pull-down transistor
[0046] 208 First through-gate transistor
[0047] 210 Second through-gate transistor
[0048] 212 Fin structure
[0049] 234 dummy spacer
[0050] 244 Capping material layer
[0051] 244a Sacrificial layer
[0052] P1 Thermal oxidation fabrication process
[0053] P21, P22, P23 Etching fabrication process
[0054] R1 Distance
[0055] T1, T11, T12 Thickness
[0056] T2 Thickness
[0057] T3 Thickness Detailed implementation manners
[0058] To enable those of ordinary skill in the art to which the present invention pertains to further understand the present invention, several preferred embodiments of the present invention are specifically enumerated below, and in conjunction with the accompanying drawings, the composition content of the present invention and the effects to be achieved are described in detail. Moreover, without departing from the spirit of the present invention, the technical features in the different embodiments described below can be replaced, recombined, and mixed with each other to form other embodiments.
[0059] Please refer to Figure 1As shown, a cross-sectional schematic diagram of the semiconductor device 10 in the first embodiment of the present invention is illustrated. The semiconductor device 10 includes a substrate 100, two gate structures 110, an epitaxial structure 120, a spacer structure 130, a capping structure 140, and a metal silicide layer 150. The substrate 100 includes, for example, a silicon substrate, an epitaxial silicon substrate, a silicon-containing substrate, or a silicon-on-insulator (SOI) substrate, etc., but is not limited thereto. In one embodiment, the substrate 100 may further include a plurality of fin-shaped structures (not shown), thereby becoming a non-planar substrate, but is not limited thereto. The two gate structures 110 are disposed on the substrate 100 separately from each other, and each includes a gate dielectric layer 112 and a gate layer 114 stacked in sequence on the top surface of the substrate 100. In one embodiment, the gate dielectric layer 112 may include, for example, a dielectric material such as silicon oxide, and the gate layer 114 includes, for example, a semiconductor material such as doped polysilicon or doped amorphous silicon, but is not limited thereto. The spacer structure 130 is also disposed on the substrate 100 and surrounds each of the gate structures 110 respectively. The epitaxial structure 120 is disposed in the substrate 100 and between the two gate structures 110, and the capping structure 140 is disposed on the epitaxial structure 120 and also between the two gate structures 110. Moreover, the metal silicide layer 150 is disposed on the capping structure 140.
[0060] It should be specifically noted that the details of the spacer structure 130 include a first spacer 132, a second spacer 134, and a third spacer 136 stacked in sequence on the sidewalls of each gate stack 110. Among them, the second spacer 134 has, for example, a sidewall that vertically aligns with the sidewall of the third spacer 136, such that the second spacer 134 directly contacts the sidewall of the capping structure 140. Thus, by disposing the second spacer 134 of the spacer structure 130 between the first spacer 132 and the capping structure 140, the aspect ratio (T1 / R1) of the thickness T1 of the capping structure 140 relative to the minimum distance R1 between the capping structure 140 and the gate structure 110 can be accurately controlled between 1 and 3, preferably between 1.2 and 2.2, but is not limited thereto. With this setting, not only can the distance R1 between the capping structure 140 and / or the epitaxial structure 120 and the gate structure 110 be effectively increased, avoiding the influence of the capping structure 140 and / or the epitaxial structure 120 on the regions where the current is relatively concentrated on both sides of the gate structure 110, improving the overall electrical performance of the semiconductor device, and further enhancing the operating performance of the semiconductor structure.
[0061] In detail, the second spacer 134 includes, for example, an L-shaped cross section. The vertical portion 134a of the L-shaped cross section covers the entire sidewall of the cap structure 140 and is flush with the sidewall of the third spacer 136, while the horizontal portion 134b of the L-shaped cross section covers the top surface of the substrate 100. In one embodiment, the first spacer 132, the second spacer 134, and the third spacer 136 respectively include, for example, different dielectric materials, such as silicon oxide, silicon nitride, silicon carbonitride, or silicon oxynitride, etc. Moreover, the second spacer 134 preferably includes a material having an etching selectivity with respect to the materials of the first spacer 132 and the third spacer 136, but is not limited thereto. Those skilled in the art should easily understand that although the first spacer 132, the second spacer 134, and the third spacer 136 in this embodiment are Figure 1 illustrated as a single-layer structure, their specific arrangements are not limited thereto and may selectively have a multi-layer structure according to product requirements.
[0062] For another example Figure 1 as shown, the epitaxial structure 120 is formed, for example, along a specific crystal plane within the substrate 100 and has a cross-sectional shape such as diamond, hexagon (also known as sigma Σ), or octagon. Moreover, the semiconductor device 10 further includes a doped region 122 disposed within the epitaxial structure 120 to serve as a source / drain region. In one embodiment, the epitaxial structure 120 may have different materials according to the type of metal oxide semiconductor (MOS) transistor to be formed subsequently. For example, it may be selectively chosen to include materials such as silicon germanium (SiGe) or silicon carbide (SiC), preferably including silicon germanium, germanium boride silicide, or germanium tin silicide, etc. The doped region 122 also includes different dopants according to the type of metal oxide semiconductor transistor to be formed subsequently, such as including suitable P-type ions or N-type ions, etc., but is not limited thereto.
[0063] On the other hand, the cap structure 140 details include a first cap layer 142 and a second cap layer 144 stacked in sequence on the epitaxial structure 120. In one embodiment, the first cap layer 142 and the second cap layer 144 respectively include different epitaxial materials, and may selectively include a single-layer or multi-layer structure. Among them, the first cap layer 142 includes, for example, doped silicon germanium, and the germanium atoms thereof can also be changed in a graded manner. Preferably, the surface of the first cap layer 142 has relatively few or no germanium atoms, while the second cap layer 144 includes, for example, a semiconductor material such as silicon, but is not limited thereto. In this way, the setting of the cap structure 140 is beneficial to the subsequent setting of the metal silicide layer 150 on the cap structure 140. The first cap layer 142 and the second cap layer 144 respectively include different thicknesses T11, T12. Among them, the thickness T11 of the first cap layer 142 is about 30 angstroms to 150 angstroms, and the thickness T12 of the second cap layer 144 is about 130 angstroms to 210 angstroms, but is not limited thereto.
[0064] For the semiconductor device 10 according to the first embodiment of the present invention, a second spacer 134 in direct contact with the cap structure 140 is provided between the cap structure 140 and / or the epitaxial structure 120 and the gate structure 110. The second spacer 134 has an L-shaped cross section, for example. In this way, the semiconductor device 10 can accurately control the aspect ratio of the thickness T1 of the cap structure 140 relative to the distance R1 between it and the gate structure 110 through the setting of the second spacer 134, avoiding the influence of the cap structure 140 and / or the epitaxial structure 120 on the regions where the current is relatively concentrated on both sides of the gate structure 110, improving the overall electrical performance of the semiconductor device 10, and further enhancing the operating performance of the semiconductor structure 10. Accordingly, the semiconductor device 10 of the present invention can be further applied to various functional semiconductor devices including epitaxial structures, such as metal oxide semiconductor transistor devices, or static random access memory devices, etc., but is not limited thereto.
[0065] For example, such as Figure 2As shown, the static random access memory device 20 includes, for example, a static random access memory (6T-SRAM) cell 202 composed of six transistors. Among them, each static random access memory cell 202 details include a first inverter 204, a second inverter 206, and two N-type transistors 208, 210, such as a first pass-gate (PG) transistor 208 and a second pass-gate transistor 210. The first inverter 204 and the second inverter 206 respectively include two P-type transistors 204a / 206a, 204b / 206b, such as a first pull-up (PU) transistor 204a and a first pull-down (PD) transistor 204b, and a second pull-up transistor 206a and a second pull-down transistor 206b. It should be noted that each of the foregoing transistors is composed of a gate structure 110 extending in a first direction D1 straddling at least one fin structure 212 extending in a second direction D2 on a substrate 100. And, epitaxial structures 120 and capping structures 140, etc. are further provided in the fin structures 212 on two opposite sides of each gate structure 110 in the second direction D2. Thus, those skilled in the art should easily understand Figure 1 The semiconductor device 10 shown is, for example, Figure 2 A cross-sectional schematic diagram along the tangent A-A' in the figure, so that the distances from two adjacent transistors (the first pull-up transistor 204a and the second pull-up transistor 206a) in the static random access memory cell 202 to the epitaxial structure 120 and / or the capping structure 140 provided therebetween can be accurately controlled, avoiding the influence of the capping structure 140 and / or the epitaxial structure 120 on the currents on both sides of the gate structure 110, which is not conducive to the operation performance of the static random access memory cell 202.
[0066] To enable those of ordinary skill in the art to which the present invention pertains to easily understand the semiconductor device 10 of the present invention, the formation method of the semiconductor device 10 of the present invention will be further described below. Please refer to Figures 3 to 6 Shown is a cross-sectional schematic diagram of the formation method of the semiconductor device 10 in the first embodiment of the present invention.
[0067] First, as Figure 3As shown, a substrate 100 is provided, such as a silicon substrate, an epitaxial silicon substrate, a silicon-containing substrate (such as a silicon germanium substrate or a silicon carbide substrate), or a silicon-on-insulator substrate, etc. Then, a plurality of gate structures 110 are formed on the substrate 100. In one embodiment, at least one fin structure (not shown) may also be formed on the substrate 100 in advance using a photolithography and etching manufacturing process or a multiple exposure manufacturing process, etc., and then the gate structure 110 is formed on the at least one fin structure, but this is not limiting. Among them, the formation method of the at least one fin structure includes, for example, but is not limited to the following steps: first, a patterned mask (not shown) is formed on the substrate 100, an etching manufacturing process is performed through the patterned mask to form at least one trench (not shown) in the substrate 100, and then the patterned mask is removed. After that, an insulating material is filled in the at least one trench, so that the substrate 100 protruding from the insulating material becomes the at least one fin structure, and the insulating material forms a shallow trench isolation (STI, not shown).
[0068] The details of the gate structure 110 include a gate dielectric layer 112 and a gate layer 114 stacked in sequence on the top surface of the substrate 100. In one embodiment, the formation method of the gate structure 110 includes, for example, but is not limited to the following steps. A comprehensively covering dielectric material layer (not shown), which includes a dielectric material such as silicon oxide, and a gate material layer (not shown), which includes a semiconductor material such as doped polysilicon or doped amorphous silicon, are formed on the substrate 100 in sequence. Then, the stacked material layers are patterned to form the gate structure 110. Those skilled in the art should easily understand that the gate structure 110 of the present invention may also be formed in other ways or have other aspects. For example, in another embodiment, the gate structure 110 may also include a metal gate structure (not shown), which at least includes a work function layer and a metal gate stacked in sequence.
[0069] Then, at least one deposition and etch-back process is performed to sequentially form a first spacer 132 and dummy spacers 234 that surround each gate structure 110 on the substrate 100, and then an epitaxial structure 120 is formed in the substrate 100 on both sides of the gate structure 110. Among them, the first spacer 132 and the dummy spacers 234 can optionally have a single-layer or composite-layer structure, and preferably include dielectric materials with etching selectivity to each other, such as silicon oxide, silicon nitride, silicon carbonitride, or silicon oxynitride, etc., but are not limited thereto. It should be noted that the thickness T2 of the dummy spacers 234 varies according to the expected distance R1 from the subsequently formed capping structure 140 to the gate structure 110, for example, about 150 Å to 200 Å, but is not limited thereto. In one embodiment, the formation method of the epitaxial structure 120 includes, for example, but is not limited to the following steps. First, after the first spacer 132 and the dummy spacers 234 are formed, an etching process is performed on the substrate 100 using the gate structure 110, the first spacer 132, and the dummy spacers 234 as an etching mask, such as including a dry etching process, a wet etching process, or a sequential dry etching and wet etching process, to form a groove (not shown) in the substrate 100 on both sides of the gate structure 110. Then, a selective epitaxial growth (SEG) process is performed to form the epitaxial structure 120 in the groove.
[0070] Specifically, the epitaxial structure 120 is formed, for example, along a specific crystal plane in the substrate 100, its top surface is flush with the top surface of the substrate 100, and preferably has a cross-sectional shape such as diamond, hexagonal, or octagonal, etc., but is not limited thereto. In one embodiment, the epitaxial structure 120 can have different materials according to the type of metal-oxide semiconductor transistor required subsequently, for example, including silicon germanium, germanium boron silicide, or germanium tin silicide (for P-type transistors), or including silicon carbide, carbon phosphorus silicon, or silicon phosphide (for N-type transistors), but is not limited thereto. In another embodiment, the selective epitaxial process can also be performed in a single-layer or multi-layer manner, and its heteroatoms (such as germanium atoms or carbon atoms) can also be changed in a graded manner.
[0071] Thereafter, an ion implantation process is performed using the gate structure 110, the first spacer 132, and the dummy spacer 234 as masks to form a doped region 122 in at least a portion of the epitaxial structure 120 as a source / drain region. The doped region 122 also includes different dopants according to the type of metal-oxide-semiconductor transistor required subsequently, for example, including P-type ions or N-type ions, etc., but not limited thereto. Also, these dopants can be formed in a graded manner. In one embodiment, the formation of the doped region 122 can also be performed in-situ during the selective epitaxial growth process. For example, when forming a silicon-germanium epitaxial structure, a germanium-boron-silicide epitaxial structure, or a tin-germanium-silicide epitaxial structure (for P-type transistors), P-type dopants are implanted, or when forming a silicon-carbide epitaxial structure, a phosphorus-silicon-carbide epitaxial structure, or a silicon-phosphide epitaxial structure (for N-type transistors), N-type dopants are implanted, so as to omit the ion implantation process and simplify the overall manufacturing process.
[0072] Thereafter, as Figure 3 shown, another selective epitaxial growth process is performed again using the gate structure 110, the first spacer 132, and the dummy spacer 234 as masks to sequentially form a first capping layer 142 and a cap material layer 244 on the epitaxial structure 120. The first capping layer 142 (such as doped silicon-germanium) and the cap material layer 244 (such as a semiconductor material including silicon, etc.) respectively include different epitaxial materials, for example, and can selectively form a single-layer or multi-layer structure. It should be noted that the cap material layer 244 preferably has a relatively large thickness T13, for example, about 140 Å to 250 Å, which is greater than the thickness T11 of the first capping layer 142 (such as about 30 Å to 150 Å), but not limited thereto.
[0073] As Figure 4 shown, a selective thermal oxidation process P1 is performed through a mask layer (not shown), for example, a rapid thermal oxidation (RTO) process, to consume the top of the cap material layer 244 and further oxidize the top of the cap material layer 244 to form a sacrificial layer 244a. It should be noted that the thickness T3 of the sacrificial layer 244a varies according to the overall thickness of the cap structure 140 formed subsequently, for example, about 10 Å to 40 Å, but not limited thereto. Then, the mask layer is completely removed. In one embodiment, the rapid thermal oxidation process is performed, for example, by introducing oxygen at a temperature of about 700 °C to 900 °C, but not limited thereto.
[0074] As Figure 5As shown, at least one etching process P21 is performed to remove the sacrificial layer 244a, such that the remaining portion of the capping material layer 244 forms a second capping layer 144 with a relatively small thickness T12. Herein, the thickness T12 of the second capping layer 144 is less than the original thickness T13 of the capping material layer 244 and greater than the thickness T11 of the first capping layer 142. Thus, the first capping layer 142 and the second capping layer 144 stacked in sequence on the epitaxial structure 120 together form a capping structure 140 with an overall thickness T1. On the other hand, by performing at least one etching process P21, at least a portion of the dummy spacer 234 is removed to form a second spacer 134. In this embodiment, since a portion of the dummy spacer 234 is sandwiched between the first spacer 132 and the capping structure 140, affecting the contact with the etchant, a portion of the dummy spacer 234 covering the sidewall of the capping structure 140 and / or a portion of the dummy spacer 234 covering the top surface of the substrate 100 remains and respectively forms a vertical portion 134a and a horizontal portion 134b of the second spacer 134. Under this operation, the second spacer 134 can have an L-shaped cross-section as shown in Figure 5 and directly contact the capping structure 140, so as to maintain the distance R1 between the capping structure 140 and the gate structure 110.
[0075] As shown in Figure 6 , a deposition and etch-back process is sequentially performed to form a third spacer 136 on the second spacer 134. Specifically, the third spacer 136 directly covers the sidewall of the first spacer 132, such that the sidewall of the third spacer 136 is vertically aligned with the vertical portion 134a of the second spacer 134. Thus, the first spacer 132, the second spacer 134, and the third spacer 136 together form a spacer structure 130 disposed around the gate structure 110. In other words, the third spacer 136 is formed in the remaining space after removing the dummy spacer 234, such that the distance R1 between the capping structure 140 and the gate structure 110 can be maintained, and the thickness T1 of the capping structure 140 can also be precisely controlled by the aforementioned selective thermal oxidation process P1. Accordingly, the aspect ratio (T1 / R1) of the thickness T1 of the capping structure 140 to the distance R1 between the capping structure 140 and the gate structure 110 can be precisely controlled between 1 and 3, preferably between 1.2 and 2.2, but not limited thereto.
[0076] Subsequently, after forming the third spacer 136, the salicidation process can be continued to form, on the capping structure 140, as shown in Figure 1The metal silicide layer 150 shown is formed, and the fabrication of the semiconductor device 10 in this embodiment is completed. Under this operation, the aspect ratio of the thickness T1 of the capping structure 140 of the semiconductor device 10 to the distance R1 between the capping structure 140 and the gate structure 110 can be accurately controlled, avoiding the regions with relatively dense current on both sides of the gate structure 110 from being affected by the capping structure 140 and / or the epitaxial structure 120, thereby improving the overall electrical performance of the semiconductor device 10 and effectively enhancing the operating performance of the semiconductor structure 10.
[0077] According to the method for forming a semiconductor device in this embodiment, by forming the second capping layer 144 in the capping structure 140 and the second spacer 134 in the spacer structure 130 respectively, the thickness T1 of the capping structure 140 and the distance R1 between the capping structure 140 and the gate structure 110 are precisely controlled, and the aspect ratio of the thickness T1 of the capping structure 140 to the distance R1 between the capping structure 140 and the gate structure 110 is controlled within a specific range to improve the overall electrical performance of the semiconductor device 10.
[0078] Those skilled in the art should easily understand that to meet actual requirements, there may be other aspects of the semiconductor device and its forming method of the present invention, which are not limited to the foregoing. The following will further describe other embodiments or variations of the semiconductor device and its forming method of the present invention. And for the sake of simplicity of description, the following description mainly details the differences between the embodiments, and the same parts will not be repeated. In addition, the same elements in the embodiments of the present invention are labeled with the same reference numerals for easy comparison between the embodiments.
[0079] Please refer to Figures 7 to 8 As shown, the figure shows a schematic diagram of the method for forming a semiconductor device 30 in the second embodiment of the present invention. The method for forming the semiconductor device 30 and its structure are generally the same as those of the semiconductor device 10 in the foregoing first embodiment, and the same parts will not be repeated. The main difference between this embodiment and the foregoing embodiment is that a second spacer 334 with a straight cross-section is formed.
[0080] Specifically, as Figure 7 shown, when performing at least one etching process P22 on the sacrificial layer 244a, by adjusting its etching parameters, only the partial dummy spacer 234 covering the top surface of the substrate 100 is retained to form the second spacer 334 of this embodiment. Among them, the second spacer 334 only directly contacts a part of the sidewall of the capping structure 140. And the third spacer 136 formed on the second spacer 334 can directly contact another part of the sidewall of the capping structure 140, as Figure 8As shown. Moreover, the sidewalls of the third spacer wall 136 are flush with the sidewalls of the second spacer wall 334. Thus, the first spacer wall 132, the second spacer wall 334, and the third spacer wall 136 of this embodiment together form a spacer wall structure 330 surrounding the gate structure 110. Then, after the third spacer wall 136 is formed, a metal silicide layer 150 is formed on the capping structure 140.
[0081] Under this operation, by forming the linear second spacer wall 334, the distance R1 between the capping structure 140 and the gate structure 110 can also be maintained, and the aspect ratio of the thickness T1 of the capping structure 140 of the semiconductor device 30 relative to the distance R1 between the capping structure 140 and the gate structure 110 can be accurately controlled within a certain value, such as between 1 and 3, preferably between 1.2 and 2.2. Similarly, it is possible to avoid the regions where the current is relatively concentrated on both sides of the gate structure 110 from being affected by the capping structure 140 and / or the epitaxial structure 120, thereby improving the overall electrical performance of the semiconductor device 30 and effectively enhancing the operating performance of the semiconductor structure 30.
[0082] Please refer to Figures 9 to 10 As shown, the figure is a schematic diagram of the formation method of the semiconductor device 50 in the third embodiment of the present invention. The formation method and structure of the semiconductor device 40 are generally the same as those of the semiconductor device 10 in the foregoing first embodiment, and the same parts will not be described again. The main difference between this embodiment and the foregoing embodiments is that the setting of the second spacer wall is omitted.
[0083] Specifically, as Figure 9 shown, when at least one etching process P23 is performed on the sacrificial layer 244a, the dummy spacer wall 234 is completely removed by adjusting its etching parameters. Then, as Figure 10 shown, the subsequently formed third spacer wall 136 is formed in the space after the dummy spacer wall 234 is removed, and the distance between the capping structure 140 and the gate structure 110 can also be maintained. In other words, only the first spacer wall 132 and the third spacer wall 136 are formed in this embodiment, and the third spacer wall 136 directly contacts the entire sidewall of the capping structure 140. Thus, the first spacer wall 132 and the third spacer wall 136 of this embodiment together form a spacer wall structure 530 surrounding the gate structure 110. Then, after the third spacer wall 136 is formed, a metal silicide layer 150 is formed on the capping structure 140.
[0084] Under this operation, by forming a dummy spacer 234 on the sidewalls of the gate structure 110 in advance before forming the capping structure 140, the distance R1 between the capping structure 140 and the gate structure 110 is defined. Then, after the capping structure 140 is formed, the dummy spacer 234 is completely removed. Thus, the forming method of this embodiment can also control the aspect ratio of the thickness T1 of the capping structure 140 of the semiconductor device 40 relative to the distance R1 between the capping structure 140 and the gate structure 110 to a certain value, such as between 1 and 3, preferably between 1.2 and 2.2, so as to avoid the regions with relatively concentrated current on both sides of the gate structure 110 from being affected by the capping structure 140 and / or the epitaxial structure 120, thereby improving the overall electrical performance of the semiconductor device 50 and effectively enhancing the operating performance of the semiconductor structure 50.
[0085] Generally speaking, in the semiconductor device of the present invention, at least a second spacer that at least partially contacts the capping structure is provided between the capping structure and / or the epitaxial structure and the gate structure to precisely control the aspect ratio of the thickness of the capping structure relative to the distance between it and the gate structure, avoid the regions with relatively concentrated current on both sides of the gate structure from being affected by the capping structure and / or the epitaxial structure, improve the overall electrical performance of the semiconductor device, and further enhance the operating performance of the semiconductor structure. Accordingly, the semiconductor device of the present invention can be further applied to various functional semiconductor devices including epitaxial structures, such as metal oxide semiconductor transistor devices, or static random access memory devices, etc., but not limited thereto.
[0086] The above are only the preferred embodiments of the present invention, and all equivalent changes and modifications made according to the claims of the present invention should fall within the scope of the present invention.
Claims
1. A semiconductor device, characterized in that, Comprising: A substrate; A two-gate structure disposed on the substrate; A spacer structure disposed on the substrate and surrounding each of the gate structures respectively; An epitaxial structure disposed within the substrate and between the two gate structures; A capping structure disposed on the epitaxial structure and between the two gate structures; And A metal silicide layer disposed on the capping structure; Wherein, the spacer structure includes a first spacer, a second spacer, and a third spacer sequentially stacked on the sidewalls of each gate structure, and the second spacer contacts at least a part of the sidewall of the capping structure.
2. The semiconductor device according to claim 1, wherein, The second spacer includes an L-shaped cross-section, the vertical portion of the L-shaped cross-section covers the entire sidewall of the capping structure, and the horizontal portion of the L-shaped cross-section is disposed on the top surface of the substrate.
3. The semiconductor device according to claim 1, wherein, The second spacer includes a straight cross-section and is disposed on the top surface of the substrate.
4. The semiconductor device according to claim 3, wherein, The third spacer covers another part of the sidewall of the capping structure.
5. The semiconductor device according to claim 1, wherein, The material included in the second spacer is different from the materials of the first spacer or the third spacer.
6. The semiconductor device according to claim 1, wherein, The ratio of the thickness of the capping structure to the minimum distance from the capping structure to one of the two gate structures is 1.2 to 2.
2.
7. The semiconductor device according to claim 1, wherein, The capping structure includes a first capping layer and a second capping layer sequentially stacked on the epitaxial structure.
8. The semiconductor device according to claim 7, wherein, The second capping layer has a thickness of 130 to 210 angstroms.
9. The semiconductor device according to claim 1, wherein, The semiconductor device includes a static random access memory device.
10. A method for forming a semiconductor device, characterized in that, Comprising: Providing a substrate; Forming a two-gate structure on the substrate; Sequentially forming a first spacer and a dummy spacer on the substrate while surrounding the two gate structures; Forming an epitaxial structure within the substrate and between the two gate structures; Forming a capping structure on the epitaxial structure and between the two gate structures, the capping structure includes a first capping layer and a second capping layer sequentially stacked on the epitaxial structure; And Forming a metal silicide layer on the capping structure; Wherein, forming the capping structure further includes: Forming the first capping layer; Forming a capping material layer on the first capping layer; Oxidizing a part of the capping material layer; and Removing the oxidized part of the capping material layer to form the second capping layer on the first capping layer.
11. The method of forming a semiconductor device according to claim 10, wherein, The thickness of the second capping layer is less than the thickness of the capping material layer.
12. The method of forming a semiconductor device according to claim 11, wherein, The thickness of the oxidized part is between 10 and 40 angstroms, and the thickness of the capping material layer is between 140 and 250 angstroms.
13. The method of forming a semiconductor device according to claim 10, wherein, The epitaxial structure is formed after the first spacer is formed, and the first capping layer is formed after the dummy spacer is formed.
14. The method for forming a semiconductor device according to claim 10, further comprising: After oxidizing the part of the capping material layer, completely removing the dummy spacer; And Forming a third spacer surrounding the first spacer and each gate structure, wherein the metal silicide layer is formed after the third spacer is formed.
15. The method for forming a semiconductor device according to claim 10, further comprising: After oxidizing the part of the capping material layer, when removing the oxidized part of the capping material layer, partially removing the dummy spacer to form a second spacer, the second spacer contacts at least a part of the sidewall of the capping structure; and Forming a third spacer on the second spacer, the metal silicide layer is formed after the third spacer is formed.
16. The method for forming a semiconductor device according to claim 15, wherein, The second spacer wall includes an L-shaped cross-section or a straight cross-section.
17. The method of forming a semiconductor device according to claim 10, wherein, A rapid thermal oxidation process is performed to oxidize the capping material layer of this part.
18. The method of forming a semiconductor device according to claim 10, wherein, The ratio of the thickness of the capping structure to the minimum distance from the capping structure to one of the two gate structures is 1.2 to 2.2.