Semiconductor element with sidewall oxidation dielectric

Abstract

The invention discloses a semiconductor element with sidewall oxidation dielectric and a preparation method thereof. The semiconductor element comprises a substrate; a channel insulating layer disposed on the substrate; a floating gate disposed on the channel insulating layer; a lateral oxidation interposer disposed on the floating gate; and a control gate disposed on the lateral oxidation interposer. The lateral oxidation interposer includes a sidewall portion and a central portion, where the sidewall portion has a first oxygen concentration, the central portion has a second oxygen concentration, and the first oxygen concentration is greater than the second oxygen concentration.

Description

[0001] Cross-reference

[0002] This application claims priority to U.S. Patent Application No. 18 / 409,990 (i.e., the priority date is "January 11, 2024"), the content of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates to a semiconductor device and a method of manufacturing the same, and more particularly to a semiconductor device having a sidewall oxide dielectric and a method of manufacturing the same. Background Art

[0004] Semiconductor devices are used in a variety of electronic applications, including personal computers, mobile phones, digital cameras, and other electronic devices. To meet the growing demand for computing power, the size of semiconductor devices is continuously shrinking. However, the challenges associated with shrinking device size are increasing and having a greater impact. Therefore, there are still many challenges to overcome while improving quality, yield, performance, and reliability and reducing complexity.

[0005] The above description of "prior art" is provided only for background information and does not admit that the above description of "prior art" discloses the subject matter of the present disclosure, does not constitute prior art of the present disclosure, and any description of the above "prior art" should not be taken as any part of the present disclosure. Summary of the Invention

[0006] One aspect of the present disclosure provides a semiconductor device including a substrate; a channel insulating layer disposed on the substrate; a floating gate disposed on the channel insulating layer; a lateral oxidation intermediate layer disposed on the floating gate; and a control gate disposed on the lateral oxidation intermediate layer. The lateral oxidation intermediate layer includes a sidewall portion and a central portion, wherein the sidewall portion has a first oxygen concentration, the central portion has a second oxygen concentration, and the first oxygen concentration is greater than the second oxygen concentration.

[0007] In some embodiments, the semiconductor device further includes a plurality of doped regions disposed in the substrate.

[0008] In some embodiments, the semiconductor device further includes a first well region disposed in the substrate, wherein the plurality of doped regions are disposed in the first well region.

[0009] In some embodiments, the semiconductor device further includes a plurality of memory cell spacers disposed on the substrate, and the plurality of memory cell spacers are attached to a sidewall of the channel insulating layer.

[0010] In some embodiments, the semiconductor device further includes a memory top conductive layer disposed on the control gate.

[0011] In some embodiments, the lateral oxidation interlayer has a thickness that is between 10 angstroms and about 350 angstroms.

[0012] In some embodiments, the channel insulating layer has a first thickness, the lateral oxidation interlayer has a second thickness, the first thickness is different from the second thickness, and the channel insulating layer comprises a first material, the lateral oxidation interlayer comprises a second material, and the first material is different from the second material.

[0013] In some embodiments, the semiconductor device further comprises a passivation insulating layer disposed on the substrate, and the passivation insulating layer covers the top conductive layer of the memory and the memory cell spacer.

[0014] In some embodiments, the semiconductor device further comprises a plurality of first doped region contacts extending from a top surface of the passivation insulating layer into the doped region, wherein the first doped region contacts are electrically coupled to the doped region.

[0015] In some embodiments, the first doped region contact comprises a lower portion and an upper portion, wherein the lower portion of the first doped region contact extends into the doped region, and the upper portion of the first doped region contact is surrounded by the passivation insulating layer.

[0016] In some embodiments, the lower portion of the first doped region contact has a first critical dimension, the upper portion of the first doped region contact has a second critical dimension, and the second critical dimension is greater than the first critical dimension.

[0017] In some embodiments, the dimension of the first critical dimension at a position gradually decreases as the distance from the position to a top surface of the substrate increases, while the second critical dimension remains unchanged.

[0018] In some embodiments, the lower portion of the first doped region contact has a first peripheral surface, the upper portion of the first doped region contact has a second peripheral surface, and the first peripheral surface is discontinuous with the second peripheral surface.

[0019] In some embodiments, the lower portion of the first doped region contact and the upper portion of the first doped region contact are integrally formed.

[0020] In another embodiment, the semiconductor device further comprises a plurality of second doped region contacts extending from a top surface of the passivation insulating layer to a top surface of the substrate, wherein the second doped region contacts are electrically coupled to the doped region.

[0021] In some embodiments, the second doped region contact includes a barrier layer and a conductive layer disposed on and surrounded by the barrier layer, wherein the passivation insulating layer surrounds the barrier layer of the second doped region contact.

[0022] In some embodiments, the barrier layer has a third thickness on a sidewall of the corresponding conductive layer and a fourth thickness under a bottom surface of the corresponding conductive layer, and the third thickness is less than the fourth thickness.

[0023] Another aspect of the present disclosure provides a semiconductor device, which includes a substrate; a channel insulating layer disposed on the substrate; a floating gate disposed on the channel insulating layer; a lateral oxidation intermediate layer disposed on the floating gate; a control gate disposed on the lateral oxidation intermediate layer; and a selection unit disposed on the substrate. The selection unit includes a selection unit insulating layer and a selection unit conductive layer.

[0024] In some embodiments, the lateral oxidation intermediate layer includes a sidewall portion and a central portion, wherein the sidewall portion has a first oxygen concentration, the central portion has a second oxygen concentration, and the first oxygen concentration is greater than the second oxygen concentration.

[0025] In some embodiments, the selection unit is separated from the floating gate.

[0026] In some embodiments, the semiconductor device further includes a plurality of doped regions disposed in the substrate.

[0027] In some embodiments, the semiconductor device further includes a first well region disposed in the substrate, wherein the plurality of doped regions are disposed in the first well region.

[0028] In some embodiments, the semiconductor device further includes a plurality of selection unit spacers disposed on a sidewall of the selection unit.

[0029] In some embodiments, the semiconductor device further includes a selection unit top conductive layer disposed on the selection unit.

[0030] In some embodiments, the selection unit insulating layer has a first thickness, and the first thickness is between about 5 angstroms and about 50 angstroms.

[0031] In some embodiments, the selection unit conductive layer has a second thickness, and the second thickness is between about 150 nanometers and about 300 nanometers.

[0032] In some embodiments, the semiconductor device further includes a passivation insulating layer disposed on the substrate, wherein the passivation insulating layer covers the selection unit top conductive layer and the selection unit spacers.

[0033] In some embodiments, the semiconductor element further includes a plurality of doped region contacts extending from a top surface of the passivation insulating layer to a top surface of the substrate, wherein the doped region contacts are electrically coupled to the doped regions.

[0034] In some embodiments, the doped region contact includes a lower portion and an upper portion, wherein the lower portion of the doped region contact extends into the doped region, and the upper portion of the doped region contact is surrounded by the passivation insulating layer.

[0035] In some embodiments, the lower portion of the doped region contact has a first critical dimension, the upper portion of the doped region contact has a second critical dimension, and the second critical dimension is greater than the first critical dimension.

[0036] In some embodiments, the dimension of the first critical dimension at a position gradually decreases as the distance from the position to a top surface of the substrate increases, while the second critical dimension remains unchanged.

[0037] In some embodiments, the lower portion of the doped region contact has a first peripheral surface, the upper portion of the doped region contact has a second peripheral surface, and the first peripheral surface is discontinuous with the second peripheral surface.

[0038] In some embodiments, the lower portion of the doped region contact and the upper portion of the doped region contact are integrally formed.

[0039] In some embodiments, the doped region contact includes a barrier layer and a conductive layer disposed on and surrounded by the barrier layer, wherein the passivation insulating layer surrounds the barrier layer of the doped region contact.

[0040] In some embodiments, the barrier layer has a third thickness on a sidewall of the corresponding conductive layer and a fourth thickness under a bottom surface of the corresponding conductive layer, and the third thickness is less than the fourth thickness.

[0041] Another aspect of the present disclosure provides a method for manufacturing a semiconductor element, the manufacturing method including: providing a substrate; forming a first well region and an isolation structure in the substrate; forming a memory cell, a control unit, and a selection unit on the substrate; forming a plurality of doped regions in the substrate; performing a lateral oxidation process on the substrate; forming a plurality of memory cell spacers, a memory top conductive layer, a plurality of selection unit spacers, and a selection unit top conductive layer on the substrate; forming a passivation insulating layer on the substrate; and forming a plurality of doped region contacts in the passivation insulating layer.

[0042] In some embodiments, the process temperature of the lateral oxidation process is between about 300 °C and about 600 °C.

[0043] In some embodiments, the memory cell includes a channel insulating layer, a memory cell conductive layer, and a lateral oxidation intermediate layer.

[0044] In some embodiments, the selection unit includes a selection unit insulating layer and a selection unit conductive layer.

[0045] In some embodiments, the doped region contact includes a lower portion and an upper portion, wherein the lower portion of the doped region contact extends into the doped region, and the upper portion of the doped region contact is surrounded by the passivation insulating layer.

[0046] Due to the design of the semiconductor device of the present disclosure, the dielectric constant of the lateral oxidation intermediate layer increases. Therefore, the capacitive coupling between the control unit and the memory cell conductive layer becomes more effective. Accordingly, the performance of the semiconductor device can be improved.

[0047] The technical features and advantages of the present disclosure have been outlined quite widely above, so that the following detailed description of the present disclosure can be better understood. Other technical features and advantages constituting the subject matter of the claims of the present disclosure will be described below. Those skilled in the art to which the present disclosure pertains should understand that the concepts disclosed below and specific embodiments can be quite easily used as a basis for modifying or designing other structures or processes to achieve the same purpose as the present disclosure. Those skilled in the art to which the present disclosure pertains should also understand that such equivalent structures cannot depart from the spirit and scope of the present disclosure defined by the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] The disclosure of the present application can be more fully understood when considering the detailed description and the claims in conjunction with the drawings. It should be noted that, in accordance with industry standard practice, the various features are not drawn to scale. For ease of discussion, the dimensions of the various features can be increased or decreased arbitrarily.

[0049] Figure 1 is a top view illustrating a semiconductor device of some embodiments of the present disclosure.

[0050] Figure 2 is a cross-sectional view illustrating an embodiment of the present disclosure along Figure 1 line A - A' in

[0051] Figure 3 is a cross-sectional view illustrating some embodiments of the present disclosure along Figure 1 line B - B' in

[0052] Figure 4 is a cross-sectional view illustrating various embodiments of the present disclosure along Figure 1 line A - A' in

[0053] Figure 5 is a flowchart illustrating a method for manufacturing a semiconductor device of some embodiments of the present disclosure.

[0054] Figure 6 is a top view, illustrating an intermediate stage of the preparation of a semiconductor device according to some embodiments of the present disclosure.

[0055] Figure 7 is a cross-sectional view, illustrating some embodiments of the present disclosure along Figure 6 the line A-A' in

[0056] Figure 8 is a cross-sectional view, illustrating some embodiments of the present disclosure along Figure 6 the line B-B' in

[0057] Figure 9 is a top view, illustrating an intermediate stage of the preparation of a semiconductor device according to some embodiments of the present disclosure.

[0058] Figure 10 is a cross-sectional view, illustrating some embodiments of the present disclosure along Figure 9 the line A-A' in

[0059] Figure 11 is a cross-sectional view, illustrating some embodiments of the present disclosure along Figure 9 the line B-B' in

[0060] Figure 12 is a top view, illustrating an intermediate stage of the preparation of a semiconductor device according to some embodiments of the present disclosure.

[0061] Figure 13 is a cross-sectional view, illustrating some embodiments of the present disclosure along Figure 12 the line A-A' in

[0062] Figure 14 is a cross-sectional view, illustrating some embodiments of the present disclosure along Figure 12 the line B-B' in

[0063] Figure 15 is a top view, illustrating an intermediate stage of the preparation of a semiconductor device according to some embodiments of the present disclosure.

[0064] Figure 16 is a cross-sectional view, illustrating some embodiments of the present disclosure along Figure 15 the line A-A' in

[0065] Figure 17 is a cross-sectional view, illustrating some embodiments of the present disclosure along Figure 15 the line B-B' in

[0066] Figure 18 is a top view, illustrating an intermediate stage of the preparation of a semiconductor device according to some embodiments of the present disclosure.

[0067] Figure 19is a cross-sectional view illustrating some embodiments of the present disclosure along Figure 18 the line A-A' in

[0068] Figure 20 is a cross-sectional view illustrating some embodiments of the present disclosure along Figure 18 the line B-B' in

[0069] Figure 21 is a top view illustrating an intermediate stage of the preparation of a semiconductor element according to some embodiments of the present disclosure.

[0070] Figure 22 is a cross-sectional view illustrating some embodiments of the present disclosure along Figure 21 the line A-A' in

[0071] Figure 23 is a cross-sectional view illustrating some embodiments of the present disclosure along Figure 21 the line B-B' in

[0072] Figure 24 is a cross-sectional view illustrating some embodiments of the present disclosure along Figure 21 the line A-A' in

[0073] Figure 25 is a cross-sectional view illustrating some embodiments of the present disclosure along Figure 21 the line B-B' in

[0074] Figure 26 is a cross-sectional view illustrating some embodiments of the present disclosure along Figure 21 the line A-A' in

[0075] Figure 27 is a cross-sectional view illustrating some embodiments of the present disclosure along Figure 21 the line B-B' in

[0076] Figure 28 is a top view illustrating an intermediate stage of the preparation of a semiconductor element according to some embodiments of the present disclosure.

[0077] Figure 29 is a cross-sectional view illustrating some embodiments of the present disclosure along Figure 28 the line A-A' in

[0078] Figure 30 is a cross-sectional view illustrating some embodiments of the present disclosure along Figure 28 the line B-B' in

[0079] Figures 31 to 35 is a cross-sectional view illustrating some embodiments of the present disclosure along Figure 28 the line A-A' in

[0080] Explanation of reference numerals:

[0081] 10: First Region

[0082] 20: Second Region

[0083] 30: Preparation Method

[0084] 100A: Semiconductor Element

[0085] 100B: Semiconductor Element

[0086] 101: Substrate

[0087] 101TS: Top Surface

[0088] 103: Isolation Structure

[0089] 105: Passivation Insulating Layer

[0090] 105TS: Top Surface

[0091] 107: First Well Region

[0092] 108: Second Contact Hole

[0093] 201: Memory Cell

[0094] 203: Handle Portion

[0095] 205: Fork Portion

[0096] 207: Channel Insulating Layer

[0097] 209: Lateral Oxidation Interlayer

[0098] 211: Memory Cell Conductive Layer

[0099] 213: Memory Cell Spacer

[0100] 217: Memory Top Conductive Layer

[0101] 301: First Doped Region

[0102] 303: Second Doped Region

[0103] 305: Third Doped Region

[0104] 401: Selection Unit

[0105] 403: Selection Unit Insulating Layer

[0106] 405: Selection Unit Conductive Layer

[0107] 407: Selection Unit Top Conductive Layer

[0108] 409: Selection Unit Spacer

[0109] 501: Control Unit

[0110] 600: Sacrificial film

[0111] 602: Sacrificial pad

[0112] 603A: Doped region contact

[0113] 603B: Doped region contact

[0114] 605: First contact hole

[0115] 613: Upper part

[0116] 615: Peripheral surface

[0117] 633: Lower part

[0118] 635: Peripheral surface

[0119] 653: Conductive layer

[0120] 653B: Bottom surface

[0121] 653S: Side wall

[0122] 673: Barrier layer

[0123] 701: First mask layer

[0124] 703: Bottom insulating layer

[0125] 705: Bottom conductive layer

[0126] 707: Interlayer

[0127] 707': Interlayer

[0128] 709: Top conductive layer

[0129] 709': Top conductive layer

[0130] 711: Second mask layer

[0131] 801: Oxide species

[0132] CD1: First critical dimension

[0133] CD2: Second critical dimension

[0134] CP: Central part

[0135] H1: Thickness

[0136] H2: Thickness

[0137] H3: Thickness

[0138] H4: Thickness

[0139] S1: Side wall

[0140] S2: Side wall

[0141] S3: Side wall

[0142] S4: Side wall

[0143] S11: Step

[0144] S13: Step

[0145] S15: Step

[0146] S17: Step

[0147] S19: Step

[0148] SP: Side wall portion

[0149] T1: First thickness

[0150] T2: Second thickness

[0151] W1: First width

[0152] W2: Second width

[0153] X: Second direction

[0154] Y: First direction

[0155] Z: Direction Detailed implementation manners

[0156] The following disclosure provides many different embodiments, or examples, for implementing different features of the provided claims. To simplify the present disclosure, specific examples of elements and arrangements are described below. Of course, these are merely examples and are not intended to be restrictive. For example, in the following description, the formation of a first feature on or above a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. Additionally, the present disclosure may repeat reference numerals and / or letters in various embodiments. This repetition is for simplicity and clarity and does not in itself determine the relationship between the various embodiments and / or configurations discussed.

[0157] In addition, relative spatial terms, such as "beneath", "below", "lower", "above", "upper", etc., are used herein for ease of description to describe the relationship of one element or feature to another (s) element or feature shown in the figures. Relative spatial terms are intended to include different orientations of the element in use or operation, as well as the orientations described in the figures. The element may have other orientations (rotated 90 degrees or other orientations), and the relative spatial descriptors used herein may be interpreted accordingly.

[0158] It should be understood that when an element or layer is referred to as "connected to" or "coupled to" another element or layer, it can be directly connected to or coupled to the other element or layer, or there may be intervening elements or layers.

[0159] It should be understood that although terms such as first and second may be used herein to describe various elements, these elements should not be limited by these terms. Unless otherwise specified, these terms are only used to distinguish one element from another. Thus, for example, a first element, first component, or first portion discussed below may be referred to as a second element, second component, or second portion without departing from the teachings of the present disclosure.

[0160] Unless the context otherwise indicates, when referring to directions, layouts, positions, shapes, sizes, quantities, or other measures herein, terms such as "same", "equal", "planar", or "coplanar" do not necessarily refer to exactly the same direction, layout, position, shape, size, quantity, or other measure, but rather refer to within an acceptable range of variation that may occur, for example, due to the manufacturing process, and include nearly the same direction, layout, position, shape, size, quantity, or other measure. The term "substantially" may be used herein to reflect this meaning. For example, an item described as "substantially the same", "substantially equal", or "substantially planar" may be exactly the same, equal, or planar, or may be the same, equal, or planar within an acceptable range of variation, such as variation that may occur due to the manufacturing process.

[0161] In the present disclosure, a semiconductor element generally refers to an element that can function by utilizing semiconductor characteristics, and optoelectronic elements, light-emitting display elements, semiconductor circuits, and electronic elements are all included within the scope of semiconductor elements.

[0162] It should be noted that in the description of the present disclosure, the arrow direction above (or upper) corresponds to the direction of the arrow in the Z direction, and the arrow direction below (or lower) corresponds to the opposite direction of the arrow in the Z direction.

[0163] Figure 1 is a top view illustrating a semiconductor element 100A of some embodiments of the present disclosure. Figure 2 is along Figure 1 a cross-sectional view taken along line A - A' in Figure 3 is along Figure 1 a cross-sectional view taken along line B - B' in

[0164] Refer to Figures 1 to 3, the semiconductor device 100A includes a substrate 101, an isolation structure 103, a passivation insulating layer 105, a first well region 107, a memory cell 201, a memory top conductive layer 217, a first doped region 301, a second doped region 303, a third doped region 305, a selection unit 401, a selection unit top conductive layer 407, a control unit 501, and a doped region contact 603A.

[0165] Referring to Figures 1 to 3 , the substrate 101 includes a first region 10 and a second region 20. The second region 20 is adjacent to the first region 10. The substrate 101 includes, for example, silicon, doped silicon, germanium, silicon germanium, silicon carbide, silicon germanium carbide, gallium, gallium arsenide, indium arsenide, indium phosphide, or other IV-IV, III-V, or II-VI semiconductor materials. In some embodiments, the substrate 101 includes doped silicon and has a first electrical type. The substrate 101 is doped with a dopant such as boron.

[0166] It should be noted that the first region 10 may include a part of the substrate 101 and the space above this part of the substrate 101. Disposing an element on the first region 10 means disposing the element on a top surface of this part of the substrate 101. Disposing an element in the first region 10 means disposing the element within this part of the substrate 101; however, a top surface of the element may be flush with the top surface of this part of the substrate 101. Disposing an element above the first region 10 means disposing the element above the top surface of this part of the substrate 101. Therefore, the second region 20 may include another part of the substrate 101 and the space above this other part of the substrate 101.

[0167] See Figures 1 to 3 , the first well region 107 is disposed in the first region 10 and the second region 20 of the substrate 101. The first well region 107 is doped with a dopant such as phosphorus, arsenic, or antimony and has a second electrical property.

[0168] Referring to Figures 1 to 3 , the isolation structure 103 is disposed in the first region 10 and the second region 20 of the substrate 101. In some embodiments, the isolation structure 103 includes an insulating material such as silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, or fluorinated silicate.

[0169] It should be noted that in the present disclosure, silicon oxynitride refers to a substance containing silicon, nitrogen, and oxygen, where the proportion of oxygen is greater than the proportion of nitrogen. Silicon nitride oxide refers to a substance containing silicon, oxygen, and nitrogen, where the proportion of nitrogen is greater than the proportion of oxygen.

[0170] See Figures 1 to 3, the memory cell 201 is disposed on the first region 10 and the second region 20. The memory cell 201 includes a channel insulating layer 207, a memory cell conductive layer 211, and a lateral oxidation intermediate layer 209. The memory cell 201 has sidewalls S1 and S2. That is, the sidewalls of the channel insulating layer 207, the sidewalls of the memory cell conductive layer 211, and the sidewalls of the lateral oxidation intermediate layer 209 are aligned with each other, and each side is coplanar. The portion of the memory cell 201 disposed on the first region 10 is referred to as the handle portion 203. The portion of the memory cell 201 disposed on the second region 20 is referred to as the fork portion 205. In a top view, one end of the fork portion 205 is connected to the handle portion 203. The other end of the fork portion 205 is divided into four segments, and each of the four segments extends along a direction away from the handle portion 203 and opposite to the first direction Y. The four portions of the fork 205 are shown in Figure 3 in a cross-sectional view.

[0171] Referring to Figure 2 and Figure 3 , the channel insulating layer 207 is disposed on the first region 10 and the second region 20 of the substrate 101. The thickness of the channel insulating layer 207 is between about 30 angstroms and 130 angstroms. The channel insulating layer 207 includes, for example, silicon oxide, silicon nitride, silicon oxynitride, oxynitride silicon oxide, aluminum oxide, hafnium oxide, zirconium oxide, or a combination thereof.

[0172] Referring to Figure 2 and Figure 3 , the memory cell conductive layer 211 is disposed above the first region 10 and the second region 20 of the substrate 101. The memory cell conductive layer 211 is respectively disposed on the channel insulating layer 207. The memory cell conductive layer 211 includes materials such as polysilicon or polysilicon-germanium.

[0173] Referring to Figure 2 and Figure 3 , the lateral oxidation intermediate layer 209 is disposed above the first region 10 and the second region 20 of the substrate 101. The lateral oxidation intermediate layer 209 is respectively disposed on the memory cell conductive layer 211. The lateral oxidation intermediate layer 209 includes, for example, an insulating material having a dielectric constant of about 4.0 or a larger dielectric constant. Alternatively, in another embodiment, the insulating material is silicon oxide, silicon nitride, silicon oxynitride, oxynitride silicon oxide, or a similar material. The lateral oxidation intermediate layer 209 has a higher oxygen concentration in the sidewall portion SP of the lateral oxidation intermediate layer 209 than in the central portion CP of the lateral oxidation intermediate layer 209. The thickness of the lateral oxidation intermediate layer 209 is between 10 angstroms and about 350 angstroms. The thickness H2 of the lateral oxidation intermediate layer 209 is different from the thickness H1 of the channel insulating layer 207, and the lateral oxidation intermediate layer 209 includes a material different from the channel insulating layer 207.

[0174] Reference Figure 2 and Figure 3 ,The control unit 501 is disposed above the first region 10 and the second region 20 of the substrate 101. The control unit 501 is respectively disposed on the lateral oxidation interlayer 209. The control unit 501 includes materials such as polysilicon or polysilicon-germanium. It should be noted that, from the cross-sectional view, the sidewalls of the control unit 501 are substantially aligned with the sidewalls S1 and S2 of the memory cell.

[0175] Reference Figure 2 and Figure 3 ,The memory top conductive layer 217 is disposed above the first region 10 and the second region 20 of the substrate 101. The memory top conductive layer 217 is respectively disposed on the control unit 501. The memory top conductive layer 217 includes, for example, metal silicide.

[0176] Reference Figure 2 and Figure 3 ,The memory cell spacer 213 is disposed on the sidewalls of the control unit 501 and the sidewalls S1 and S2 of the memory cell 201. The memory cell spacer 213 includes, for example, silicon oxide, silicon nitride, silicon oxynitride, or silicon oxynitride.

[0177] Reference Figures 1 to 3 ,The selection unit 401 is disposed on the first region 10 and the second region 20 of the substrate 101. The selection unit 401 is separated from the memory cell 201 along the second direction X perpendicular to the first direction Y. The selection unit 401 includes a selection unit insulating layer 403 and a selection unit conductive layer 405. The selection unit insulating layer 403 is disposed on the substrate 101. The selection unit conductive layer 405 is disposed on the selection unit insulating layer 403. The selection unit 401 has sidewalls S3 and S4. The sidewalls of the selection unit insulating layer 403 and the sidewalls of the selection unit conductive layer 405 are aligned with each other and coplanar on each side. The thickness of the selection unit insulating layer 403 is between about 5 angstroms and about 50 angstroms. It should be noted that the thickness of the selection unit insulating layer 403 can be arbitrarily set according to specific circumstances. For example, the selection unit insulating layer 403 includes an insulating material with a dielectric constant of about 4.0 or a larger dielectric constant. Alternatively, in some embodiments, the insulating material includes silicon oxide, silicon nitride, silicon oxynitride, silicon oxynitride, or similar materials. The thickness of the selection unit conductive layer 405 is between about 150 nanometers and about 300 nanometers. The selection unit conductive layer 405 includes, for example, doped polysilicon.

[0178] Please refer to Figures 1 to 3, the top conductive layer 407 of the selection unit is disposed above the first region 10 and the second region 20 of the substrate 101. The top conductive layer 407 of the selection unit is disposed on the selection unit conductive layer 405. The top conductive layer 407 of the selection unit includes, for example, metal silicide. The metal silicide includes nickel silicide, platinum silicide, titanium silicide, molybdenum silicide, cobalt silicide, tantalum silicide, tungsten silicide, etc.

[0179] Refer to Figures 1 to 3 , on the sidewalls of the selection unit insulating layer 403 and the selection unit conductive layer 405 (i.e., the sidewalls S3 and S4 of the selection unit 401), there is a selection unit spacer 409. The selection unit spacer 409 includes, for example, silicon oxide, silicon nitride, silicon oxynitride, or oxynitride silicon oxide.

[0180] See Figure 2 , the first doped region 301, the second doped region 303, and the third doped region 305 are disposed in the first well region 107. The doped regions 303, 305, and 307 are doped with a dopant such as boron and thus have the first electrical type. The first doped region 301 is adjacent to one side of the channel insulating layer 207. A part of the top surface of the first doped region 301 is in contact with the bottom of the channel insulating layer 207. The second doped region 303 is adjacent to the other side of the channel insulating layer 207. One side of the second doped region 303 is in contact with the bottom of the channel insulating layer 207. The other side of the second doped region 303 is adjacent to one side of the selection unit insulating layer 403. The third doped region 305 is adjacent to the other side of the selection unit insulating layer 403.

[0181] Refer to Figures 1 to 3 , the doped region contact 603A is disposed on the first region 10 of the substrate 101. The doped region contact 603A extends from the top surface 105TS of the passivation insulating layer 105 into the first doped region 301, the second doped region 303, or the third doped region 305 and is electrically coupled to the first doped region 301, the second doped region 303, or the third doped region 305. The doped region contact 603A is disposed on both sides of the handle portion 203 of the memory cell 201 or on both sides of the selection unit 401.

[0182] More specifically, the doped region contact 603A includes a lower portion 633 extending to the first doped region 301, the second doped region 303, or the third doped region 305, and an upper portion 613 disposed in the passivation insulating layer 105. The upper portion 613 of the doped region contact 603A is surrounded by the passivation insulating layer 105.

[0183] Still refer to Figures 1 to 3, the lower part 633 of the doped region contact 603A is lower than the top surface 101TS of the substrate 101 and has a first critical dimension CD1, while the upper part 613 of the doped region contact 603A is higher than the top surface 101TS of the substrate 101 and has a second critical dimension CD2 greater than the first critical dimension CD1. In some embodiments, the first critical dimension CD1 gradually decreases at positions farther from the top surface 101TS of the substrate 101, while the second critical dimension CD2 remains unchanged. In particular, the peripheral surface 635 of the lower part 633 of the doped region contact 603A is discontinuous with the peripheral surface 615 of the upper part 613 of the doped region contact 603A. It is noted that the lower part 633 and the upper part 613 of the doped region contact 603A are integrally formed. The doped region contact 603A includes, for example, doped polysilicon, metal, metal nitride, or metal silicide.

[0184] Figure 4 is a cross-sectional view illustrating another embodiment of the present disclosure along the Figure 1 line A-A' in Figure 1 . Figure 3 Referring to Figure 4 , the semiconductor element 100B is similar to the semiconductor element 100A in many aspects, and the description of similar features will not be repeated here.

[0185] See Figure 4 , the semiconductor element 100B includes a doped region contact 603B. The doped region contact 603B is disposed in the first region 10 of the substrate 101. The doped region contact 603B extends from the top surface 105TS of the passivation insulating layer 105 to the top surface 101TS of the substrate 101 and is electrically coupled to the first doped region 301, the second doped region 303, or the third doped region 305. The doped region contact 603B is disposed on both sides of the handle portion 203 of the memory cell 201 or on both sides of the selection unit 401.

[0186] More specifically, the doped region contact 603B includes a barrier layer 673 and a conductive layer 653 disposed on and surrounded by the barrier layer 673. The barrier layer 673 of the doped region contact 603B is surrounded by the passivation insulating layer 105.

[0187] Still referring to Figure 1 , Figure 3 and Figure 4, the barrier layer 673 has a first thickness T1 on the sidewall 653S of the corresponding conductive layer 653 and a second thickness T2 under the bottom surface 653B of the corresponding conductive layer 653. In some embodiments, the fabrication technique of the barrier layer 673 includes an anisotropic deposition process, so the first thickness T1 is less than the second thickness T2. In some embodiments, the anisotropic deposition process is a physical vapor deposition (PVD) process. The barrier layer 673 includes, for example, titanium (Ti), titanium nitride (TiN), or a combination thereof, and the conductive layer 653 includes tungsten (W). In some embodiments, the conductive layer 653 is separated from the passivation insulating layer 105, the first doped region 301, the second doped region 303, and the third doped region 305 by the barrier layer 673. In some embodiments, the fabrication technique of the conductive layer 653 includes a deposition process and a subsequent planarization process.

[0188] Figure 5 is a flowchart illustrating a method 30 for fabricating a semiconductor device 100A according to some embodiments of the present disclosure. Figure 6 is a top view illustrating an intermediate stage of fabricating a semiconductor device 100A by the fabrication method 30. Figure 7 is along Figure 6 the cross-sectional view taken along line A-A' in Figure 8 is along Figure 6 the cross-sectional view taken along line B-B' in

[0189] Referring to Figure 5 and Figures 6 to 8 , in step S11, a substrate 101 is provided, and a first well region 107 and an isolation structure 103 are formed in the substrate 101. The substrate 101 includes a first region 10 and a second region 20 adjacent to the first region 10. In some embodiments, the first well region 107 can be formed in the first region 10 and the second region 20 by a single-step implantation process or a multi-step implantation process. In some embodiments, the isolation structure 103 is formed in the first region 10 and the second region 20.

[0190] Figure 9 , 12 , 15, 18, and 21 are top views illustrating intermediate stages of fabricating a semiconductor device 100A by the fabrication method 30. Figure 10 , 13 , 16, 19, and 22 are cross-sectional views taken along Figure 9 , 12 , 15, 18, and 21 along line A-A' respectively. Figure 11 , 14 , 17, 20, and 23 are cross-sectional views taken along Figure 9 , 12 , 15, 18, and 21 along line B-B' respectively.

[0191] Referring to Figure 5and Figures 9 to 23 In step S13, a memory cell 201, a control unit 501, and a selection unit 401 are formed on a substrate 101, and a plurality of doped regions 301, 303, and 305 are formed in the substrate 101.

[0192] See Figures 9 to 11 As shown, a bottom insulating layer 703, a bottom conductive layer 705, an intermediate layer 707, and a top conductive layer 709 are sequentially deposited on the substrate 101. The bottom insulating layer 703 includes an insulating material having a dielectric constant of about 4.0 or greater. Alternatively, in some embodiments, the insulating material includes silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, or similar materials. The bottom conductive layer 705 includes, for example, polysilicon or polysilicon-germanium. The intermediate layer 707 includes a material different from the bottom insulating layer 703. In some embodiments, the intermediate layer 707 includes an insulating material having a dielectric constant of about 4.0 or greater (all dielectric constants mentioned herein are relative to vacuum unless otherwise specified). For example, an insulating material having a dielectric constant of about 4.0 or greater is hafnium oxide, zirconium oxide, aluminum oxide, titanium oxide, lanthanum oxide, strontium titanate, lanthanum aluminate, yttrium oxide, gallium trioxide, gadolinium gallium oxide, lead zirconate titanate, barium strontium titanate, or a mixture thereof. The top conductive layer 709 includes polysilicon or polysilicon-germanium. A first mask layer 701 can be used to perform a photolithography process to define the positions of the memory cell 201 and the selection unit 401.

[0193] Referring to Figures 12 to 14 After the photolithography process, an etching process, such as an anisotropic dry etching process, is performed to remove a portion of the top conductive layer 709, the intermediate layer 707, the bottom conductive layer 705, and the bottom insulating layer 703. The remaining portions remain in place to form a handle portion 203, a fork portion 205, and the selection unit 401. After the etching process, the bottom insulating layer 703 in the handle portion 203 and the fork portion 205 becomes a channel insulating layer 207 on the first region 10 and the second region 20, the bottom conductive layer 705 in the handle portion 203 and the fork portion 205 becomes a memory cell conductive layer 211 on the first region 10 and the second region 20, the intermediate layer 707 in the handle portion 203 and the fork portion 205 becomes a lateral oxidation intermediate layer 209 on the first region 10 and the second region 20, and the top conductive layer 709 in the handle portion 203 and the fork portion 205 becomes a control unit 501 on the first region 10 and the second region 20. In addition, on the first region 10 and the second region 20, a portion of the bottom insulating layer 703 becomes a selection unit insulating layer 403, a portion of the bottom conductive layer 705 becomes a selection unit conductive layer 405, a portion of the intermediate layer 707 becomes an intermediate layer 707', and a portion of the top conductive layer 709 becomes a top conductive layer 709'.

[0194] Refer to Figures 15 to 17 and pattern the second mask layer 711 to mask the second region 20. Perform an implantation process to form a plurality of doped regions in the first well region 107. The doped regions may include a first doped region 301, a second doped region 303, and a third doped region 305. The first doped region 301 and the second doped region 303 are respectively formed near the sidewalls of the channel insulating layer 207. The second doped region 303 is formed between the channel insulating layer 207 and the selection unit insulating layer 403. The third doped region 305 is opposite to the second doped region 303 and is adjacent to one sidewall of the selection unit insulating layer 403. After the implantation process is completed, remove the second mask layer 711.

[0195] Refer to Figures 18 to 23 and, from a top-down perspective, pattern the third mask layer 721 to mask the regions other than the selection unit 401. After forming the patterned third mask layer 721, perform an etching process, such as an anisotropic dry etching process, to remove the interlayer 707' and the top conductive layer 709' on the first region 10 and the second region 20. After the etching process is completed, remove the third mask layer 721.

[0196] Refer to Figure 5 and Figures 24 to 25 In step S15, perform a lateral oxidation process on the substrate 101 to oxidize the lateral oxidation interlayer 209. In the lateral oxidation process, the intermediate semiconductor element is placed in an oxidation environment that includes oxidation species 801 ( Figure 24 and Figure 25 represented by small circles). The oxidation species 801 diffuses from the sidewalls of the lateral oxidation interlayer 209 into the lateral oxidation interlayer 209 and fills the oxygen vacancies in the lateral oxidation interlayer 209. The process temperature of the lateral oxidation process is between about 300 °C and about 600 °C. Preferably, the process temperature of the lateral oxidation process is between about 400 °C and about 500 °C. The oxygen partial pressure of the lateral oxidation process is between about 100 mTorr and about 20 atm. Preferably, the oxygen partial pressure of the lateral oxidation process is between about 0.1 atm and about 1.0 atm. The duration of the lateral oxidation process is between about 10 minutes and about 6 hours. After the lateral oxidation process is completed, the threshold voltage of the lateral oxidation interlayer 209 increases. The oxidation species 801 is a molecule including oxygen, such as molecular oxygen, water vapor, nitric oxide, or nitrous oxide. The process temperature of the lateral oxidation process, the oxygen partial pressure of the lateral oxidation process, and the duration of the lateral oxidation process can jointly determine the oxidation degree of the lateral oxidation interlayer 209.

[0197] After the lateral oxidation process, the oxygen concentration in the sidewall portion of the lateral oxidation interlayer 209 is greater than the oxygen concentration in the central portion of the lateral oxidation interlayer 209. It should be noted that other oxygen partial pressures of the lateral oxidation process greater than or less than the above-mentioned oxygen partial pressure of the lateral oxidation process can also be adopted. Other lateral oxidation processes with a duration greater than or less than the above-mentioned duration of the lateral oxidation process can also be adopted. Generally, the duration of the lateral oxidation process can be shortened as the process temperature of the lateral oxidation process or the oxygen partial pressure of the lateral oxidation process increases. Alternatively, in another embodiment, when the duration of the lateral oxidation process is long, the oxygen concentrations in both the sidewall portion and the central portion of the lateral oxidation interlayer 209 will increase. In some embodiments, the oxygen concentration in the sidewall portion of the lateral oxidation interlayer 209 may be equal to the oxygen concentration in the central portion of the lateral oxidation interlayer 209.

[0198] Refer to Figure 5 and Figures 26 to 27 , in step S17, a plurality of memory cell spacers 213, a plurality of select cell spacers 409, a memory top conductive layer 217, and a select cell top conductive layer 407 are formed above the substrate 101. A spacer layer (not shown) is formed on the substrate 101. The spacer layer may cover the top surfaces of the control unit 501 and the select cell conductive layer 405, and may cover the sidewalls of the control unit 501, the sidewalls of the memory cells 201 (i.e., the sidewalls of the lateral oxidation interlayer 209, the memory cell conductive layer 211, and the channel insulating layer 207), and the sidewalls of the select cells 401 (i.e., the sidewalls of the select cell conductive layer 405 and the select cell insulating layer 403). An etching process, such as an anisotropic dry etching process, is performed on a part of the spacer layer to simultaneously form a plurality of memory cell spacers 213 and a plurality of select cell spacers 409.

[0199] Please refer to Figure 26 and Figure 27 , a self-aligned silicide process is performed to form a memory top conductive layer 217 on the control unit 501 and a select cell top conductive layer 407 on the select cell conductive layer 405.

[0200] Refer to Figure 5 and Figures 28 to 35 , in step S19, a passivation insulating layer 105 is formed on the substrate 101, and a plurality of doped region contacts 603A are formed in the passivation insulating layer 105.

[0201] Please refer to Figures 28 to 30, the passivation insulating layer 105 is formed to cover the top conductive layer 217 of the memory, the memory cell spacer 213, the top conductive layer 407 of the selection cell, and the selection cell spacer 409. A planarization process, such as chemical mechanical polishing, is performed on the passivation insulating layer 105 to provide a substantially flat surface for subsequent process steps.

[0202] Referring to Figure 28 and Figures 31 to 35 , a plurality of doped region contacts 603A can be subsequently formed on the plurality of doped regions 301, 303, and 305 on the first region 10.

[0203] Referring to Figure 31 , an etching process, such as an anisotropic dry etching process, is performed on a portion of the passivation insulating layer 105, thereby forming a plurality of first contact holes 605 exposing the doped regions 301, 303, and 305.

[0204] Referring to Figure 32 , a sacrificial film 600 is conformally formed on the exposed portions of the passivation insulating layer 105 and the exposed portions of the doped regions 301, 303, and 305. The sacrificial film 600 has a substantially uniform thickness, and the morphological structure is consistent with the morphological structures of the exposed portions of the passivation insulating layer 105 and the doped regions 301, 303, and 305. It should be noted that the sacrificial film 600 includes a dielectric material whose etching characteristics are different from those of the substrate 101. For example, the sacrificial film 600 can include a nitride, and the manufacturing technique includes deposition by CVD process, ALD process, or similar processes.

[0205] Referring to Figure 33 , a removal process is performed to remove at least a portion of the sacrificial film 600 covering the doped regions 301, 303, and 305. Specifically, an anisotropic etching process is used to remove the horizontal portions of the sacrificial film 600 on the doped regions 301, 303, and 305 and on the passivation insulating layer 105, while leaving the vertical portions of the sacrificial film 600 on the passivation insulating layer 105, thereby forming a plurality of sacrificial pads 602 in the first contact holes 605. The horizontal portions of the sacrificial film 600 are removed by an anisotropic etching process, and the chemical composition of the anisotropic etching process is selective for the material of the sacrificial film 600. In other words, when etching the horizontal portions of the sacrificial film 600, the materials of the substrate 101 and the passivation insulating layer 105 are not substantially removed.

[0206] See Figure 34, the portions of the doped regions 301, 303, and 305 exposed through the passivation insulating layer 105 and the sacrificial liner 602 are etched away. Thus, a plurality of second contact holes 108 connected to the first contact holes 605 are formed. The portions of the doped regions 301, 303, and 305 exposed through the passivation insulating layer 105 and the sacrificial liner 602 are anisotropically dry-etched using at least one reactive ion etching (RIE) process. For example, dry etching is performed through the first contact holes 605 to form the second contact holes 108 in the doped regions 301, 303, and 305.

[0207] Please refer to Figure 34 and Figure 35 , after the second contact holes 108 are formed, the sacrificial liner 602 is removed, and a conductive layer is deposited in the first contact holes 605 and the second contact holes 108 to form the doped region contacts 603A. The sacrificial liner 602 is removed using a stable process such as a wet etching process. As Figure 34 shown, the first contact holes 605 have a substantially uniform first width W1, while the second contact holes 108 have a non-uniform second width W2. In some embodiments, the second width W2 gradually decreases at positions farther from the top surface 101TS of the substrate 101. The doped region contacts 603A including polysilicon are deposited in the first and second contact holes 605 and 108 using, for example, a CVD process. The portions of the doped region contacts 603A in the substrate 101 may have a funnel shape. It should be noted that once the sacrificial liner 602 is removed, the portions of the doped region contacts 603A surrounded by the passivation insulating layer 105 may have a larger critical dimension; thus, the resistance of the passivation insulating layer 105 can be reduced. However, in some embodiments, if the material of the passivation insulating layer 105 has an acceptable resistivity, the sacrificial liner 602 remains in the resulting semiconductor device 100A. In these embodiments, a diffusion barrier layer with a substantially uniform thickness can be deposited on the exposed portions of the substrate 101 and the sacrificial liner 602 to prevent the passivation insulating layer 105 from peeling off or flaking from the sacrificial liner 602.

[0208] See Figure 35 , the doped region contacts 603A include lower portions 633 extending to the first doped region 301, the second doped region 303, or the third doped region 305 and upper portions 613 disposed in the passivation insulating layer 105. The upper portions 613 of the doped region contacts 603A are surrounded by the passivation insulating layer 105.

[0209] Due to the design of the semiconductor device 100A of the present disclosure, the dielectric constant of the lateral oxidation interlayer 209 can be increased. Thus, the capacitive coupling between the control unit 501 and the memory unit 201 may become more effective. Therefore, the performance of the semiconductor device 100A can be improved.

[0210] One aspect of the present disclosure provides a semiconductor device, which includes a substrate; a channel insulating layer disposed on the substrate; a floating gate disposed on the channel insulating layer; a lateral oxidation intermediate layer disposed on the floating gate; and a control gate disposed on the lateral oxidation intermediate layer. The lateral oxidation intermediate layer includes a sidewall portion and a central portion, wherein the sidewall portion has a first oxygen concentration, the central portion has a second oxygen concentration, and the first oxygen concentration is greater than the second oxygen concentration.

[0211] Another aspect of the present disclosure provides a semiconductor device, which includes a substrate; a channel insulating layer disposed on the substrate; a floating gate disposed on the channel insulating layer; a lateral oxidation intermediate layer disposed on the floating gate; a control gate disposed on the lateral oxidation intermediate layer; and a selection unit disposed on the substrate. The selection unit includes a selection unit insulating layer and a selection unit conductive layer.

[0212] Another aspect of the present disclosure provides a method for manufacturing a semiconductor device, the method comprising: providing a substrate; forming a first well region and an isolation structure in the substrate; forming a memory unit, a control unit, and a selection unit on the substrate; forming a plurality of doped regions in the substrate; performing a lateral oxidation process on the substrate; forming a plurality of memory unit spacers, a memory top conductive layer, a plurality of selection unit spacers, and a selection unit top conductive layer on the substrate; forming a passivation insulating layer on the substrate; and forming a plurality of doped region contacts in the passivation insulating layer.

[0213] Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions, and alternatives can be made without departing from the spirit and scope of the present disclosure as defined by the claims. For example, many of the processes described above can be implemented in different ways, and many of the processes described above can be replaced by other processes, or combinations thereof.

[0214] Furthermore, the scope of the present application is not limited to the specific embodiments of the processes, machines, manufactures, compositions of matter, means, methods, and steps described in the specification. Those skilled in the art can understand from the disclosure of the present disclosure that existing or future-developed processes, machines, manufactures, compositions of matter, means, methods, or steps that have the same function or achieve substantially the same result as the corresponding embodiments described herein can be used according to the present disclosure. Accordingly, these processes, machines, manufactures, compositions of matter, means, methods, or steps are included in the claims of the present application.

Claims

1. A semiconductor device, comprising: a substrate; a channel insulating layer disposed on the substrate; a floating gate disposed on the channel insulating layer; a lateral oxidation intermediate layer disposed on the floating gate, wherein the lateral oxidation intermediate layer includes a sidewall portion and a central portion, and the sidewall portion has a first oxygen concentration, the central portion has a second oxygen concentration, and the first oxygen concentration is greater than the second oxygen concentration; and a control gate disposed on the lateral oxidation intermediate layer.

2. The semiconductor device according to claim 1, further comprising a plurality of doped regions disposed in the substrate.

3. The semiconductor device according to claim 2, further comprising a first well region disposed in the substrate, wherein the plurality of doped regions are disposed in the first well region.

4. The semiconductor device according to claim 3, further comprising a plurality of memory cell spacers disposed on the substrate, and the plurality of memory cell spacers are attached to a sidewall of the channel insulating layer.

5. The semiconductor device according to claim 4, further comprising a memory top conductive layer disposed on the control gate.

6. The semiconductor device according to claim 5, wherein the lateral oxidation intermediate layer has a thickness, and the thickness is between 10 angstroms and about 350 angstroms.

7. The semiconductor device according to claim 6, wherein the channel insulating layer has a first thickness, the lateral oxidation intermediate layer has a second thickness, the first thickness is different from the second thickness, and the channel insulating layer includes a first material, the lateral oxidation intermediate layer includes a second material, and the first material is different from the second material.

8. The semiconductor device according to claim 7, further comprising a passivation insulating layer disposed on the substrate, and the passivation insulating layer covers the memory top conductive layer and the memory cell spacers.

9. The semiconductor device according to claim 8, further comprising a plurality of doped region contacts extending from a top surface of the passivation insulating layer into the plurality of doped regions, wherein the plurality of doped region contacts are electrically coupled to the plurality of doped regions.

10. The semiconductor device according to claim 9, wherein each of the plurality of doped region contacts includes a lower portion and an upper portion, the lower portions of the plurality of doped region contacts extend into the plurality of doped regions, and the upper portions of the plurality of doped region contacts are surrounded by the passivation insulating layer.

11. The semiconductor device according to claim 10, wherein the lower portions of the plurality of doped region contacts have a first critical dimension, the upper portions of the plurality of doped region contacts have a second critical dimension, and the second critical dimension is greater than the first critical dimension.

12. The semiconductor device according to claim 11, wherein the dimension of the first critical dimension at a position gradually decreases as the distance from the position to a top surface of the substrate increases, while the second critical dimension remains unchanged.

13. The semiconductor device according to claim 12, wherein the lower portions of the plurality of doped region contacts have a first peripheral surface, the upper portions of the plurality of doped region contacts have a second peripheral surface, and the first peripheral surface is discontinuous with the second peripheral surface.

14. The semiconductor device as claimed in claim 13, wherein the lower portions of the plurality of doped regions in contact respectively and the upper portions of the plurality of doped regions in contact are integrally formed.

15. The semiconductor device as claimed in claim 8, further comprising a plurality of doped region contacts extending from a top surface of the passivation insulating layer to a top surface of the substrate, wherein the plurality of doped region contacts are electrically coupled to the plurality of doped regions.

16. The semiconductor device as claimed in claim 15, wherein each of the plurality of doped region contacts includes a barrier layer and a conductive layer disposed on and surrounded by the barrier layer, wherein the passivation insulating layer surrounds the barrier layer of the plurality of doped region contacts.

17. The semiconductor device as claimed in claim 16, wherein the barrier layer has a third thickness on a sidewall of the conductive layer and a fourth thickness under a bottom surface of the conductive layer, and the third thickness is less than the fourth thickness.

18. A semiconductor device, comprising: a substrate; a channel insulating layer disposed on the substrate; a floating gate disposed on the channel insulating layer; a lateral oxidation intermediate layer disposed on the floating gate; a control gate disposed on the lateral oxidation intermediate layer; and a selection unit disposed on the substrate, wherein the selection unit includes a selection unit insulating layer and a selection unit conductive layer.

19. The semiconductor device as claimed in claim 18, wherein the selection unit is separated from the floating gate.

20. The semiconductor device as claimed in claim 19, further comprising a plurality of doped regions disposed in the substrate.

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