Semiconductor device

Abstract

The invention relates to a semiconductor device. Provided is a semiconductor device having high field-effect mobility. The present invention includes an oxide semiconductor, a first conductor and a second conductor separated from each other on the oxide semiconductor, and a first insulator disposed on the first conductor and the second conductor and having an opening overlapping a region between the first conductor and the second conductor. A second insulator disposed in the opening of the first insulator and in contact with the top surface of the oxide semiconductor, the side surface of the first conductor, the side surface of the second conductor, and the side surface of the first insulator; and a third conductor disposed on the second insulator in the opening of the first insulator and having a region overlapping with the oxide semiconductor via the second insulator, the oxide semiconductor including a first layer, a second layer on the first layer, and a third layer on the second layer in the region overlapping with the third conductor, the first layer including gallium, the second layer including gallium, and the third layer including gallium. The second layer contains indium oxide, the third layer contains indium, gallium, and oxygen, and the indium content of the second layer is higher than the indium content of the third layer.

Description

Technical Field

[0001] One aspect of the present invention relates to a semiconductor device, a storage device, and an electronic device using an oxide semiconductor. Another aspect of the present invention relates to a method for manufacturing the semiconductor device described above.

[0002] Note that one aspect of the present invention is not limited to the above technical field. As an example of the technical field of one aspect of the present invention, semiconductor devices, display devices, light-emitting devices, power storage devices, storage devices, electronic devices, lighting devices, input devices (e.g., touch sensors), input / output devices (e.g., touch panels), and driving methods or manufacturing methods of the above devices can be cited.

[0003] Note that in this specification and the like, a semiconductor device refers to all devices that can operate by utilizing semiconductor characteristics. In addition to semiconductor elements such as transistors, semiconductor circuits, arithmetic units, and storage devices are also one aspect of semiconductor devices. Sometimes it can be said that display devices (liquid crystal display devices, light-emitting display devices, etc.), projection devices, lighting devices, electro-optical devices, power storage devices, storage devices, semiconductor circuits, imaging devices, electronic devices, etc. include semiconductor devices. Background Art

[0004] In recent years, semiconductor devices have been developed, and LSI (Large Scale Integration), CPU (Central Processing Unit), memories, etc. are mainly used for semiconductor devices. A CPU is an aggregate of semiconductor elements including a semiconductor integrated circuit (including at least transistors and memories) obtained by processing a semiconductor wafer into a chip and having electrodes as connection terminals formed thereon.

[0005] Semiconductor circuits (IC chips) such as LSI, CPU, and memories are mounted on a circuit board, for example, a printed wiring board, and are used as one of the components of various electronic devices.

[0006] In addition, a technique of forming a transistor using a semiconductor thin film formed on a substrate having an insulating surface has attracted attention. This transistor is widely used in electronic devices such as integrated circuits (ICs) and image display devices (simply referred to as display devices). As a semiconductor thin film that can be applied to a transistor, silicon-based semiconductor materials are widely known. As other materials, oxide semiconductors have attracted attention.

[0007] In addition, it is known that the leakage current of a transistor using an oxide semiconductor is extremely small in the non-conducting state. For example, Patent Document 1 has disclosed a low-power CPU or the like that applies the characteristic of small leakage current of a transistor using an oxide semiconductor. In addition, for example, Patent Document 2 has disclosed a storage device or the like that realizes long-term retention of stored content by utilizing the characteristic of small leakage current of a transistor using an oxide semiconductor.

[0008] [Patent Document 1] Japanese Patent Application Laid-Open No. 2012-257187

[0009] [Patent Document 2] Japanese Patent Application Laid-Open No. 2011-151383 Summary of the Invention

[0010] One of the objects of one embodiment of the present invention is to provide a semiconductor device having a high field-effect mobility. In addition, one of the objects of one embodiment of the present invention is to provide a semiconductor device having good electrical characteristics. In addition, one of the objects of one embodiment of the present invention is to provide a highly reliable semiconductor device. In addition, one of the objects of one embodiment of the present invention is to provide a semiconductor device that can be miniaturized or highly integrated. In addition, one of the objects of one embodiment of the present invention is to provide a semiconductor device with a high operating speed. In addition, one of the objects of one embodiment of the present invention is to provide a semiconductor device with low power consumption. In addition, one of the objects of one embodiment of the present invention is to provide a semiconductor device in which the electrical characteristics of transistors are less non-uniform. In addition, one of the objects of one embodiment of the present invention is to provide a novel semiconductor device. In addition, one of the objects of one embodiment of the present invention is to provide a method for manufacturing a semiconductor device with high productivity. In addition, one of the objects of one embodiment of the present invention is to provide a novel method for manufacturing a semiconductor device. In addition, one of the objects of one embodiment of the present invention is to provide a novel display device.

[0011] Note that the description of these objects does not preclude the existence of other objects. One embodiment of the present invention does not need to achieve all of the above objects. Objects other than the above can be extracted from the description of the specification, drawings, and claims.

[0012] One aspect of the present invention is a semiconductor device including an oxide semiconductor, a first conductor and a second conductor separated from each other on the oxide semiconductor, a first insulator disposed on the first conductor and the second conductor and having an opening overlapping a region between the first conductor and the second conductor, a second insulator disposed in the opening and in contact with the top surface of the oxide semiconductor, the side surfaces of the first conductor, the side surfaces of the second conductor, and the side surfaces of the first insulator, a third conductor disposed on the second insulator in the opening and having a region overlapping the oxide semiconductor with the second insulator therebetween, the oxide semiconductor including a first layer, a second layer on the first layer, and a third layer on the second layer in a region overlapping the third conductor, the first layer containing gallium and oxygen, the second layer containing indium oxide, the third layer containing indium, gallium, and oxygen, and the indium content rate of the second layer being higher than the indium content rate of the third layer.

[0013] In the above semiconductor device, preferably, the bottom of the conduction band of the first layer is closer to the vacuum level side than the bottom of the conduction band of the second layer, and the bottom of the conduction band of the third layer is closer to the vacuum level side than the bottom of the conduction band of the second layer.

[0014] In addition, in the above semiconductor device, preferably, the first layer contains indium, and the indium content rate in the first layer is lower than the gallium content rate.

[0015] In addition, in the above semiconductor device, preferably, when viewed from a plane, the side surface of a part of the first insulator is aligned or substantially aligned with the side surfaces of the first conductor and the second conductor.

[0016] In addition, the above semiconductor device preferably further includes a third insulator in contact with the top surface of the third conductor, the upper end portion of the second insulator, and the top surface of the first insulator, and a fourth insulator in contact with the top surface of the third insulator.

[0017] In addition, in the above semiconductor device, the third insulator preferably contains aluminum oxide.

[0018] In addition, in the above semiconductor device, the fourth insulator preferably contains silicon nitride.

[0019] In addition, in the above semiconductor device, preferably, both the first conductor and the second conductor include a first conductive layer and a second conductive layer on the first conductive layer, and the shortest distance between the first conductive layers of the first conductor and the second conductor is smaller than the shortest distance between the second conductive layers of the first conductor and the second conductor.

[0020] In addition, in the above semiconductor device, preferably, when viewed from a plane, the side surface of a part of the first insulator is aligned or substantially aligned with the side surfaces of the second conductive layer of the first conductor and the second conductive layer of the second conductor.

[0021] In addition, in the above semiconductor device, the first conductive layer of the first conductor and the first conductive layer of the second conductor preferably contain tantalum nitride.

[0022] In addition, preferably, the above semiconductor device further includes a fifth insulator, which is disposed in the opening and contacts the top surface of the first conductive layer of the first conductor, the side surface of the second conductive layer of the first conductor, the top surface of the first conductive layer of the second conductor, and the side surface of the second conductive layer of the second conductor. The fifth insulator has an opening overlapping with the region between the first conductive layer of the first conductor and the first conductive layer of the second conductor.

[0023] In addition, in the above semiconductor device, the fifth insulator preferably contains silicon nitride.

[0024] In addition, in the above semiconductor device, preferably, the second insulator includes a first insulating layer, and the first insulating layer contains an oxide containing hafnium.

[0025] In addition, in the above semiconductor device, the first insulating layer preferably contains hafnium zirconium oxide.

[0026] In addition, in the above semiconductor device, preferably, the second insulator includes a second insulating layer on the first insulating layer, and the second insulating layer contains silicon nitride.

[0027] According to one aspect of the present invention, a semiconductor device with a high field-effect mobility can be provided. In addition, according to one aspect of the present invention, a semiconductor device with good electrical characteristics can be provided. In addition, according to one aspect of the present invention, a semiconductor device with high reliability can be provided. In addition, according to one aspect of the present invention, a semiconductor device that can be miniaturized or highly integrated can be provided. In addition, according to one aspect of the present invention, a semiconductor device with a high operating speed can be provided. In addition, according to one aspect of the present invention, a semiconductor device with low power consumption can be provided. In addition, according to one aspect of the present invention, a semiconductor device with less non-uniformity in the electrical characteristics of transistors can be provided. In addition, according to one aspect of the present invention, a novel semiconductor device can be provided. In addition, according to one aspect of the present invention, a manufacturing method of a semiconductor device with high productivity can be provided. In addition, according to one aspect of the present invention, a manufacturing method of a novel semiconductor device can be provided. In addition, according to one aspect of the present invention, a novel display device can be provided.

[0028] Note that the description of these effects does not preclude the existence of other effects. One aspect of the present invention does not necessarily have all of the above effects. Effects other than the above can be extracted from the descriptions in the specification, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1A is a plan view showing an example of a semiconductor device, Figures 1B to 1D is a cross-sectional view showing an example of a semiconductor device;

[0030] Figure 2A and Figure 2B is a cross-sectional view showing an example of a semiconductor device;

[0031] Figures 3A to 3E is a cross-sectional view showing an example of a semiconductor device;

[0032] Figure 4A is a plan view showing an example of a semiconductor device, Figures 4B to 4D is a cross-sectional view showing an example of a semiconductor device;

[0033] Figure 5A is a plan view showing an example of a semiconductor device, Figures 5B to 5D is a cross-sectional view showing an example of a semiconductor device;

[0034] Figures 6A to 6C is a cross-sectional view showing an example of a semiconductor device;

[0035] Figure 7A is a plan view showing an example of a semiconductor device, Figures 7B to 7D is a cross-sectional view showing an example of a semiconductor device;

[0036] Figure 8 is a cross-sectional view showing an example of a semiconductor device;

[0037] Figure 9A is a plan view showing an example of a manufacturing method of a semiconductor device, Figures 9B to 9D is a cross-sectional view showing an example of a manufacturing method of a semiconductor device;

[0038] Figure 10A is a plan view showing an example of a manufacturing method of a semiconductor device, Figures 10B to 10D is a cross-sectional view showing an example of a manufacturing method of a semiconductor device;

[0039] Figure 11A is a plan view showing an example of a manufacturing method of a semiconductor device, Figures 11B to 11D is a cross-sectional view showing an example of a manufacturing method of a semiconductor device;

[0040] Figure 12A is a plan view showing an example of a manufacturing method of a semiconductor device, Figures 12B to 12D is a cross-sectional view showing an example of a manufacturing method of a semiconductor device;

[0041] Figure 13A1 ,Figure 13A2 , Figure 13B1 , Figure 13B2 , Figure 13C1 , Figure 13C2 , Figure 13D1 and Figure 13D2 is a cross-sectional view showing an example of a method for manufacturing a semiconductor device;

[0042] Figure 14A is a plan view showing an example of a method for manufacturing a semiconductor device, Figures 14B to 14D is a cross-sectional view showing an example of a method for manufacturing a semiconductor device;

[0043] Figure 15A is a plan view showing an example of a method for manufacturing a semiconductor device, Figures 15B to 15D is a cross-sectional view showing an example of a method for manufacturing a semiconductor device;

[0044] Figure 16A is a plan view showing an example of a method for manufacturing a semiconductor device, Figures 16B to 16D is a cross-sectional view showing an example of a method for manufacturing a semiconductor device;

[0045] Figure 17 is a band diagram of an oxide semiconductor;

[0046] Figure 18 is a graph showing an example of a hysteresis characteristic;

[0047] Figures 19A to 19C is an equivalent circuit diagram of a semiconductor device, Figure 19D is a diagram for explaining the Id-Vg characteristics of a transistor;

[0048] Figure 20A is a timing diagram for explaining the operation of a semiconductor device, Figure 20B is a circuit diagram for explaining the operation of a semiconductor device;

[0049] Figure 21A is a timing diagram for explaining the operation of a semiconductor device, Figure 21B is a circuit diagram for explaining the operation of a semiconductor device;

[0050] Figure 22A is a timing diagram for explaining the operation of a semiconductor device, Figure 22B is a circuit diagram for explaining the operation of a semiconductor device;

[0051] Figure 23 is a block diagram showing an example of the structure of a semiconductor device;

[0052] Figures 24A to 24H is a diagram showing an example of the circuit structure of a memory cell;

[0053] Figure 25 is a cross-sectional view showing an example of a semiconductor device;

[0054] Figure 26A and Figure 26B is a perspective view illustrating an example of the structure of a semiconductor device;

[0055] Figure 27 is a cross-sectional view showing an example of a semiconductor device;

[0056] Figure 28 is a cross-sectional view showing an example of a semiconductor device;

[0057] Figure 29 is a block diagram illustrating a CPU;

[0058] Figure 30A and Figure 30B is a perspective view of a semiconductor device;

[0059] Figure 31A and Figure 31B is a perspective view of a semiconductor device;

[0060] Figure 32A and Figure 32B is a diagram showing the hierarchy of various storage devices;

[0061] Figure 33A and Figure 33B is a diagram showing an example of an electronic device, Figures 33C to 33E is a diagram showing an example of a mainframe computer;

[0062] Figure 34 is a diagram showing an example of a space device;

[0063] Figure 35 is a diagram showing an example of a storage system applicable to a data center;

[0064] Figure 36A and Figure 36B is an example of the structure of a display device;

[0065] Figure 37 is an example of the structure of a display device;

[0066] Figure 38 is an example of the structure of a display device;

[0067] Figure 39 is an example of the structure of a display device;

[0068] Figures 40A to 40D is an example of the structure of a display device;

[0069] Figure 41A andFigure 41B is an example of the structure of a display device;

[0070] Figure 42A and Figure 42B is a diagram for explaining an example of the structure of a display device;

[0071] Figures 43A to 43D is a diagram for explaining an example of the structure of a display device;

[0072] Figures 44A to 44D is a diagram for explaining an example of the structure of a display device;

[0073] Figure 45 is a diagram for explaining an example of the structure of a display device;

[0074] Figures 46A to 46F is an example of the structure of an electronic device;

[0075] Figures 47A to 47F is an example of the structure of an electronic device;

[0076] Figures 48A to 48G is an example of the structure of an electronic device. Detailed implementation mode

[0077] The implementation mode will be described in detail with reference to the accompanying drawings. Note that the present invention is not limited to the following description, and it is easily understandable for those of ordinary skill in the art that the manner and details can be changed into various forms without departing from the gist and scope of the present invention. Therefore, the present invention should not be construed as being limited only to the content described in the following shown implementation mode.

[0078] Note that in the structure of the invention described below, the same reference numerals are used commonly among different drawings to denote the same parts or parts having the same functions, and the repeated description thereof is omitted. In addition, when denoting parts having the same functions, the same hatching is sometimes used without particularly attaching symbols.

[0079] In addition, for the sake of easy understanding, the positions, sizes, ranges, etc. of the respective constituent elements shown in the drawings do not represent their actual positions, sizes, ranges, etc. Therefore, the disclosed invention is not necessarily limited to the positions, sizes, ranges, etc. disclosed in the drawings.

[0080] In the present specification, etc., for convenience, ordinal numbers such as "first" and "second" are added, and they do not limit the number of constituent elements or the order of constituent elements (for example, the process order or the stacking order). In addition, the ordinal numbers attached to a constituent element in a certain part of the present specification are sometimes inconsistent with the ordinal numbers attached to the same constituent element in other parts of the present specification or in the claims.

[0081] In addition, "film" and "layer" can be interchanged according to circumstances or states. For example, "conductive layer" can be interchanged with "conductive film". In addition, "insulating film" can be interchanged with "insulating layer". Further, "oxide semiconductor film" can be interchanged with "oxide semiconductor layer". Additionally, according to circumstances or states, "conductor" can be interchanged with "conductive layer" or "conductive film". Additionally, according to circumstances or states, "insulator" can be interchanged with "insulating layer" or "insulating film". Additionally, according to circumstances or states, "oxide semiconductor" can be interchanged with "oxide semiconductor layer" or "oxide semiconductor film".

[0082] In this specification and the like, "parallel" means a state where the angle formed by two straight lines is -10° or more and 10° or less. Therefore, it also includes the state where the angle is -5° or more and 5° or less. "Substantially parallel" means a state where the angle formed by two straight lines is -20° or more and 20° or less. In addition, "perpendicular" means a state where the angle between two straight lines is 80° or more and 100° or less. Therefore, it also includes the state where the angle is 85° or more and 95° or less. "Substantially perpendicular" means a state where the angle formed by two straight lines is 70° or more and 110° or less.

[0083] An opening includes, for example, a groove, a slit, etc. In addition, the region where an opening is formed is sometimes referred to as an opening portion.

[0084] In addition, the drawings used in this specification and the like show a case where the side wall of the insulator in the opening of the insulator is perpendicular or substantially perpendicular to the substrate surface or the formation surface, but the side wall can also be a conical shape.

[0085] Note that in this specification and the like, a conical shape means a shape in which at least a part of the side surface of a constituent element is inclined with respect to the substrate surface or the formation surface. For example, a region having an angle (hereinafter, sometimes also referred to as a cone angle) formed by the inclined side surface and the substrate surface or the formation surface less than 90° is preferable. Note that the side surface of the constituent element and the substrate surface do not necessarily have to be completely flat, and may be an approximately planar shape having a minute curvature or an approximately planar shape having fine irregularities.

[0086] In this specification and the like, a transistor using an oxide semiconductor or a metal oxide as a semiconductor layer and a transistor including an oxide semiconductor or a metal oxide in a channel formation region are sometimes referred to as an OS transistor. In addition, a transistor including silicon in a channel formation region is sometimes referred to as a Si transistor.

[0087] Embodiment 1

[0088] In this embodiment, with reference to Figures 1A to 16D a semiconductor device using an oxide semiconductor and a manufacturing method of the semiconductor device are described.

[0089] <Structural Example of Semiconductor Device>

[0090] Refer to Figures 1A to 1D and Figure 2A and Figure 2B Describe a structural example of a semiconductor device. Figures 1A to 1D It is a plan view and a cross-sectional view of a semiconductor device (transistor 200).

[0091] Figure 1A It is a plan view of the semiconductor device. Additionally, Figures 1B to 1D It is a cross-sectional view of the semiconductor device. Here, Figure 1B It is a cross-sectional view of the portion along the dash-dot line A1 - A2 in Figure 1A , and it is also a cross-sectional view in the channel length direction of transistor 200. Furthermore, Figure 1C It is a cross-sectional view of the portion along the dash-dot line A3 - A4 in Figure 1A , and it is also a cross-sectional view in the channel width direction of transistor 200. Additionally, Figure 1D It is a cross-sectional view of the portion along the dash-dot line A5 - A6 in Figure 1A , and it is also a cross-sectional view in the channel width direction of transistor 200. In the Figure 1A plan view, some components are omitted for clarity. Additionally, Figure 2A and Figure 2B show enlarged cross-sectional views in the channel length direction of transistor 200.

[0092] Transistor 200 includes a conductor 205 disposed in an embedded insulator 216, insulator 216, insulator 221 on conductor 205, insulator 222 on insulator 221, insulator 224 on insulator 222, an oxide semiconductor 230 on insulator 224, conductors 242a and 242b on oxide semiconductor 230, insulator 271a on conductor 242a, insulator 271b on conductor 242b, insulator 250 on oxide semiconductor 230, and conductor 260 on insulator 250.

[0093] The oxide semiconductor 230 has a region that serves as a channel formation region of the transistor 200. In addition, the conductor 260 has a region that serves as a first gate electrode (which may also be referred to as an upper gate electrode, a top gate electrode) of the transistor 200. The insulator 250 has a region that serves as a first gate insulator of the transistor 200. In addition, the conductor 205 has a region that serves as a second gate electrode (which may also be referred to as a lower gate electrode, a bottom gate electrode) of the transistor 200. Each of the insulators 224, 222, and 221 has a region that serves as a second gate insulator of the transistor 200. The conductor 242a has a region that serves as one of a source electrode and a drain electrode of the transistor 200. The conductor 242b has a region that serves as the other of the source electrode and the drain electrode of the transistor 200.

[0094] An insulator 275 is provided on the insulators 271a and 271b, and an insulator 280 is provided on the insulator 275. An opening reaching the insulator 222 and the oxide semiconductor 230 is formed in the insulator 280 and the insulator 275, and the opening overlaps with a region between the conductor 242a and the conductor 242b. In a plan view (which may also be referred to as a view from a plane), the side surface of the insulator 280 in the opening is aligned or substantially aligned with the side surfaces of the conductor 242a and the conductor 242b. The insulator 250 and the conductor 260 are disposed inside the opening formed in the insulator 280 and the insulator 275. In addition, an insulator 282 is provided in contact with the top surface of the insulator 280, the upper end portion of the insulator 250, and the top surface of the conductor 260. In addition, an insulator 283 is provided on the insulator 282. In addition, an insulator 285 is provided on the insulator 283. In addition, an insulator 214 is provided under the insulator 216 and the conductor 205. In addition, an insulator 212 is provided under the insulator 214. The insulators 212, 214, 280, 282, 283, and 285 are used as interlayer films.

[0095] Openings reaching the conductor 242a are formed in the insulators 285, 283, 282, 280, 275, and 271a. A conductor 240a and an insulator 241a are provided in the openings. The insulator 241a is provided in contact with the side walls of the openings, and the conductor 240a is provided inside the insulator 241a. In addition, openings reaching the conductor 242b are formed in the insulators 285, 283, 282, 280, 275, and 271b. A conductor 240b and an insulator 241b are provided in the openings. The insulator 241b is provided in contact with the side walls of the openings, and the conductor 240b is provided inside the insulator 241b. The conductors 240a and 240b are used as vias for connecting wirings or the like provided on the transistor 200 to the source or drain of the transistor 200.

[0096] The oxide semiconductor 230 has a channel formation region. The oxide semiconductor 230 also has a source region and a drain region. The source region and the drain region are n-type regions (low resistance regions) where the carrier concentration is higher than that in the channel formation region. The oxide semiconductor 230 can have a single-layer structure or a stacked structure of two or more layers.

[0097] There is no particular limitation on the crystallinity of the semiconductor material used for the oxide semiconductor 230, and an amorphous semiconductor, a single crystal semiconductor, or a semiconductor having crystallinity other than a single crystal (microcrystalline semiconductor, polycrystalline semiconductor, or a semiconductor having a crystalline region in part thereof) can be used. When a single crystal semiconductor or a semiconductor having crystallinity is used, deterioration of transistor characteristics can be suppressed, which is therefore preferable.

[0098] The bandgap of the metal oxide used as the semiconductor is preferably 2.0 eV or more, more preferably 2.5 eV or more. By using a metal oxide with a wider bandgap for the oxide semiconductor 230, the off-state current of the transistor 200 can be reduced. Since the off-state current of the OS transistor is small, the power consumption of the semiconductor device can be sufficiently reduced. In addition, since the frequency characteristics of the OS transistor are high, the semiconductor device can operate at high speed.

[0099] Regarding the oxide semiconductor that can be used as the semiconductor layer of the transistor according to one embodiment of the present invention, reference can be made to the description of Embodiment 2. Here, detailed description is omitted.

[0100] In addition, transistors using other semiconductor materials in the channel formation region can also be used in the semiconductor device of the present embodiment. Examples of such other semiconductor materials include semiconductors composed of a single element or compound semiconductors.

[0101] As a semiconductor composed of a single element that can be used for semiconductor materials, silicon and germanium can be cited, for example. In addition, as silicon that can be used for semiconductor materials, single-crystalline silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon can be cited. As polycrystalline silicon, low-temperature polycrystalline silicon (LTPS: Low Temperature Poly Silicon) can be cited, for example.

[0102] As compound semiconductors that can be used for semiconductor materials, silicon carbide, silicon germanium, gallium arsenide, indium phosphide, boron nitride, and boron arsenide can be cited, etc. Boron nitride that can be used for the semiconductor layer preferably has an amorphous structure. Boron arsenide that can be used for the semiconductor layer preferably contains crystals having a cubic crystal structure. In addition, as compound semiconductors, organic semiconductors and nitride semiconductors can be cited, for example. The above oxide semiconductors are also one kind of compound semiconductors. These semiconductor materials can also contain impurities as dopants.

[0103] Here, the oxide semiconductor 230 used for the semiconductor device preferably contains indium oxide. For example, indium oxide, indium gallium oxide, indium zinc oxide, indium gallium zinc oxide, or indium gallium tin zinc oxide can be used for the oxide semiconductor 230. In addition, the oxide semiconductor 230 can have a stacked structure. For example, the oxide semiconductor 230 can have a stacked structure of indium oxide and indium gallium zinc oxide on indium oxide. In addition, as Figure 2A shown, the oxide semiconductor 230 can include an oxide semiconductor 230a on an insulator 224, an oxide semiconductor 230b on the oxide semiconductor 230a, and an oxide semiconductor 230c on the oxide semiconductor 230b. For example, indium oxide can be used for the oxide semiconductor 230b, and indium gallium zinc oxide can be used for the oxide semiconductor 230a and the oxide semiconductor 230c. As described above, when the oxide semiconductor 230 contains indium oxide, a semiconductor device with a high field-effect mobility can be provided. In addition, a semiconductor device with at least one of good electrical characteristics, frequency characteristics, and reliability can be provided. The detailed structure of the oxide semiconductor 230 can be referred to the description of Embodiment 2.

[0104] In the oxide semiconductor 230, a channel formation region of the transistor 200 and a source region and a drain region provided so as to sandwich the channel formation region are formed. At least a part of the channel formation region overlaps with the conductor 260. The source region overlaps with the conductor 242a, and the drain region overlaps with the conductor 242b. Note that the source region and the drain region can be swapped.

[0105] Since it has fewer oxygen vacancies or a lower impurity concentration than the source region and the drain region, the channel formation region is a high-resistance region with a low carrier concentration. Therefore, the channel formation region can be said to be an i-type (intrinsic) or substantially i-type region.

[0106] In addition, due to a large number of oxygen vacancies or a high impurity concentration of hydrogen, nitrogen, metal elements, etc., the source region and the drain region are low-resistance regions with a high carrier concentration. That is to say, the source region and the drain region are n-type regions (low-resistance regions) with a higher carrier concentration than the channel formation region.

[0107] The carrier concentration in the channel formation region is preferably 1×10 18 cm -3 or less, lower than 1×10 17 cm -3 or less, lower than 1×10 16 cm -3 or less, lower than 1×10 15 cm -3 or less, lower than 1×10 14 cm -3 or less, lower than 1×10 13 cm -3 or less, lower than 1×10 12 cm -3 or less, lower than 1×10 11 cm -3 or lower than 1×10 10 cm -3 . Note that there is no particular limitation on the lower limit value of the carrier concentration in the channel formation region. For example, it can be 1×10 -9 cm -3 .

[0108] In the case of aiming to reduce the carrier concentration of the oxide semiconductor 230, the impurity concentration in the oxide semiconductor 230 can be reduced to reduce the density of defect states. In this specification, etc., a state with a low impurity concentration and a low density of defect states is referred to as highly pure intrinsic or substantially highly pure intrinsic. In addition, an oxide semiconductor (or metal oxide) with a low carrier concentration is sometimes referred to as a highly pure intrinsic or substantially highly pure intrinsic oxide semiconductor (or metal oxide).

[0109] To stabilize the electrical characteristics of the transistor 200, it is effective to reduce the impurity concentration in the channel formation region of the oxide semiconductor 230. To reduce the impurity concentration of the oxide semiconductor 230, it is preferable to also reduce the impurity concentration in the nearby film. Examples of impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, silicon, etc. Note that the impurities in the oxide semiconductor 230 refer to elements other than the main components constituting the oxide semiconductor 230. For example, an element with a concentration lower than 0.1 atomic% can be said to be an impurity.

[0110] In addition, in the oxide semiconductor 230, it is sometimes difficult to clearly observe the boundaries of the respective regions. The concentrations of metal elements and impurity elements such as hydrogen and nitrogen detected in the respective regions not only change stepwise for each region, but can also change gradually in each region. That is, the closer to the channel formation region, the lower the concentrations of metal elements and impurity elements such as hydrogen and nitrogen can be.

[0111] In a transistor using an oxide semiconductor, if impurities and oxygen vacancies are present in the region where the channel is formed in the oxide semiconductor, the electrical characteristics are likely to vary, and the reliability sometimes decreases. In addition, hydrogen near the oxygen vacancy forms a defect in which hydrogen enters the oxygen vacancy (hereinafter sometimes referred to as V O H), and electrons that become carriers may be generated. Therefore, when the channel formation region of the oxide semiconductor contains oxygen vacancies, the transistor is likely to have a normally-on characteristic (a characteristic in which a channel exists even when no voltage is applied to the gate electrode and current flows through the transistor). Thus, in the channel formation region of the oxide semiconductor, it is preferable to minimize impurities, oxygen vacancies, and V O H. In other words, it is preferable that the carrier concentration in the channel formation region of the oxide semiconductor is reduced and is i-type (intrinsic) or substantially i-type.

[0112] In contrast, by performing heat treatment by providing an insulator containing oxygen that is released by heating (hereinafter sometimes referred to as excess oxygen) near the oxide semiconductor, oxygen can be supplied from the insulator to the oxide semiconductor to reduce oxygen vacancies and V O H. Note that when too much oxygen is supplied to the source region or the drain region, there is a possibility of causing a decrease in the on-state current of the transistor 200 or a decrease in the field-effect mobility. Also, when the amount of oxygen supplied to the source region or the drain region is non-uniform in the substrate surface, the characteristics of the semiconductor device including the transistor become non-uniform. In addition, when too much oxygen is supplied from the insulator to the oxide semiconductor, it sometimes has a negative impact on the electrical characteristics and reliability of the transistor. Furthermore, there is also a concern that oxygen diffuses into conductors such as the gate electrode, the source electrode, and the drain electrode, and the conductor is oxidized, resulting in a decrease in conductivity.

[0113] Preferably, first, an insulator having hydrogen barrier properties is formed near the transistor 200 to reduce V O H in the channel formation region of the oxide semiconductor 230 and its vicinity.

[0114] At least one of the insulators 212, 214, 221, 222, 275, 282, and 283 is preferably used as a hydrogen-blocking insulator. In addition, at least one of the insulators 212, 214, 221, 222, 275, 282, and 283 is preferably used as an impurity-blocking insulator. In addition, at least one of the insulators 212, 214, 221, 222, 275, 282, and 283 is preferably used as an oxygen-blocking insulator. Note that it is not necessarily required to provide all of the insulators 212, 214, 221, 222, 275, 282, and 283. As long as it has sufficient blocking properties against hydrogen, impurities, oxygen, etc., it can be appropriately selected from the insulators 212, 214, 221, 222, 275, 282, and 283 to form. For example, a structure may be adopted in which the insulator 214 is not provided and the insulators 216 and the conductor 205 are formed in contact with the top surface of the insulator 212.

[0115] Note that in this specification, etc., a blocking insulator refers to an insulator having a blocking property. In this specification, etc., having a blocking property means a property of not easily diffusing the corresponding substance (also referred to as a property of not easily permeating the corresponding substance, a property of low permeability of the corresponding substance, or a function of suppressing the diffusion of the corresponding substance). Or, it means a function of capturing or fixing the corresponding substance (also called gettering) inside the insulator. In addition, the hydrogen referred to as the corresponding substance, for example, refers to at least one of a hydrogen atom, a hydrogen molecule, a water molecule, and a substance hydrogen-bonded to OH - etc. In addition, unless otherwise stated, the impurities referred to as the corresponding substance refer to impurities in the channel formation region or the semiconductor layer, and for example, refer to at least one of a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom, a nitrogen molecule, a nitrogen oxide molecule (N2O, NO, NO2, etc.), a copper atom, etc. In addition, the oxygen referred to as the corresponding substance, for example, refers to at least one of an oxygen atom and an oxygen molecule.

[0116] As an insulator having a function of suppressing hydrogen diffusion, for example, silicon nitride or silicon oxynitride is preferably used. In addition, for example, alumina, magnesia, hafnium oxide, zirconium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), an oxide containing hafnium and zirconium (hafnium zirconium oxide), gallium oxide, indium gallium zinc oxide, etc. may sometimes be used.

[0117] As the insulators 212, 221, 275, and 283, an insulator having a function of suppressing hydrogen diffusion is preferably used. For example, the insulators 212, 221, 275, and 283 can use silicon nitride having a higher hydrogen-blocking property.

[0118] A part of the insulator having a function of suppressing hydrogen diffusion has a function of capturing or fixing hydrogen. As the insulator having a function of capturing or fixing hydrogen, for example, metal oxides such as hafnium-containing oxide, aluminum-containing oxide, aluminum and hafnium-containing oxide (hafnium aluminate), hafnium and zirconium-containing oxide (hafnium zirconium oxide), or magnesium oxide are preferably used. The insulator having a function of capturing or fixing hydrogen preferably has an amorphous structure. The above-mentioned metal oxide having an amorphous structure sometimes has the following property: oxygen atoms have dangling bonds and capture or fix hydrogen by these dangling bonds. That is to say, the ability of the metal oxide having an amorphous structure to capture or fix hydrogen is high. By adding silicon to the above-mentioned metal oxide, polycrystallization can be suppressed and amorphization can be more easily achieved. Therefore, metal oxides obtained by adding silicon to the above-mentioned metal oxides (for example, hafnium silicate, aluminum silicate, etc.) are preferably used.

[0119] As the insulators 214, 222, and 282, insulators having a function of capturing or fixing hydrogen are preferably used. For example, alumina can be used as the insulators 214 and 282. For example, as the insulator 222 used as the second gate insulator, hafnium oxide as a high dielectric constant (high-k) material is preferably used.

[0120] In addition, the inorganic insulators cited as the insulators having a function of suppressing hydrogen diffusion and the insulators having a function of capturing or fixing hydrogen also have an oxygen barrier property.

[0121] As Figure 2A shown, it is preferable to provide an insulator 212 having a function of suppressing hydrogen diffusion and an insulator 214 having a function of capturing or fixing hydrogen under the transistor 200. By providing the insulator 212 under the transistor 200, hydrogen diffusion from the lower layer of the transistor 200 can be suppressed. In addition, by providing the insulator 214 on the insulator 212, hydrogen contained in the insulator 216 or the like can be captured or fixed by the insulator 214. Thereby, the hydrogen concentration in the oxide semiconductor 230 and its vicinity can be reduced.

[0122] In addition, as Figure 2A shown, it is preferable to provide an insulator 221 having a function of suppressing hydrogen diffusion and an insulator 222 having a function of capturing or fixing hydrogen under the transistor 200. By providing the insulator 221 under the transistor 200, hydrogen diffusion from the lower layer of the transistor 200 can be suppressed. In addition, by providing the insulator 222 on the insulator 221, hydrogen contained in the insulator 224 or the like can be captured or fixed by the insulator 222. Thereby, the hydrogen concentration in the oxide semiconductor 230 and its vicinity can be reduced.

[0123] In addition, as Figure 2AAs shown, it is preferable to provide the insulator 275 so as to cover the oxide semiconductor 230, the conductor 242a, the conductor 242b, etc. By providing the insulator 275 in this way, diffusion of hydrogen from the insulator 280 into the oxide semiconductor 230, the conductor 242a, the conductor 242b, etc. can be suppressed.

[0124] In addition, as Figure 2A shown, it is preferable to provide an insulator 282 having a function of capturing or fixing hydrogen and an insulator 283 having a function of suppressing hydrogen diffusion on the transistor 200. By providing the insulator 283 on the transistor 200, diffusion of hydrogen from the upper layer of the transistor 200 can be suppressed. In addition, by providing the insulator 282 under the insulator 283, the hydrogen contained in the insulator 280, etc. can be captured or fixed by the insulator 282. Thereby, the hydrogen concentration in the oxide semiconductor 230 and its vicinity can be reduced.

[0125] In this way, by adopting a structure in which the transistor 200 is surrounded by hydrogen-blocking insulators above and below, hydrogen diffusion into the oxide semiconductor can be reduced, and VH in the channel formation region can be reduced. O Thereby, the electrical characteristics and reliability of the transistor 200 can be improved.

[0126] Furthermore, it is preferable that the insulator 280 contains oxygen that is released by heating. By supplying this oxygen to the oxide semiconductor 230 through the insulator 250 using a heat treatment, oxygen vacancies in the channel formation region can be reduced.

[0127] In addition, as Figure 2A shown, the insulator 282 may also have a stacked structure of an insulator 282a and an insulator 282b on the insulator 282a.

[0128] At this time, by depositing the insulator 282b by sputtering in an atmosphere containing oxygen gas, oxygen can be added to the insulator 280. At this time, by depositing the insulator 282b in a state where the insulator 282a is formed, oxygen is added through the insulator 282a, so the amount of oxygen added to the insulator 280 can be controlled. When the thickness of the insulator 282a is large, the above oxygen addition is easily hindered and the amount of oxygen injected into the insulator 280 decreases. When the thickness of the insulator 282a is small, the above oxygen addition is not easily hindered and the amount of oxygen injected into the insulator 280 increases. For example, by setting the thickness of the insulator 282a to 1 nm or more and 20 nm or less, preferably 3 nm or more and 10 nm or less, an appropriate amount of oxygen can be supplied to the insulator 280.

[0129] In addition, in order to prevent oxygen from being added to the insulator 280 during the deposition of the insulator 282a, the insulator 282a is preferably deposited by atomic layer deposition (ALD: Atomic Layer Deposition). In order to reduce the thickness of the insulator 282a as described above, deposition using the ALD method is preferred. The ALD method includes a thermal ALD (Thermal ALD) method that causes a precursor and a reactant to react only using thermal energy, a plasma enhanced ALD (PEALD) method that uses a reactant excited by plasma, and the like.

[0130] The precursor used in the ALD method sometimes contains carbon or the like. Therefore, a film formed using the ALD method sometimes contains more carbon or other impurities than a film formed using other deposition methods. Therefore, the carbon concentration of the insulator 282a is sometimes higher than that of the insulator 282b. In addition, the quantification of impurities can be performed using secondary ion mass spectrometry (SIMS: Secondary Ion Mass Spectrometry), X-ray photoelectron spectroscopy (XPS: X-ray Photoelectron Spectroscopy), or Auger electron spectroscopy (AES: Auger Electron Spectroscopy).

[0131] For example, when both the insulator 282a and the insulator 282b contain aluminum oxide, the carbon concentration of the insulator 282a is sometimes higher than that of the insulator 282b. At this time, the carbon concentration of the insulator 282a in the SIMS analysis is preferably 1×10 18 atoms / cm 3 or more and 1×10 21 atoms / cm 3 or less. The insulator 282a sometimes has a region with a carbon concentration of 1×10 19 atoms / cm 3 or more and 1×10 21 atoms / cm 3 or less. In addition, the carbon concentration of the insulator 282b in the SIMS analysis is preferably above the detection limit and 1×10 20 atoms / cm 3 or less. The insulator 282b sometimes has a region with a carbon concentration of 4.46×10 17 atoms / cm 3 or more and 1×10 19 atoms / cm 3 or less.

[0132] As described above, by heat-treating the insulator 280 in a state containing oxygen released by heating, an appropriate amount of oxygen can be supplied to the oxide semiconductor 230 through the insulator 250. In this heat treatment, since the oxygen barrier insulators 282 and 283 are formed on the insulator 280, excessive diffusion of the oxygen contained in the insulator 280 from the insulator 280 can be prevented. In addition, since the oxygen barrier insulator 275 is formed between the insulator 280 and the oxide semiconductor 230, the conductor 242a, and the conductor 242b, excessive diffusion of the oxygen contained in the insulator 280 from the insulator 280 can be prevented. In addition, by performing this heat treatment in a state where openings are formed in a part of the insulator 280, the insulator 282, and the insulator 283, a part of the oxygen contained in the insulator 280 can be diffused outward to adjust the amount of oxygen supplied from the insulator 280 to the oxide semiconductor 230.

[0133] Here, the insulator 250 preferably has a structure that diffuses oxygen from the insulator 280 to the oxide semiconductor 230 and inhibits oxidation of the conductor 242a, the conductor 242b, and the conductor 260.

[0134] As Figure 1B and Figure 1C shown, the insulator 250 is disposed in the openings formed in the insulator 280 and the insulator 275. Inside the openings, the insulator 250 is formed so as to be in contact with the top surface of the insulator 222, the side surfaces of the insulator 224, the side surfaces and the top surface of the oxide semiconductor 230, the side surfaces of the conductor 242a, the side surfaces of the conductor 242b, the side surfaces of the insulator 271a, the side surfaces of the insulator 271b, the side surfaces of the insulator 275, and the side surfaces of the insulator 280. In addition, as Figure 2A shown, when the oxide semiconductor 230 includes the oxide semiconductors 230a to 230c, the insulator 250 is in contact with the side surfaces of the oxide semiconductor 230a, the side surfaces of the oxide semiconductor 230b, and the top surface and the side surfaces of the oxide semiconductor 230c. Here, it is preferable to improve Figure 2A the crystallinity of the oxide semiconductor 230c shown. Since the contact area of the oxide semiconductor 230c with the insulator 250 is large, the carrier mobility can be improved when the transistor 200 is in the on state.

[0135] Here, as Figure 2A shown, the insulator 250 preferably has a stacked structure including the insulator 250a in contact with the oxide semiconductor 230, the insulator 250b on the insulator 250a, and the insulator 250c on the insulator 250b.

[0136] The insulator 250b preferably uses silicon oxide, silicon oxynitride, etc. with high insulation breakdown voltage. Additionally, in order to increase the insulation breakdown voltage, the thickness of the insulator 250b can also be made larger than that of the insulator 250a. By using the above-mentioned oxide insulator, a high-temperature heat treatment can be performed to diffuse oxygen in the insulator 250b. Therefore, by performing the heat treatment, the oxygen contained in the insulator 280 can be supplied to the oxide semiconductor 230 through the insulator 250b. Note that in this specification, etc., "oxynitride" refers to a material in which the oxygen content is more than the nitrogen content in its composition, and "nitroxide" refers to a material in which the nitrogen content is more than the oxygen content in its composition. For example, when it is described as "silicon oxynitride", it refers to a material in which the oxygen content is more than the nitrogen content in its composition, and when it is described as "silicon nitroxide", it refers to a material in which the nitrogen content is more than the oxygen content in its composition.

[0137] Furthermore, in order to suppress the oxidation of the conductors 242a, 242b, and 260, it is preferable to provide an oxygen barrier insulator near each of the conductors 242a, 242b, and 260. For example, it is preferable to provide an oxygen barrier insulator as the insulator 250a and the insulator 250c.

[0138] The insulator 250a preferably has oxygen barrier properties. The insulator 250a is preferably at least less permeable to oxygen than the insulator 250b. The insulator 250a has regions in contact with the side surfaces of the conductor 242a and the conductor 242b. When the insulator 250a has oxygen barrier properties, oxidation of the side surfaces of the conductors 242a and 242b can be suppressed, and an oxide film can be prevented from being formed on these side surfaces. Therefore, a decrease in the on-state current or the field-effect mobility of the transistor 200 can be suppressed. In addition, by adopting such a structure, the amount of oxygen absorbed by the conductors 242a and 242b from the insulator 250b can be reduced. Therefore, an appropriate amount of oxygen can be supplied from the insulator 250b to the oxide semiconductor 230, and thereby the oxygen vacancies in the channel formation region of the oxide semiconductor 230 can be reduced.

[0139] In addition, by providing the insulator 250a between the insulator 280 and the insulator 250b and between the insulator 250b and the oxide semiconductor 230, excessive supply of oxygen from the insulator 280 to the oxide semiconductor 230 can be suppressed, and an appropriate amount of oxygen can be supplied to the oxide semiconductor 230. Therefore, the amount of oxygen in the channel formation region of the oxide semiconductor 230 and its vicinity can be controlled to an appropriate amount, so that over-closure of the transistor 200 can be prevented and the reliability can be improved. In addition, over-oxidation of the source region and the drain region can be suppressed, resulting in a decrease in the on-state current or the field-effect mobility of the transistor 200.

[0140] Therefore, the thickness of the insulator 250a is preferably such that it does not overly block the diffusion of oxygen from the insulator 280 to the insulator 250b and the diffusion of oxygen from the insulator 250b to the oxide semiconductor 230. For example, the thickness of the insulator 250a is preferably 0.1 nm or more and 5.0 nm or less, more preferably 0.5 nm or more and 5.0 nm or less, further preferably 0.5 nm or more and less than 3.0 nm, and even more preferably 0.5 nm or more and 2.0 nm or less.

[0141] As described above, it is preferable that oxygen is appropriately diffused from the insulator 280 to the insulator 250b and oxygen is diffused from the insulator 250b to the oxide semiconductor 230, and the diffusion of oxygen from the insulator 250b to the conductors 242a and 242b is suppressed as much as possible. Here, in the semiconductor device according to the present embodiment, the contact areas of the insulator 250a with the conductors 242a and 242b are much smaller than the contact area of the insulator 250a with the oxide semiconductor 230. That is, it can be speculated that the amount of oxygen diffusing from the insulator 250b through the insulator 250a to the conductors 242a and 242b is less than the amount of oxygen diffusing from the insulator 250b through the insulator 250a to the oxide semiconductor 230. Therefore, by controlling the amount of oxygen contained in the insulator 280 to supply an appropriate amount of oxygen from the insulator 280 to the insulator 250b and the oxide semiconductor 230, the oxidation of the conductors 242a and 242b can be reduced.

[0142] The insulator 250a in contact with the channel formation region in the oxide semiconductor 230 preferably has a function of capturing or fixing hydrogen. Thereby, the hydrogen concentration in the channel formation region of the oxide semiconductor 230 can be reduced. Therefore, V O H in the channel formation region can be reduced to make the channel formation region i-type or substantially i-type.

[0143] In addition, the insulator 250a is preferably made of a high dielectric constant (high-k) material. Further, as an example of the high-k material, there is an oxide containing one or both of aluminum and hafnium. When a high-k material is used as the insulator 250a, the gate potential applied during transistor operation can be reduced while maintaining the physical thickness of the gate insulator. In addition, the equivalent oxide thickness (EOT) of the insulator used as the gate insulator can be reduced.

[0144] Therefore, as the insulator 250a, an oxide containing one or both of aluminum and hafnium is preferably used, and an oxide having an amorphous structure and containing one or both of aluminum and hafnium is more preferably used. Since aluminum oxide can be easily deposited as an amorphous film by ALD method, an aluminum oxide having an amorphous structure is further preferably used. In the present embodiment, an aluminum oxide film is used as the insulator 250a. Aluminum oxide has a function of capturing or fixing hydrogen and has an oxygen barrier property, so it can be suitably used as the insulator 250a.

[0145] The insulator 250c also preferably has an oxygen barrier property. The insulator 250c is provided between the channel formation region of the oxide semiconductor 230 and the conductor 260, and between the insulator 280 and the conductor 260. By adopting this structure, oxygen diffusion from the channel formation region of the oxide semiconductor 230 to the conductor 260 can be suppressed, and oxygen vacancies can be formed in the channel formation region of the oxide semiconductor 230. In addition, oxidation of the conductor 260 caused by oxygen diffusion from the oxide semiconductor 230 and the insulator 280 can be suppressed. The insulator 250c is preferably at least less permeable to oxygen than the insulator 250b. In addition, the insulator 250c preferably has a function of suppressing hydrogen diffusion. Thereby, impurities such as hydrogen contained in the conductor 260 can be prevented from diffusing into the oxide semiconductor 230. For example, a silicon nitride film is preferably used as the insulator 250c.

[0146] In addition, as Figure 2BAs shown, it is preferable to adopt a structure in which an insulator 250d is provided on an insulator 250b. In this case, as the insulator 250d, an insulator having a function of capturing or fixing hydrogen and usable as the insulator 250a can be provided. For example, an oxide containing hafnium is preferably used as the insulator 250d. As the oxide containing hafnium, for example, hafnium oxide, hafnium aluminate, hafnium silicate, hafnium zirconium oxide, hafnium zirconium oxide containing yttrium, etc. can be used. In addition, as the insulator 250d, hafnium zirconium oxide containing lanthanide elements such as lanthanum can also be used. Here, by providing the insulator 250d between the insulator 250c and the insulator 250b, hydrogen contained in the insulator 250b, etc. can be captured and fixed more effectively. A channel formation region of an oxide semiconductor 230, an insulator 250a having a function of capturing and fixing hydrogen, and an insulator 250d are provided under an insulator 250c having a function of suppressing hydrogen diffusion. In a region where hydrogen diffusion from above is blocked by the insulator 250c, hydrogen contained in the channel formation region of the oxide semiconductor 230, etc. can be captured or fixed by the insulator 250a and the insulator 250d. Thereby, the hydrogen concentration in the oxide semiconductor 230 can be reduced, and thus the negative drift of the initial characteristics of the transistor 200 can be suppressed to achieve a normally-off characteristic. In addition, negative drift degradation in a +GBT (Gate Bias-Temperature) stress test can be suppressed.

[0147] Alternatively, the insulator 250c may not be provided, and the insulators 250a, 250b, and 250d may be provided. At this time, it is preferable to provide an insulator (for example, silicon nitride, etc.) having a function of suppressing hydrogen diffusion as an insulator 283 on the insulator 250. By adopting such a structure, the oxide semiconductor 230, the insulator 250a having a function of capturing or fixing hydrogen, and the insulator 250d are formed in a region covered with silicon nitride having high hydrogen barrier properties. Therefore, hydrogen contained in the channel formation region of the oxide semiconductor 230, etc. can be captured or fixed by the insulator 250a and the insulator 250d.

[0148] By adopting the above structure, the channel formation region can be i-type or substantially i-type, and the source region and the drain region can be n-type, and a semiconductor device having good electrical characteristics can be provided. By adopting the above structure, even if the semiconductor device is miniaturized or highly integrated, it can have good electrical characteristics. In addition, by miniaturizing the transistor 200, the frequency characteristics can be improved. Specifically, the cut-off frequency can be increased.

[0149] In addition, a hafnium-containing metal oxide for the insulator 250d is preferably used as a high-k material. By adopting such a structure, the gate potential applied during transistor operation can be reduced while maintaining the physical thickness of the gate insulator. In addition, the equivalent oxide thickness (EOT) of the insulator used as the gate insulator can be reduced.

[0150] In addition, the insulator 250d preferably has ferroelectricity. For example, hafnium zirconium oxide having ferroelectricity, hafnium zirconium oxide containing yttrium, etc. can be used as the insulator 250d. In addition, the insulator 250d may also have a structure in which a layer of hafnium zirconium oxide is laminated on a layer of hafnium zirconium oxide containing yttrium. Note that when a ferroelectric is used for the insulator 250d, the insulator 250d does not necessarily need to have a function of capturing or fixing hydrogen. For example, the insulator 250d can use the material that can have ferroelectricity described in Embodiment 4.

[0151] Thus, by using a ferroelectric as the insulator 250d, the transistor 200 can function as a FeFET (Ferroelectric Field Effect Transistor). The FeFET alone is used as a storage element. Therefore, compared with a DRAM (Dynamic Random Access Memory) type storage element including a transistor and a capacitor, the structure of the storage element can be reduced. Therefore, miniaturization and high integration of the storage device including the transistor 200 can be achieved. In addition, the productivity of the storage device including the transistor 200 can be improved.

[0152] Insulators 250a to 250d are used as part of the first gate insulator. Insulators 250a to 250d and conductor 260 are disposed in an opening formed in insulator 280 or the like. In order to miniaturize transistor 200, the thickness of each of insulators 250a, 250c, and 250d is preferably small. The thickness of each of insulators 250a, 250c, and 250d is preferably 0.1 nm or more and 20 nm or less, more preferably 0.1 nm or more and 10 nm or less, further preferably 0.5 nm or more and 5.0 nm or less, still further preferably 1.0 nm or more and less than 5.0 nm, and even more preferably 1.0 nm or more and 3.0 nm or less. For example, alumina with a thickness of 1 nm can be used as insulator 250a, silicon oxide with a thickness of 2 nm can be used as insulator 250b, hafnium oxide, hafnium zirconium oxide, or yttrium-containing hafnium zirconium oxide with a thickness of 2 nm can be used as insulator 250d, and silicon nitride with a thickness of 1 nm can be used as insulator 250c. It is sufficient that at least a part of each of insulators 250a, 250c, and 250d has a region where its thickness is within the above range.

[0153] In order to reduce the thickness of insulators 250a, 250c, and 250d as described above, deposition is preferably performed by the ALD method. In addition, in order to form insulators 250a to 250d with high coverage in the opening of insulator 280 or the like, insulators 250a to 250d are preferably deposited by the ALD method.

[0154] Note that in the above, insulator 250 is described as having a three-layer structure of insulators 250a to 250c or a four-layer structure of insulators 250a to 250d, but the present invention is not limited thereto. Insulator 250 may have a single-layer structure, a two-layer structure, or a stacked structure of five or more layers. In addition, insulator 250 may include at least one of insulators 250a to 250d. For example, insulator 250 may also have a single-layer structure of insulator 250c. In this case, a single-layer hafnium zirconium oxide may also be used to form insulator 250. By forming insulator 250 from one, two, or three of insulators 250a to 250d, the manufacturing process of the semiconductor device can be simplified, and thus the productivity can be improved.

[0155] In the case where insulator 250 has a four-layer structure or a five-layer structure, for example, it may have Figures 3A to 3E the stacked structure shown. Here, Figures 3A to 3E is an enlarged view corresponding to Figure 2B the region A shown.

[0156] Figure 3AAn example of a stacked structure in which the insulator 250 is shown to have an insulator 250a on the oxide semiconductor 230, an insulator 250d on the insulator 250a, an insulator 250b on the insulator 250d, and an insulator 250c on the insulator 250b is shown. In other words, Figure 3A The shown insulator 250 has Figure 2B a structure in which the positions of the insulator 250b and the insulator 250d in the shown insulator 250 are swapped. For example, alumina with a thickness of 1 nm can be used as the insulator 250a, hafnium zirconium oxide or hafnium zirconium oxide containing yttrium with a thickness of 2 nm can be used as the insulator 250d, silicon oxide with a thickness of 2 nm can be used as the insulator 250b, and silicon nitride with a thickness of 1 nm can be used as the insulator 250c. In addition, the insulator 250d may also have a structure in which a layer of hafnium zirconium oxide is stacked on a layer of hafnium zirconium oxide containing yttrium. However, it is not limited to this, and the above insulating materials can be appropriately selected as the insulator 250a to the insulator 250d, and the thicknesses of the insulator 250a to the insulator 250d can also be appropriately selected. By stacking the insulator 250a to the insulator 250d as Figure 3A shown, the insulator 250a and the insulator 250d having the function of capturing or fixing hydrogen are arranged adjacent to each other, so that hydrogen can be captured and fixed more effectively.

[0157] In addition, as Figure 3B shown, a structure in which the positions of the insulator 250c and the insulator 250b are swapped can also be adopted. In this case, the insulator 250 has a stacked structure of an insulator 250a on the oxide semiconductor 230, an insulator 250d on the insulator 250a, an insulator 250c on the insulator 250d, and an insulator 250b on the insulator 250c.

[0158] In addition, a structure in which the insulator 250c is arranged in Figure 3A such a way as to be in contact with the top surface and the bottom surface of the insulator 250b can also be adopted. In this case, as Figure 3C shown, the insulator 250 has a stacked structure of an insulator 250a on the oxide semiconductor 230, an insulator 250d on the insulator 250a, an insulator 250c1 on the insulator 250d, an insulator 250b on the insulator 250c1, and an insulator 250c2 on the insulator 250b. Here, the insulator 250c1 and the insulator 250c2 can use the insulators that can be used for the insulator 250c described above. For example, both the insulator 250c1 and the insulator 250c2 can use silicon nitride with a thickness of 1 nm.

[0159] Figure 3DAn example of a stacked structure is shown in which the insulator 250 has an insulator 250a on the oxide semiconductor 230, an insulator 250b on the insulator 250a, an insulator 250d1 on the insulator 250b, an insulator 250c on the insulator 250d1, and an insulator 250d2 on the insulator 250c. That is, Figure 3D The shown insulator 250 has a structure in which Figure 2B an insulator that can be used for the insulator 250d is provided in the shown insulator 250 in a manner of contacting the top surface and the bottom surface of the insulator 250c. Here, as the insulator 250d1, an insulator having a function of capturing or fixing hydrogen (for example, hafnium oxide) can be used, and as the insulator 250d2, an insulator having ferroelectricity (for example, hafnium zirconium oxide or hafnium zirconium oxide containing yttrium) can be used. In addition, the insulator 250d2 may also have a structure in which a layer of hafnium zirconium oxide is stacked on a layer of hafnium zirconium oxide containing yttrium. When such a structure is adopted and a ferroelectric is used for the insulator 250d2, the transistor 200 can function as a FeFET. Furthermore, since hydrogen can be captured or fixed by the insulator 250d1, the electrical characteristics and reliability of the transistor 200 can be improved.

[0160] In addition, in the case where the insulator 250d2 is formed and a ferroelectric material such as hafnium zirconium oxide is used as the insulator 250d2, as Figure 3E shown, a conductor 252 may also be provided in a manner of contacting the bottom surface of the insulator 250d2. As the conductor 252, a material that easily polarizes the insulator 250d2 is preferably used, for example, titanium nitride is preferably used. In this case, the portion of the lower part of the conductor 260 that contacts the insulator 250d2 (for example, the conductor 260a) is also preferably made of titanium nitride. By adopting such a structure, the insulator 250d2 can be a ferroelectric, and the transistor 200 can function as a FeFET.

[0161] In the transistor 200, the conductor 205 is arranged so as to overlap with the oxide semiconductor 230 and the conductor 260. As the conductor 205, the conductive material described in <<Conductor>> can be used. Here, the conductor 205 is preferably provided in a manner of being embedded in an opening formed in the insulator 216. In addition, as Figure 1A and Figure 1C shown, the conductor 205 is preferably extended in the channel width direction. By adopting such a structure, the conductor 205 is used as a wiring when a plurality of transistors are provided.

[0162] As Figure 2AAs shown, the conductor 205 preferably includes a conductor 205a and a conductor 205b. The conductor 205a is disposed in contact with the bottom surface and the side wall of the above-mentioned opening. The conductor 205b is disposed in a concave portion of the conductor 205a formed along the above-mentioned opening. Here, the height of the top surface of the conductor 205 is the same as or substantially the same as the height of the top surface of the insulator 216.

[0163] Here, as the conductor 205a, a conductive material having a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N2O, NO, NO2, etc.), and copper atoms is preferably included. Alternatively, a conductive material having a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.) is preferably included.

[0164] By using a conductive material having a function of reducing hydrogen diffusion as the conductor 205a, impurities such as hydrogen contained in the conductor 205b can be prevented from diffusing into the oxide semiconductor 230 through the insulator 216 or the like. In addition, by using a conductive material having a function of suppressing oxygen diffusion as the conductor 205a, oxidation of the conductor 205b can be suppressed and the conductivity can be prevented from decreasing. As a conductive material having a function of suppressing oxygen diffusion, for example, titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, and ruthenium oxide can be cited. The conductor 205a may have a single-layer structure or a laminated structure of the above-mentioned conductive materials. For example, the conductor 205a preferably contains titanium nitride.

[0165] In addition, as the conductor 205b, a conductive material mainly composed of tungsten, copper, or aluminum is preferably used. For example, the conductor 205b preferably contains tungsten.

[0166] The conductor 205 can be used as a second gate electrode. In this case, by independently changing the potential applied to the conductor 205 without linking it to the potential applied to the conductor 260, the threshold voltage (Vth) of the transistor 200 can be controlled. In particular, by applying a negative potential to the conductor 205, the Vth of the transistor 200 can be further increased and the off-state current can be reduced. Thus, compared with the case where a negative potential is not applied to the conductor 205, the drain current when the potential applied to the conductor 260 is 0V can be reduced when a negative potential is applied to the conductor 205.

[0167] In addition, the resistivity of the conductor 205 is designed in consideration of the potential applied to the conductor 205 as described above, and the thickness of the conductor 205 is set according to this resistivity. In addition, the thickness of the insulator 216 is substantially the same as that of the conductor 205. Here, it is preferable to reduce the thicknesses of the conductor 205 and the insulator 216 within the range allowed by the design of the conductor 205. By reducing the thickness of the insulator 216, the absolute amount of impurities such as hydrogen contained in the insulator 216 can be reduced, so that the diffusion of such impurities into the oxide semiconductor 230 can be suppressed.

[0168] Note that, in Figure 2A , a stacked structure of the conductor 205a and the conductor 205b is shown, but the present invention is not limited thereto, and the conductor 205 may have a single-layer structure or a stacked structure of three or more layers. For example, the conductor 205a may have a two-layer structure of tantalum nitride and titanium nitride on the tantalum nitride, and a conductor 205b containing tungsten may be provided on the conductor 205a. By adopting such a structure, the diffusion of impurities such as hydrogen and metal impurities such as copper contained in the lower layer of the transistor 200 into the conductor 205 can be suppressed.

[0169] The insulators 224, 221, and 222 are used as the second gate insulator.

[0170] As the insulator 224 in contact with the oxide semiconductor 230, the insulating materials described in <<Insulator>> can be used. The insulator 224 preferably contains, for example, silicon oxide or silicon oxynitride. Thereby, oxygen can be supplied from the insulator 224 to the oxide semiconductor 230 to reduce oxygen vacancies. In addition, the insulator 224 may also have a stacked structure of two or more layers. In this case, it is not limited to a stacked structure formed of the same material, and a stacked structure formed of different materials may also be used.

[0171] In addition, the insulator 224 is preferably processed into an island shape in the same manner as the oxide semiconductor 230. Thereby, when a plurality of transistors 200 are provided, each transistor 200 includes an insulator 224 having substantially the same size. Therefore, the amount of oxygen supplied from the insulator 224 to the oxide semiconductor 230 in each transistor 200 is substantially equal. Thereby, the non-uniformity of the electrical characteristics of the transistors 200 in the substrate surface can be suppressed.

[0172] Note that it is not necessarily required to process the insulator 224 into an island shape. For example, as shown in Figures 4A to 4D , the insulator 224 may also have a shape in which an opening is partially formed instead of an island shape. Here, Figures 4A to 4D corresponds to Figures 1A to 1D respectively, and is the same as Figures 1A to 1D except for the difference in the shape of the insulator 224.

[0173] In Figures 4A to 4DIn the insulator 224 shown, the thickness of the region that does not overlap with the oxide semiconductor 230 is smaller than the thickness of the region that overlaps with the oxide semiconductor 230. In addition, an opening is formed in the region that does not overlap with the oxide semiconductor 230 and overlaps with the insulator 250. When a plurality of transistors are provided on the same substrate, by forming the insulator 224 in this way, the oxide semiconductors 230 of the respective transistors are formed on the same insulator 224. Thereby, the non-uniformity of the amount of oxygen supplied from the insulator 224 to the oxide semiconductors 230 of the respective transistors can be reduced. Therefore, the non-uniformity of the electrical characteristics of the respective transistors can be reduced.

[0174] Note that in Figures 4A to 4D In the insulator 224 shown, an opening is formed in the region that does not overlap with the oxide semiconductor 230 and overlaps with the insulator 250, but this opening may not be provided.

[0175] As the conductors 242a, 242b, and 260, the conductive materials described in <<Conductive Material>> can be used. In particular, as the conductors 242a, 242b, and 260, a conductive material that is not easily oxidized or a conductive material having a function of suppressing oxygen diffusion is preferably used. As such a conductive material, for example, a conductive material containing nitrogen and a conductive material containing oxygen can be cited. Thereby, a decrease in the conductivity of the conductors 242a, 242b, and 260 can be suppressed. When a conductive material containing metal and nitrogen is used as the conductors 242a, 242b, and 260, the conductors 242a, 242b, and 260 are conductors containing at least metal and nitrogen.

[0176] Metal nitrides are preferably used as the conductors 242a and 242b. For example, nitrides containing tantalum, nitrides containing titanium, nitrides containing molybdenum, nitrides containing tungsten, nitrides containing tantalum and aluminum, nitrides containing titanium and aluminum, etc. are preferably used. For example, tantalum nitride can be used as the conductors 242a and 242b. In addition, for example, ruthenium, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel, etc. can also be used. These materials are conductive materials that are not easily oxidized or materials that maintain conductivity even when they absorb oxygen, so they are preferred.

[0177] Note that sometimes hydrogen contained in the oxide semiconductor 230 or the like diffuses into the conductor 242a or the conductor 242b. In particular, when a tantalum-containing nitride is used as the conductor 242a and the conductor 242b, sometimes hydrogen contained in the oxide semiconductor 230 or the like easily diffuses into the conductor 242a or the conductor 242b, and sometimes the diffused hydrogen bonds with the nitrogen contained in the conductor 242a or the conductor 242b. That is, sometimes hydrogen contained in the oxide semiconductor 230 or the like is absorbed by the conductor 242a or the conductor 242b.

[0178] In addition, the conductor 242a and the conductor 242b may also have a stacked structure. In this case, the above-described conductive material may be used as the lower layer of the conductor 242a and the conductor 242b, and a conductive material having higher conductivity may be used as the upper layer of the conductor 242a and the conductor 242b. For example, tantalum nitride may be used as the lower layer, and tungsten may be used as the upper layer.

[0179] The insulators 271a and 271b are inorganic insulators that protect the conductors 242a and 242b and are used as an etch stop layer in the processing of the conductors 242a and 242b. In addition, since they are in contact with the conductors 242a and 242b, the insulators 271a and 271b are preferably inorganic insulators that do not easily oxidize the conductors 242a and 242b. Therefore, as Figure 2A shown, preferably, the insulator 271a has a stacked structure of the insulator 271a1 and the insulator 271a2 on the insulator 271a1, and the insulator 271b has a stacked structure of the insulator 271b1 and the insulator 271b2 on the insulator 271b1. Here, the insulators 271a1 and 271b1 are preferably nitride insulators that can be used for the insulator 250c so as not to oxidize the conductors 242a and 242b. In addition, in order to be used as an etch stop layer, the insulators 271a2 and 271b2 are preferably oxide insulators that can be used for the insulator 250b.

[0180] Here, the insulator 271a1 is in contact with the top surface of the conductor 242a and a part of the insulator 275, and the insulator 271b1 is in contact with the top surface of the conductor 242b and a part of the insulator 275. In addition, the insulator 271a2 is in contact with the top surface of the insulator 271a1 and the bottom surface of the insulator 275, and the insulator 271b2 is in contact with the top surface of the insulator 271b1 and the bottom surface of the insulator 275. For example, silicon nitride may be used as the insulators 271a1 and 271b1, and silicon oxide may be used as the insulators 271a2 and 271b2.

[0181] The insulator that will become insulators 271a and 271b is used as a mask for the conductor that will become conductors 242a and 242b. Therefore, as Figure 1D shown, there is no curved surface between the side surface and the top surface of conductors 242a and 242b. As a result, the end where the side surface and the top surface of conductors 242a and 242b intersect has an angular shape. When the end where the side surface and the top surface of conductors 242a and 242b intersect has an angular shape, the cross-sectional area of conductors 242a and 242b is larger than when the end has a curved surface. Furthermore, by using a nitride insulator that is not easily oxidized as insulators 271a1 and 271b1, conductors 242a and 242b can be prevented from being overly oxidized. As a result, the resistance of conductors 242a and 242b is reduced, so the on-state current of the transistor can be increased.

[0182] As Figure 1B and Figure 1C shown, conductor 260 is disposed in the openings formed in insulator 280 and insulator 275. Conductor 260 is disposed so as to cover the top surface of insulator 222, the side surface of insulator 224, the side surface and the top surface of oxide semiconductor 230 with insulator 250 interposed therebetween in the opening. In addition, the top surface of conductor 260 is disposed to be flush with or substantially flush with the upper end portion of insulator 250 and the top surface of insulator 280.

[0183] In the above-described opening in which conductor 260 and insulator 250 are disposed, the side wall of the opening may be perpendicular or substantially perpendicular to the top surface of insulator 222, or may have a tapered shape. By having a tapered shape for the side wall, the coverage of insulator 250 and the like provided in the opening formed in insulator 280 can be improved, and thus defects such as voids can be reduced.

[0184] Conductor 260 is used as the first gate electrode of transistor 200. Here, as Figure 1A and Figure 1C shown, conductor 260 is preferably extended in the channel width direction. By adopting such a structure, conductor 260 is used as a wiring when a plurality of transistors are provided.

[0185] In the case of adopting the above-described structure, as Figure 1C shown, when the transistor 200 is cross-sectioned in the channel width direction, there may also be a curved surface between the side surface and the top surface of oxide semiconductor 230. That is, the end of the side surface and the end of the top surface may also be curved (hereinafter, also referred to as rounded).

[0186] The radius of curvature of the above-mentioned curved surface is preferably greater than 0 nm and less than the thickness of the oxide semiconductor 230 in the region overlapping with the conductor 242a and the conductor 242b, or less than half the length of the region without the above-mentioned curved surface. Specifically, the radius of curvature of the above-mentioned curved surface is greater than 0 nm and 20 nm or less, preferably 1 nm or more and 15 nm or less, more preferably 2 nm or more and 10 nm or less. By adopting the above shape, the coverage of the insulator 250 and the conductor 260 on the oxide semiconductor 230 can be improved.

[0187] In this specification and the like, a transistor structure in which at least the electric field of the first gate electrode electrically surrounds the channel formation region is referred to as a surrounded channel (S-channel) structure. In addition, the S-channel structure disclosed in this specification and the like is different from the Fin type structure and the planar type structure. On the other hand, the S-channel structure disclosed in this specification and the like can be regarded as a kind of Fin type structure. In addition, in this specification and the like, the Fin type structure refers to a structure in which the gate electrode is arranged so as to surround at least two or more surfaces of the channel (specifically, two surfaces, three surfaces, four surfaces, etc.). By adopting the Fin type structure and the S-channel structure, the tolerance to the short channel effect can be improved. In other words, a transistor that is not likely to have a short channel effect can be realized.

[0188] By adopting the above S-channel structure as the transistor 200, the channel formation region can be electrically surrounded. Since the S-channel structure is a structure that electrically surrounds the channel formation region, it can also be said that this structure is substantially the same as the GAA (Gate All Around: all-around gate) structure or the LGAA (Lateral Gate All Around: lateral all-around gate) structure. By making the transistor 200 have an S-channel structure, a GAA structure, or an LGAA structure, the channel formation region formed at the interface or near the interface between the oxide semiconductor 230 and the gate insulator can be regarded as the entire bulk of the oxide semiconductor 230. Therefore, the current density flowing through the transistor can be increased, so an increase in the on-state current of the transistor or an increase in the field-effect mobility of the transistor can be expected.

[0189] This embodiment adopts a structure in which the insulator 224 is provided in an island shape. Therefore, as Figure 1CAs shown, at least a part of the bottom surface of the conductor 260 can be disposed below the bottom surface of the oxide semiconductor 230. Thus, the conductor 260 can be disposed to face the top surface and the side surfaces of the oxide semiconductor 230, so that the electric field of the conductor 260 can act on the top surface and the side surfaces of the oxide semiconductor 230. In this way, by adopting the structure in which the insulator 224 is formed in an island shape, the transistor 200 can have an S-channel structure.

[0190] Note that, as Figure 1C the transistor 200 shown has an S-channel structure, but the semiconductor device according to one embodiment of the present invention is not limited thereto. For example, as the structure of the transistor that can be used in one embodiment of the present invention, any one or more selected from a planar structure, a Fin structure, and a GAA structure can also be adopted.

[0191] As Figure 2A shown, the conductor 260 preferably has a two-layer structure. Here, the conductor 260 preferably includes a conductor 260a and a conductor 260b disposed on the conductor 260a. For example, the conductor 260a is preferably disposed so as to surround the bottom surface and the side surfaces of the conductor 260b. At this time, as the conductor 260a, a conductive material that is not easily oxidized or a conductive material having a function of suppressing oxygen diffusion is preferably used.

[0192] As the conductor 260a, a conductive material having a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules, and copper atoms is preferably used. In addition, a conductive material having a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms and oxygen molecules) is preferably used.

[0193] In addition, when the conductor 260a has a function of suppressing oxygen diffusion, it is possible to suppress the oxidation of the conductor 260b by the oxygen contained in the insulator 280 or the like, resulting in a decrease in conductivity. As the conductive material having a function of suppressing oxygen diffusion, for example, titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, ruthenium oxide, etc. are preferably used.

[0194] In addition, the conductor 260b is preferably a conductor having high conductivity. For example, the conductor 260b can use a conductive material mainly composed of tungsten, copper, or aluminum. In addition, the conductor 260b can have a laminated structure, for example, a laminated structure of titanium or titanium nitride and the above conductive material.

[0195] In addition, in the transistor 200, the conductor 260 is formed self-alignedly so as to be embedded in an opening formed in the insulator 280 or the like. By forming the conductor 260 in this way, the conductor 260 can be disposed to overlap with the region between the conductor 242a and the conductor 242b without alignment.

[0196] The dielectric constants of the insulators 216, 280, and 285 are each preferably lower than that of the insulator 222. By using a material with a low dielectric constant for the interlayer film, the parasitic capacitance generated between the wirings can be reduced.

[0197] For example, the insulators 216, 280, and 285 preferably contain one or more of silicon oxide, silicon oxynitride, silicon oxide added with fluorine, silicon oxide added with carbon, silicon oxide added with carbon and nitrogen, and silicon oxide having pores, respectively.

[0198] In particular, silicon oxide and silicon oxynitride are preferred because they have thermal stability. In particular, materials such as silicon oxide, silicon oxynitride, and silicon oxide having pores are preferred because they easily form regions containing oxygen that dissociates by heating.

[0199] In addition, the top surfaces of the insulators 216 and 280 can also be planarized.

[0200] The concentrations of impurities such as water and hydrogen in the insulator 280 are preferably reduced. For example, silicon-containing oxides such as silicon oxide and silicon oxynitride are preferably used as the insulator 280.

[0201] As the conductors 240a and 240b, the conductive materials described in <<Conductor>> can be used. The conductors 240a and 240b preferably use, for example, a conductive material mainly composed of tungsten, copper, or aluminum. In addition, the conductors 240a and 240b can also have a laminated structure.

[0202] For example, as Figure 2A shown, the conductors 240a and 240b can also have a two-layer laminated structure. The conductor 240a includes a conductor 240a1 formed along the opening and a conductor 240a2 formed inside the conductor 240a1. In addition, the conductor 240b includes a conductor 240b1 formed along the opening and a conductor 240b2 formed inside the conductor 240b1.

[0203] Similar to the conductor 205a, as the conductors 240a1 and 240b1, a conductive material having a function of suppressing the permeation of impurities such as water and hydrogen is preferably used. For example, tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, ruthenium oxide, etc. are preferably used. In addition, a single layer or a laminate of a conductive material having a function of suppressing the permeation of impurities such as water and hydrogen can also be used. By providing the conductors 240a1 and 240b1, impurities such as water and hydrogen can be prevented from mixing into the oxide semiconductor 230 through the conductors 240a2 and 240b2. In addition, the conductors 240a2 and 240b2 can be made of the above-mentioned conductive material that can be used for the conductors 240a and 240b.

[0204] In addition, as Figure 1B shown, the top surfaces of the conductors 240a and 240b can be formed to be aligned or substantially aligned with the top surface of the insulator 285. In addition, as Figure 2A shown, the lower part of the conductor 240a is sometimes formed to be embedded in the conductor 242a. Similarly, the lower part of the conductor 240b is sometimes formed to be embedded in the conductor 242b.

[0205] As the insulators 241a and 241b, a barrier insulator that can be used for the insulator 275 or the like can be used. For example, silicon nitride can be used as the insulators 241a and 241b. The insulators 241a and 241b are provided in contact with the insulator 285, the insulator 283, the insulator 282, the insulator 275, the insulator 271a, and the insulator 271b. Thereby, impurities such as water and hydrogen contained in the insulator 280 or the like can be prevented from mixing into the oxide semiconductor 230 through the conductors 240a and 240b. In particular, silicon nitride is preferred because it has a high barrier property against hydrogen. In addition, oxygen contained in the insulator 280 can be prevented from being absorbed by the conductors 240a and 240b.

[0206] In addition, the insulators 241a and 241b can also have a laminated structure. In this case, an oxygen barrier insulator and a hydrogen barrier insulator are preferably used in combination as the first insulator in contact with the side wall of the opening of the insulator 280 or the like and the second insulator inside it.

[0207] <Modification Example 1>

[0208] In Figure 1B etc., in the opening provided in the insulator 280, the insulator 250 is in contact with the side surface of the insulator 280, but the present invention is not limited to this structure. For example, in this opening, an insulator can also be provided between the insulator 250 and the insulator 280.

[0209] Refer to Figures 5A to 6CDescribe a modified example of the semiconductor device described in <Structural Example of Semiconductor Device>. Figures 5A to 5D are a plan view and a cross-sectional view of a semiconductor device including a transistor 200, corresponding respectively to Figures 1A to 1D the shown plan view and cross-sectional view. Additionally, Figures 6A to 6C is a magnified cross-sectional view in the channel length direction of the transistor 200, corresponding respectively to Figure 2B the shown magnified cross-sectional view.

[0210] Figures 5A to 5D The transistor 200 shown in Figures 1A to 1D is a modified example of the transistor 200 shown in Figures 5A to 5D Specifically, the transistor 200 shown in Figures 1A to 1D includes an insulator 255 and is mainly different from the transistor 200 shown in

[0211] In addition, in Figures 5A to 5D both the conductor 242a and the conductor 242b have a two-layer structure. The conductor 242a has a stacked structure of a conductor 242a1 and a conductor 242a2 on the conductor 242a1. The conductor 242b has a stacked structure of a conductor 242b1 and a conductor 242b2 on the conductor 242b1. The conductor 242a1 and the conductor 242b1 correspond to the lower layers of the above-mentioned conductor 242a and conductor 242b, and the conductor 242a2 and the conductor 242b2 correspond to the upper layers of the above-mentioned conductor 242a and conductor 242b.

[0212] As shown in Figure 5B and Figure 5C the insulator 255 is disposed inside an opening formed in an insulator 280 or the like and is in contact with the side surface of the insulator 280 in the opening, the side surfaces of the conductor 242a2 and the conductor 242b2, the top surface of the conductor 242a1, the top surface of the conductor 242b1, and the top surface of the insulator 222. In other words, it can also be said that the insulator 255 is formed in a sidewall shape so as to be in contact with the sidewall of the opening formed in the insulator 280 or the like. Here, the sidewall of the opening corresponds to, for example, the side surface of the insulator 280 or the like in the opening.

[0213] In addition, the insulator 250 is in contact with the side surface of the insulator 255.

[0214] The insulator 255 preferably has an oxygen barrier property. When the insulator 255 has an oxygen barrier property, oxidation of the sides of the conductors 242a and 242b can be suppressed, and an oxide film can be prevented from forming on these sides. Therefore, a decrease in the on-state current or field-effect mobility of the transistor 200 can be suppressed. As the insulator 255, a barrier insulator that can be used for the insulator 275 or the like can be used. For example, silicon nitride can be used as the insulator 255.

[0215] The opening provided in the insulator 280 overlaps with the region between the conductors 242a2 and 242b2. In a plan view, the side surfaces of the insulator 280 in the above-described opening are aligned or substantially aligned with the side surfaces of the conductor 242a2 and the conductor 242b2. In addition, a part of the conductors 242a1 and 242b1 is formed to protrude inward of the above-described opening. In other words, in the conductor 242a1, the portion where the insulator 255 is formed on its top surface (hereinafter, sometimes referred to as the protruding portion of the conductor 242a1) is formed so as to protrude toward the conductor 260 side more than the conductor 242a2. Similarly, in the conductor 242b1, the portion where the insulator 255 is formed on its top surface (hereinafter, sometimes referred to as the protruding portion of the conductor 242b1) is formed so as to protrude toward the conductor 260 side more than the conductor 242b2.

[0216] Here, a part of the top surface of the conductor 242a1 is in contact with the conductor 242a2, and a part of the top surface of the conductor 242b1 is in contact with the conductor 242b2. Therefore, the insulator 255 is in contact with another part of the top surface of the conductor 242a1, another part of the top surface of the conductor 242b1, the side surfaces of the conductor 242a2, and the side surfaces of the conductor 242b2 inside the above-described opening. In addition, the insulator 250 is in contact with the top surface of the oxide semiconductor 230, the side surfaces of the conductor 242a1, the side surfaces of the conductor 242b1, and the side surfaces of the insulator 255.

[0217] After the conductive layer is divided into the conductors 242a2 and 242b2, the insulator 255 is formed by anisotropic etching. The insulator 255 is formed in a sidewall shape so as to be in contact with the sidewall of the opening provided in the insulator 280. The insulator 255 is formed so as to be in contact with the side surfaces of the conductor 242a2 and the conductor 242b2, and has a function of protecting the conductor 242a2 and the conductor 242b2.

[0218] In addition, the insulator 255 is used as a mask when the conductive layer is divided into the conductors 242a1 and 242b1. Therefore, as Figure 6A shown, when the transistor 200 is viewed in cross section, the side ends of the insulator 255 are preferably aligned with the side ends of the conductor 242a1 and the side ends of the conductor 242b1.

[0219] After being divided into the conductor 242a1 and the conductor 242b1 and before depositing the insulator 250, heat treatment is preferably performed in an oxygen-containing atmosphere. At this time, since the insulator 255 is formed in contact with the side surfaces of the conductor 242a2 and the conductor 242b2, over-oxidation of the conductor 242a2 and the conductor 242b2 can be prevented. When microwave treatment is performed after being divided into the conductor 242a1 and the conductor 242b1, formation of an oxide film on the side surfaces of the conductor 242a and the conductor 242b can also be suppressed.

[0220] The arrangements of the insulator 255, the insulator 250, and the conductor 260 are set in the portion of the opening formed in the insulator 280 to reflect the shape of the opening. Therefore, the insulator 255 is arranged to cover the side wall of the opening, the insulator 250 is arranged to cover the bottom of the opening and the insulator 255, and the conductor 260 is arranged to be embedded in the recess of the insulator 250.

[0221] Note that, similar to the above <structural example of a semiconductor device>, the insulator 250 may also have a laminated structure. For example, as Figure 6A shown, the insulator 250 may also have a three-layer structure of the insulator 250a, the insulator 250b, and the insulator 250c. In addition, for example, as Figure 6B shown, the insulator 250 may also have a four-layer structure of the insulator 250a, the insulator 250b, the insulator 250c, and the insulator 250d. Additionally, not limited to the Figure 6B shown structure, any one or more of the insulator 250a, the insulator 250b, the insulator 250c, and the insulator 250d can be selected to form the insulator 250. For example, an insulator 250 having the Figures 3A to 3D shown structure can be used.

[0222] In addition, the thickness of the insulator 255 is preferably 0.5 nm or more and 20 nm or less, more preferably 0.5 nm or more and 10 nm or less, and still more preferably 0.5 nm or more and 3 nm or less. When the insulator 255 has the above thickness, over-oxidation of the conductors 242a2 and 242b2 can be suppressed. Note that the insulator 255 only needs to have a region with a thickness of the above value in at least a part thereof. In addition, since the insulator 255 is provided in contact with the side walls of the openings formed in the insulator 280 and the like, deposition by an ALD method or the like with good coverage is preferably used. When the thickness of the insulator 255 is too large, the deposition time of the insulator 255 by the ALD method becomes long, resulting in a decrease in productivity. Therefore, the thickness of the insulator 255 is preferably set to the above range approximately. In addition, as the thickness of the insulator 255, a thickness that does not excessively block the diffusion of excess oxygen from the insulator 280 to the insulator 250b and the diffusion of excess oxygen from the insulator 250b to the oxide semiconductor 230 is preferably employed.

[0223] As Figure 6A shown, when the transistor 200 is viewed in cross-section in the channel length direction, the distance L1 between the conductors 242a1 and 242b1 is smaller than the distance L2 between the conductors 242a2 and 242b2. Here, the distance L1 refers to the shortest distance between the conductors 242a1 and 242b1, and the distance L2 refers to the shortest distance between the conductors 242a2 and 242b2. By adopting such a structure, the distance between the source and the drain can be further reduced and, correspondingly, the channel length can be reduced. Therefore, the frequency characteristics of the transistor 200 can be improved. In this way, by realizing miniaturization of the semiconductor device, a semiconductor device with an increased operating speed can be provided.

[0224] In Figure 6A the structure shown, the difference between the distance L2 and the distance L1 is equal to twice the thickness of the insulator 255. In other words, the distance L2 is equal to the distance L1 plus twice the thickness of the insulator 255. Here, the thickness of the insulator 255 refers to the width in the A1 - A2 direction of at least a part of the insulator 255.

[0225] In addition, the insulator 255 may also have a stacked structure of two or more layers. In this case, as long as at least one layer is the above-mentioned inorganic insulator that is not easily oxidized. For example, the above-mentioned inorganic insulator that is not easily oxidized can be used as the first insulator of the insulator 255, and an insulator that can be used for the insulator 250b (such as silicon oxide, etc.) can be used as the second insulator on the first insulator of the insulator 255. The dielectric constant of the second insulator of the insulator 255 is preferably lower than that of the first insulator of the insulator 255. In this way, by adopting a two-layer structure as the insulator 255 to increase the thickness, the distance between the conductor 260 and the conductor 242a or the conductor 242b can be increased to reduce the parasitic capacitance.

[0226] An example of forming the insulator 255 into a sidewall shape by anisotropic etching is shown above, but the present invention is not limited thereto. As Figure 6C shown, the insulator 255 may also have a shape with an opening inside the opening formed in the insulator 280 or the like. In this case, a part of the insulating film that will become the insulator 255 can be removed by lithography to form the opening of the insulator 255. The opening of the insulator 255 preferably overlaps with the region between the conductor 242a1 and the conductor 242b1.

[0227] As Figure 6C shown, when viewed in cross-section, a protruding portion is formed below the insulator 255. The protruding portion of the insulator 255 overlaps with the protruding portion of the conductor 242a1 and the protruding portion of the conductor 242b1.

[0228] <Modification Example 2>

[0229] In Modification Example 1, a structure in which the insulator 255 is provided in contact with the sidewall of the opening formed in the insulator 280 or the like is described, but the present invention is not limited to this structure. For example, the insulator 255 may not be provided in the opening.

[0230] Refer to Figures 7A to 8 to describe a modification example of the semiconductor device described in Modification Example 1. Figures 7A to 7D are a plan view and a cross-sectional view of a semiconductor device including the transistor 200, corresponding to the Figures 5A to 5D shown plan view and cross-sectional view respectively. In addition, Figure 8 is a cross-sectional enlarged view in the channel length direction of the transistor 200, corresponding to the Figure 6C shown cross-sectional enlarged view.

[0231] Figures 7A to 7D The transistor 200 shown in Figures 5A to 5D is a modification example of the transistor 200 shown in Figures 7A to 7D Specifically, the transistor 200 shown in Figures 5A to 5Dis different from the transistor 200 shown below. Hereinafter, the parts different from the descriptions of the above <Structural Example of Semiconductor Device> and <Modification Example 1> will be mainly described, and the descriptions of the overlapping parts may be omitted with reference to those parts.

[0232] As Figure 8 shown, in the case where the insulator 255 is not provided, a part of the insulator 250 is arranged so as to overlap the protruding portions of the conductor 242a1 and the conductor 242b1. In addition, a part of the conductor 260 may be arranged so as to overlap the protruding portions of the conductor 242a1 and the conductor 242b1. Here, the protruding portions of the conductor 242a1 and the conductor 242b1 are in contact with the insulator 250. In addition, the side surface of the insulator 250 is in contact with the side surfaces of the insulator 280, the insulator 275, the insulator 271a, the insulator 271b, the side surface of the conductor 242a2, and the side surface of the conductor 242b2.

[0233] The arrangement of the insulator 250 is formed by reflecting the shape of the opening provided in the insulator 280 in the portion provided in the opening. Therefore, the insulator 250 is formed by reflecting the shapes of the conductors 242a1 and 242b1 protruding into the opening.

[0234] As Figure 8 shown, when the transistor 200 is cross-sectioned in the channel length direction, the distance L1 between the conductor 242a1 and the conductor 242b1 is smaller than the distance L2 between the conductor 242a2 and the conductor 242b2. By adopting such a structure, the distance between the source and the drain can be further reduced and the channel length can be reduced accordingly. Therefore, the frequency characteristics of the transistor 200 can be improved. In this way, by miniaturizing the semiconductor device, a semiconductor device with an increased operating speed can be provided.

[0235] Furthermore, by adopting Figure 8 the structure shown, the width of the upper part of the conductor 260 can be made larger than the distance L1. Thereby, the wiring resistance of the conductor 260 can be reduced. Therefore, the power consumption of the semiconductor device can be reduced.

[0236] Note that, similar to the above <Structural Example of Semiconductor Device>, the insulator 250 may also have a laminated structure. For example, as Figure 6A shown, the insulator 250 may also have a three-layer structure of the insulator 250a, the insulator 250b, and the insulator 250c. In addition, for example, as Figure 6B shown, the insulator 250 may also have a four-layer structure of the insulator 250a, the insulator 250b, the insulator 250c, and the insulator 250d. In addition, not limited to Figure 6BFor the structure shown, any one or more of insulator 250a, insulator 250b, insulator 250c, and insulator 250d can be selected to form insulator 250. For example, an insulator 250 having the Figures 3A to 3D structure shown can be used.

[0237] <Constituent Materials of Semiconductor Devices>

[0238] Hereinafter, the constituent materials that can be used for semiconductor devices will be described. Note that each layer constituting the semiconductor device can have either a single-layer structure or a stacked structure.

[0239] <<Substrate>>

[0240] As the substrate for forming transistors, for example, an insulator substrate, a semiconductor substrate, or a conductor substrate can be used. As the insulator substrate, for example, a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (such as a yttria-stabilized zirconia substrate), and a resin substrate can be cited. In addition, as the semiconductor substrate, for example, a semiconductor substrate made of silicon or germanium, and a compound semiconductor substrate composed of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide can be cited. Also, a semiconductor substrate having an insulator region inside the above semiconductor substrate can be cited, for example, an SOI (Silicon On Insulator) substrate, etc. As the conductor substrate, for example, a graphite substrate, a metal substrate, an alloy substrate, and a conductive resin substrate can be cited. In addition, as the substrate, for example, a substrate containing a metal nitride, a substrate containing a metal oxide, an insulator substrate provided with a conductor or a semiconductor, a semiconductor substrate provided with a conductor or an insulator, and a conductor substrate provided with a semiconductor or an insulator can be cited. Or, the above substrate provided with one or more elements can also be used. As the elements provided on the substrate, for example, a capacitor, a resistor, a switching element, a light-emitting element, and a storage element can be cited.

[0241] <<Insulator>>

[0242] The insulators 212, 214, 216, 221, 222, 224, 250, 275, 280, 282, 283, 285, 241a, 241b, 271a, 271b, and 255 shown in this embodiment can appropriately use any of the insulators shown below. As the insulator, for example, oxides, nitrides, oxynitrides, nitroxides, metal oxides, metal oxynitrides, and metal nitroxides having insulating properties can be cited.

[0243] For example, when miniaturizing and highly integrating transistors, problems such as leakage current sometimes occur due to the thinning of the gate insulator film. By using a high-k material as the insulator for the gate insulator, it is possible to achieve a lower voltage during transistor operation while maintaining the physical thickness. On the other hand, by using a material with a low relative permittivity as the insulator for the interlayer film, the parasitic capacitance generated between the wirings can be reduced. Therefore, it is preferable to select a material according to the function of the insulator.

[0244] Examples of insulators with a high relative permittivity include gallium oxide, hafnium oxide, zirconium oxide, an oxide containing aluminum and hafnium, an oxynitride containing aluminum and hafnium, an oxide containing silicon and hafnium, an oxynitride containing silicon and hafnium, or a nitride containing silicon and hafnium.

[0245] Examples of insulators with a low relative permittivity include silicon oxide, silicon oxynitride, silicon oxynitride, silicon nitride, silicon oxide added with fluorine, silicon oxide added with carbon, silicon oxide added with carbon and nitrogen, silicon oxide having holes, and resin.

[0246] In addition, by surrounding a transistor using a metal oxide with an insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen, the electrical characteristics of the transistor can be stabilized. Examples of insulators having a function of suppressing the permeation of impurities such as hydrogen and oxygen include a single layer or a stack of insulators containing one or more of boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, and tantalum. Specifically, examples of insulators having a function of suppressing the permeation of impurities such as hydrogen and oxygen include metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, and nitrides such as aluminum nitride, silicon oxynitride, and silicon nitride.

[0247] In addition, the insulator used as the gate insulator is preferably an insulator having a region containing oxygen that can be removed by heating. For example, when adopting a structure in which silicon oxide or silicon oxynitride having a region containing oxygen that can be removed by heating is in contact with the oxide semiconductor 230, the oxygen vacancies contained in the oxide semiconductor 230 can be filled.

[0248] <<Conductor>>

[0249] As the conductors 205, 242a, 242b, 260, 240a, and 240b shown in this embodiment, any of the conductors shown below can be appropriately used. As the conductor, it is preferable to use a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, cobalt, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, and lanthanum, an alloy containing the above metal element as a component, or an alloy combining the above metal elements. As the conductor, for example, tantalum nitride, titanium nitride, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, and an oxide containing lanthanum and nickel can be cited. In addition, tantalum nitride, titanium nitride, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, and an oxide containing lanthanum and nickel are conductive materials that are not easily oxidized or materials that maintain conductivity even when absorbing oxygen, so they are preferable. In addition, a semiconductor with high conductivity typified by polysilicon containing impurity elements such as phosphorus or a silicide such as nickel silicide can also be used.

[0250] In the case of using a laminated conductor, for example, a laminated structure combining a material containing the above metal element and a conductive material containing oxygen, a laminated structure combining a material containing the above metal element and a conductive material containing nitrogen, or a laminated structure combining a material containing the above metal element, a conductive material containing oxygen, and a conductive material containing nitrogen can also be adopted.

[0251] In addition, when an oxide is used for the channel formation region of the transistor, as the conductor used for the gate electrode, a laminated structure combining a material containing the above metal element and a conductive material containing oxygen is preferably adopted. In this case, it is preferable to dispose the conductive material containing oxygen on the channel formation region side. By disposing the conductive material containing oxygen on the channel formation region side, the oxygen released from the conductive material is easily supplied to the channel formation region.

[0252] In particular, as the conductor used for the gate electrode, a conductive material containing the metal element and oxygen contained in the metal oxide forming the channel is preferably used. In addition, a conductive material containing the above metal element and nitrogen can also be used. For example, a nitrogen-containing conductive material such as titanium nitride and tantalum nitride can be used. In addition, indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, indium tin oxide added with silicon, or one or more thereof can also be used. In addition, indium gallium zinc oxide containing nitrogen can also be used. By using the above materials, it is sometimes possible to capture the hydrogen contained in the metal oxide forming the channel. Or, it is sometimes possible to capture the hydrogen mixed in from an external insulator or the like.

[0253] <Example of manufacturing method of semiconductor device>

[0254] Refer to Figures 9A to 16D An example of a manufacturing method of a semiconductor device according to one embodiment of the present invention will be described. Here, the case of manufacturing the Figures 1A to 1D shown semiconductor device will be taken as an example for description.

[0255] Figure 9A , Figure 10A , Figure 11A , Figure 12A , Figure 14A , Figure 15A and Figure 16A are plan views. Figure 9B , Figure 10B , Figure 11B , Figure 12B , Figure 14B , Figure 15B and Figure 16B are cross-sectional views along the dashed line A1 - A2 in Figure 9A , Figure 10A , Figure 11A , Figure 12A , Figure 14A , Figure 15A and Figure 16A respectively. This cross-sectional view corresponds to the cross-sectional view in the channel length direction of the transistor 200. Figure 9C , Figure 10C , Figure 11C , Figure 12C , Figure 14C , Figure 15C and Figure 16C are cross-sectional views along the dashed line A3 - A4 in Figure 9A , Figure 10A , Figure 11A , Figure 12A , Figure 14A , Figure 15A and Figure 16A respectively. This cross-sectional view corresponds to the cross-sectional view in the channel width direction of the transistor 200. Figure 9D , Figure 10D , Figure 11D , Figure 12D , Figure 14D , Figure 15D and Figure 16D are cross-sectional views along the dashed line A5 - A6 in Figure 9A , Figure 10A , Figure 11A , Figure 12A , Figure 14A , Figure 15A and Figure 16A respectively. This cross-sectional view corresponds to the cross-sectional view in the channel width direction of the transistor 200. Note that in Figure 9A ,Figure 10A , Figure 11A , Figure 12A , Figure 14A , Figure 15A and Figure 16A In the plan views of, for clarity, some constituent elements are omitted. Further, Figure 13A1 , Figure 13B1 , Figure 13C1 , Figure 13D1 correspond to Figure 1B a partial cross-sectional view, which is a cross-sectional view corresponding to the channel length direction of the transistor 200. Further, Figure 13A2 , Figure 13B2 , Figure 13C2 , Figure 13D2 correspond to Figure 1C a partial cross-sectional view, which is a cross-sectional view corresponding to the channel width direction of the transistor 200.

[0256] Hereinafter, as the insulating material for forming the insulator, the conductive material for forming the conductor, or the semiconductor material for forming the semiconductor, sputtering method, chemical vapor deposition (CVD: Chemical Vapor Deposition) method, molecular beam epitaxy (MBE: Molecular Beam Epitaxy) method, pulsed laser deposition (PLD: Pulsed Laser Deposition) method, ALD method, etc. can be appropriately used for deposition.

[0257] First, a substrate (not shown) is prepared, and an insulator 212 is deposited on the substrate, and an insulator 214 is deposited on the insulator 212 (see Figures 9A to 9D ). The insulator 212 and the insulator 214 can use the above-mentioned insulating materials. For example, the insulator 212 and the insulator 214 can be deposited by sputtering method, CVD method, MBE method, PLD method or ALD method. By using the sputtering method that does not require using a molecule containing hydrogen as a deposition gas, the hydrogen concentration in the insulator 212 and the insulator 214 can be reduced, so it is preferable.

[0258] In the present embodiment, silicon nitride is deposited as the insulator 212 by sputtering method, and aluminum oxide is deposited as the insulator 214 by sputtering method. Thus, by using silicon nitride having a function of suppressing hydrogen diffusion as the insulator 212, hydrogen diffusion from the lower layer of the transistor 200 can be suppressed. And, by using aluminum oxide having a function of capturing or fixing hydrogen as the insulator 214, hydrogen contained in the insulator 216 etc. can be captured or fixed by the insulator 214. Thereby, the hydrogen concentration in the oxide semiconductor 230 and its vicinity can be reduced.

[0259] In addition, it is preferable to perform a heat treatment before depositing the insulator 212 to reduce water and hydrogen adsorbed to the substrate (including circuit elements and interlayer films formed on the substrate). In the present embodiment, the temperature of the heat treatment is set to 400°C.

[0260] Next, an insulator 216 is deposited on the insulator 214. The insulator 216 is preferably deposited by sputtering. By using a sputtering method that does not require molecules containing hydrogen as deposition gases, the hydrogen concentration in the insulator 216 can be reduced. Note that the deposition method of the insulator 216 is not limited to the sputtering method, and for example, a CVD method, MBE method, PLD method, ALD method, etc. can also be appropriately used. In the present embodiment, silicon oxide is deposited as the insulator 216 by sputtering.

[0261] The insulators 212, 214, and 216 are preferably continuously deposited without being exposed to the atmosphere. For example, a deposition apparatus with a multi-chamber system can be used. Thereby, the insulators 212, 214, and 216 can be deposited while reducing hydrogen in the film, and hydrogen can be prevented from being mixed into the film between the respective deposition processes.

[0262] Next, an opening reaching the insulator 214 is formed in the insulator 216. The opening is formed in the region where the conductor 205 will be formed. When forming the opening, wet etching can be used, but dry etching is preferred for microfabrication. As the insulator 214, an insulator that serves as an etch stop film when etching the insulator 216 is preferably selected. For example, when silicon oxide or silicon oxynitride is used as the insulator 216, the insulator 214 is preferably silicon nitride, aluminum oxide, hafnium oxide, or the like.

[0263] After forming the opening, a conductive film that will become the conductor 205 is deposited, and CMP processing is performed until the insulator 216 is exposed, removing a part of the conductive film that will become the conductor 205. Thereby, the conductor 205 embedded in the insulator 216 can be formed (refer to Figures 9A to 9D ).

[0264] Here, the conductive film that will become the conductor 205 can use the above-mentioned conductive materials and be deposited by sputtering, CVD method, MBE method, PLD method, ALD method, etc. For example, a tantalum nitride film, a titanium nitride film, and a tungsten film can be deposited in layers by CVD method. Thereby, as Figure 2A shown, the conductor 205 can have a laminated structure of a conductor 205a having titanium nitride laminated on tantalum nitride and a conductor 205b made of tungsten.

[0265] Next, an insulator 221 is deposited on the insulator 216 and the conductor 205 (refer to Figures 9A to 9D ).

[0266] The insulator 221 can be the above-described insulator that has a barrier property against oxygen, hydrogen, and water. The insulator 221 can be deposited, for example, by a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. In the present embodiment, silicon nitride is deposited as the insulator 221 by a PEALD method.

[0267] Next, an insulator 222 is deposited on the insulator 221 (see Figures 9A to 9D ).

[0268] As the insulator 222, an insulator containing an oxide of one or both of aluminum and hafnium is preferably deposited. As the insulator containing an oxide of one or both of aluminum and hafnium, for example, alumina, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate) is preferably used. Alternatively, hafnium zirconium oxide is preferably used. The insulator containing an oxide of one or both of aluminum and hafnium has a barrier property against oxygen, hydrogen, and water. When the insulator 222 has a barrier property against hydrogen and water, hydrogen and water contained in the structure around the transistor can be inhibited from diffusing into the inside of the transistor through the insulator 222, and thus generation of oxygen vacancies in the oxide semiconductor 230 can be inhibited.

[0269] The insulator 222 can be deposited, for example, by a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. In the present embodiment, hafnium oxide is deposited as the insulator 222 by a thermal ALD method.

[0270] In the present embodiment, silicon nitride is deposited as the insulator 221 by a PEALD method, and hafnium oxide is deposited as the insulator 222 by a thermal ALD method. Thus, by using silicon nitride having a function of suppressing hydrogen diffusion as the insulator 221, diffusion of hydrogen from the lower layer of the transistor 200 can be suppressed. Furthermore, by using hafnium oxide having a function of capturing or fixing hydrogen as the insulator 222, hydrogen in the insulator 224 or the like can be captured or fixed by the insulator 222. Thereby, the hydrogen concentration in and around the oxide semiconductor 230 can be reduced.

[0271] Next, an insulating film 224f is deposited on the insulator 222 (see Figures 9A to 9D ). As the insulating film 224f, an insulator corresponding to the above-described insulator 224 can be used. By forming the insulating film 224f in this way, the insulating film 224f is formed parallel to or substantially parallel to the substrate surface.

[0272] The insulating film 224f can be deposited, for example, by a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. In this embodiment, silicon oxide is deposited as the insulating film 224f by a sputtering method. By using a sputtering method that does not require the use of a molecule containing hydrogen as a deposition gas, the hydrogen concentration in the insulating film 224f can be reduced. Since the insulating film 224f comes into contact with the oxide semiconductor 230 in a subsequent process, it is preferable that the hydrogen concentration is reduced as described above.

[0273] Next, an oxide semiconductor film 230f is deposited on the insulating film 224f (see Figures 9A to 9D ). The oxide semiconductor film 230f can be deposited using the same method as the deposition of the oxide semiconductor described in Embodiment 2. It is preferable to use indium oxide (for example, indium oxide, indium gallium oxide, indium zinc oxide, indium gallium zinc oxide, or indium gallium tin zinc oxide, etc.) for the oxide semiconductor film 230f. When the oxide semiconductor film 230f contains indium oxide, a semiconductor device with a high field-effect mobility can be provided. In addition, a semiconductor device with at least one of good electrical characteristics, frequency characteristics, and reliability can be provided. When the oxide semiconductor film 230f is formed as described above, the oxide semiconductor film 230f is formed parallel to or substantially parallel to the substrate surface.

[0274] For example, as Figure 2A shown, in the case where the oxide semiconductor 230 has a three-layer structure of oxide semiconductors 230a to 230c, a film that will become the oxide semiconductors 230a and 230b can be deposited by an ALD method, and a film that will become the oxide semiconductor 230c can be deposited by a sputtering method. Specifically, a film that will become the oxide semiconductor 230a can be deposited in such a manner that it has a composition of In:Ga:Zn = 1:3:2 [atomic ratio] or near it. Alternatively, gallium oxide can also be used for the film that will become the oxide semiconductor 230a. In addition, indium oxide can be used to deposit the film that will become the oxide semiconductor 230b. In addition, a film that will become the oxide semiconductor 230c can be deposited using an oxide target having a composition of In:Ga:Zn = 1:1:1.2 [atomic ratio] or near it.

[0275] For example, in the above structure, the oxide semiconductor 230a can also be deposited by a sputtering method. Specifically, a film that will become the oxide semiconductor 230a can be deposited using an oxide target having a composition of In:Ga:Zn = 1:3:2 [atomic ratio] or near it.

[0276] Next, a heat treatment is preferably performed. The heat treatment of the oxide semiconductor film 230f can be performed using the same method as the heat treatment described in Embodiment 2.

[0277] For example, as the heat treatment, a treatment can be performed for 1 hour at a temperature of 450°C with a flow rate ratio of nitrogen gas to oxygen gas of 4:1.

[0278] By performing the heat treatment, the crystallinity of the oxide semiconductor 230 can be improved. Thereby, the on-state current, S value (subthreshold swing value), field-effect mobility, and frequency characteristics of the transistor 200 can be improved to provide a semiconductor device having good electrical characteristics. In addition, a semiconductor device with high reliability can be provided.

[0279] The heat treatment is performed in a nitrogen gas or inert gas atmosphere or an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. The heat treatment can also be performed under reduced pressure. Alternatively, the heat treatment can be performed in a nitrogen gas or inert gas atmosphere and then, in order to replenish the oxygen that has escaped, the heat treatment can be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas.

[0280] In addition, the gas used in the above heat treatment is preferably highly purified. For example, the amount of moisture in the gas used in the above heat treatment is preferably 1 ppb or less, more preferably 0.1 ppb or less, and still more preferably 0.05 ppb or less. By performing the heat treatment using a highly purified gas, absorption of moisture and the like by the oxide semiconductor film 230f and the like can be prevented as much as possible. In addition, highly purified gas can also be used for the heat treatment before this process and the heat treatment after this process.

[0281] By such a heat treatment including oxygen gas, impurities such as carbon, water, and hydrogen in the oxide semiconductor film 230f can be reduced. By reducing the impurities in the film in this way, the crystallinity of the oxide semiconductor film 230f is improved, and a denser structure with a higher density can be achieved. Therefore, the crystalline region in the oxide semiconductor film 230f can be increased, and the in-plane non-uniformity of the crystalline region in the oxide semiconductor film 230f can be reduced. Therefore, the in-plane non-uniformity of the electrical characteristics of the transistor can be reduced.

[0282] In addition, by performing the heat treatment, oxygen can be supplied to the oxide semiconductor film 230f to reduce the oxygen vacancies in the oxide semiconductor film 230f. Thereby, the reliability of the transistor 200 can be improved.

[0283] In addition, by performing a heat treatment, hydrogen in the insulator 216, the insulating film 224f, and the oxide semiconductor film 230f moves to the insulator 222 and is absorbed by the insulator 222. In other words, hydrogen in the insulator 216, the insulating film 224f, and the oxide semiconductor film 230f diffuses into the insulator 222. Therefore, although the hydrogen concentration in the insulator 222 increases, the hydrogen concentrations in the insulator 216, the insulating film 224f, and the oxide semiconductor film 230f all decrease. Here, when the insulator 221 is provided in contact with the bottom surface of the insulator 222, it is possible to prevent impurities such as moisture or hydrogen from entering from below the insulator 221 due to this heat treatment.

[0284] In particular, the insulating film 224f (the subsequent insulator 224) is used as the second gate insulator of the transistor 200, and the oxide semiconductor film 230f (the subsequent oxide semiconductor 230) is used as the channel formation region of the transistor 200. The transistor 200 formed using the insulating film 224f and the oxide semiconductor film 230f with reduced hydrogen concentration has high reliability, so it is preferable.

[0285] Next, a conductive film 242f is deposited on the oxide semiconductor film 230f (refer to Figures 9A to 9D ). As the conductive film 242f, a conductor corresponding to the above-mentioned conductors 242a and 242b can be used. After depositing the oxide semiconductor film 230f, the conductive film 242f is deposited on and in contact with the oxide semiconductor film 230f without an etching process or the like. Thus, the top surface of the oxide semiconductor film 230f can be protected by the conductive film 242f. As a result, since the diffusion of impurities into the oxide semiconductor 230 constituting the transistor can be reduced, the electrical characteristics and reliability of the semiconductor device can be improved.

[0286] The conductive film 242f can be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method.

[0287] In this embodiment, tantalum nitride is deposited as the conductive film 242f by a sputtering method. In addition, a heat treatment can also be performed before depositing the conductive film 242f. This heat treatment can also be performed under reduced pressure, and the conductive film 242f is continuously deposited in a manner not exposed to the atmosphere. By performing such a treatment, moisture and hydrogen adsorbed on the surface of the oxide semiconductor 230 can be removed, and the moisture concentration and hydrogen concentration in the oxide semiconductor 230 can be reduced. The temperature of the heat treatment is preferably 100°C or higher and 400°C or lower.

[0288] Next, an insulating film 271f is deposited on the conductive film 242f (refer to Figures 9A to 9D)。The insulating film 271f can be deposited by methods such as sputtering, CVD, MBE, PLD, or ALD. The insulating film 271f is preferably an insulating film having a function of suppressing oxygen permeation. For example, as the insulating film 271f, a laminated film of a silicon nitride film and a silicon oxide film on the silicon nitride film deposited by sputtering can be used. By adopting such a structure, the insulator 271a (insulator 271b) can have a laminated structure of an insulator 271a1 (insulator 271b1) made of silicon nitride and an insulator 271a2 (insulator 271b2) made of silicon oxide.

[0289] Here, when a laminated film is used as the insulating film 271f, the deposition is continuously performed in such a manner as not to be exposed to the atmospheric environment. By performing the deposition without being exposed to the atmosphere, the cleanliness near the interface of the laminated film of the insulating film 271f can be maintained. In addition, it is more preferably to continuously deposit the conductive film 242f to the insulating film 271f without being exposed to the atmosphere.

[0290] In addition, a heat treatment can also be performed before depositing the insulating film 271f. This heat treatment can also be performed under reduced pressure, and the insulating film 271f is continuously deposited in such a manner as not to be exposed to the atmosphere. By performing such treatment, moisture and hydrogen adsorbed on the surface of the conductive film 242f can be removed, and the moisture concentration and hydrogen concentration in the conductive film 242f can be reduced. The temperature of the heat treatment is preferably 100 °C or higher and 400 °C or lower.

[0291] Next, the insulating film 224f, the oxide semiconductor film 230f, the conductive film 242f, and the insulating film 271f are processed into island shapes by lithography to form an insulator 224, an oxide semiconductor 230, a conductor 242A, and an insulator 271A (see Figures 10A to 10D ).

[0292] The above processing can use a dry etching method or a wet etching method. Processing using the dry etching method is suitable for microfabrication. In addition, the processing of the insulating film 224f, the oxide semiconductor film 230f, the conductive film 242f, and the insulating film 271f can also be performed under different conditions respectively.

[0293] Here, it is preferable to process the insulator 224, the oxide semiconductor 230, the conductor 242A, and the insulator 271A into island shapes at one time. At this time, the side end portion of the conductor 242A is preferably aligned or substantially aligned with the side end portion of the oxide semiconductor 230. Furthermore, the side end portion of the insulator 224 is preferably aligned or substantially aligned with the side end portion of the oxide semiconductor 230. In addition, the side end portion of the insulator 271A is preferably aligned or substantially aligned with the side end portion of the conductor 242A. By adopting the above structure, the number of processes of the semiconductor device according to one aspect of the present invention can be reduced. Thereby, a manufacturing method of a semiconductor device with good productivity can be provided.

[0294] In addition, the insulator 224, the oxide semiconductor 230, the conductor 242A, and the insulator 271A are formed such that at least a part thereof overlaps with the conductor 205. Further, in a region that does not overlap with the insulator 224, the oxide semiconductor 230, the conductor 242A, and the insulator 271A, the insulator 222 is exposed. However, not limited thereto, a structure in which the insulator 224 remains on the insulator 222 in a region that does not overlap with the oxide semiconductor 230 may also be employed. In this case, as in the transistor 200 of Figures 4A to 4D , the insulator 224 is not in an island shape but has a shape in which an opening is partially formed.

[0295] As in Figures 10B to 10D shown, the side surface shapes of the insulator 224, the oxide semiconductor 230, the conductor 242A, and the insulator 271A may also be tapered shapes. The taper angles of the side surfaces of the insulator 224, the oxide semiconductor 230, the conductor 242A, and the insulator 271A may be, for example, 60° or more and less than 90°. Thus, when the side surfaces are tapered, in subsequent processes, the coverage of the insulator 275 or the like is improved, and defects such as voids can be reduced.

[0296] In addition, not limited thereto, a structure in which the side surfaces of the insulator 224, the oxide semiconductor 230, the conductor 242A, and the insulator 271A are perpendicular or substantially perpendicular to the top surface of the insulator 222 may also be employed. By adopting such a structure, miniaturization and high density can be achieved when a plurality of transistors are provided.

[0297] Note that in lithography, first, a resist is exposed through a mask. Next, a resist mask is formed by removing or leaving the exposed region using a developer. Next, an etching process is performed through the resist mask to process a conductor, a semiconductor, an insulator, or the like into a desired shape. For example, a resist mask can be formed by exposing a resist using a KrF excimer laser, an ArF excimer laser, EUV (Extreme Ultraviolet) light, or the like. In addition, a liquid immersion technique in which exposure is performed in a state where a liquid (for example, water) is filled between a substrate and a projection lens can also be used. In addition, an electron beam or an ion beam can be used instead of the above light. In addition, in the case of using an electron beam or an ion beam, a photomask may sometimes not be used.

[0298] The unnecessary resist mask after processing can be removed by performing a dry etching process such as ashing using oxygen plasma (hereinafter, sometimes referred to as oxygen plasma treatment), performing a wet etching process, performing a wet etching process after a dry etching process, or performing a dry etching process after a wet etching process.

[0299] Furthermore, a hard mask made of an insulator or a conductor can also be used under the resist mask. When using a hard mask, an insulating film or a conductive film that becomes the hard mask material can be formed on the insulating film 271f, and a resist mask can be formed thereon, and then the hard mask material can be etched to form a hard mask having a desired shape. For example, tungsten can also be used as the hard mask material. The etching of the insulating film 271f or the like can be performed after removing the resist mask, or can be performed without removing the resist mask. In the latter case, the resist mask sometimes disappears during etching. The hard mask can also be removed by etching after the etching of the oxide semiconductor film 230f or the like. On the other hand, when the hard mask material does not affect the subsequent processes or can be used in the subsequent processes, it is not necessary to remove the hard mask.

[0300] In addition, an SOC (Spin On Carbon) film and an SOG (Spin On Glass) film can also be deposited between the workpiece and the resist mask. By using the SOC film and the SOG film as masks, the adhesion between the workpiece and the resist mask can be improved, and the durability of the mask pattern can be improved. For example, lithography can be performed by sequentially depositing an SOC film, an SOG film, and a resist mask on the workpiece.

[0301] As the etching gas for dry etching treatment, an etching gas containing a halogen can be used. Specifically, an etching gas containing one or more of fluorine, chlorine, and bromine can be used. As the etching gas, for example, a mixed gas of one or more of C4F6 gas, C5F6 gas, C4F8 gas, CF4 gas, SF6 gas, CHF3 gas, CH2F2 gas, Cl2 gas, BCl3 gas, SiCl4 gas, and BBr3 gas can be used. In addition, oxygen gas, carbon dioxide gas, nitrogen gas, helium gas, argon gas, hydrogen gas, or hydrocarbon gas can be appropriately added to the above etching gas. In addition, depending on the workpiece to be dry-etched, a gas containing a hydrocarbon gas or a hydrogen gas instead of a halogen gas can also be used as the etching gas. As the hydrocarbon for the etching gas, one or more of methane (CH4), ethane (C2H6), propane (C3H8), butane (C4H 10 )), ethylene (C2H4), propylene (C3H6), acetylene (C2H2), and propyne (C3H4) can be used. The etching conditions can be appropriately set according to the etching object.

[0302] In addition, as a dry etching device, a capacitively coupled plasma (CCP) etching device including parallel plate electrodes can be used. A capacitively coupled plasma etching device including parallel plate electrodes can also adopt a structure in which a high-frequency voltage is applied to one of the parallel plate electrodes. Alternatively, a structure in which high-frequency voltages of the same frequency are applied to each of the parallel plate electrodes can also be adopted. In addition, a structure in which a plurality of different high-frequency voltages are applied to the parallel plate electrodes can also be adopted. Such a CCP etching device is called a dual frequency capacitively coupled plasma (DF-CCP) etching device. In the DF-CCP etching device, high-frequency voltages of different frequencies may be applied to each of the parallel plate electrodes. Alternatively, a structure in which a plurality of different high-frequency voltages are applied to one of the parallel plate electrodes can also be adopted. Alternatively, a dry etching device having a high-density plasma source can be used. For example, as a dry etching device having a high-density plasma source, an inductively coupled plasma (ICP) etching device or the like can be used. The etching device can be appropriately set according to the object to be etched. Note that in the above dry etching device, a self-bias potential is generated by applying a high-frequency voltage to the electrode on the substrate side, and reactive ion etching can be performed. In reactive ion etching, etching is performed by accelerating ion species in the plasma and colliding them with the object to be processed, so that an etching process with high anisotropy can be performed.

[0303] In addition, in the above etching process, the insulator 271A can also be used as an etch stop layer for protecting the conductor 242A. For example, when a metal hard mask is formed on the insulator 271A in the above etching process, it is sometimes difficult to obtain an etch selectivity with respect to the conductor 242A when removing the hard mask. However, by forming the insulator 271A on the conductor 242A, the insulator 271A can be used as an etch stop layer for protecting the conductor 242A in the etching process of removing the hard mask. Thereby, it is possible to prevent the formation of a curved surface between the side surface and the top surface of the conductor 242A, so that as Figure 1D shown, the end portion where the side surface and the top surface of the subsequently formed conductor 242a and the conductor 242b intersect has sharp corners. When the end portion where the side surface and the top surface of the conductor 242A intersect has sharp corners, the cross-sectional area of the conductor 242A is larger than that in the case where the end portion has a curved surface. Furthermore, by using a nitride insulator that does not easily oxidize the metal as the insulator 271A, it is possible to prevent the conductor 242A from being over-oxidized. As a result, the resistance of the conductor 242a and the conductor 242b is reduced, so that the on-state current of the transistor can be increased.

[0304] In addition, by processing the insulator 224 into an island shape, the insulator 275 can be provided in a manner that contacts the side surface of the insulator 224 and the top surface of the insulator 222 in the subsequent process. That is, the insulator 224 can be separated from the insulator 280 by the insulator 275. By having such a structure, it is possible to prevent excessive impurities such as oxygen and hydrogen from mixing into the oxide semiconductor 230 from the insulator 280 through the insulator 224.

[0305] Next, the insulator 275 is deposited so as to cover the insulator 224, the oxide semiconductor 230, the conductor 242A, and the insulator 271A, and the insulator 280 is deposited on the insulator 275 (see Figures 11A to 11D ). As the insulator 275 and the insulator 280, the above-mentioned insulating materials can be used.

[0306] Here, the insulator 275 preferably contacts the top surface of the insulator 222.

[0307] As the insulator 280, it is preferable to form an insulating film that will become the insulator 280 and perform CMP processing on the insulating film to form an insulator with a flat top surface. In addition, silicon nitride can be deposited on the insulator 280 by, for example, sputtering until reaching the insulator 280, and CMP processing is performed on the silicon nitride.

[0308] The insulator 275 and the insulator 280 can each be deposited by, for example, sputtering, CVD, MBE, PLD, or ALD methods.

[0309] The insulator 275 preferably uses an insulator having a function of suppressing oxygen permeation. For example, it is preferable to deposit silicon nitride by PEALD as the insulator 275. Alternatively, alumina can be deposited by sputtering as the insulator 275 and silicon nitride can be deposited thereon by PEALD. When the insulator 275 has the above structure, the function of suppressing the diffusion of impurities such as water, hydrogen, and oxygen can be improved.

[0310] In this way, the oxide semiconductor 230 and the conductor 242A can be covered by the insulator 275 having a function of suppressing oxygen diffusion. Thereby, it is possible to suppress oxygen from directly diffusing into the oxide semiconductor 230 and the conductor 242A from the insulator 280 and the like in the subsequent process.

[0311] In addition, silicon oxide is preferably deposited as the insulator 280 by sputtering. By depositing an insulating film that will become the insulator 280 by sputtering in an oxygen-containing atmosphere, an insulator 280 containing excess oxygen can be formed. By using sputtering, which does not require a hydrogen-containing molecule for the deposition gas, the hydrogen concentration in the insulator 280 can be reduced. In addition, a heat treatment may be performed before depositing the insulating film. The heat treatment may also be performed under reduced pressure, and the insulating film may be continuously deposited in a manner that does not expose it to the atmosphere. By performing such a treatment, moisture and hydrogen adsorbed on the surface of the insulator 275 or the like can be removed. The heat treatment may employ the conditions of the above-described heat treatment.

[0312] Next, the conductor 242A, the insulator 271A, the insulator 275, and the insulator 280 are processed using lithography to form openings reaching the oxide semiconductor 230 and the insulator 222 (see Figures 12A to 12D ). Here, the conductor 242A is divided to form the conductor 242a and the conductor 242b, and the insulator 271A is divided to form the insulator 271a and the insulator 271b. The openings formed in the insulator 280 and the insulator 275 overlap the oxide semiconductor 230 and the conductor 205.

[0313] The lithography can appropriately utilize the above methods. In order to finely process the opening of the insulator 280, lithography using light with a short wavelength such as EUV light or an electron beam is preferably employed. For example, by using the method shown in Figures 13A1 to 13D2 , an opening is formed in the insulator 280, and the conductor 242a and the conductor 242b can be formed.

[0314] First, a coating film 277 is deposited on the insulator 280, and a coating film 278 is also deposited (see Figure 13A1 and Figure 13A2 ). The coating film 277 and the coating film 278 may also have a function of improving the adhesion between the resist mask described later and the insulator 280. The deposition of the coating film 277 and the coating film 278 can be performed, for example, by spin coating or the like. As the coating film 277 and the coating film 278, a non-photosensitive organic resin can be used.

[0315] Here, the coating film 278 is used as a mask in the etching process for processing the coating film 277. Therefore, under the etching conditions of the coating film 277, the etching rate of the coating film 278 is preferably less than that of the coating film 277. For example, the coating film 277 may be a carbon-containing film, and the coating film 278 may be a silicon- and carbon-containing film. In the present embodiment, an SOC film is deposited as the coating film 277, and an SOG film is deposited as the coating film 278.

[0316] Note that the coating films 277 and 278 contain organic solvents such as alcohol during coating, but the organic substances contained therein sometimes decrease or are removed in subsequent processes or at the completion of the semiconductor device. In addition, the coating film may be provided as needed. A single-layer coating film may be provided, or the coating film may not be provided when only the resist mask described below is sufficient.

[0317] Next, a resist mask 279 having an opening is formed on the coating film 278 by lithography (see Figure 13A1 and Figure 13A2 ). The resist mask 279 can be formed, for example, by exposing a resist using a KrF excimer laser, an ArF excimer laser, EUV (Extreme Ultraviolet) light, or the like. In addition, a liquid immersion technique in which exposure is performed in a state where a liquid (for example, water) is filled between the substrate and the projection lens can also be used. In addition, an electron beam or an ion beam can be used instead of the above light. Note that when an electron beam or an ion beam is used, a mask may sometimes not be used.

[0318] Next, in the process according to Figures 13B1 to 13D2 , it is preferable to process the object to be processed by a dry etching method. Anisotropic etching can be performed in the dry etching method, so the dry etching method is suitable for forming an opening having a high aspect ratio. When performing anisotropic etching, for example, reactive ion etching is preferably performed. Note that the dry etching method conditions and the dry etching apparatus can be referred to the above description. Note that the process according to Figures 13B1 to 13D2 is preferably continuously performed without being exposed to the atmosphere. For example, it can be continuously performed without being exposed to the atmosphere using an etching apparatus of a multi-chamber type.

[0319] First, the coating film 278 is processed using the resist mask 279 to form a coating film 278 having an opening. For example, when a SOG film is used for the coating film 278, a DF-CCP etching apparatus can be used and etching treatment can be performed using CF4 as an etching gas.

[0320] Next, the coating film 277 is processed using the coating film 278 as a mask to form a coating film 277 having an opening (see Figure 13B1 and Figure 13B2 ). For example, when a SOC film is used for the coating film 277, a DF-CCP etching apparatus can be used and etching treatment can be performed using H2 and N2 as etching gases. Here, since a SOG film is used as the coating film 278, disappearance of the coating film 278 can be prevented in the etching process of the coating film 277.

[0321] In addition, it is preferable to remove the resist mask 279 simultaneously during the processing of the coating film 277. Since the SOC film is used as the coating film 277, the resist mask 279 can be easily removed. In addition, when the resist mask 279 remains after the formation of the coating film 277, it is preferable to remove the resist mask 279.

[0322] Next, the coating film 277 is used as a mask to process the insulator 280 to form an insulator 280 having an opening. For example, in the case where a silicon oxide film is used for the insulator 280, a DF-CCP etching apparatus can be used and etching treatment can be performed using C4F8, C4F6, O2, and Ar as etching gases.

[0323] Furthermore, the coating film 277 is used as a mask to process the insulators 275 and 271A to form insulators 275, 271a, and 271b having openings (see Figure 13C1 and Figure 13C2 ). For example, when a silicon oxide film and a silicon nitride film are used for the insulators 275 and 271A, a DF-CCP etching apparatus can be used and etching treatment can be performed using CH2F2, O2, and Ar as etching gases. At this time, the conductors 242A and the insulator 222 can be used as an etching stop layer. In addition, it is preferable to remove the coating film 278 simultaneously during the processing of the insulators 275 and 271A.

[0324] It is preferable to perform dry etching treatment such as ashing using oxygen plasma to remove the coating film 277 after the formation of the insulators 271a and 271b. However, it is not limited thereto, and the coating film 277 can also be removed after the formation of the conductors 242a and 242b.

[0325] Next, it is preferable to use the insulator 280 as a mask to remove the surface oxide film of the conductor 242A. For example, when a tantalum nitride film is used for the conductor 242A, an ICP etching apparatus can be used and etching treatment can be performed using BCl3 and Cl2 as etching gases.

[0326] Furthermore, the insulator 280 is used as a mask to process the conductor 242A to form conductors 242a and 242b (see Figure 13D1 and Figure 13D2 ). For example, when a tantalum nitride film is used for the conductor 242A, an ICP etching apparatus can be used and etching treatment can be performed using Cl2 and Ar as etching gases. At this time, the oxide semiconductor 230 and the insulator 222 can be used as an etching stop layer. At this time, as Figure 13D2As shown, when the transistor 200 is cross-sectioned in the channel width direction, there is sometimes a curved surface between the side surface and the top surface of the oxide semiconductor 230. That is to say, sometimes the end of the side surface and the end of the top surface are round.

[0327] Sometimes a recess is formed in the portion of the oxide semiconductor 230 exposed from the conductors 242a and 242b. In other words, on the top surface of the oxide semiconductor 230, the height of the region sandwiched between the conductors 242a and 242b is sometimes smaller than the regions overlapping with the conductor 242a and the region overlapping with the conductor 242b.

[0328] Through the above steps, openings can be formed in the insulators 275 and 280, and the insulators 271a, 271b, the conductors 242a, and the conductors 242b can be formed.

[0329] After processing the conductor 242A, an ashing process using oxygen plasma can also be performed. By performing such an oxygen plasma treatment, impurities generated in the above etching process and diffused into the oxide semiconductor 230 and the like can be removed. Examples of such impurities include impurities caused by components in the workpiece in the above etching process and impurities caused by components in the gas used in the etching. For example, chlorine, fluorine, tantalum, silicon, hafnium, etc. can be cited. By removing the impurities adhering to the oxide semiconductor 230 in this way, the electrical characteristics and reliability of the transistor can be improved.

[0330] In addition, the processing of the conductor 242A and the oxygen plasma treatment can be continuously performed without being exposed to the atmosphere. For example, it can be continuously performed without being exposed to the atmosphere using an etching apparatus with a multi-chamber method.

[0331] Preferably, in order to remove impurities and the like adhering to the surface of the oxide semiconductor 230 in the above etching process, a washing process is performed. As washing methods, there are wet washing using a washing liquid etc. (which can also be called wet etching treatment), plasma treatment using plasma, washing using heat treatment, etc., and the above washings can also be appropriately combined. Note that sometimes the above recess becomes deeper by performing this washing process.

[0332] The wet washing can also be performed using an aqueous solution obtained by diluting one or more of oxalic acid, phosphoric acid, and hydrofluoric acid with carbonated water or pure water. In addition, the wet washing can also be performed using an aqueous solution obtained by diluting ammonia water with carbonated water or pure water. In addition, the wet washing can also be performed using pure water, carbonated water, etc. Or, ultrasonic washing can also be performed using the above aqueous solution, pure water, or carbonated water. In addition, the above washings can also be appropriately combined.

[0333] Note that, in this specification and the like, an aqueous solution obtained by diluting hydrofluoric acid with pure water is sometimes referred to as dilute hydrofluoric acid, and an aqueous solution obtained by diluting ammonia water with pure water is sometimes referred to as dilute ammonia water. In addition, the concentration, temperature, etc. of the aqueous solution are appropriately adjusted according to the impurities to be removed, the structure of the semiconductor device to be washed, and the like. The ammonia concentration of the dilute ammonia water is preferably set to 0.01% or more and 5% or less, more preferably set to 0.1% or more and 0.5% or less. In addition, the hydrogen fluoride concentration of the dilute hydrofluoric acid is preferably set to 0.01 ppm or more and 100 ppm or less, more preferably set to 0.1 ppm or more and 10 ppm or less.

[0334] In addition, as the ultrasonic cleaning, a frequency of 200 kHz or more is preferably used, and a frequency of 900 kHz or more is more preferably used. By using this frequency, the damage to the oxide semiconductor 230 and the like can be reduced.

[0335] In addition, the above cleaning process can be performed multiple times, and the cleaning liquid can also be changed for each cleaning process. For example, as the first cleaning process, a process using dilute hydrofluoric acid or dilute ammonia water can also be performed, and as the second cleaning process, a process using pure water or carbonated water can also be performed.

[0336] As the above cleaning process, in the present embodiment, wet cleaning is performed using carbonated water. By performing this cleaning process, impurities attached to the surface of the oxide semiconductor 230 and the like or diffused into the inside thereof can be removed. In addition, the surface layer of the oxide semiconductor 230 damaged in the above etching process can also be removed.

[0337] The heat treatment is preferably performed after the above etching or after the above cleaning. The temperature of the heat treatment is 100 °C or more and 650 °C or less, preferably 250 °C or more and 600 °C or less, more preferably 300 °C or more and 550 °C or less, and further preferably 350 °C or more and 400 °C or less. The heat treatment is performed in an atmosphere of nitrogen gas, an inert gas, or an oxidizing gas containing 10 ppm or more, 1% or more, or 10% or more. For example, it is preferable to perform the heat treatment in an oxygen-containing atmosphere, and it is preferable to perform a treatment at a temperature of 350 °C for 1 hour with a flow rate ratio of nitrogen gas to oxygen gas of 4:1. Thereby, oxygen is supplied to the oxide semiconductor 230, and thus the oxygen vacancies can be reduced. In addition, by performing the above heat treatment, the crystallinity of the oxide semiconductor 230 can be improved. Furthermore, when the hydrogen remaining in the oxide semiconductor 230 reacts with the supplied oxygen, the hydrogen can be removed in the form of H2O (dehydration). Thereby, the recombination of the hydrogen remaining in the oxide semiconductor 230 with the oxygen vacancies to form V can be suppressed. OH. Thus, the electrical characteristics of the transistor provided with the oxide semiconductor 230 can be improved to enhance the reliability. In addition, the non-uniformity of the electrical characteristics of a plurality of transistors formed on the same substrate can be suppressed. Further, the above heat treatment can also be performed under a reduced pressure state. Alternatively, the heat treatment can be performed in an oxygen atmosphere and then continuously performed in a nitrogen atmosphere without being exposed to the atmosphere. In addition, the above heat treatment can also serve as the heat treatment after the deposition of the oxide semiconductor film 230f. Therefore, sometimes the crystal region of the oxide semiconductor 230 grows by the above heat treatment.

[0338] Note that when the heat treatment is performed in a state where the conductor 242a and the conductor 242b are in contact with the oxide semiconductor 230, the sheet resistance of the region of the oxide semiconductor 230 overlapping with the conductor 242a and the region overlapping with the conductor 242b sometimes decreases. In addition, sometimes the carrier concentration increases. Therefore, the regions of the oxide semiconductor 230 overlapping with the conductor 242a and the conductor 242b can be self-aligned to have a low resistance.

[0339] For example, as Figure 2A shown, even if the oxide semiconductor 230 has a stacked structure and a metal oxide with a low conductivity or a metal oxide with a large bandgap is used as the oxide semiconductor 230c, the resistance of the regions of the oxide semiconductor 230 overlapping with the conductor 242a and the conductor 242b can be reduced as described above. Thereby, a source region and a drain region can be formed in the oxide semiconductor 230c.

[0340] Next, an insulating film 250f that will become the insulator 250 is deposited so as to cover the openings formed in the insulator 280 and the like (refer to Figures 14A to 14D ). Here, the insulating film 250f is deposited along the openings of the insulator 280 and the insulator 275. The insulating film 250f is in contact with the insulator 280, the conductor 242a, the conductor 242b, the insulator 222, the insulator 224, and the oxide semiconductor 230.

[0341] The insulating film 250f can be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. For example, the insulating film 250f is preferably deposited by the ALD method. The insulating film 250f is preferably formed thin, and it is necessary to suppress the thickness non-uniformity to be small. In this regard, the ALD method is a deposition method in which a precursor and a reactant (e.g., an oxidizing agent, etc.) are alternately introduced, and the thickness can be adjusted according to the number of times this cycle is repeated, so the thickness can be precisely adjusted. In addition, the insulating film 250f needs to be deposited on the bottom surface and the side surface of the above opening with high coverage. By using the ALD method, atomic layers of each layer can be deposited on the bottom surface and the side surface of the above opening, and thus the insulating film 250f can be formed in the opening with high coverage.

[0342] In addition, when depositing the insulating film 250f by ALD method, ozone (O3), oxygen (O2), water (H2O), etc. can be used as the oxidant. By using ozone (O3), oxygen (O2), etc. that do not contain hydrogen as the oxidant, the hydrogen diffusing into the oxide semiconductor 230 can be reduced.

[0343] Such as Figure 2B shown, the insulator 250 can have a stacked structure. Hereinafter, the deposition method of the insulating film 250f when the insulator 250 has a four-layer structure of the insulator 250a, the insulator 250b, the insulator 250d, and the insulator 250c will be described. Figure 2B Similarly, when there is a four-layer structure of the insulator 250a, the insulator 250b, the insulator 250d, and the insulator 250c, the deposition method of the insulating film 250f will be described.

[0344] First, a film that will become the insulator 250a is deposited so as to cover the opening formed in the insulator 280 and the like, and a film that will become the insulator 250b is deposited on the film that will become the insulator 250a. In the present embodiment, aluminum oxide is deposited by thermal ALD method as the film that will become the insulator 250a, and silicon oxide is deposited by PEALD method as the film that will become the insulator 250b.

[0345] Next, microwave treatment is preferably performed in an oxygen-containing atmosphere. Here, the microwave treatment refers to, for example, a treatment using a device including a power source that generates high-density plasma with microwaves. In addition, in this specification and the like, microwaves refer to electromagnetic waves having a frequency of 300 MHz or more and 300 GHz or less.

[0346] The microwave treatment preferably uses, for example, a microwave treatment device including a power source that generates high-density plasma with microwaves. Here, the frequency of the microwave treatment device is preferably set to 300 MHz or more and 300 GHz or less, more preferably 2.4 GHz or more and 2.5 GHz or less, and can be, for example, 2.45 GHz. By using high-density plasma, high-density oxygen radicals can be generated. In addition, the power of the power source for applying microwaves of the microwave treatment device is preferably 1000 W or more and 10000 W or less, more preferably 2000 W or more and 5000 W or less. In addition, the microwave treatment device may also include a power source for applying RF to the substrate side. In addition, by applying RF to the substrate side, the oxygen ions generated by the high-density plasma can be efficiently introduced into the oxide semiconductor 230.

[0347] In addition, the above microwave treatment is preferably carried out under reduced pressure, and the pressure is preferably 10 Pa or more and 1000 Pa or less, more preferably 300 Pa or more and 700 Pa or less. In addition, the treatment temperature is preferably 750 °C or less, more preferably 500 °C or less, and may be about 250 °C, for example. In addition, the heat treatment may be continuously carried out in a manner that does not expose to external air after the oxygen plasma treatment. The temperature of the heat treatment is preferably 100 °C or more and 750 °C or less, more preferably 300 °C or more and 500 °C or less, for example.

[0348] In addition, for example, the above microwave treatment can be carried out using oxygen gas and argon gas. Here, the oxygen flow ratio (O2 / (O2+Ar)) is greater than 0% and 100% or less. Preferably, the oxygen flow ratio (O2 / (O2+Ar)) is greater than 0% and 50% or less. More preferably, the oxygen flow ratio (O2 / (O2+Ar)) is 10% or more and 40% or less. Further preferably, the oxygen flow ratio (O2 / (O2+Ar)) is 10% or more and 30% or less. Thus, by carrying out the microwave treatment in an oxygen-containing atmosphere, the carrier concentration in the region of the oxide semiconductor 230 exposed from the opening can be reduced. In addition, by preventing excessive introduction of oxygen into the processing chamber during the microwave treatment, an excessive reduction in the carrier concentration in the oxide semiconductor 230 can be prevented.

[0349] By carrying out the microwave treatment in an oxygen-containing atmosphere, oxygen gas can be plasmaized using high-frequency waves such as microwaves or RF, and the oxygen plasma can act on the region between the conductor 242a and the conductor 242b of the oxide semiconductor 230. Through the action of plasma, microwaves, etc., the V O H can be separated into oxygen vacancies and hydrogen, and hydrogen can be removed from this region. Here, in the case of adopting the structure shown in Figure 2B etc., as the film that will become the insulator 250a, an insulating film having a function of capturing or fixing hydrogen (for example, alumina, etc.) is preferably used. By adopting the above structure, the film that will become the insulator 250a can capture or fix the hydrogen generated by the microwave treatment. Thus, the V O H contained in the channel formation region can be reduced. Thereby, the oxygen vacancies and V O H in the channel formation region can be reduced, and the carrier concentration can be lowered. In addition, by supplying oxygen radicals generated in the above oxygen plasma to the oxygen vacancies formed in the channel formation region, the oxygen vacancies in the channel formation region can be further reduced, and thereby the carrier concentration can be lowered.

[0350] As the oxygen injected into the channel formation region, there are various forms such as oxygen atoms, oxygen molecules, oxygen ions, and oxygen free radicals (also known as O radicals, atoms, molecules, or ions containing unpaired electrons). The oxygen injected into the channel formation region can be any one or more of the above forms, and oxygen free radicals are particularly preferred. In addition, since the film quality of the insulator 250 can be improved, the reliability of the transistor is improved.

[0351] On the other hand, the oxide semiconductor 230 has a region overlapping with either the conductor 242a or the conductor 242b. This region can be used as a source region or a drain region. Here, the conductors 242a and 242b are preferably used as shielding films that protect against the action of high frequencies such as microwaves, RF, etc. or oxygen plasmas during microwave treatment in an oxygen-containing atmosphere. Therefore, the conductors 242a and 242b preferably have the function of shielding electromagnetic waves of 300 MHz or more and 300 GHz or less, for example, 2.4 GHz or more and 2.5 GHz or less.

[0352] Since the conductors 242a and 242b shield the action of high frequencies such as microwaves or RF and oxygen plasmas, they do not act on the region of the oxide semiconductor 230 that overlaps with either the conductor 242a or the conductor 242b. As a result, during microwave treatment, there is no decrease in VH and no excessive supply of oxygen in the source region and the drain region, so a decrease in carrier concentration can be prevented. O H's decrease and excessive oxygen supply, so a decrease in carrier concentration can be prevented.

[0353] As described above, oxygen vacancies and V can be selectively removed in the channel formation region of the oxide semiconductor O H to make the channel formation region i-type or substantially i-type. Also, it is possible to suppress the region used as the source region or the drain region from being supplied with excessive oxygen and maintain the conductivity (state of the low-resistance region) before microwave treatment. As a result, fluctuations in the electrical characteristics of the transistor can be suppressed, and non-uniformity in the electrical characteristics of the transistor within the substrate surface can be suppressed.

[0354] In addition, by performing microwave treatment, the film quality of the film that will become the insulator 250a and the film that will become the insulator 250b can be modified, and the diffusion of hydrogen, water, impurities, etc. can be suppressed. As a result, it is possible to suppress the diffusion of hydrogen, water, impurities, etc. through the insulator 250 into the oxide semiconductor 230, etc. due to post-processes such as the deposition of the conductive film that will become the conductor 260 or post-treatments such as heat treatment. In this way, by improving the film quality of the insulator 250, the reliability of the transistor can be improved.

[0355] Next, a film that will become insulator 250d is deposited on the film that will become insulator 250b. In the present embodiment, hafnium oxide is deposited by thermal ALD as the film that will become insulator 250d. Further, hafnium zirconium oxide may be deposited by thermal ALD as the film that will become insulator 250d. In addition, microwave treatment may be performed again after depositing the film that will become insulator 250d.

[0356] Next, a film that will become insulator 250c is deposited on the film that will become insulator 250d. In the present embodiment, silicon nitride is deposited by PEALD as the film that will become insulator 250c. Thus, an insulating film 250f including the film that will become insulator 250a to the film that will become insulator 250d can be formed.

[0357] Note that in the above structure, examples are shown in which microwave treatment is performed after depositing the film that will become insulator 250b and after depositing the film that will become insulator 250d, but the present invention is not limited thereto. Microwave treatment may be performed after proceeding to the deposition of the film that will become insulator 250c. Alternatively, microwave treatment may be performed before depositing the film that will become insulator 250a. In addition, microwave treatment may be performed three or more times. Further, the above microwave treatment may sometimes serve as the heating treatment shown in Embodiment 2. Therefore, the crystalline region of the oxide semiconductor 230 sometimes grows by the above microwave treatment.

[0358] In addition, heat treatment may be performed while maintaining a reduced pressure state after performing microwave treatment. By performing this treatment, hydrogen in the insulating film and in the oxide semiconductor 230 can be efficiently removed. Further, the step of performing heat treatment while maintaining a reduced pressure state after performing microwave treatment may be repeated multiple times. By repeatedly performing the heat treatment, hydrogen in the insulating film and in the oxide semiconductor 230 can be further efficiently removed. Note that the heat treatment temperature is preferably 300°C or higher and 500°C or lower. Further, the above heat treatment may serve as the heat treatment shown in Embodiment 2. Therefore, the crystalline region of the oxide semiconductor 230 sometimes grows by the above heat treatment.

[0359] Next, a conductive film 260f that will become a conductor 260 is formed (see Figures 14A to 14D ). The conductive film 260f can be deposited using the above-described conductive material by sputtering, CVD, MBE, PLD, electroplating, or ALD. For example, a titanium nitride film and a tungsten film can be laminated and deposited by CVD. As Figure 2AAs shown, the conductor 260 may have a stacked structure of a conductor 260a made of titanium nitride and a conductor 260b made of tungsten. In addition, the conductive film 260f may be deposited while heating the substrate. The substrate heating may also serve as the heating treatment shown in Embodiment 2. Therefore, sometimes the crystal region of the oxide semiconductor 230 grows by the above substrate heating.

[0360] Next, the insulating film 250f and the conductive film 260f are polished by CMP processing until the insulator 280 is exposed. That is, a part of the insulating film 250f and the conductive film 260f exposed from the above opening is removed. Thereby, the insulator 250 and the conductor 260 (conductor 260a and conductor 260b) are formed in the opening overlapping with the conductor 205 (see Figures 15A to 15D ).

[0361] Thereby, the insulator 250 is disposed so as to contact the conductor 242a, the conductor 242b, the oxide semiconductor 230, the insulator 224, and the insulator 222 in the above opening. In addition, the conductor 260 is disposed so as to be embedded in the above opening with the insulator 250 interposed therebetween. Thereby, the transistor 200 is formed.

[0362] Next, an insulator 282 is deposited on the insulator 250, the conductor 260, and the insulator 280 (see Figures 16A to 16D ). The insulator 282 can be deposited, for example, by a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. The insulator 282 is preferably deposited by a sputtering method. By using a sputtering method that does not require a molecule containing hydrogen for the deposition gas, the hydrogen concentration in the insulator 282 can be reduced.

[0363] In addition, as Figure 2A shown, the insulator 282 preferably has a stacked structure of an insulator 282a and an insulator 282b. Here, the insulator 282a is preferably deposited by an ALD method, and the insulator 282b is preferably deposited by a sputtering method.

[0364] In this embodiment, it is sufficient to deposit aluminum oxide by a thermal ALD method as the insulator 282a. Here, the thickness of the insulator 282a is 1 nm or more and 20 nm or less, and preferably 3 nm or more and 10 nm or less.

[0365] By depositing the insulator 282a by an ALD method, the insulator 282a can be deposited without causing excessive damage to the surface to be formed. Therefore, it is possible to prevent excessive damage to the upper end portion of the insulator 250 and the top surface of the conductor 260, so that the electrical characteristics and reliability of the transistor 200 can be improved.

[0366] In addition, by depositing the insulator 282a using the ALD method, the insulator 282a can be deposited without adding oxygen to the insulator 280. Thereby, it is possible to prevent an excessive amount of oxygen from being added to the insulator 280. Therefore, the electrical characteristics and reliability of the transistor 200 can be improved.

[0367] In the present embodiment, alumina may be deposited using the sputtering method as the insulator 282b. By using the sputtering method that does not require a molecule containing hydrogen as a deposition gas, the hydrogen concentration in the insulator 282 can be reduced.

[0368] Here, by depositing the insulator 282b in an oxygen-containing atmosphere using the sputtering method, oxygen can be added to the insulator 280 while deposition is being performed. Thereby, the insulator 280 can contain excess oxygen. At this time, it is preferable to deposit the insulator 282b while heating the substrate. Here, since the insulator 282b is deposited on the insulator 282a and oxygen is added through the insulator 282a, the amount of oxygen injected into the insulator 280 can be controlled. When the thickness of the insulator 282a is large, the above oxygen addition is likely to be hindered and the amount of oxygen injected into the insulator 280 decreases. When the thickness of the insulator 282a is small, the above oxygen addition is not easily hindered and the amount of oxygen injected into the insulator 280 increases. For example, by setting the thickness of the insulator 282a within the above range, a sufficient amount of oxygen can be supplied to the oxide semiconductor 230, and an excessive amount of oxygen can be prevented from being supplied to the oxide semiconductor 230. Thereby, improvement in the electrical characteristics and reliability of the transistor 200 can be achieved. In addition, when depositing the above insulator 282b, not only can oxygen be added to the insulator 280 but also oxygen can be added to the upper end portion of the insulator 250.

[0369] In addition, by depositing the insulator 282b on the insulator 282a, the upper end portion of the insulator 250 and the top surface of the conductor 260 can be protected from the impact of ion collisions generated by the sputtering deposition of the insulator 282b.

[0370] Alumina is deposited using an aluminum target in an atmosphere containing oxygen gas. The amount of oxygen injected into the insulator 280 can be controlled according to the magnitude of the bias power applied to the substrate by the sputtering method. For example, the smaller the bias power, the smaller the amount of oxygen injected into the insulator 280, and this amount is likely to saturate even when the thickness of the insulator 282b is small. In addition, the larger the bias power, the larger the amount of oxygen injected into the insulator 280. By reducing the bias power, the amount of oxygen injected into the insulator 280 can be suppressed. Note that when applying a substrate bias using an RF power supply, the frequency of the RF is preferably 10 MHz or higher. Typically, it is 13.56 MHz. The higher the frequency of the RF, the less damage to the substrate can be caused.

[0371] In addition, a heat treatment may also be performed before depositing the insulator 282b. This heat treatment may also be performed under reduced pressure, and the insulator 282b is continuously deposited in a manner not exposed to the atmosphere. By performing such a treatment, moisture and hydrogen adsorbed on the surface of the insulator 280 can be captured or fixed by the insulator 282a, and the moisture concentration and hydrogen concentration in the insulator 280 can be reduced. The temperature of the heat treatment is preferably 100°C or higher and 400°C or lower. In the present embodiment, the temperature of the heat treatment is set to 250°C.

[0372] Next, an insulator 283 is formed on the insulator 282 (see Figures 16A to 16D ). The insulator 283 can be deposited, for example, by a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. The insulator 283 is preferably deposited by a sputtering method. By using a sputtering method that does not require molecules containing hydrogen for the deposition gas, the hydrogen concentration in the insulator 283 can be reduced. In the present embodiment, silicon nitride is deposited as the insulator 283 by a sputtering method.

[0373] In the present embodiment, silicon nitride is deposited as the insulator 283 by a sputtering method, and aluminum oxide is deposited as the insulator 282 by a thermal ALD method and a sputtering method. In this way, by using silicon nitride having a function of suppressing hydrogen diffusion as the insulator 283, hydrogen diffusion from the upper layer of the transistor 200 can be suppressed. And, by using aluminum oxide having a function of capturing or fixing hydrogen as the insulator 282, hydrogen contained in the insulator 280 or the like can be captured or fixed by the insulator 282. Thereby, the hydrogen concentration in the oxide semiconductor 230 and its vicinity can be reduced.

[0374] Next, an insulator 285 is formed on the insulator 283 (see Figures 16A to 16D ). The insulator 285 can be deposited, for example, by a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. The insulator 285 is preferably deposited by a sputtering method. By using a sputtering method that does not require molecules containing hydrogen for the deposition gas, the hydrogen concentration in the insulator 285 can be reduced. In the present embodiment, silicon oxide is deposited as the insulator 285 by a sputtering method.

[0375] Here, it is preferable to continuously deposit the insulator 282, the insulator 283, and the insulator 285 by a sputtering method in a manner not exposed to the atmospheric environment. By performing the deposition in a manner not exposed to the atmosphere, since impurities or moisture from the atmospheric environment can be prevented from adhering to the insulator 282, the insulator 283, and the insulator 285, the vicinity of the interface between the insulator 282 and the insulator 283 and the vicinity of the interface between the insulator 283 and the insulator 285 can be kept clean.

[0376] Next, openings reaching the conductor 242a are formed in the insulator 271a, the insulator 275, the insulator 280, the insulator 282, the insulator 283, and the insulator 285, and openings reaching the conductor 242b are formed in the insulator 271b, the insulator 275, the insulator 280, the insulator 282, the insulator 283, and the insulator 285. The formation of the openings can be carried out using lithography. When forming the openings, it is preferable to process the object to be processed using a dry etching method. Anisotropic etching can be performed in the dry etching method, so the dry etching method is suitable for forming openings with a high aspect ratio. When performing anisotropic etching, for example, reactive ion etching is preferably performed. Note that the dry etching method conditions and the dry etching apparatus can be referred to the above description. In addition, the shape of the opening when viewed from above can be a circular shape, an approximately circular shape such as an ellipse, a polygonal shape such as a quadrangle, a shape in which the corners of a polygonal shape such as a quadrangle have an arc shape, etc.

[0377] Next, a heat treatment is performed after forming the above-mentioned openings. The temperature of the heat treatment can be 100°C or higher and 600°C or lower, preferably 250°C or higher and 550°C or lower, more preferably 350°C or higher and 450°C or lower. The heat treatment is preferably performed in a nitrogen gas or inert gas atmosphere. In addition, since the heat treatment is performed in a state where the conductor 242a and the conductor 242b are exposed, it is preferably performed in an atmosphere that does not contain an oxidizing gas and oxygen gas. For example, it is preferable to perform a heat treatment at a temperature of 400°C for 1 hour in a nitrogen gas atmosphere. In addition, the above heat treatment can also be performed under reduced pressure. Through the above heat treatment, the oxygen contained in the insulator 280 can be supplied to the oxide semiconductor 230 through the insulator 250. Thereby, the oxygen vacancies in the channel formation region of the oxide semiconductor 230 can be reduced. In addition, the above heat treatment can also serve as the heat treatment shown in Embodiment 2. Therefore, sometimes the crystal region of the oxide semiconductor 230 grows through the above heat treatment.

[0378] Here, since the side surface of the insulator 280 is exposed in the above opening, the oxygen contained in the insulator 280 can be diffused outward by the above heat treatment to control the amount of oxygen contained in the insulator 280. On the other hand, since the insulator 282 and the insulator 283 having oxygen barrier properties are provided on the insulator 280, oxygen does not diffuse outward from the top surface of the insulator 280. Thereby, it is possible to prevent excessive oxygen from diffusing outward from the insulator 280 and forming oxygen vacancies in the insulator 280. In addition, the oxide semiconductor 230, the conductor 242a, and the conductor 242b are covered by the insulator 275. Thereby, it is possible to prevent excessive oxygen from directly diffusing from the insulator 280 to the oxide semiconductor 230, the conductor 242a, and the conductor 242b during the above heat treatment.

[0379] As described above, when depositing the insulator 282b, the amount of oxygen added to the insulator 280 can be controlled by adding oxygen through the insulator 282a to the insulator 280. Furthermore, when the oxygen diffuses outward from the side surface of the insulator 280 by the above heat treatment, the amount of oxygen in the insulator 280 can be made more appropriate. Thus, by supplying oxygen from the insulator 280 with the adjusted amount of oxygen to the oxide semiconductor 230, an appropriate amount of oxygen can be supplied to the oxide semiconductor 230. Thereby, oxygen vacancies in the oxide semiconductor 230 can be reduced and excessive oxygen supply to the oxide semiconductor 230 can be prevented. Therefore, the electrical characteristics and reliability of the transistor 200 can be improved. In addition, the process of exposing the side surface of the insulator 280 can also serve as the process of forming the openings for embedding the conductive bodies 240a and 240b, so the manufacturing process of the semiconductor device can be simplified.

[0380] In addition, by performing the above heat treatment, hydrogen contained in the insulator 280, the insulator 250, and the oxide semiconductor 230 moves to the insulator 282 and is captured by the insulator 282. In other words, hydrogen in the insulator 280, the insulator 250, and the oxide semiconductor 230 diffuses to the insulator 282. Therefore, although the hydrogen concentration of the insulator 282 becomes high, the hydrogen concentrations of the insulator 280, the insulator 250, and the oxide semiconductor 230 all become low. Moreover, when the insulator 283 is provided in contact with the top surface of the insulator 282, it is possible to prevent impurities such as moisture or hydrogen from entering from above the insulator 283 during this heat treatment. In addition, by performing the heat treatment, hydrogen contained in the insulator 216, the insulator 224, and the oxide semiconductor 230 moves to the insulator 222 and is captured by the insulator 222. In other words, hydrogen in the insulator 216, the insulator 224, and the oxide semiconductor 230 diffuses to the insulator 222. Therefore, although the hydrogen concentration of the insulator 222 becomes high, the hydrogen concentrations of the insulator 216, the insulator 224, and the oxide semiconductor 230 all become low. Here, when the insulator 221 is provided in contact with the bottom surface of the insulator 222, it is possible to prevent impurities such as moisture or hydrogen from entering from below the insulator 221 due to this heat treatment.

[0381] Next, an insulating film that will become the insulators 241a and 241b is deposited along the shape of the above opening. This insulating film can be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. Since the insulating film that will become the insulators 241a and 241b is deposited in an opening with a high aspect ratio, it is preferably deposited by the ALD method. As the insulating film that will become the insulators 241a and 241b, an insulating film having a function of suppressing oxygen permeation is preferably used. For example, it is preferable to deposit silicon nitride by the PEALD method. Silicon nitride has a high barrier property against hydrogen, so it is preferable.

[0382] Next, anisotropic etching is performed on the above-mentioned insulating film to form insulators 241a and 241b. Here, insulator 241a is formed so as to cover the side walls of the openings on conductor 242a, and insulator 241b is formed so as to cover the side walls of the openings on conductor 242b. As the anisotropic etching of the insulating film that will become insulators 241a and 241b, a dry etching method or the like can be used. For example, reactive ion etching is preferably performed. By providing insulators 241a and 241b on the side wall portions of the openings, oxygen permeation from the outside can be suppressed, and oxidation of conductors 240a and 240b formed next can be prevented. In addition, diffusion of impurities such as water and hydrogen contained in insulator 280 or the like into conductors 240a and 240b can be prevented. Note that sometimes recesses are formed in a part of the top surfaces of conductors 242a and 242b due to this anisotropic etching.

[0383] Next, a conductive film that will become conductors 240a and 240b is deposited. This conductive film preferably has a stacked structure including a conductor having a function of suppressing permeation of impurities such as water and hydrogen. For example, a stack of tantalum nitride, titanium nitride, etc. and tungsten, molybdenum, copper, etc. can be used. The conductive film that will become conductors 240a and 240b can be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0384] Next, by performing CMP processing, a part of the conductive film that will become conductors 240a and 240b is removed to expose the top surface of insulator 285. As a result, only this conductive film remains in the openings, whereby conductors 240a and 240b having flat top surfaces can be formed (see Figures 1A to 1D ). Note that sometimes a part of the top surface of insulator 285 is removed due to this CMP processing.

[0385] In addition, a heat treatment can also be performed after forming conductors 240a and 240b. This heat treatment can be performed under the same conditions as the above-mentioned heat treatment. By performing this heat treatment, the amount of oxygen supplied to oxide semiconductor 230 can be adjusted. Thereby, improvement in the electrical characteristics and reliability of transistor 200 can be achieved.

[0386] Through the above steps, a Figures 1A to 1D semiconductor device as shown can be manufactured.

[0387] The semiconductor device according to the present embodiment includes an OS transistor. In the present embodiment, by using indium oxide (e.g., indium oxide, indium gallium oxide, indium zinc oxide, indium gallium zinc oxide, indium gallium tin zinc oxide, etc.) as the oxide semiconductor layer of the OS transistor, a semiconductor device with a high field-effect mobility can be provided. For example, the electrical characteristics, on-state current, S value, frequency characteristics, etc. of the transistor can be improved. In addition, a semiconductor device with high reliability can be provided.

[0388] The present embodiment can be appropriately combined with other embodiments. In addition, in this specification, when multiple structural examples are shown in one embodiment, the structural examples can be appropriately combined.

[0389] Embodiment 2

[0390] In the present embodiment, the oxide semiconductor that can be used as the semiconductor layer of the transistor will be described. As the oxide semiconductor according to one aspect of the present invention, a single layer or a stacked layer including a layer of a metal oxide can be used. Note that in the oxide semiconductor having a stacked structure, as described later, it is sometimes difficult to confirm the boundary between the stacked films.

[0391] [Metal Oxide]

[0392] The metal oxide according to one aspect of the present invention preferably contains at least indium (In) or zinc (Zn), and particularly preferably contains indium as the main component. In addition, the metal oxide preferably contains two or three selected from indium, element M, and zinc, and particularly preferably contains indium and zinc as the main components. Here, the metal oxide can contain indium and zinc as the main components and can also contain element M. Note that element M is a metal element or a semi-metal element with a high bond energy with oxygen, for example, a metal element or a semi-metal element with a higher bond energy with oxygen than indium. As element M, specifically, aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, antimony, etc. can be cited. The element M contained in the metal oxide is preferably any one or more of the above elements, more preferably one or more selected from aluminum, gallium, tin, and yttrium, and further preferably one or more selected from gallium and tin. When the element M contained in the metal oxide is gallium, the metal oxide according to one aspect of the present invention preferably contains any one or more selected from indium, gallium, and zinc. In this specification and the like, sometimes a metal element and a semi-metal element are collectively referred to as a "metal element", and the "metal element" described in this specification and the like sometimes includes a semi-metal element.

[0393] As a metal oxide according to one aspect of the present invention, for example, indium zinc oxide (In-Zn oxide, also denoted as IZO (registered trademark)), indium tin oxide (In-Sn oxide, also denoted as ITO), indium titanium oxide (In-Ti oxide), indium gallium oxide (In-Ga oxide), indium gallium aluminum oxide (In-Ga-Al oxide), indium gallium tin oxide (In-Ga-Sn oxide, also denoted as IGTO), indium aluminum zinc oxide (In-Al-Zn oxide, also denoted as IAZO), indium tin zinc oxide (also denoted as In-Sn-Zn oxide), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide, also denoted as IGZO), indium tin oxide containing silicon oxide (ITSO), indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide, also denoted as IGZTO), indium gallium aluminum zinc oxide (In-Ga-Al-Zn oxide, also denoted as IGAZO or IAGZO), etc. can be used. Alternatively, gallium zinc oxide (Ga-Zn oxide, also denoted as GZO), aluminum zinc oxide (Al-Zn oxide, also denoted as AZO), gallium tin oxide (Ga-Sn oxide), aluminum tin oxide (Al-Sn oxide), etc. can be used. In addition, as a metal oxide according to one aspect of the present invention, indium oxide can be used. In addition, as a metal oxide according to one aspect of the present invention, gallium oxide, zinc oxide, etc. can be used.

[0394] By increasing the indium content ratio of the metal oxide, a transistor can obtain a large on-state current and high-frequency characteristics.

[0395] Note that the metal oxide may also contain one or more metal elements in a large period number of the periodic table instead of indium. Alternatively, the metal oxide may also contain one or more metal elements in a large period number of the periodic table in addition to indium. There is a tendency that the larger the overlap of the orbits of the metal elements, the greater the carrier conduction in the metal oxide. Therefore, by containing a metal element in a large period number of the periodic table, the field-effect mobility of the transistor can sometimes be improved. As the metal element in a large period number of the periodic table, metal elements belonging to the 5th period and metal elements belonging to the 6th period, etc. can be cited. Specifically, as the metal element, yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium, etc. can be cited. Note that lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium are called light rare earth elements.

[0396] In addition, the metal oxide may also contain one or more non-metal elements. When the metal oxide contains a non-metal element, the field-effect mobility of the transistor can sometimes be improved. As the non-metal element, for example, carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen, etc. can be cited.

[0397] In addition, by increasing the zinc content rate of the metal oxide, the metal oxide has high crystallinity, so that diffusion of impurities in the metal oxide can be suppressed. Thereby, variations in the electrical characteristics of the transistor are suppressed and reliability can be improved.

[0398] In addition, by increasing the content rate of element M in the metal oxide, formation of oxygen vacancies in the metal oxide can be suppressed. Accordingly, generation of carriers due to the oxygen vacancies is suppressed, and thereby a transistor with a small off-state current can be realized. In addition, variations in the electrical characteristics of the transistor are suppressed and reliability can be improved.

[0399] Structural examples of the oxide semiconductor that can improve the field-effect mobility of the transistor will be described. For example, a stacked structure of indium oxide and IGZO is preferably employed. Specifically, the oxide semiconductor preferably contains indium oxide and IGZO on the indium oxide. In addition, as the oxide semiconductor, IGZO containing nitrogen is preferably used. For example, by performing N2O plasma treatment during or after deposition, IGZO containing nitrogen can be formed. In addition, as the oxide semiconductor, at least one of indium oxide, In-Ga oxide, In-Zn oxide, and IGZTO is preferably used.

[0400] In the present embodiment, In-M-Zn oxide may be described as an example of the metal oxide.

[0401] The oxide semiconductor according to one embodiment of the present invention preferably includes a metal oxide having crystallinity. As the structure of the metal oxide having crystallinity, for example, a CAAC (c-axis aligned crystal) structure, a poly-crystal structure, or a nc (nano-crystal) structure can be cited. By using the metal oxide having crystallinity for the oxide semiconductor, the density of defect states in the oxide semiconductor can be reduced. Accordingly, the reliability of the transistor using the oxide semiconductor according to one embodiment of the present invention can be improved, and the reliability of the semiconductor device equipped with the transistor can be improved.

[0402] Note that there is no particular limitation on the crystallinity of the metal oxide included in the oxide semiconductor. For example, the oxide semiconductor may include one or more of an amorphous semiconductor (a semiconductor having an amorphous structure), a single-crystal semiconductor (a semiconductor having a single-crystal structure), and a semiconductor having crystallinity other than single crystal (a microcrystalline semiconductor, a polycrystalline semiconductor, or a semiconductor in which a part has a crystalline region). When the oxide semiconductor has crystallinity, degradation of the transistor characteristics can sometimes be suppressed.

[0403] The crystallinity of the oxide semiconductor can be analyzed, for example, by X-ray diffraction (XRD), transmission electron microscopy (TEM), or electron diffraction (ED). Alternatively, multiple of the above methods may be combined for analysis.

[0404] The oxide semiconductor of one embodiment of the present invention preferably includes a metal oxide having a CAAC structure. The CAAC structure is a crystal structure in which a plurality of microcrystals (typically, a plurality of microcrystals having a hexagonal crystal structure) have c-axis orientation and the plurality of microcrystals are connected without orientation on the a-b plane. In addition, when observing a cross-section of an oxide semiconductor having a CAAC structure using a high-resolution TEM image (also referred to as a multi-beam interference image), it can be confirmed that metal atoms are arranged in layers in the crystalline portion. Therefore, it can also be said that the oxide semiconductor having a CAAC structure has a layered crystalline portion.

[0405] The CAAC structure is formed, for example, such that the c-axis is perpendicular or substantially perpendicular to the formed surface or the surface of the oxide semiconductor. In the CAAC structure, metal atoms are arranged in layers in a direction parallel or substantially parallel to the formed surface. In the region having the CAAC structure, the angle of the c-axis with respect to the formed surface is preferably within 90° ± 20° (70° or more and 110° or less), more preferably within 90° ± 15° (75° or more and 105° or less), further preferably within 90° ± 10° (80° or more and 100° or less), and even more preferably within 90° ± 5° (85° or more and 95° or less).

[0406] When the oxide semiconductor has a CAAC structure, a group of bright spots (specifically, bright spots arranged in layers) reflecting the layered arrangement of metal atoms is observed in the cross-section of the oxide semiconductor observed using a TEM image. Specifically, it is observed that the bright spots are arranged in layers in a direction parallel or substantially parallel to the formed surface.

[0407] When performing electron diffraction on an oxide semiconductor having a CAAC structure, spots (bright spots) indicating c-axis orientation are observed in the electron diffraction pattern.

[0408] In addition, the FFT pattern obtained by performing a fast Fourier transform (FFT) process on the TEM image reflects the same reciprocal space information as the electron diffraction pattern.

[0409] Obtain a cross-sectional TEM image of an oxide semiconductor having a CAAC structure. By performing FFT processing on each region in the cross-sectional TEM image to form an FFT pattern, the direction of the crystal axis of each region can be calculated based on the produced FFT pattern. Specifically, among the spots observed in the produced FFT pattern, the direction of the line segment connecting two spots with high brightness and approximately equal distances from the center is the crystal axis direction. The angle of the crystal axis direction of each region calculated based on the FFT pattern with respect to the formed surface is preferably 70° or more and 110° or less (within 90° ± 20°), more preferably 75° or more and 105° or less (within 90° ± 15°), still more preferably 80° or more and 100° or less (within 90° ± 10°), and further preferably 85° or more and 95° or less (within 90° ± 5°) of the region can be regarded as the CAAC structure.

[0410] When observing an oxide semiconductor having a CAAC structure from a direction perpendicular to the formed surface using a TEM image, a triangular or hexagonal atomic arrangement is observed on the a-b plane and exhibits crystallinity.

[0411] [Composition of metal oxide]

[0412] The metal oxide according to one embodiment of the present invention preferably contains indium (In), and more preferably, the In content rate is high. By using a metal oxide with a high In content rate as an oxide semiconductor, the on-state current of the transistor can be increased, thereby improving the frequency characteristics. For example, indium oxide is preferably used as the oxide semiconductor.

[0413] In addition, the metal oxide according to one embodiment of the present invention may contain zinc. When the metal oxide contains zinc, the metal oxide is a metal oxide with high crystallinity, such as a metal oxide having a CAAC structure. For example, In-Zn oxide can be used as the oxide semiconductor. Specifically, a metal oxide having a composition of In:Zn = 1:1 [atomic ratio] or around it, In:Zn = 2:1 [atomic ratio] or around it, or In:Zn = 4:1 [atomic ratio] or around it can be used. Note that the composition around it includes a range of ±30% of the desired atomic ratio.

[0414] In addition, the metal oxide according to one embodiment of the present invention may contain element M. When the metal oxide contains element M, the formation of oxygen vacancies in the metal oxide can be suppressed. Therefore, the reliability of the transistor using the oxide semiconductor can be improved.

[0415] For example, as the oxide semiconductor, an In-Zn oxide containing a trace amount of element M can be used. Specifically, a metal oxide having a composition of In:Ga:Zn = 4:0.1:1 [atomic ratio] or around it, a composition of In:Ga:Zn = 2:0.1:1 [atomic ratio] or around it, or a composition of In:Ga:Zn = 1:0.1:1 [atomic ratio] or around it can be used. In addition, a metal oxide having a composition of In:Sn:Zn = 4:0.1:1 [atomic ratio] or around it, a composition of In:Sn:Zn = 2:0.1:1 [atomic ratio] or around it, or a composition of In:Sn:Zn = 1:0.1:1 [atomic ratio] or around it can be used.

[0416] In addition, as the oxide semiconductor, an In-Zn oxide containing element M can be used. Specifically, a metal oxide having a composition of In:M:Zn = 1:1:1 [atomic ratio] or around it, a composition of In:M:Zn = 1:1:1.2 [atomic ratio] or around it, a composition of In:M:Zn = 1:1:0.5 [atomic ratio] or around it, a composition of In:M:Zn = 1:1:2 [atomic ratio] or around it, a composition of In:M:Zn = 4:2:3 [atomic ratio] or around it, a composition of In:M:Zn = 1:3:2 [atomic ratio] or around it, or a composition of In:M:Zn = 1:3:4 [atomic ratio] or around it can be used.

[0417] Note that in the case of forming a metal oxide by a sputtering method, the composition of the formed metal oxide is sometimes different from that of the sputtering target. In particular, the zinc content rate of the formed metal oxide sometimes decreases to about 50% of the zinc content rate of the sputtering target.

[0418] In addition, in the case of depositing a metal oxide containing a plurality of metal elements such as an In-Ga-Zn oxide by an ALD method, the cycle number ratio of the precursors containing the respective metal elements can be set according to the target composition. For example, when depositing an In-Ga-Zn oxide having an In:Ga:Zn = 1:3:2 [atomic ratio], the cycle of depositing the precursor containing In and the treatment using an oxidizing agent can be performed once, the cycle of depositing the precursor containing Ga and the treatment using an oxidizing agent can be performed three times, and the cycle of depositing the precursor containing Zn and the treatment using an oxidizing agent can be performed twice. Note that the cycle number ratio of the precursors containing the respective metal elements sometimes does not match the atomic ratio of the respective metal elements in the deposited metal oxide.

[0419] The compositional analysis of the metal oxide for the oxide semiconductor can be performed using, for example, EDX, XPS, inductively coupled plasma mass spectrometry (ICP-MS), or inductively coupled plasma atomic emission spectrometry (ICP-AES). Alternatively, multiple of the above methods can be combined for analysis. Note that elements with low content rates are sometimes affected by the analysis accuracy, and the actual content rate may differ from the content rate obtained by analysis. For example, when the content rate of element M is low, the content rate of element M obtained by analysis may be lower than the actual content rate.

[0420] The oxide semiconductor according to one embodiment of the present invention may also have a stacked structure of two or more layers. When the oxide semiconductor has a two-layer structure including a first layer and a second layer on the first layer, the composition of the second layer is preferably different from that of the first layer. In addition, when the oxide semiconductor has a three-layer structure including a first layer, a second layer on the first layer, and a third layer on the second layer, the composition of the second layer is preferably different from that of the first layer and the third layer. In addition, the same composition as that of the third layer may be adopted as the composition of the first layer. Alternatively, the compositions of the first layer and the third layer may also be different from each other.

[0421] The first to third layers can each use the above metal oxide.

[0422] The second layer can use, for example, indium oxide, In-Zn oxide, or In-Zn oxide containing a trace amount of element M. By increasing the In content rate of the second layer, the on-state current can be increased and the frequency characteristics can be improved.

[0423] The conduction band bottom of each of the first layer and the third layer is preferably closer to the vacuum level side than the conduction band bottom of the second layer. In other words, the energy of the conduction band bottom of each of the first layer and the third layer is preferably less than the energy of the conduction band bottom of the second layer. At this time, the second layer is sandwiched between the first layer and the third layer whose conduction band bottoms are closer to the vacuum level side, and can mainly be used as a current path (channel).

[0424] When the second layer is sandwiched between the first layer and the third layer, the carriers trapped at the interface of the second layer and in its vicinity can be reduced. In addition, the channel can be separated from the surface of the gate insulating layer, and the influence of surface scattering can be reduced. As a result, an embedded channel type transistor with a channel separated from the insulating layer interface can be realized, and the field effect mobility can be improved. In addition, the influence of the interface energy level that can be formed on the back channel side is reduced, and the optical degradation (for example, photo negative bias degradation) of the transistor can be suppressed, thereby improving the reliability of the transistor.

[0425] For example, Figure 2AThe energy band diagram of the oxide semiconductor 230 including the oxide semiconductors 230a to 230c and its vicinity is as follows Figure 17 as shown. In Figure 17 , the vertical axis represents energy, and the horizontal direction represents the thickness direction at the center of the channel formation region. Figure 17 The valence band maximum (VBM) and conduction band minimum (CBM) of the oxide semiconductor 230a, the oxide semiconductor 230b, the oxide semiconductor 230c, and the insulator 250 in a state where no voltage is applied between the gate and the source are shown. In addition, in Figure 17 , the vacuum level Vac is represented by a dashed line.

[0426] Note that the energy of the valence band maximum and the energy of the conduction band minimum vary depending on the respective constituent elements and compositions of the oxide semiconductor 230a, the oxide semiconductor 230b, the oxide semiconductor 230c, and the insulator 250. Therefore, the energy band diagram used Figure 17 mainly illustrates the high-low relationship between the energies of the valence band maximums and the high-low relationship between the energies of the conduction band minimums.

[0427] Depending on the respective constituent elements and compositions of the oxide semiconductor 230a, the oxide semiconductor 230b, and the oxide semiconductor 230c, as Figure 17 shown, the oxide semiconductor 230b is sandwiched between the oxide semiconductor 230a and the oxide semiconductor 230c whose conduction band minimums are closer to the vacuum level side than that of the oxide semiconductor 230b. By adopting this structure, an embedded channel can be realized. In other words, in this structure, a path through which more current (electrons are shown as carriers in Figure 17 ) can flow is formed in the oxide semiconductor 230b. Therefore, an increase in the on-state current or an improvement in reliability can be achieved.

[0428] When forming an embedded channel using the first layer to the third layer, for example, a metal oxide having a higher Ga content ratio than the second layer can be used as the first layer and the third layer. Specifically, as each of the first layer and the third layer, a metal oxide having a composition of In:Ga:Zn = 1:1:1 [atomic ratio] or around it, a metal oxide having a composition of In:Ga:Zn = 1:3:2 [atomic ratio] or around it, or a metal oxide having a composition of In:Ga:Zn = 1:3:4 [atomic ratio] or around it can be used. Alternatively, a Ga-Zn oxide or gallium oxide can be used. When increasing the Ga content ratio of the first layer and the third layer, the conduction band minimums of the first layer and the third layer may be closer to the vacuum level side than that of the second layer.

[0429] In addition, by increasing the Ga content rate of the first layer and the third layer, the hydrogen barrier property of the first layer and the third layer can be improved. Therefore, the diffusion of hydrogen from below the first layer or above the third layer to the second layer can be suppressed. In addition, by increasing the Ga content rate of the first layer and the third layer, impurities such as hydrogen or water contained in the oxide semiconductor can be reduced by heat applied after forming the oxide semiconductor or the like.

[0430] In addition, by increasing the Ga content rate of the first layer and the third layer, the oxygen barrier property of the first layer and the third layer can be improved. Therefore, the release of oxygen from the second layer where the channel is formed can be suppressed, and the formation of oxygen vacancies in the second layer or an increase in the amount of oxygen vacancies in the second layer can be suppressed. Thereby, the electrical characteristics of the transistor can be improved.

[0431] In addition, when the Ga content rate of the first layer is increased, the resistivity of the first layer can sometimes be made higher than the resistivity of the second layer. When the first layer is provided on the back channel side, by providing a layer with a high resistivity as the first layer, the negative shift of the threshold voltage or the decrease in the on-state current can be suppressed. Therefore, the threshold voltage of the transistor drifts in the positive direction, and thus the transistor can be made normally off. Thereby, the electrical characteristics of the transistor can be made good and the reliability of the transistor can be improved.

[0432] When evaluating the band gap of a metal oxide, optical evaluation using a spectrophotometer, spectroscopic ellipsometry, photoluminescence method, X-ray photoelectron spectroscopy, or X-ray absorption fine structure (XAFS: X-ray Absorption Fine Structure) can be used. In addition, multiple of the above methods can be combined for analysis. The electron affinity or the bottom of the conduction band can be obtained from the ionization potential and the band gap of the energy difference between the vacuum level and the top of the valence band. When evaluating the ionization potential, for example, ultraviolet photoelectron spectroscopy (UPS: Ultraviolet Photoelectron Spectroscopy) can be used.

[0433] In addition, a metal oxide having an In content rate higher than that of the second layer can also be used for the first layer and the third layer. In addition, one of the first layer and the third layer and the other can respectively use a metal oxide having an In content rate higher than that of the second layer and a metal oxide having a Ga content rate higher than that of the second layer.

[0434] In addition, the first layer, the second layer, and the third layer can also each include a stack of multiple layers having the above composition. For example, the first layer can also have a structure in which a metal oxide having a high Ga content rate is stacked on a metal oxide having a high In content rate. In addition, for example, the third layer can also have a structure in which a metal oxide having a high In content rate is stacked on a metal oxide having a high Ga content rate.

[0435] [Manufacturing method of oxide semiconductor]

[0436] The oxide semiconductor according to one embodiment of the present invention can be formed by a sputtering method, a chemical vapor deposition (CVD) method, a vacuum evaporation method, a molecular beam epitaxy (MBE) method, a pulsed laser deposition (PLD) method, an atomic layer deposition (ALD) method, or the like.

[0437] In addition, the oxide semiconductor according to one embodiment of the present invention can be manufactured by forming a metal oxide using two deposition methods. For example, the oxide semiconductor according to one embodiment of the present invention can be manufactured by forming a metal oxide using a first deposition method and a second deposition method.

[0438] The oxide semiconductor according to one embodiment of the present invention can have a two-layer structure including a first layer and a second layer on the first layer. When the oxide semiconductor has a two-layer structure, the oxide semiconductor can be manufactured by forming the first layer on a formation surface using a first deposition method and then forming the second layer thereon using a second deposition method.

[0439] As the first deposition method, a deposition method that causes less damage to the formation surface than the second deposition method is preferably used. Thereby, the formation of a mixed layer at the interface between the oxide semiconductor and the layer on the formation surface of the oxide semiconductor can be suppressed. In addition, since impurities such as silicon can be suppressed from being mixed into the second layer formed on the first layer, the crystallinity of the oxide semiconductor can sometimes be further improved.

[0440] As the first deposition method, for example, an ALD method, a CVD method, an MBE method, or the like can be cited. In addition, as the CVD method, a plasma CVD (PECVD: Plasma Enhanced CVD) method, a thermal CVD method, a photo CVD method, a metalorganic CVD (MOCVD) method, or the like can be cited. The MBE method is a deposition method in which a thin film having a crystal structure that reflects the crystal system of the substrate grows, and can be said to be one of the deposition methods that cause less damage to the formation surface. In addition, as the first deposition method, a wet method can be used. The wet method is one of the deposition methods that cause less damage to the formation surface. As the wet method, for example, a spraying method or the like can be cited.

[0441] As the second deposition method, a method capable of depositing a crystalline metal oxide is preferably used. The metal oxide deposited at this time particularly preferably has a CAAC structure. As the second deposition method, for example, a sputtering method, a PLD method, or the like can be cited. Since the metal oxide deposited by the sputtering method easily has crystallinity, the sputtering method is suitable as the second deposition method.

[0442] In addition, when a metal oxide is formed on a surface to be formed by a second deposition method, damage to the surface to be formed sometimes causes alloying between the components contained in the metal oxide and the components contained in the layer of the surface to be formed. When alloying occurs, a mixed layer sometimes forms at the interface between the metal oxide and the layer of the surface to be formed. This mixed layer can also be referred to as an alloying region. In addition, the formation of the mixed layer can also be referred to as alloying.

[0443] For example, when the sputtering method is used as the second deposition method, a mixed layer sometimes forms due to particles released from a target or the like (also referred to as sputtered particles) or energy supplied to the substrate side by sputtered particles or the like. Specifically, when a metal oxide is deposited on a silicon-containing insulating layer such as a silicon oxide film as the surface to be formed by the second deposition method, there is a concern that silicon may be mixed into the metal oxide. When impurities such as silicon are mixed into the metal oxide, crystallization of the metal oxide may be blocked. In addition, when an oxide semiconductor containing impurities is used for a transistor, there is a concern that it may have a negative impact on the initial characteristics or reliability of the transistor. In addition, it is also difficult to improve the crystallinity of the alloying region in the case of performing heat treatment described later.

[0444] Thus, as described above, by forming a metal oxide by the first deposition method before forming a metal oxide by the second deposition method, mixing of impurities into the oxide semiconductor can be suppressed. In addition, alloying with the layer of the surface to be formed can be suppressed. Therefore, the initial characteristics and reliability of the transistor can be improved. In addition, the crystallinity of the oxide semiconductor can be further improved.

[0445] Note that a mixed layer sometimes forms at the interface between the first layer and the second layer. The mixed layer contains the components contained in the first layer and the components contained in the second layer. For example, when gallium oxide is used as the first layer and a metal oxide containing indium is used as the second layer, the mixed layer contains gallium and indium. For example, when the indium content rate of the second layer is higher than that of the first layer, the indium content rate of the mixed layer is equal to or higher than that of the first layer and equal to or lower than that of the second layer.

[0446] Compared with the sputtering method, the ALD method can suppress damage to the surface to be formed, so it is suitable as the first deposition method. In addition, the ALD method is a deposition method with higher coverage than the sputtering method. By using the ALD method as the deposition method for the first layer, the coverage of the oxide semiconductor can be improved. Therefore, the oxide semiconductor can be used to well cover steps, openings, etc. with a high aspect ratio.

[0447] As the first layer, for example, a metal oxide having a microcrystalline structure or an amorphous structure with lower crystallinity than the CAAC structure is sometimes formed. By forming a second layer with high crystallinity on the first layer with low crystallinity, or by performing heat treatment after forming the second layer, the crystallinity of the first layer is sometimes improved with the second layer as the nucleus. Thus, it is sometimes possible to improve the crystallinity of the entire oxide semiconductor including the vicinity of the interface with the formation surface.

[0448] The layer on the formation surface is, for example, an insulating film such as a silicon oxide film, a silicon oxynitride film, a silicon nitride film, a silicon nitride oxide film, an aluminum oxide film, or a hafnium oxide film. In addition, depending on the transistor structure, the layer on the formation surface may be a conductive film such as a titanium nitride film, a tungsten film, or an ITSO film. In addition, the layer on the formation surface may not have crystallinity. Further, in the case where the layer has crystallinity, it may have a crystal structure with low lattice matching with the metal oxide contained in the oxide semiconductor.

[0449] The first layer is preferably formed by the ALD method. Here, a method of forming In-M-Zn oxide by the ALD method as the first layer will be described.

[0450] First, a source gas including a precursor containing indium is introduced into a reaction chamber (also referred to as a processing chamber), and the precursor is adsorbed onto the formation surface. Next, an oxidizing agent is introduced into the reaction chamber as a reactant, and it reacts with the adsorbed precursor, and components other than indium are removed in a state where indium is adsorbed onto the substrate, thereby forming a layer in which indium and oxygen are bonded.

[0451] Next, a source gas including a precursor containing element M is introduced into the reaction chamber, and it is adsorbed onto the layer in which indium and oxygen are bonded. Next, an oxidizing agent is introduced into the reaction chamber as a reactant, and it reacts with the adsorbed precursor, and components other than element M are removed in a state where element M is adsorbed onto the substrate, thereby forming a layer in which element M and oxygen are bonded.

[0452] Next, a source gas including a precursor containing zinc is introduced into the reaction chamber and adsorbed onto the layer in which element M and oxygen are bonded. Next, an oxidizing agent is introduced into the reaction chamber as a reactant, and it reacts with the adsorbed precursor, and components other than zinc are removed in a state where zinc is adsorbed onto the substrate, thereby forming a layer in which zinc and oxygen are bonded.

[0453] By repeating the above method, In-M-Zn oxide can be formed as an oxide semiconductor on the layer on the formation surface by the ALD method.

[0454] In the case of forming an oxide semiconductor by the ALD method, ozone (O3), oxygen (O2), water (H2O), etc. can be used as the oxidizing agent. By using ozone (O3), oxygen (O2), etc. that do not contain hydrogen as the oxidizing agent, the amount of hydrogen mixed into the oxide semiconductor can be reduced.

[0455] In the above, preferably, after the precursor is adsorbed, the introduction of the source gas containing the precursor is stopped, purging is performed in the reaction chamber, and then the remaining precursor, reaction products, etc. are discharged from the reaction chamber. In the above, preferably, after the adsorbed precursor reacts with the oxidant, the introduction of the oxidant is stopped, purging is performed in the reaction chamber, and then the remaining reactants, reaction products, etc. are discharged from the reaction chamber.

[0456] In addition, in the descriptions such as this specification, when ozone, oxygen, or water is used as a reactant or an oxidant without special description, they also include the plasma state, radical state, and ionic state, not limited to the gas state or molecular state.

[0457] The second layer is preferably formed by a sputtering method.

[0458] As the target for the sputtering method, In-M-Zn oxide can be used. For example, when forming a metal oxide by the sputtering method, oxygen or a mixed gas of oxygen and a noble gas is used as the sputtering gas. In addition, by increasing the proportion of oxygen contained in the sputtering gas, the excess oxygen in the deposited oxide film can be increased.

[0459] In addition, sometimes the higher the flow ratio of oxygen gas (hereinafter, also referred to as the oxygen flow ratio) with respect to the entire deposition gas used during formation, the higher the crystallinity of the metal oxide that can be formed.

[0460] When forming a metal oxide by the sputtering method, an oxygen-excess type metal oxide can sometimes be formed under the condition that the proportion of oxygen contained in the sputtering gas is higher than 30% and 100% or less, preferably 70% or more and 100% or less. Using the oxygen-excess type metal oxide for the transistor in the channel formation region can obtain higher reliability. Note that one aspect of the present invention is not limited to this. By depositing under the condition that the proportion of oxygen contained in the sputtering gas is 1% or more and 30% or less, preferably 5% or more and 20% or less, an oxygen-deficient type metal oxide is formed. Using the oxygen-deficient type metal oxide for the transistor in the channel formation region can have a higher field-effect mobility.

[0461] When forming a metal oxide by the sputtering method, it is preferable to heat the substrate. By increasing the substrate temperature (stage temperature) when forming the metal oxide, a metal oxide with high crystallinity can sometimes be formed. When forming a metal oxide by the sputtering method, the temperature for heating the substrate is, for example, preferably 100 °C or more and 400 °C or less, more preferably 200 °C or more and 300 °C or less.

[0462] By adopting the above manufacturing method, the thickness of the mixed layer at the interface between the layer formed on the formation surface and the metal oxide can be reduced, or the alloying region at the interface between the layer formed on the formation surface and the metal oxide can be thinned to an extent that it cannot be observed. For example, the thickness of the alloying region can be 0 nm or more and 3 nm or less, preferably 0 nm or more and 2 nm or less, more preferably 0 nm or more and 1 nm or less, and further preferably 0 nm or more and less than 0.3 nm.

[0463] In addition, the thickness of the alloying region can sometimes be calculated by performing a line analysis of the composition on this region and its periphery using SIMS or energy dispersive X-ray spectroscopy (EDX).

[0464] For example, with the direction perpendicular to the formation surface of the first layer as the depth direction, a line analysis of EDX is performed on the alloying region and its surroundings. Then, in the distribution of the quantitative values of each element with respect to the depth direction obtained by this analysis, the depth at which the quantitative value of the metal that is the main component of the first layer rather than the main component of the layer to be formed on the formation surface (In when the first layer contains In) reaches half value is defined as the depth (position) of the interface between the above region and the first layer. In addition, the depth at which the quantitative value of the element that is the main component of the layer to be formed on the formation surface rather than the main component of the first layer (such as Si) reaches half value is defined as the depth (position) of the interface between the above region and the layer to be formed on the formation surface. Through the above steps, the thickness of the alloying region can be calculated.

[0465] In the case of observing the thickness of the alloying region in the oxide semiconductor of one embodiment of the present invention using EDX analysis, for example, the thickness is 0 nm or more and 3 nm or less, preferably 0 nm or more and 2 nm or less, more preferably 0 nm or more and 1 nm or less, and further preferably 0 nm or more and less than 0.3 nm.

[0466] In addition, for example, when performing SIMS analysis on the oxide semiconductor formed on the silicon oxide film on the formation surface, the depth at which the silicon concentration reaches 50% of the maximum value of the concentration of the silicon oxide film is defined as the interface, and the distance between the depth at which the silicon concentration decreases to 1.0×10 21 atoms / cm 3 、preferably decreases to 5.0×10 20 atoms / cm 3 、more preferably decreases to 1.0×10 20 atoms / cm 3 and the interface is defined as the thickness t. The thickness t is preferably 3 nm or less, more preferably 2 nm or less.

[0467] By reducing the thickness of the alloying region, the thickness t can be set to a value within the above range.

[0468] In addition, by reducing the alloying region, a CAAC structure can be formed near the formation surface. Here, the vicinity of the formation surface refers to a region having a thickness greater than 0 nm and 3 nm or less, preferably greater than 0 nm and 2 nm or less, and more preferably 1 nm or more and 2 nm or less in a direction substantially perpendicular to the formation surface of the oxide semiconductor.

[0469] Note that the CAAC structure near the formation surface can sometimes be confirmed by observation using TEM. For example, when observing a cross section of an oxide semiconductor using high-resolution TEM, bright spots arranged in layers in a direction parallel to the formation surface are confirmed near the formation surface.

[0470] In addition, an oxide semiconductor according to one embodiment of the present invention may have a three-layer structure including a first layer, a second layer on the first layer, and a third layer on the second layer.

[0471] When the oxide semiconductor has a three-layer structure, the oxide semiconductor can be manufactured by the following steps: after forming the first layer on the formation surface using a first deposition method, forming the second layer using a second deposition method, and forming the third layer using the first deposition method.

[0472] In the above oxide semiconductor, even when a composition that is not easily formed into a CAAC structure by forming a single layer is used for the first layer and the third layer, since crystal growth occurs with the second layer as a nucleus, the entire oxide semiconductor including the first layer and the third layer can have a CAAC structure. Alternatively, a region including at least a part of each of the first layer and the third layer to a region including the second layer can have a CAAC structure.

[0473] In particular, in a composition having a high In content in the first layer and the third layer, it is also possible to have crystallinity suitable for a semiconductor layer of a transistor. In an oxide semiconductor according to one embodiment of the present invention, while increasing the In content to improve the turn-on characteristics of the transistor, a CAAC structure with high crystallinity can be adopted to improve reliability.

[0474] In addition, the first layer and the third layer may also use a metal oxide having the same composition as the second layer. By using the same composition, CAAC formation after heat treatment sometimes easily occurs.

[0475] Since the second layer has high crystallinity, the third layer can crystallize and grow with the crystals of the second layer as nuclei or seeds. Therefore, even when a deposition method that does not easily impart crystallinity is used as the deposition method for the third layer, the third layer can be crystallized. Here, for example, by forming the third layer using a deposition method with a higher coverage ratio than the second layer, the oxide semiconductor can have both high crystallinity and high coverage over the entire layer.

[0476] In addition, by providing the first layer to reduce the influence of the formation surface, the crystallinity of the second layer is improved, resulting in extremely excellent crystallinity. Therefore, it is expected that a layer with extremely excellent crystallinity will also be formed in the third layer that crystallizes with the second layer as nuclei or seeds.

[0477] Note that when an oxide semiconductor is used as the semiconductor layer of a transistor, the third layer, which is the uppermost layer of the oxide semiconductor, sometimes contacts the gate insulating layer. By improving the crystallinity of the layer in contact with the gate insulating layer, the carrier mobility of the transistor in the on state can be increased.

[0478] The crystallinity of the first layer and the third layer is improved with the second layer having high crystallinity as nuclei or seeds. Specifically, the crystallinity of the first layer is sometimes improved by heat treatment during the deposition of the second layer or after the deposition of the third layer. In addition, the crystallinity of the third layer is sometimes improved by heat treatment during the deposition of the third layer or after the deposition of the third layer. Furthermore, the above heat treatment plays an auxiliary role in improving crystallinity.

[0479] In this way, in the method for manufacturing an oxide semiconductor according to one embodiment of the present invention, the crystallinity of the metal oxides above and below (here, the first layer and the third layer) can be improved with the second layer containing a metal oxide with high crystallinity (i.e., CAAC) as nuclei or seeds. Thereby, the crystallinity of the entire oxide semiconductor can be improved. In other words, with the second layer as nuclei or seeds, the metal oxides above and below it are solid-phase grown, so that an oxide semiconductor with high crystallinity can be formed. The oxide semiconductor formed using the above deposition method, here the CAAC film can be called Axial Growth CAAC (AGCAAC).

[0480] In the oxide semiconductor, regions having a CAAC structure are preferably widely present throughout the layer. The crystal regions of the first layer having a CAAC structure are crystal-bonded to the crystal regions of the second layer having a CAAC structure. The crystal regions of the third layer having a CAAC structure are crystal-bonded to the crystal regions of the second layer having a CAAC structure. As a result, the boundary between the first layer and the second layer is sometimes not observable. In addition, the boundary between the second layer and the third layer is sometimes not observable. Sometimes it can be expressed that the oxide semiconductor is a layer without a clearly observable interface. Sometimes it can be expressed that the oxide semiconductor is a single layer.

[0481] In each of the first to third layers, for example, when performing cross-sectional observation using high-resolution TEM, bright spots arranged parallel or substantially parallel to the formation surface are confirmed in the region having a CAAC structure. In addition, the c-axis of the CAAC structure possessed by each of the first to third layers is preferably parallel or substantially parallel to the normal direction of the formation surface or the surface of the oxide semiconductor.

[0482] In addition, a part of the first layer or the third layer may not be crystallized.

[0483] In addition, in the case where the oxide semiconductor has a three-layer structure, the oxide semiconductor can also be manufactured by the following steps: after forming the first layer on the formation surface using the first deposition method, forming the second layer using the first deposition method, and forming the third layer using the second deposition method.

[0484] As described above, by using a metal oxide with a high In content rate for the transistor, the field-effect mobility of the transistor can be improved. On the other hand, a metal oxide with a high In content rate tends to have a cubic crystal structure. Thus, by using a metal oxide with a high In content rate for the second layer in contact with the third layer, crystals reflecting the orientation of the crystals contained in the third layer can be formed.

[0485] In addition, the lattice mismatch degree between the crystals contained in the third layer and the crystals contained in the second layer is preferably small. Thus, crystals reflecting the orientation of the crystals contained in the third layer can be formed in the second layer. At this time, for example, when observing the cross section of the oxide semiconductor using high-resolution TEM, bright spots arranged in layers in the direction parallel to the formation surface are observed in the second layer.

[0486] As long as the lattice mismatch degree between the crystals contained in the third layer and the crystals contained in the second layer is small, there is no particular limitation on the crystal structure of the second layer. The crystal structure of the second layer can be cubic, tetragonal, orthorhombic, hexagonal, monoclinic, or trigonal.

[0487] In the above structure, typically, the first layer can be a layer containing a metal oxide having a composition of In:Ga:Zn = 1:3:2 [atomic ratio] or near it or gallium oxide, the second layer can be a layer containing the above metal oxide containing a trace amount of element M or indium oxide, and the third layer can be a layer containing a metal oxide having a composition of In:Ga:Zn = 1:1:1 [atomic ratio] or near it. At this time, the first layer contains gallium. In addition, in the case where the first layer contains a metal oxide having a composition of In:Ga:Zn = 1:3:2 [atomic ratio] or near it, the indium content rate in the first layer is lower than the gallium content rate. In addition, the indium content rate of the second layer is higher than the indium content rate of the third layer.

[0488] When forming the first layer and the second layer using the first deposition method, it is preferable to continuously deposit the first layer and the second layer without being exposed to the atmosphere. By continuously depositing the first layer and the second layer without being exposed to the atmosphere, productivity can be improved. In addition, impurities (typically moisture, etc.) introduced into the interface between the first layer and the second layer and its vicinity can be reduced.

[0489] In addition, one or more of the first layer to the third layer may also be laminated to include a plurality of layers having different compositions. For example, the first layer can also be manufactured by the following steps: after forming a layer containing a metal oxide with a high Ga content rate using the first deposition method, a layer containing a metal oxide with an In content rate higher than that of this layer is formed using the first deposition method.

[0490] It is preferable to perform microwave plasma treatment after forming a layer using the first deposition method.

[0491] In this specification, etc., microwaves refer to electromagnetic waves having a frequency of 300 MHz or more and 300 GHz or less. Microwave plasma treatment is, for example, a treatment using a device including a power source for generating high-density plasma using microwaves. Microwave plasma treatment may also be referred to as microwave-excited high-density plasma treatment.

[0492] By performing microwave plasma treatment in an oxygen-containing atmosphere, the impurity concentration in the oxide semiconductor 230 can be reduced. As impurities, hydrogen and carbon can be particularly mentioned. Note that the above shows a structure in which microwave plasma treatment is performed on a metal oxide in an oxygen-containing atmosphere, but it is not limited thereto. For example, microwave plasma treatment can also be performed on an insulating film provided near the metal oxide, more specifically, on a silicon oxide film, in an oxygen-containing atmosphere. In addition, sometimes the crystallinity of the oxide semiconductor is improved due to the heat in the microwave plasma treatment.

[0493] Microwave plasma treatment is preferably performed under reduced pressure, and the pressure is preferably 10 Pa or more and 1000 Pa or less, more preferably 50 Pa or more and 700 Pa or less, and further preferably 100 Pa or more and 400 Pa or less. In addition, the treatment temperature is preferably room temperature (25 °C) or more and 750 °C or less, more preferably 300 °C or more and 500 °C or less, and may be 400 °C or more and 450 °C or less.

[0494] When performing microwave plasma treatment, the substrate can also be heated. The heating temperature of the substrate is preferably room temperature (for example, 25 °C) or more, 100 °C or more, 200 °C or more, 300 °C or more, or 400 °C or more and 500 °C or less or 450 °C or less.

[0495] Microwave plasma treatment can be carried out, for example, using oxygen gas and argon gas. For example, the oxygen flow ratio (O2 / (O2+Ar)) in the microwave plasma treatment is preferably greater than 0% and 10% or less, more preferably 0.5% or more and 5% or less, still more preferably 0.5% or more and 3% or less, and typically preferably 1%.

[0496] By performing microwave plasma treatment in an oxygen-containing atmosphere, oxygen gas can be plasmaized using high-frequency waves such as microwaves or RF, and oxygen radicals generated by plasmaizing oxygen gas can act on the oxide semiconductor. Through the action of plasma, microwaves, or oxygen radicals, etc., the defect in which hydrogen in the oxide semiconductor enters the oxygen vacancy (sometimes hereinafter referred to as V O H) can be separated into an oxygen vacancy and hydrogen, and hydrogen as an impurity can be removed from the oxide semiconductor. Thus, V O H contained in the oxide semiconductor can be reduced. At this time, carbon bonded to oxygen or hydrogen, etc. can sometimes also be removed. Thus, by performing microwave plasma treatment, impurities such as carbon or hydrogen can be reduced. In addition, by supplying the above-mentioned oxygen radicals to the oxygen vacancies formed in the oxide semiconductor, the oxygen vacancies in the oxide semiconductor can be further reduced.

[0497] In addition, by performing microwave plasma treatment, the crystallinity of the layer formed by the first deposition method can be improved. Here, the principle of improving the crystallinity of the oxide semiconductor by microwave plasma treatment will be described. First, active species such as oxygen radicals excited by microwaves reach the surface of the oxide semiconductor, and a substitution reaction between the active species and oxygen in the oxide semiconductor occurs. At this time, nuclei or seeds are formed. In addition, lateral growth of the nuclei or seeds is caused. In addition, when the active species excited by microwaves contains oxygen (typically oxygen ions) that is easily adsorbed to the side surface of the nuclei or seeds, the above-mentioned lateral growth is promoted, so this is preferable. By performing microwave plasma treatment, formation of nuclei or seeds and lateral growth of the nuclei or seeds occur, and the crystallinity of the oxide semiconductor is improved.

[0498] On the other hand, when a part of the oxygen in the oxide semiconductor present before microwave plasma treatment reacts with hydrogen in the oxide semiconductor, that is, the reaction of "2H+O→H2O↑" occurs, the hydrogen can be removed as H2O (also referred to as dehydration or dehydrogenation). Since H2O is one of the main reasons that hinder the improvement of crystallinity, it is preferable to remove H2O from the oxide semiconductor. Removing hydrogen in the oxide semiconductor as H2O to reduce the hydrogen concentration in the oxide semiconductor can also promote the improvement of crystallinity. In addition, by increasing the temperature in the microwave plasma treatment, the hydrogen concentration in the oxide semiconductor can be further reduced.

[0499] In addition, the heat treatment may be continuously performed in a manner not exposing to the atmosphere after the microwave plasma treatment. The temperature of the heat treatment is, for example, preferably 100°C or higher and 750°C or lower, more preferably 300°C or higher and 500°C or lower, and further preferably 400°C or higher and 450°C or lower.

[0500] Note that a plasma treatment including an oxygen gas may be performed instead of the microwave plasma treatment to improve crystallinity.

[0501] When the crystallinity of the layer formed by the first deposition method is improved, the crystallinity of the layer formed on this layer can be further improved. Therefore, the crystallinity of the entire oxide semiconductor can be improved.

[0502] As the oxygen supplied to the oxide semiconductor, there are various forms such as oxygen atoms, oxygen molecules, oxygen ions (charged oxygen atoms or oxygen molecules), and oxygen radicals (oxygen atoms, oxygen molecules, or oxygen ions containing unpaired electrons). The oxygen injected into the oxide semiconductor is preferably any one or more of the above forms, and particularly preferably an oxygen radical.

[0503] In addition, a heat treatment is preferably performed after forming the oxide semiconductor. By performing the heat treatment, the crystallinity of the oxide semiconductor can be improved. Here, the heat treatment is not limited to the heating treatment. For example, it may be heat applied in the manufacturing process or the like.

[0504] The temperature of the heat treatment can be, for example, 100°C or higher and 800°C or lower, preferably 250°C or higher and 650°C or lower, and more preferably 350°C or higher and 550°C or lower. Typically, it can be 400°C ± 25°C (375°C or higher and 425°C or lower). In addition, the treatment time can be 10 hours or less, for example, it can be 1 minute or more and 5 hours or less, or 1 minute or more and 2 hours or less. Further, in the case of using an RTA apparatus, the treatment time can be, for example, 1 second or more and 5 minutes or less. By this heat treatment, it is expected that the gaps of the atomic-level crystal parts in the CAAC structure of the second layer formed by the second deposition method are filled with the third layer (in other words, each crystalline molecule formed by the ALD method) formed by the first deposition method.

[0505] There is no particular limitation on the heating device for heat treatment, and it can also be a device that heats the object to be treated by heat conduction or heat radiation from a heating element such as a resistance heating element. For example, an electric furnace or an RTA (Rapid Thermal Anneal) device such as an LRTA (Lamp Rapid Thermal Anneal) device or a GRTA (Gas Rapid Thermal Anneal) device can be used. The LRTA device is a device that heats the object to be treated by the radiation of light (electromagnetic wave) emitted from a lamp such as a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high-pressure sodium lamp, or a high-pressure mercury lamp. The GRTA device is a device that uses high-temperature gas for heat treatment.

[0506] Through this heat treatment process, sometimes in the third layer formed by the first deposition method, the crystallinity of the region having the CAAC structure is improved. In addition, when this region is only formed below the above-mentioned third layer after deposition by the ALD method, sometimes this region expands upward through this heat treatment process. That is to say, by performing this heat treatment, a region having the CAAC structure is sometimes formed in the entire above-mentioned third layer.

[0507] In addition, it is preferable to make at least a part of the first layer or the second layer formed by the first deposition method CAAC through this heat treatment process. It can be expected that it is easy to cause CAAC to occur with the mixed layer formed in the first layer or the second layer as the nucleus or seed when forming a layer by the second deposition method. Preferably, the CAAC region in the first layer or the second layer is large and expands to the vicinity of the formation surface.

[0508] In addition, since CAAC is performed from the upper part to the lower part of the first layer or the second layer, it is not limited by the material or crystallinity of the layer on the formation surface, and the vicinity of this layer can also be CAAC. For example, even if this layer has an amorphous structure, the crystallinity of the first layer or the second layer can be improved. Therefore, the method for manufacturing an oxide semiconductor according to one aspect of the present invention is particularly suitable for the case where the layer on the formation surface has an amorphous structure.

[0509] As described above, by performing one or both of microwave plasma treatment and heat treatment, the crystallinity of the entire oxide semiconductor can be improved. In addition, impurities in the oxide semiconductor can be reduced. By performing crystal growth in a state where the impurity concentration in the oxide semiconductor is reduced, the crystallinity can be further improved.

[0510] By improving the crystallinity of an oxide semiconductor, an increase in the resistance of a semiconductor layer of a transistor using the oxide semiconductor is suppressed, or the initial characteristics (especially the on-state current) of the transistor are improved. As a result, a transistor suitable for high-speed driving can be expected to be realized. In addition, the reliability of the transistor can be improved and the on-state current can be increased.

[0511] In addition, one or both of the microwave plasma treatment and the heat treatment can be directly performed on the oxide semiconductor or can be performed after forming an insulating film or the like on the oxide semiconductor.

[0512] Before depositing the first layer or after forming the first layer or the second layer by the first deposition method, a treatment of supplying oxygen to the first layer or the second layer can also be performed. As a result, oxygen can be supplied to the oxide semiconductor by heat or the like applied after this treatment.

[0513] Examples of the treatment of supplying oxygen include heat treatment in an oxygen-containing atmosphere or plasma treatment (including microwave plasma treatment) in an oxygen-containing atmosphere. Alternatively, oxygen can be supplied to the first layer or the second layer formed by the first deposition method by depositing an oxide film (preferably a metal oxide film) in an oxygen-containing atmosphere using a sputtering method. The deposited oxide film can be immediately removed or can remain. When the deposited oxide film remains, the oxide film can be used as a layer (the second layer or the third layer) provided on the first layer or the second layer. In addition, as the oxygen-containing atmosphere, in addition to oxygen gas (O2), an atmosphere containing an oxygen-containing compound gas such as ozone (O3) or nitrous oxide (N2O) is included. In addition, the substrate temperature in the plasma treatment is 25°C or higher and 450°C or lower.

[0514] The oxide semiconductor of one embodiment of the present invention has high crystallinity throughout the layer. Therefore, the boundary between the stacked films in the first layer to the third layer may not be confirmed in the oxide semiconductor. In particular, after the heat treatment, it may be difficult to confirm the boundary between the stacked films. For example, a cross-sectional TEM, a cross-sectional STEM (scanning transmission electron microscope), or the like can be used to confirm whether there is a boundary between the stacked films.

[0515] In addition, compared with an oxide semiconductor having a CAAC structure formed by one deposition method, any one or more of the relative dielectric constant, film density, and film hardness of the film of the oxide semiconductor having a CAAC structure formed by the above two deposition methods may be higher.

[0516] By using the oxide semiconductor having a CAAC structure formed by the above two deposition methods in the channel formation region of a transistor, a transistor with excellent characteristics (for example, a transistor with a large on-state current, a transistor with a high field-effect mobility, a transistor with a small S value, a transistor with high frequency characteristics (also referred to as f characteristics), a transistor with high reliability, etc.) can be achieved.

[0517] In addition, an oxide semiconductor according to one embodiment of the present invention can sometimes be manufactured by using one or both of a first deposition method and microwave plasma treatment and heat treatment. In other words, an oxide semiconductor according to one embodiment of the present invention can sometimes be manufactured without using a second deposition method. For example, by performing one or both of microwave plasma treatment and heat treatment after forming a first layer by using a first deposition method, the crystallinity of the first layer can be improved. Therefore, the crystallinity of a second layer formed on the first layer by using the first deposition method can be improved with the first layer as a core or seed. In addition, by performing one or both of microwave plasma treatment and heat treatment after forming the second layer, the crystallinity of the oxide semiconductor can be improved. Therefore, a CAAC structure can be formed in the oxide semiconductor.

[0518] As described above, in a manufacturing method without using a second deposition method, solid-phase growth of the upper oxide semiconductor can also be performed with the first layer formed by using the first deposition method as a core or seed to form an oxide semiconductor with high crystallinity. The oxide semiconductor formed by the above deposition method can also be referred to as AG CAAC.

[0519] In addition, in the case where the oxide semiconductor has a stacked structure of two or more layers, the oxide semiconductor can also be manufactured by forming a metal oxide by using one deposition method. In the case where the oxide semiconductor has a two-layer structure of a first layer and a second layer on the first layer, for example, the oxide semiconductor can be manufactured by sequentially forming the first layer and the second layer by using a sputtering method. Since the deposition rate of the sputtering method is faster than that of the ALD method, the productivity can be improved. In addition, for example, when the oxide semiconductor has a three-layer structure of a first layer, a second layer on the first layer, and a third layer on the second layer, the first layer to the third layer can also be formed by using a sputtering method. Furthermore, a part of the first layer to the third layer can also be deposited by using the ALD method. For example, one or both of the second layer and the third layer can also be deposited by using the ALD method.

[0520] [Oxide Semiconductor of Transistor]

[0521] The oxide semiconductor of the present embodiment can be used as a semiconductor layer of a transistor.

[0522] The oxide semiconductor of this embodiment can be used as the oxide semiconductor 230 and the like included in each transistor described in Embodiment 1. For example, the first layer can be used as the oxide semiconductor 230a, the second layer can be used as the oxide semiconductor 230b, and the third layer can be used as the oxide semiconductor 230c. In addition, the layer on the formation surface corresponds to the insulator 224 described in Embodiment 1.

[0523] The oxide semiconductor of this embodiment preferably has a CAAC structure. In the oxide semiconductor having a CAAC structure, metal atoms are arranged in layers in a direction parallel to or substantially parallel to the formation surface in the crystal part.

[0524] It can be speculated that the oxide semiconductor having a CAAC structure exhibits current anisotropy. For example, in IGZO crystals, current is more likely to flow along the a-axis direction than along the c-axis direction. In other words, it can be speculated that in the oxide semiconductor having a CAAC structure, current is more likely to flow along the lateral direction than along the longitudinal direction.

[0525] In the semiconductor device described in the above embodiment, metal atoms in the oxide semiconductor 230 are arranged in layers in a direction parallel to or substantially parallel to the formation surface. In addition, it can also be expressed that the a-b plane of the CAAC structure is provided in a direction parallel to or substantially parallel to the formation surface. By adopting such a structure, the a-b plane of the CAAC structure can be provided in the channel of the transistor in the direction of current flow. Thereby, the on-state current of the transistor can be increased.

[0526] When the oxide semiconductor of this embodiment is used as the semiconductor layer of a transistor, the thickness of the oxide semiconductor is preferably, for example, 3 nm or more and 200 nm or less, more preferably 3 nm or more and 100 nm or less, more preferably 5 nm or more and 100 nm or less, more preferably 10 nm or more and 100 nm or less, more preferably 10 nm or more and 70 nm or less, more preferably 15 nm or more and 70 nm or less, more preferably 15 nm or more and 50 nm or less, more preferably 20 nm or more and 50 nm or less. In addition, in a transistor for a more miniaturized semiconductor device, the thickness of the oxide semiconductor is preferably 1 nm or more and 20 nm or less, preferably 3 nm or more and 15 nm or less, preferably 5 nm or more and 12 nm or less, preferably 5 nm or more and 10 nm or less. In addition, the average thickness of the oxide semiconductor in the channel formation region of the transistor is preferably, for example, 2 nm or more and 15 nm or less.

[0527] The thickness of the first layer is, for example, preferably 0.5 nm or more and 50 nm or less, more preferably 0.5 nm or more and 30 nm or less, more preferably 0.5 nm or more and 20 nm or less, more preferably 1 nm or more and 50 nm or less, more preferably 1 nm or more and 30 nm or less, more preferably 1 nm or more and 20 nm or less, more preferably 2 nm or more and 20 nm or less. Further, the first layer is more preferably 0.5 nm or more and 3 nm or less.

[0528] Further, the first layer preferably has a region with a thickness of 0.1 nm or more and 3 nm or less, and more preferably has a region with a thickness of 0.1 nm or more and 2 nm or less. Alternatively, it more preferably has a region with a thickness of 0.5 nm or more and 3 nm or less, and further preferably has a region with a thickness of 0.5 nm or more and 2 nm or less.

[0529] The thickness of the second layer is, for example, preferably 200 nm or less. In addition, when the second layer is in a layered form, the thickness is, for example, preferably 1 nm or more and 200 nm or less, more preferably 1 nm or more and 100 nm or less, and further preferably 2 nm or more and 100 nm or less.

[0530] Alternatively, when the second layer can act as a crystal nucleus, the second layer sometimes does not exist in a layered form but becomes an aggregate of island regions. In this case, for example, the island regions included in the second layer are dispersed.

[0531] The preferred range of the thickness of the third layer can refer to the description of the thickness of the first layer.

[0532] [Impurities in the oxide semiconductor]

[0533] Here, the effects of various impurities in the oxide semiconductor are described.

[0534] As described in the above embodiments, in a transistor using an oxide semiconductor as a semiconductor layer, when there are oxygen vacancies (V O ) and impurities in the channel formation region of the oxide semiconductor, the electrical characteristics sometimes easily change and the reliability decreases. Therefore, in order to stabilize the electrical characteristics of the OS transistor, it is effective to reduce the impurity concentration in the oxide semiconductor. In order to reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in the nearby film. Examples of impurities include hydrogen, carbon, nitrogen, etc. Note that impurities in the oxide semiconductor refer to elements other than the main components constituting the oxide semiconductor. For example, an element with a concentration lower than 0.1 atomic% can be said to be an impurity.

[0535] When the oxide semiconductor contains silicon or carbon, which is one of the Group 14 elements, defect states are formed in the oxide semiconductor. Accordingly, the carbon concentration in the channel formation region of the oxide semiconductor measured by SIMS is set to 1×10 20 atoms / cm 3 or less, preferably 5×10 19 atoms / cm 3 or less, more preferably 3×10 19 atoms / cm 3 or less, more preferably 1×10 19 atoms / cm 3 or less, more preferably 3×10 18 atoms / cm 3 or less, further preferably 1×10 18 atoms / cm 3 or less. In addition, the silicon concentration in the channel formation region of the oxide semiconductor measured by SIMS is set to 1×10 20 atoms / cm 3 or less, preferably 5×10 19 atoms / cm 3 or less, more preferably 3×10 19 atoms / cm 3 or less, more preferably 1×10 19 atoms / cm 3 or less, more preferably 3×10 18 atoms / cm 3 or less, further preferably 1×10 18 atoms / cm 3 or less.

[0536] In addition, when the oxide semiconductor contains nitrogen, electrons are generated as carriers, increasing the carrier concentration and making it easy to be n-type. As a result, when the oxide semiconductor containing nitrogen is used for a semiconductor transistor, it tends to have a normally-on characteristic. Or, when the oxide semiconductor contains nitrogen, trap states are sometimes formed. As a result, the electrical characteristics of the transistor are sometimes unstable. Therefore, the nitrogen concentration in the channel formation region of the oxide semiconductor measured by SIMS is set to 1×10 20 atoms / cm 3 or less, preferably 5×10 19 atoms / cm 3 or less, more preferably 1×10 19 atoms / cm 3 or less, more preferably 5×10 18 atoms / cm 3 or less, more preferably 1×1018 atoms / cm 3 Hereinafter, it is further preferably 5×10 17 atoms / cm 3 Hereinafter.

[0537] In addition, hydrogen contained in the oxide semiconductor reacts with oxygen bonded to metal atoms to generate water, so oxygen vacancies are sometimes formed. When hydrogen enters the oxygen vacancies, electrons serving as carriers are sometimes generated. In addition, sometimes electrons serving as carriers are generated because a part of hydrogen bonds with oxygen bonded to metal atoms. Therefore, a transistor using an oxide semiconductor containing hydrogen easily has normally-on characteristics. Thus, it is preferable to reduce hydrogen in the channel formation region of the oxide semiconductor as much as possible. Specifically, the hydrogen concentration in the channel formation region of the oxide semiconductor measured by SIMS is set to be lower than 1×10 20 atoms / cm 3 , preferably lower than 5×10 19 atoms / cm 3 , more preferably lower than 1×10 19 atoms / cm 3 , further preferably lower than 5×10 18 atoms / cm 3 , still further preferably lower than 1×10 18 atoms / cm 3 , yet further preferably lower than 1×10 17 atoms / cm 3 .

[0538] In addition, when the oxide semiconductor contains an alkali metal or an alkaline earth metal, defect states are sometimes formed to generate carriers. Therefore, a transistor using an oxide semiconductor containing an alkali metal or an alkaline earth metal easily has normally-on characteristics. Thus, the concentration of the alkali metal or alkaline earth metal in the channel formation region of the oxide semiconductor measured by SIMS is set to 1×10 18 atoms / cm 3 Hereinafter, preferably 2×10 16 atoms / cm 3 Hereinafter.

[0539] By using an oxide semiconductor with sufficiently reduced impurities for the channel formation region of the transistor, the transistor can have stable electrical characteristics.

[0540] This embodiment can be appropriately combined with other embodiments. In addition, in this specification, when a plurality of structural examples are shown in one embodiment, the structural examples can be appropriately combined.

[0541] Embodiment 3

[0542] In this embodiment, an example of the operation method of a storage device according to one aspect of the present invention will be described. The storage cell shown below may use the transistor including a ferroelectric body shown in Embodiment 1.

[0543] [Hysteresis Characteristics of Ferroelectric Body]

[0544] A ferroelectric body has hysteresis characteristics. Figure 18 FIG. is an example showing the hysteresis characteristics of a ferroelectric body. The hysteresis characteristics can be measured by using a capacitor including a ferroelectric body (ferroelectric capacitor). In Figure 18 , the horizontal axis represents the voltage (electric field) applied to the ferroelectric body. This voltage is the potential difference between one electrode and the other electrode of the ferroelectric capacitor. In addition, the electric field strength can be obtained by dividing this potential difference by the thickness of the ferroelectric body.

[0545] In Figure 18 , the vertical axis represents the polarization of the ferroelectric body. When the polarization is positive, the positive charges in the ferroelectric body are biased toward one electrode side of the capacitor, and the negative charges are biased toward the other electrode side of the capacitor. On the other hand, when the polarization is negative, the negative charges in the ferroelectric body are biased toward one electrode side of the capacitor, and the positive charges are biased toward the other electrode side of the capacitor.

[0546] In addition, Figure 18 the polarization shown on the vertical axis of the graph of can also be positive when the negative charges are biased toward one electrode side of the capacitor and the positive charges are biased toward the other electrode side of the capacitor, and can also be negative when the positive charges are biased toward one electrode side of the capacitor and the negative charges are biased toward the other electrode side of the capacitor.

[0547] As Figure 18 shown, the hysteresis characteristics of the ferroelectric body can be represented by curve 651 and curve 652. The voltages at the intersection points of curve 651 and curve 652 are referred to as the saturation polarization voltage +VSP (also referred to as “+VSP”) and the saturation polarization voltage -VSP (also referred to as “-VSP”). It can be said that the polarities of +VSP and -VSP are different.

[0548] When the voltage applied to the ferroelectric body is increased after applying a voltage of -VSP or less to the ferroelectric body, the polarization of the ferroelectric body increases according to curve 651. On the other hand, when the voltage applied to the ferroelectric body is decreased after applying a voltage of +VSP or more to the ferroelectric body, the polarization of the ferroelectric body decreases according to curve 652. Note that +VSP is sometimes referred to as “positive saturation polarization voltage” or “first saturation polarization voltage”. In addition, -VSP is sometimes referred to as “negative saturation polarization voltage” or “second saturation polarization voltage”. The absolute value of the first saturation polarization voltage and the absolute value of the second saturation polarization voltage may be the same or different.

[0549] The voltage at which the polarization of the ferroelectric is 0 when the polarization of the ferroelectric changes according to curve 651 is referred to as the coercive voltage +Vc. In addition, the voltage at which the polarization of the ferroelectric is 0 when the polarization of the ferroelectric changes according to curve 652 is referred to as the coercive voltage -Vc. The values of +Vc and -Vc are values between +VSP and -VSP. Note that sometimes +Vc is referred to as the "positive coercive voltage" or the "first coercive voltage" and -Vc is referred to as the "negative coercive voltage" or the "second coercive voltage". The absolute value of the first coercive voltage and the absolute value of the second coercive voltage may be the same or different.

[0550] In addition, the maximum value of the polarization when no voltage is applied to the ferroelectric (when the voltage is 0 V) is referred to as the "remnant polarization +Pr" or the "remnant polarization Pr1", and the minimum value is referred to as the "remnant polarization -Pr" or the "remnant polarization Pr2". In addition, the absolute value of the difference between the remnant polarization +Pr and the remnant polarization -Pr is referred to as the "remnant polarization 2Pr". The larger the remnant polarization 2Pr, the larger the variation range of the capacitance value of the ferroelectric capacitor caused by polarization reversal. Therefore, the larger the remnant polarization 2Pr, the better.

[0551] [Relationship between the polarization of the ferroelectric and the Id-Vg characteristics]

[0552] Next, a structure in which a capacitor including a ferroelectric is provided for the transistor will be described. Hereinafter, the relationship between the polarization of the ferroelectric included in the capacitor 620 and the Id-Vg characteristics of the transistor 610 will be described.

[0553] Figure 19A and Figure 19B are equivalent circuit diagrams of the semiconductor device 600 including the transistor 610 and the capacitor 620 as a ferroelectric capacitor. The capacitor 620 includes an electrode 663 that also serves as the gate of the transistor 610, an electrode 668 connected to the wiring WL, and an insulating layer 667 therebetween. The transistor 610 includes an electrode 663, an electrode 660 connected to the wiring BL, and an electrode 655 connected to the wiring SL. The electrode 660 is used as one of the source electrode and the drain electrode, and the electrode 655 is used as the other of the source electrode and the drain electrode. The insulating layer 667 is used as a ferroelectric layer. Figure 19A and Figure 19B schematically show the polarization of the insulating layer 667. In addition, the electrode 663 may also be referred to as the node FN.

[0554] The semiconductor device 600 corresponds to the semiconductor device including the insulator 250 and the conductor 252 shown in Embodiment 1 Figure 3E shown, and the insulating layer 667 of the capacitor 620 corresponds to Figure 3E the insulator 250d2 shown. Note that the structure in which the gate of the transistor 610 is connected to the capacitor 620 as a ferroelectric capacitor will be described below, but the present invention is not limited thereto. As Figure 19CAs shown, a structure can also be adopted in which the capacitor 620 is not provided in the semiconductor device 600 and the insulating layer 667 serving as a ferroelectric body is provided as the gate insulating layer of the transistor 610 (which can also be referred to as a FeFET). Here, the electrode 663 of the transistor 610 is connected to the wiring WL. Figure 19C The semiconductor device 600 shown corresponds to the transistor 200 provided with the insulator 250 of the first embodiment. Figures 3A to 3D Below, the operating principle and method shown below can also be applied to Figure 19C the semiconductor device 600 shown.

[0555] Figure 19D It is a diagram for explaining the Id-Vg characteristics of the transistor 610 when the voltage between the source and the drain (also referred to as "drain voltage" or "Vd") is constant. Figure 19D The horizontal axis represents the voltage between the source and the gate (also referred to as "gate voltage" or "Vg"), and the vertical axis represents the current flowing between the source and the drain (also referred to as "drain current" or "Id").

[0556] In Figure 19D , the characteristic 690 shows the Id-Vg characteristics of the transistor 610 when no polarization occurs in the insulating layer 667 constituting the capacitor 620.

[0557] In Figure 19D , the characteristic 691 shows the Id-Vg characteristics when the polarization of the insulating layer 667 is the remanent polarization Pr1. In addition, Figure 19A is a schematic diagram showing the polarization of the insulating layer 667 constituting the capacitor 620 in the characteristic 691.

[0558] Since the remanent polarization Pr1 is positive polarization, a positive voltage is generated at the node FN. Therefore, the Id-Vg characteristic of the characteristic 690 drifts toward the negative side of Vg to become the characteristic 691. That is, the threshold voltage of the transistor 610 drifts toward the negative side of Vg.

[0559] In Figure 19D , the characteristic 692 shows the Id-Vg characteristics when the polarization of the insulating layer 667 is the remanent polarization Pr2. In addition, Figure 19B is a schematic diagram showing the polarization of the insulating layer 667 constituting the capacitor 620 in the characteristic 692.

[0560] Since the remanent polarization Pr2 is negative polarization, a negative voltage is generated at the node FN. Therefore, the Id-Vg characteristic of the characteristic 690 drifts toward the positive side of Vg to become the characteristic 692. That is, the threshold voltage of the transistor 610 drifts toward the positive side of Vg.

[0561] As Figures 19A to 19CAs shown, the Id-Vg characteristics of the transistor 610 can be changed according to the polarization of the insulating layer 667 serving as the ferroelectric layer. In other words, by controlling the polarization of the insulating layer 667, the threshold voltage of the transistor 610 can be controlled. Therefore, the semiconductor device 600 including the transistor 610 and the capacitor 620 can be used as a memory cell capable of holding binary data.

[0562] For example, in the case of writing binary data of "0" or "1" to the semiconductor device 600 serving as a memory cell, when writing data "1", the polarization of the insulating layer 667 is set to the remanent polarization Pr1, and when writing data "0", the polarization of the insulating layer 667 is set to the remanent polarization Pr2. The Id-Vg characteristics of the semiconductor device 600 written with data "1" become characteristic 691. In addition, the Id-Vg characteristics of the semiconductor device 600 written with data "0" become characteristic 692.

[0563] Next, the erase operation, write operation, hold operation, and read operation of the semiconductor device 600 will be described.

[0564] <Erase operation>

[0565] Before writing data to the semiconductor device 600 serving as a memory cell, it is necessary to erase the data. In the present embodiment, as the erase operation, an operation of writing data "0" to the semiconductor device 600 is performed. In other words, the polarization of the insulating layer 667 is set to the remanent polarization Pr2.

[0566] Figure 20A is a timing chart for explaining the erase operation. Figure 20B is a circuit diagram showing the state of the semiconductor device 600 during the period T11. Note that in circuit diagrams and the like, in order to easily understand the potential of wirings and the like, symbols indicating the potential of the wiring are sometimes attached adjacent to the wiring and the like. In addition, symbols indicating the potential are sometimes described in a framed form for wirings and the like where potential changes occur.

[0567] During the period T11, a potential L is supplied to the wiring WL, and potentials H are supplied to the wiring BL and the wiring SL.

[0568] In addition, between the wiring WL and the wiring BL and between the wiring WL and the wiring SL, the gate capacitance of the transistor 610 is connected in series with the capacitor 620. The voltage applied to the capacitor 620 depends on the capacitance ratio between the gate capacitance of the transistor 610 and the capacitor 620. In the present embodiment, the capacitance ratio between the gate capacitance of the transistor 610 and the capacitor 620 is 1:1. Therefore, the potential difference between the potential H and the potential L is more than twice the absolute value of VSP. In addition, in order to make the polarization of the insulating layer 667 the remanent polarization Pr2, the potential H is supplied to the wiring BL and the wiring SL, and the potential L is supplied to the wiring WL. The potential H is higher than the potential L.

[0569] For example, when the potential COM is the reference potential (0V), the potential H may be a potential higher than the potential COM and the potential difference between the potential H and the potential COM is the potential of +VSP. Similarly, the potential L may be a potential lower than the potential COM and the potential difference between the potential L and the potential COM is the potential of -VSP.

[0570] Under the above conditions, the potential L is supplied to the wiring WL, and the potential H is supplied to the wiring BL and the wiring SL, whereby -VSP is applied to the capacitor 620. Next, during the period T12, 0V is supplied to the wiring WL, the wiring BL, and the wiring SL. That is, the wiring WL, the wiring BL, and the wiring SL are made to have the same potential.

[0571] During the period T12, the polarization of the insulating layer 667 becomes the remanent polarization Pr2 (refer to Figure 18 ). As described above, since the remanent polarization Pr2 is a negative polarization, a negative voltage is generated at the node FN. Therefore, the Id-Vg characteristic of the characteristic 690 drifts in the positive direction of Vg to become the characteristic 692. That is, the threshold voltage of the transistor 610 drifts in the positive direction of Vg (refer to Figure 19D ).

[0572] During the period T13, the potential RL is supplied to the wiring WL. The potential RL will be described in detail in the description of maintaining the operation. Note that the period T12 may be omitted, and the period T13 may be performed after the period T11. By passing through the period T11, even if the period T12 is omitted, a negative voltage is generated at the node FN.

[0573] <Writing operation>

[0574] Next, the operation of writing the data "1" to the semiconductor device 600 used as a storage cell will be described. Figure 21A is a timing chart for explaining the writing operation. Figure 21B is a circuit diagram showing the state of the semiconductor device 600 during the period T21.

[0575] After the erasing operation is performed during period T11, during period T21, a potential H is supplied to the wiring WL, and potentials L are supplied to the wiring BL and the wiring SL. As a result, +VSP is applied to the capacitor 620, and the polarization of the insulating layer 667 changes along the curve 651 (see Figure 18 ). Next, during period T22, 0 V is supplied to the wiring WL, the wiring BL, and the wiring SL. That is, the wiring WL, the wiring BL, and the wiring SL are made to have the same potential.

[0576] During period T22, the polarization of the insulating layer 667 becomes the remanent polarization Pr1 (see Figure 18 ). As described above, since the remanent polarization Pr1 is a positive polarization, a positive voltage is generated in the node FN. Therefore, the Id-Vg characteristic of the characteristic 690 drifts in the negative direction of Vg to become the characteristic 691. In other words, the threshold voltage of the transistor 610 drifts in the negative direction of Vg (see Figure 19D ).

[0577] In this way, data "1" can be written to the semiconductor device 600. In addition, since the capacitor 620 is a ferroelectric capacitor, the insulating layer 667 as a ferroelectric body maintains polarization even when the supply of power to the semiconductor device 600 is stopped. Therefore, even when the supply of power to the semiconductor device 600 is stopped, the data written to the semiconductor device 600 is retained. Therefore, the semiconductor device 600 serves as a non-volatile memory cell.

[0578] The operation of writing data "0" to the semiconductor device 600 is the same as the above-described erasing operation. Therefore, there is no need to perform the operation of writing data "0" after the erasing operation.

[0579] <Retention Operation>

[0580] After data is written to the semiconductor device 600, during period T23, a potential RL is supplied to the wiring WL. The potential RL is a potential that keeps the transistor 610 in the off state even when the Id-Vg characteristic of the transistor 610 is the characteristic 691 (see Figure 19D ). Therefore, the potential RL only needs to be a potential lower than the threshold voltage of the characteristic 691. In addition, in order not to easily cause a change in the polarization of the insulating layer 667, the potential RL is set to a voltage equal to or higher than the coercive voltage -Vc of the voltage applied to the capacitor 620.

[0581] Preferably, the potential of the wiring WL is the potential RL from the end of the writing operation until the reading operation is performed. By setting the potential of the wiring WL to the potential RL, the transistor 610 is surely turned off, whereby the power consumption of the semiconductor device 600 is reduced. In addition, when the semiconductor devices 600 are arranged in a matrix to form a memory cell array, interference with the reading operations of other memory cells (semiconductor devices 600) can be prevented. Therefore, the reliability of a memory device including the memory cell array can be improved.

[0582] Note that the period T22 may be omitted, and the period T23 may be performed after the period T21.

[0583] <Reading operation>

[0584] Next, the reading operation of the data held by the semiconductor device 600 used as a memory cell will be described. Figure 22A This is a timing chart for explaining the reading operation. Figure 22B This is a circuit diagram showing the state of the semiconductor device 600 during the period T31.

[0585] In the present embodiment, the reading operation of the semiconductor device 600 holding the data "1" will be described.

[0586] During the period T31, the potential H is pre-charged to the wiring BL. That is, after the potential of the wiring BL is set to the potential H, the wiring BL is made to be in a floating state (a state where there is no power supply from anywhere). In addition, the potential COM is supplied to the wiring SL.

[0587] Next, during the period T32, the potential RH as a reading potential is supplied to the wiring WL. The potential RH is a potential that is equal to or higher than the threshold voltage of the characteristic 691 and lower than the threshold voltage of the characteristic 692. In addition, in order not to easily cause polarization changes in the insulating layer 667, the potential RH is set to a voltage such that the voltage applied to the capacitor 620 becomes equal to or lower than the coercive voltage +Vc.

[0588] When the data "1" is held in the semiconductor device 600, the transistor 610 is turned on when the potential RH is supplied to the wiring WL, and the current Id1 flows between the source and the drain (refer to Figure 19D ). Therefore, the wiring BL and the wiring SL are in a conducting state, and the potential of the floating wiring BL changes to the potential COM.

[0589] When the potential of the wiring BL changes after the potential RH is supplied to the wiring WL, it can be determined that the data "1" is written to the semiconductor device 600. In addition, when it is determined that the potential of the wiring BL does not change even when the potential RH is supplied to the wiring WL, it can be determined that the data "0" is written to the semiconductor device 600.

[0590] After the read operation is completed, the potential RL is supplied to the wiring WL during the period T33. By setting the potential RH to a voltage equal to or lower than the coercive voltage +Vc of the voltage applied to the capacitor 620, the polarization of the insulating layer 667 constituting the capacitor 620 is not easily changed. Therefore, non-destructive reading of the semiconductor device 600 can be achieved.

[0591] Note that the hysteresis characteristics of the ferroelectric material vary depending on the material, structure, and manufacturing method. Therefore, the potential RH is preferably a voltage such that the voltage applied to the capacitor 620 reaches 0.8 times or less, more preferably 0.6 times or less, of the coercive voltage +Vc. In addition, the potential RL is preferably a voltage such that the voltage applied to the capacitor 620 reaches 0.8 times or more, more preferably 0.6 times or more, of the coercive voltage -Vc.

[0592] The above is the description of the operation method of the storage device.

[0593] At least a part of this embodiment can be implemented in appropriate combination with other embodiments described in this specification.

[0594] Embodiment 4

[0595] In this embodiment, a semiconductor device 900 according to one aspect of the present invention is described. The semiconductor device 900 can be used as a storage device.

[0596] Figure 23 A block diagram showing a structural example of the semiconductor device 900. Figure 23 The semiconductor device 900 shown includes a drive circuit 910 and a memory array 920. The memory array 920 includes one or more memory cells 950. Figure 23 An example is shown in which the memory array 920 includes a plurality of memory cells 950 arranged in a matrix.

[0597] The transistor shown in Embodiment 1 can be used for the memory cell 950. By using the above transistor, the operating speed of the storage device can be improved. In addition, miniaturization and high integration of the storage device can be achieved. Furthermore, the capacity per unit area of the storage device can be increased.

[0598] The drive circuit 910 includes a PSW931 (power switch), a PSW932, and a peripheral circuit 915. The peripheral circuit 915 includes a peripheral circuit 911, a control circuit 912 (Control Circuit), and a voltage generation circuit 928.

[0599] In the semiconductor device 900, each circuit, each signal, and each voltage can be appropriately selected or discarded as needed. Alternatively, other circuits or other signals can also be added. The signals BW, CE, GW, CLK, WAKE, ADDR, WDA, PON1, and PON2 are signals input from the outside, and the signal RDA is a signal output to the outside. The signal CLK is a clock signal.

[0600] In addition, the signals BW, CE, and GW are control signals. The signal CE is a chip enable signal, the signal GW is a global write enable signal, and the signal BW is a byte write enable signal. The signal ADDR is an address signal. The signal WDA is write data, and the signal RDA is read data. The signals PON1 and PON2 are signals for power gating control. In addition, the signals PON1 and PON2 can also be generated in the control circuit 912.

[0601] The control circuit 912 is a logic circuit having a function of controlling the overall operation of the semiconductor device 900. For example, the control circuit 912 performs a logical operation on the signals CE, GW, and BW to determine the operation mode of the semiconductor device 900 (e.g., write operation, read operation). Alternatively, the control circuit 912 generates a control signal for the peripheral circuit 91...

Claims

1. A semiconductor device, comprising: an oxide semiconductor; a first conductor and a second conductor separated from each other on the oxide semiconductor; a first insulator on the first conductor and the second conductor, the first insulator having an opening overlapping a region between the first conductor and the second conductor; a second insulator in the opening, the second insulator being in contact with a top surface of the oxide semiconductor; and a third conductor on the second insulator in the opening, the third conductor having a region overlapping the oxide semiconductor with the second insulator therebetween, wherein the oxide semiconductor includes a first layer, a second layer on the first layer, and a third layer on the second layer in a region overlapping the third conductor, the first layer contains gallium and oxygen, the second layer contains indium oxide, the third layer contains indium, gallium and oxygen, and an indium content rate of the second layer is higher than an indium content rate of the third layer.

2. The semiconductor device according to claim 1, wherein a bottom of a conduction band of the first layer is closer to a vacuum level than a bottom of a conduction band of the second layer, and a bottom of the conduction band of the third layer is closer to the vacuum level than the bottom of the conduction band of the second layer.

3. The semiconductor device according to claim 1, wherein the first layer contains indium, and an indium content rate in the first layer is lower than a gallium content rate.

4. The semiconductor device according to claim 1, wherein when viewed in plan, a side surface of a part of the first insulator is aligned or substantially aligned with a side surface of the first conductor and a side surface of the second conductor.

5. The semiconductor device according to claim 1, further comprising: a third insulator in contact with a top surface of the third conductor, an upper end portion of the second insulator, and a top surface of the first insulator; and a fourth insulator in contact with a top surface of the third insulator.

6. The semiconductor device according to claim 5, wherein the third insulator contains aluminum oxide.

7. The semiconductor device according to claim 6, wherein the fourth insulator contains silicon nitride.

8. The semiconductor device according to claim 1, wherein both the first conductor and the second conductor include a first conductive layer and a second conductive layer on the first conductive layer, a shortest distance between the first conductive layer of the first conductor and the first conductive layer of the second conductor is smaller than a shortest distance between the second conductive layer of the first conductor and the second conductive layer of the second conductor.

9. The semiconductor device according to claim 8, wherein when viewed in plan, a side surface of a part of the first insulator is aligned or substantially aligned with a side surface of the second conductive layer of the first conductor and a side surface of the second conductive layer of the second conductor.

10. The semiconductor device according to claim 8, wherein the first conductive layer of the first conductor and the first conductive layer of the second conductor both contain tantalum nitride.

11. The semiconductor device according to claim 8, further comprising: a fifth insulator, Wherein the fifth insulator is in the opening and contacts the top surface of the first conductive layer of the first conductor, the side surface of the second conductive layer of the first conductor, the top surface of the first conductive layer of the second conductor, and the side surface of the second conductive layer of the second conductor. And the fifth insulator has an opening overlapping with the region between the first conductive layer of the first conductor and the first conductive layer of the second conductor.

12. The semiconductor device according to claim 11, Wherein the fifth insulator comprises silicon nitride.

13. The semiconductor device according to claim 1, Wherein the second insulator includes a first insulating layer, And the first insulating layer contains an oxide containing hafnium.

14. The semiconductor device according to claim 13, Wherein the first insulating layer comprises hafnium zirconium oxide.

15. The semiconductor device according to claim 14, Wherein the second insulator includes a second insulating layer on the first insulating layer, and the second insulating layer comprises silicon nitride.

16. The semiconductor device according to claim 14, Wherein the top surface of the first insulating layer contacts the third conductor.

17. The semiconductor device according to claim 1, Wherein the first layer and the second layer have crystallinity.

18. A storage device including the semiconductor device according to claim 1.

19. A display device including the semiconductor device according to claim 1.

20. An electronic device including the semiconductor device according to claim 1.

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