Preparation method of semiconductor structure, semiconductor structure, device and electronic equipment

Abstract

The invention provides a preparation method of a semiconductor structure, the semiconductor structure, a device and electronic equipment, and the method comprises the steps: forming an active structure on a substrate, and the active structure comprises a first active structure and a second active structure; forming a first transistor based on the first active structure; reversing the wafer and thinning the substrate; forming a second transistor based on the second active structure; the first transistor and the second transistor are stacked in a first direction; wherein a first dipole layer is arranged between a first gate dielectric layer of the first transistor and a first gate structure of the first transistor, and / or a second dipole layer is arranged between a second gate dielectric layer of the second transistor and a second gate structure of the second transistor; the first dipole layer is made of a first semiconductor material, and the second dipole layer is made of a second semiconductor material. According to the invention, the threshold voltage of the semiconductor structure can be flexibly adjusted.

Description

Technical Field

[0001] This application relates to the field of semiconductors, and particularly to a method for manufacturing a semiconductor structure, a semiconductor structure, a device, and an electronic device. Background Art

[0002] At present, with the continuous deepening of Moore's Law, after the gate all around (GAA) technology node, continuously promoting the miniaturization of transistor size is a hot issue in the current industry research and development. Stacked transistors can achieve the integration of two or more layers of transistors in the vertical space through the stacking of three-dimensional transistors, which helps to further improve the transistor integration density and circuit performance, and is considered to be one of the important technologies to continue the miniaturization of integrated circuit size.

[0003] Currently, how to solve the threshold voltage of stacked transistors is still an urgent problem to be solved. Summary of the Invention

[0004] This application provides a method for manufacturing a semiconductor structure, a semiconductor structure, a device, and an electronic device to flexibly adjust the threshold voltage of the semiconductor structure.

[0005] In a first aspect, an embodiment of this application provides a method for manufacturing a semiconductor structure, the method including: forming an active structure on a substrate, the active structure including a first active structure and a second active structure; forming a first transistor based on the first active structure; flipping the wafer and thinning the substrate; forming a second transistor based on the second active structure; the first transistor and the second transistor are stacked in a first direction; wherein, a first dipole layer is disposed between a first gate dielectric layer of the first transistor and a first gate structure of the first transistor, and / or, a second dipole layer is disposed between a second gate dielectric layer of the second transistor and a second gate structure of the second transistor; the first dipole layer is formed of a first semiconductor material, and the second dipole layer is formed of a second semiconductor material.

[0006] In some possible implementation manners, forming a first transistor based on the first active structure includes: depositing a semiconductor material in a first gate region and a second gate region to form a first dummy gate structure of the first transistor and a second dummy gate structure of the second transistor; the first dummy gate structure and the second dummy gate structure are formed in the same deposition process; forming a second transistor based on the second active structure includes: removing the first dummy gate structure and the second dummy gate structure to form a first groove; depositing a metal material in the first groove to form a first gate structure of the first transistor and a second gate structure of the second transistor; the first gate structure and the second gate structure are formed in the same deposition process.

[0007] In some possible embodiments, after removing the first pseudo-gate structure and the second pseudo-gate structure to form a first groove, the above method further includes: depositing an insulating material on the surfaces of the first active structure and the second active structure located in the first gate region and the second gate region to form a first gate dielectric layer and a second gate dielectric layer; depositing a first semiconductor material on the surfaces of the first gate dielectric layer and the second gate dielectric layer; depositing an insulating material with a preset height in the first groove to form a first isolation structure; the first isolation structure wrapping the first gate dielectric layer; removing the first semiconductor material on the surface of the second gate dielectric layer to form a first dipole layer and expose the second gate dielectric layer; depositing a second semiconductor material on the surface of the second gate dielectric layer to form a second dipole layer.

[0008] In some possible embodiments, after removing the first pseudo-gate structure and the second pseudo-gate structure to form a first groove, the above method further includes: depositing an insulating material on the surfaces of the first active structure and the second active structure located in the first gate region and the second gate region to form a first gate dielectric layer and a second gate dielectric layer; depositing an insulating material with a preset height in the first groove to form a second isolation structure; the second isolation structure wrapping the first gate dielectric layer; depositing a second semiconductor material on the surface of the second gate dielectric layer to form a second dipole layer; removing the second isolation structure to expose the first gate dielectric layer; depositing a first semiconductor material on the surfaces of the first gate dielectric layer and the second dipole layer to form a first dipole layer; the first semiconductor material located outside the second dipole layer is isolated from the second active structure under the action of the second dipole layer.

[0009] In some possible embodiments, when the first dipole layer is not provided in the first transistor and the second dipole layer is provided in the second transistor; after removing the first pseudo-gate structure and the second pseudo-gate structure to form a first groove, the above method further includes: depositing an insulating material on the surfaces of the first active structure in the first gate region and the second active structure in the second gate region to form a first gate dielectric layer and a second gate dielectric layer; depositing an insulating material with a preset height in the first groove to form a third isolation structure; the third isolation structure wrapping the first gate dielectric layer; depositing a second semiconductor material on the surface of the second gate dielectric layer to form a second dipole layer; removing the third isolation structure to expose the first gate dielectric layer; coating a photoresist in the first groove to form a first mask structure; depositing a first semiconductor material on the first mask structure; removing the first mask structure and the first semiconductor material.

[0010] In some possible embodiments, when a first dipole layer is disposed in the first transistor and no second dipole layer is disposed in the second transistor; after removing the first dummy gate structure and the second dummy gate structure to form a first groove, the method further includes: depositing an insulating material on the surfaces of the first active structure in the first gate region and the second active structure in the second gate region to form a first gate dielectric layer and a second gate dielectric layer; depositing an insulating material with a preset height in the first groove to form a fourth isolation structure; the fourth isolation structure wraps the first gate dielectric layer; depositing a photoresist on the fourth isolation structure in the first groove to form a second mask structure; the second mask structure wraps the second gate dielectric layer; depositing a second semiconductor material on the second mask structure; removing the second mask structure and the second semiconductor material to expose the second gate dielectric layer; growing a work function metal on the surface of the second gate dielectric layer to form a second work function metal layer; removing the fourth isolation structure to expose the first gate dielectric layer; depositing a first semiconductor material on the surfaces of the first gate dielectric layer and the second work function metal layer to form a first dipole layer; wherein the first semiconductor material located on the surface of the second work function metal layer is isolated from the second active structure under the action of the second work function metal layer.

[0011] In some possible embodiments, forming the first transistor based on the first active structure includes: depositing a semiconductor material in the first gate region and the second gate region to form a first dummy gate structure of the first transistor and a second dummy gate structure of the second transistor; the first dummy gate structure and the second dummy gate structure are formed in the same deposition process; removing the first dummy gate structure to expose the first gate region; depositing an insulating material on the surface of the first active structure in the first gate region to form a first gate dielectric layer; depositing a metal material in the first gate region to form a first gate structure; forming the second transistor based on the second active structure includes: removing the second dummy gate structure to expose the second gate region; depositing an insulating material with a preset height on the first gate structure to form a gate isolation structure; the gate isolation structure is used to isolate the first gate structure and the second gate structure; depositing an insulating material on the surface of the second active structure in the second gate region to form a second gate dielectric layer; depositing a metal material in the second gate region to form a second gate structure.

[0012] In some possible embodiments, after forming the first gate dielectric layer, the method further includes: depositing a first semiconductor material on the surface of the first gate dielectric layer to form a first dipole layer; after forming the second gate dielectric layer, the method further includes: depositing a second semiconductor material on the surface of the second gate dielectric layer to form a second dipole layer.

[0013] In some possible embodiments, when the first dipole layer is not provided in the first transistor and the second dipole layer is provided in the second transistor; after forming the first gate dielectric layer, the method further includes: coating a photoresist in the first gate region to form a third mask structure; the third mask structure wraps the first gate dielectric layer; depositing a first semiconductor material on the third mask structure; removing the third mask structure and the first semiconductor material; after forming the second gate dielectric layer, the method further includes: depositing a second semiconductor material on the surface of the second gate dielectric layer to form a second dipole layer.

[0014] In some possible embodiments, when the first dipole layer is provided in the first transistor and the second dipole layer is not provided in the second transistor; after forming the first gate dielectric layer, the method further includes: depositing a first semiconductor material on the surface of the first gate dielectric layer to form a first dipole layer; after forming the second gate dielectric layer, the above method further includes: coating a photoresist in the second gate region to form a fourth mask structure; the fourth mask structure wraps the second gate dielectric layer; depositing a second semiconductor material on the fourth mask structure; removing the fourth mask structure and the second semiconductor material.

[0015] In some possible embodiments, forming a first transistor based on a first active structure includes: etching the active structure located in the first source / drain region of the first transistor and the second source / drain region of the second transistor to form a second groove; depositing an insulating material with a preset height in the second groove to form a source / drain filling structure; the source / drain filling structure fills the second source / drain region; growing source / drain epitaxy in the first source / drain region to form a first source / drain structure; forming a first source / drain metal on the first source / drain structure.

[0016] In some possible embodiments, forming a second transistor based on a second active structure includes: removing the source / drain filling structure to expose the second source / drain region; growing source / drain epitaxy in the second source / drain region to form a second source / drain structure; forming a second source / drain metal on the second source / drain structure.

[0017] In a second aspect, an embodiment of the present application provides a semiconductor structure, which is prepared by using the method described in the first aspect. The semiconductor structure includes: a first transistor; a second transistor; the first transistor and the second transistor are stacked in a first direction; wherein, a first dipole layer is provided between the first gate dielectric layer and the first gate structure of the first transistor, and / or, a second dipole layer is provided between the second gate dielectric layer and the second gate structure of the second transistor; the first dipole layer is formed of a first semiconductor material, and the second dipole layer is formed of a second semiconductor material.

[0018] In a third aspect, an embodiment of the present application provides a semiconductor device, which includes a semiconductor structure as described in the above embodiment.

[0019] In a fourth aspect, an embodiment of the present application provides an electronic device, which includes a circuit board and a semiconductor device as described in the above embodiment, and the semiconductor device is disposed on the circuit board.

[0020] In the present application, according to the actual situation, a first dipole layer can be selectively provided or not provided in the first transistor, and a second dipole layer can be selectively provided or not provided in the second transistor. In this way, the threshold voltages of the first transistor and the second transistor can be adjusted separately and flexibly.

[0021] Furthermore, the manufacturing method of the semiconductor structure described in the present application is compatible with mainstream device architectures, and can realize front and back stacking including planar transistors, FinFETs, GAAFETs, and even vertical transistors (VTFETs) and CFETs, without the need for special process development for specific device architectures. It has strong flexibility, strong extensibility from the perspective of semiconductor process node iteration, important industrial value, strong practicability, and broad expansion prospects.

[0022] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The drawings herein are incorporated into the specification and form a part of the specification, showing embodiments consistent with the present application, and are used together with the specification to explain the principles of the present application.

[0024] Figure 1 It is a schematic flowchart of an implementation process of the manufacturing method of the semiconductor structure in the embodiment of the present application;

[0025] Figure 2 It is a first schematic structural diagram of the semiconductor structure in the embodiment of the present application;

[0026] Figures 3A to 3L It is a first schematic diagram of the manufacturing process of the semiconductor structure in the embodiment of the present application;

[0027] Figures 4A to 4C It is a second schematic diagram of the manufacturing process of the semiconductor structure in the embodiment of the present application;

[0028] Figures 5A to 5I It is a first schematic diagram of the manufacturing process of the semiconductor device in the embodiment of the present application;

[0029] Figure 6 It is a second schematic structural diagram of the semiconductor structure in the embodiment of the present application;

[0030] Figures 7A to 7H This is the third schematic diagram of the manufacturing process of the semiconductor structure in the embodiments of the present application;

[0031] Figures 8A to 8I This is the second schematic diagram of the manufacturing process of the semiconductor device in the embodiments of the present application;

[0032] In the above figures:

[0033] 10. Semiconductor structure; 11. First transistor; 111. First source / drain structure; 112. First interlayer dielectric layer; 113. First source / drain metal; 114. First dielectric layer; 115. First metal interconnect layer; 116. First gate dielectric layer; 117. First dipole layer; 119. First gate structure; 12. Second transistor; 121. Second source / drain structure; 122. Second interlayer dielectric layer; 123. Second source / drain metal; 124. Second dielectric layer; 125. Second metal interconnect layer; 126. Second gate dielectric layer; 127. Second dipole layer; 128. Second work function metal layer; 129. Second gate structure; 13. Insulating layer; 14. Carrier wafer; 21. Substrate; 211. First stack; 212. First sacrificial layer; 213. Second stack; 214. Second sacrificial layer; 215. Bottom substrate; 22. Active structure; 221. First active structure; 222. Second active structure; 23. Shallow trench isolation structure; 241. First dummy gate structure; 242. Second dummy gate structure; 25. Spacer; 26. First gap; 27. Intermediate dielectric isolation layer; 281. First inner sidewall; 282. Second inner sidewall; 29. Source / drain fill structure; 30. Source / drain isolation structure; 31. First isolation structure; 32. Gate cut-off structure; 33. Second isolation structure; 34. Gate isolation structure; 40. Isolation structure; 41. First photoresist layer; 42. Second photoresist layer; 43. Third photoresist layer; 44. Fourth photoresist layer. Detailed Description of the Embodiments

[0034] Here, exemplary embodiments will be described in detail, and examples are shown in the drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application.

[0035] In some embodiments, in a fully self-aligned flip-chip stacked transistor manufacturing scheme, the gate structures of the stacked transistors on the same wafer can only be a unified split-gate structure or a unified common-gate structure. On the one hand, this limits the design flexibility and further miniaturization of the chip area. On the other hand, this unified split-gate structure or unified common-gate structure makes it impossible to flexibly adjust the threshold voltage.

[0036] To solve the above technical problems, an embodiment of the present application provides a method for manufacturing a semiconductor structure to flexibly adjust the threshold voltage of the semiconductor structure.

[0037] In some possible implementation manners, the semiconductor structure includes: a first transistor; a second transistor; the first transistor and the second transistor are stacked in a first direction; wherein, a first dipole layer is disposed between a first gate dielectric layer of the first transistor and a first gate structure of the first transistor, and / or a second dipole layer is disposed between a second gate dielectric layer of the second transistor and a second gate structure of the second transistor; the first dipole layer is formed of a first semiconductor material, and the second dipole layer is formed of a second semiconductor material.

[0038] In an embodiment of the present disclosure, dipole layers (i.e., the first dipole layer and the second dipole layer) are introduced into the semiconductor structure. The dipole layers can effectively adjust the threshold voltage of the transistor by changing the electric field distribution between the gate dielectric layers (i.e., the first gate dielectric layer and the second gate dielectric layer) and the gate structures (i.e., the first gate structure and the second gate structure). By adjusting the threshold voltage, the dipole layers help reduce the leakage current of the transistor and static power consumption, so it can be adapted to low-power design scenarios.

[0039] In some embodiments, the setting of the first dipole layer and the second dipole layer in the embodiment of the present application can be the following three cases: 1. The first dipole layer is disposed in the first transistor, and the second dipole layer is disposed in the second transistor; 2. The first dipole layer is disposed in the first transistor, and the second dipole layer is not disposed in the second transistor; 3. The first dipole layer is not disposed in the first transistor, and the second dipole layer is disposed in the second transistor.

[0040] In some embodiments, the first semiconductor material forming the first dipole layer is different from the second semiconductor material forming the second dipole layer. The first semiconductor material can be lanthanum oxide (LAO x ) or other semiconductor materials, and the second semiconductor material can be aluminum oxide (Al2O x ) or other semiconductor materials. The dipole layers formed of different semiconductor materials can be selected according to actual requirements, providing diverse electrical characteristics, enhancing design flexibility, and adapting to different application scenarios. The embodiments of the present application do not make specific limitations on this.

[0041] In some embodiments, the polarities of the first transistor and the second transistor are different. For example, the first transistor is an N-type transistor and the second transistor is a P-type transistor; or, the first transistor is a P-type transistor and the second transistor is an N-type transistor.

[0042] In some embodiments, the first transistor and the second transistor can be any of the following types of transistors: fin field-effect transistor (FinFET), gate-all-around field-effect transistor (GAAFET), and planar metal-oxide-semiconductor field-effect transistor, or other types of transistors. The embodiments of the present application do not make specific limitations thereon.

[0043] Figure 1 This is a schematic flowchart of an implementation process of a method for manufacturing a semiconductor structure according to an embodiment of the present application. Refer to Figure 1 As shown, taking the first transistor and the second transistor as gate-all-around field-effect transistors as an example, the method for manufacturing the above semiconductor structure may include:

[0044] S101, form an active structure on the substrate. Wherein, the active structure includes a first active structure and a second active structure.

[0045] It can be understood that by patterning the substrate and etching the substrate, an active structure can be formed.

[0046] In some embodiments, taking the first transistor and the second transistor as gate-all-around field-effect transistors as an example, before the above S101, the manufacturing method may include: providing an original silicon (Si) substrate, and alternately stacking silicon germanium (SiGe) material and Si material on the original Si substrate to form a stack. The stack and the original Si substrate together form the substrate.

[0047] In some embodiments, in order to isolate the first transistor and the second transistor in subsequent manufacturing, a layer of semiconductor material may be stacked at the middle position of the substrate to form a sacrificial layer. During the process of manufacturing the semiconductor structure, the sacrificial layer can play a role in isolating the first transistor and the second transistor.

[0048] In some embodiments, the sacrificial layer can be formed of SiGe material. In order to distinguish it from the SiGe material in the stack during subsequent etching, a SiGe material with a higher Ge concentration can be used to prepare the sacrificial layer. That is, the stack uses SiGe1 material, and the sacrificial layer uses SiGe2 material, and the Ge concentration of the SiGe2 material is higher than that of the SiGe1 material.

[0049] S102, form the first transistor based on the first active structure.

[0050] It can be understood that other structures in the first transistor, such as the first source / drain structure, the first source / drain metal, the first interlayer dielectric layer, and the first back-end metal interconnect layer, etc., can be formed based on the first active structure. Meanwhile, according to a preset scheme, it can be selected to form the first dipole layer or not in the first transistor.

[0051] S103, flip the wafer and thin the substrate.

[0052] It can be understood that after the first transistor is formed, the first transistor can be flipped so that the substrate is placed upward. Then, the substrate is thinned until the second active structure is exposed.

[0053] In some embodiments, before the above S103, the preparation method may further include: depositing an insulating material (such as silicon oxide) on the first transistor to form an insulating layer, and bonding the insulating layer to the carrier wafer.

[0054] In the embodiments of the present application, the bonded carrier wafer can provide physical support for the flipped first transistor after flipping, effectively avoiding the situation that the first transistor is broken by external force during the preparation process of the second transistor.

[0055] S104, form a second transistor based on the second active structure. Among them, the first transistor and the second transistor are stacked in the first direction.

[0056] In some embodiments, other structures in the second transistor, such as the second source / drain structure, the second source / drain metal, the second interlayer dielectric layer, and the second back-end metal interconnect layer, etc., can be formed based on the second active structure. Meanwhile, according to a preset scheme, it can be selected to form the second dipole layer or not in the second transistor.

[0057] In some embodiments, a first dipole layer is provided between the first gate dielectric layer and the first gate structure of the first transistor, and / or a second dipole layer is provided between the second gate dielectric layer and the second gate structure of the second transistor; the first dipole layer is formed of a first semiconductor material, and the second dipole layer is formed of a second semiconductor material.

[0058] In some possible implementation manners, the above S102 may include: depositing semiconductor materials in a first gate region and a second gate region to form a first dummy gate structure of a first transistor and a second dummy gate structure of a second transistor; the first dummy gate structure and the second dummy gate structure are formed in the same deposition process; the above S104 may include: removing the first dummy gate structure and the second dummy gate structure to form a first groove; depositing a metal material in the first groove to form a first gate structure of the first transistor and a second gate structure of the second transistor; the first gate structure and the second gate structure are formed in the same deposition process.

[0059] In some embodiments, the semiconductor material for forming the first dummy gate structure and the second dummy gate structure may be polysilicon (poly Si), or may be designed as other semiconductor materials according to actual requirements, and the embodiments of the present application do not make specific limitations thereon.

[0060] In some embodiments, the first dummy gate structure and the second dummy gate structure are formed in the same deposition process, indicating that the first dummy gate structure and the second dummy gate structure are physically continuous and form an integral body, rather than two separate parts.

[0061] It can be understood that in the process of preparing a semiconductor structure, the first gate structure and the second gate structure can be prepared by the "common gate" method; that is, after flipping the wafer, the first gate structure and the second gate structure are prepared in the same process, the first gate structure and the second gate structure are formed in the same deposition process, and the first gate structure and the second gate structure are physically continuous and form an integral body, rather than two separate parts.

[0062] In some possible implementation manners, in the case of preparing the first gate structure and the second gate structure by the above "common gate" method, the first dipole layer and the second dipole layer can be prepared by the "etch-back" method. After removing the first dummy gate structure and the second dummy gate structure to form the first groove, the above method further includes: depositing an insulating material on the surfaces of a first active structure and a second active structure located in the first gate region and the second gate region to form a first gate dielectric layer and a second gate dielectric layer; depositing a first semiconductor material on the surfaces of the first gate dielectric layer and the second gate dielectric layer; depositing an insulating material with a preset height in the first groove to form a first isolation structure; the first isolation structure wraps the first gate dielectric layer; removing the first semiconductor material on the surface of the second gate dielectric layer to form the first dipole layer and expose the second gate dielectric layer; depositing a second semiconductor material on the surface of the second gate dielectric layer to form the second dipole layer.

[0063] It can be understood that by removing the first pseudo-gate structure and the second pseudo-gate structure formed in the same deposition process, the first gate region and the second gate region are exposed, and the first active structure located in the first gate region and the second active structure located in the second gate region are also exposed accordingly. According to the standard process for fabricating transistors, a first gate dielectric layer and a second gate dielectric layer are formed. During the process of forming the dipole layer, a first semiconductor material is first deposited on the surfaces of both the first gate dielectric layer and the second gate dielectric layer, and then the first semiconductor material located on the surface of the second gate dielectric layer is removed by back-etching, and a second dipole layer is fabricated based on the exposed second gate dielectric layer.

[0064] In some embodiments, after forming the first gate dielectric layer and the second gate dielectric layer, a first semiconductor material is deposited on the surfaces of both the first gate dielectric layer and the second gate dielectric layer simultaneously; the first semiconductor material on the surface of the first gate dielectric layer forms a first dipole layer; then, an insulating material is deposited in the first groove until the insulating material can wrap the first dipole layer, and the deposited insulating material is a first isolation structure, which can protect the first dipole layer from being etched in subsequent etching processes; then, through selective etching, the first semiconductor material on the surface of the second gate dielectric layer (i.e., back-etching) is removed, so that the second gate dielectric layer is exposed; a second semiconductor material is deposited on the surface of the second gate dielectric layer to form a second dipole layer.

[0065] In some possible implementation manners, in the case of fabricating the first gate structure and the second gate structure by the above-mentioned "common gate" method, the first dipole layer and the second dipole layer can be fabricated by the "blocking diffusion" method. After removing the first pseudo-gate structure and the second pseudo-gate structure to form the first groove, the above method further includes: depositing an insulating material on the surfaces of the first active structure and the second active structure located in the first gate region and the second gate region to form a first gate dielectric layer and a second gate dielectric layer; depositing an insulating material with a preset height in the first groove to form a second isolation structure; the second isolation structure wraps the first gate dielectric layer; depositing a second semiconductor material on the surface of the second gate dielectric layer to form a second dipole layer; removing the second isolation structure to expose the first gate dielectric layer; depositing a first semiconductor material on the surfaces of the first gate dielectric layer and the second dipole layer to form a first dipole layer; the first dipole layer located outside the second dipole layer is isolated from the second active structure under the action of the second dipole layer.

[0066] It can be understood that according to the standard process for fabricating a transistor, a first gate dielectric layer and a second gate dielectric layer are formed. First, under the protection of the second isolation structure, a second semiconductor material is deposited only on the surface of the second gate dielectric layer to form a second dipole layer; then, the second isolation structure is removed, and a first semiconductor material is deposited on the surfaces of the first gate dielectric layer and the second dipole layer to form a first dipole layer on the surface of the first gate dielectric layer; regarding the first semiconductor material on the surface of the second dipole layer, due to the blocking effect of the second dipole layer, it will not diffuse to the second gate dielectric layer, so that the first semiconductor material will not have an adjusting effect on the threshold voltage of the second transistor.

[0067] In some embodiments, after the first gate dielectric layer and the second gate dielectric layer are formed, an insulating material is deposited in the first groove until the insulating material can wrap the first gate dielectric layer. The deposited insulating material is the second isolation structure, and the second isolation structure can protect the surface of the first gate dielectric layer from being deposited with unnecessary semiconductor materials during subsequent deposition processes; a second semiconductor material is deposited on the exposed surface of the second gate dielectric layer to form a second dipole layer; then, the second isolation structure is removed to expose the first gate dielectric layer; a first semiconductor material is deposited on the surfaces of the second dipole layer and the first gate dielectric layer to form a first dipole layer. The first semiconductor material located outside the second dipole layer will not diffuse to the second gate dielectric layer.

[0068] In some embodiments, the first transistor and the second transistor form a stacked transistor. During the process of fabricating a semiconductor device according to a design layout, multiple stacked transistors can be fabricated simultaneously on the same substrate, and the designs of the dipole layers in these multiple stacked transistors can be different. For example, a semiconductor device includes stacked transistor A, stacked transistor B, stacked transistor C, and stacked transistor D. Among them, the first transistor in stacked transistor A is provided with a first dipole layer, and the second transistor is provided with a second dipole layer; the first transistor in stacked transistor B is not provided with a first dipole layer, and the second transistor is provided with a second dipole layer; the first transistor in stacked transistor C is provided with a first dipole layer, and the second transistor is not provided with a second dipole layer; the first transistor in stacked transistor D is not provided with a first dipole layer, and the second transistor is not provided with a second dipole layer. As described above, the designs of the dipole layers corresponding to different stacked transistors are also different, and different dipole layer settings can be achieved by photolithography. For example, before depositing the first semiconductor material to form the first dipole layer, photoresist can be coated in the first grooves of stacked transistor B and stacked transistor D to form a mask structure, while no photoresist is coated in the first grooves of stacked transistor A and stacked transistor C; then, when depositing the first semiconductor material, the transistors with the mask structure (i.e., stacked transistor B and stacked transistor D) will not form the first dipole layer under the masking effect of the mask structure; the transistors without the mask structure (stacked transistor A and stacked transistor C) will form the first dipole layer.

[0069] In some possible implementation manners, when using the "common gate" method to fabricate the first gate structure and the second gate structure, where the first transistor is not provided with the first dipole layer and the second transistor is provided with the second dipole layer; after removing the first pseudo-gate structure and the second pseudo-gate structure to form the first groove, the method may further include: depositing an insulating material on the surfaces of the first active structure in the first gate region and the second active structure in the second gate region to form a first gate dielectric layer and a second gate dielectric layer; depositing an insulating material with a preset height in the first groove to form a third isolation structure; the third isolation structure wraps the first gate dielectric layer; depositing a second semiconductor material on the surface of the second gate dielectric layer to form a second dipole layer; removing the third isolation structure to expose the first gate dielectric layer; coating photoresist in the first groove to form a first mask structure; depositing a first semiconductor material on the first mask structure; removing the first mask structure and the first semiconductor material.

[0070] It can be understood that, according to the standard process for fabricating a transistor, a first gate dielectric layer and a second gate dielectric layer are formed. Under the protection of the third isolation structure, a second semiconductor material is deposited only on the surface of the second gate dielectric layer to form a second dipole layer; a first dipole layer is not formed on the surface of the first gate dielectric layer. To avoid depositing the first semiconductor material on the surface of the first gate dielectric layer, before depositing the first semiconductor material, a photoresist can be coated in the first groove to form a first mask structure that wraps the second dipole layer and the first gate dielectric layer. Under the masking effect of the first mask structure, the first semiconductor material will be deposited on the first mask structure.

[0071] In some possible implementation manners, when the "common gate" method is used to fabricate the first gate structure and the second gate structure, with a first dipole layer provided in the first transistor and no second dipole layer provided in the second transistor; after removing the first dummy gate structure and the second dummy gate structure to form a first groove, the above method further includes: depositing an insulating material on the surfaces of a first active structure in the first gate region and a second active structure in the second gate region to form a first gate dielectric layer and a second gate dielectric layer; depositing an insulating material with a preset height in the first groove to form a fourth isolation structure; the fourth isolation structure wraps the first gate dielectric layer; depositing a photoresist on the fourth isolation structure in the first groove to form a second mask structure; the second mask structure wraps the second gate dielectric layer; depositing a second semiconductor material on the second mask structure; removing the second mask structure and the second semiconductor material to expose the second gate dielectric layer; growing a work function metal on the surface of the second gate dielectric layer to form a second work function metal layer; removing the fourth isolation structure to expose the first gate dielectric layer; depositing a first semiconductor material on the surfaces of the first gate dielectric layer and the second work function metal layer to form a first dipole layer; wherein the first semiconductor material located on the surface of the second work function metal layer is isolated from the second active structure under the action of the second work function metal layer.

[0072] It can be understood that, according to the standard process for fabricating a transistor, a first gate dielectric layer and a second gate dielectric layer are formed. An insulating material is deposited in the first groove until the insulating material can wrap the first gate dielectric layer, and the deposited insulating material is the fourth isolation structure; in order to prevent the surface of the second gate dielectric layer from being deposited with the second semiconductor material, before depositing the second semiconductor material, a photoresist can be coated in the first groove to form a second mask structure that wraps the second gate dielectric layer, and the second mask structure is located above the fourth isolation structure; under the masking effect of the second mask structure, the second semiconductor material will be deposited on the second mask structure; then, the second mask structure and the second semiconductor material are removed to expose the second gate dielectric layer; a work function metal is grown on the surface of the second gate dielectric layer to form a second work function metal layer; then, the fourth isolation structure is removed to expose the first gate dielectric layer; a first semiconductor material is deposited on the surfaces of the first gate dielectric layer and the second work function metal layer to form a first dipole layer. The first semiconductor material located on the surface of the second work function metal layer cannot diffuse to the second gate dielectric layer under the blocking effect of the second work function metal layer.

[0073] In some embodiments, a first work function metal layer can be provided in the first transistor and / or a second work function metal layer can be provided in the second transistor according to actual situations.

[0074] In the embodiments of the present disclosure, a work function metal layer is provided outside the dipole layer, and the work function characteristics of the work function metal layer and the electric field modulation effect of the dipole layer act synergistically to enable more precise threshold voltage control and meet the requirements of different circuit designs. Further, this dual adjustment mechanism (i.e., dipole layer + work function metal layer) provides higher design flexibility and can flexibly achieve multi-threshold voltage design to meet the requirements of different circuit modules.

[0075] In some possible implementation manners, the above S102 may include: depositing a semiconductor material in the first gate region and the second gate region to form a first pseudo-gate structure of the first transistor and a second pseudo-gate structure of the second transistor; the first pseudo-gate structure and the second pseudo-gate structure are formed in the same deposition process; the first pseudo-gate structure is removed to expose the first gate region; an insulating material is deposited on the surface of the first active structure located in the first gate region to form a first gate dielectric layer; a metal material is deposited in the first gate region to form a first gate structure. The above S104 may include: removing the second pseudo-gate structure to expose the second gate region; depositing an insulating material with a preset height on the first gate structure to form a gate isolation structure; the gate isolation structure is used to isolate the first gate structure and the second gate structure; an insulating material is deposited on the surface of the second active structure located in the second gate region to form a second gate dielectric layer; a metal material is deposited in the second gate region to form a second gate structure.

[0076] It can be understood that in the process of fabricating a semiconductor structure, the first gate structure and the second gate structure can be fabricated separately by the "split gate" method; that is, the first gate dielectric layer and the first gate structure are fabricated before wafer flipping, and the second gate dielectric layer and the second gate structure are fabricated after wafer flipping.

[0077] In some possible embodiments, in the case of fabricating the first gate structure and the second gate structure separately by the "split gate" method; after forming the first gate dielectric layer, the method further includes: depositing a first semiconductor material on the surface of the first gate dielectric layer to form a first dipole layer; after forming the second gate dielectric layer, the method further includes: depositing a second semiconductor material on the surface of the second gate dielectric layer to form a second dipole layer.

[0078] It can be understood that in the case of fabricating the first gate structure and the second gate structure separately by the "split gate" method, the first dipole layer and the second dipole layer can also be formed before and after wafer flipping, respectively.

[0079] In some possible embodiments, in the case of fabricating the first gate structure and the second gate structure separately by the "split gate" method, where the first dipole layer is not provided in the first transistor and the second dipole layer is provided in the second transistor; after forming the first gate dielectric layer, the method further includes: coating a photoresist in the first gate region to form a third mask structure; the third mask structure wraps the first gate dielectric layer; depositing a first semiconductor material on the third mask structure; removing the third mask structure and the first semiconductor material; after forming the second gate dielectric layer, the method further includes: depositing a second semiconductor material on the surface of the second gate dielectric layer to form a second dipole layer.

[0080] It can be understood that in order to prevent the surface of the first gate dielectric layer from being deposited with the first semiconductor material, a photoresist can be coated in the first gate region before depositing the first semiconductor material to form a third mask structure that wraps the first gate dielectric layer; under the masking effect of the third mask structure, the first semiconductor material will be deposited on the third mask structure; then, the third mask structure and the first semiconductor material can be removed by selective etching.

[0081] In some possible embodiments, when the first gate structure and the second gate structure are respectively prepared by the "split gate" method, a first dipole layer is provided in the first transistor, and no second dipole layer is provided in the second transistor; after forming the first gate dielectric layer, the method further includes: depositing a first semiconductor material on the surface of the first gate dielectric layer to form a first dipole layer; after forming the second gate dielectric layer, the method further includes: coating a photoresist in the second gate region to form a fourth mask structure; the fourth mask structure wraps the second gate dielectric layer; depositing a second semiconductor material on the fourth mask structure; removing the fourth mask structure and the second semiconductor material.

[0082] It can be understood that, in order to prevent the surface of the second gate dielectric layer from being deposited with the second semiconductor material, before depositing the second semiconductor material, a photoresist can be first coated in the second gate region to form a fourth mask structure that wraps the second gate dielectric layer; under the masking effect of the fourth mask structure, the second semiconductor material will be deposited on the fourth mask structure; then, the fourth mask structure and the second semiconductor material can be removed by selective etching.

[0083] In some possible embodiments, S102 may include: etching the active structures in the first source / drain region of the first transistor and the second source / drain region of the second transistor to form a second groove; depositing an insulating material with a preset height in the second groove to form a source / drain filling structure; the source / drain filling structure fills the second source / drain region; growing a source / drain epitaxy in the first source / drain region to form a first source / drain structure; forming a first source / drain metal on the first source / drain structure.

[0084] It can be understood that, through the same etching process, the first source / drain region and the second source / drain region (i.e., the second groove) are formed. At this time, the first source / drain region and the second source / drain region are connected. Based on this, the formed first source / drain structure and the second source / drain structure are self-aligned. In order to protect the second source / drain region during the growth of the first source / drain structure, an insulating material can be filled in the second source / drain region to form a source / drain filling structure. Then, an insulating material different from the source / drain filling structure can be deposited on the source / drain filling structure to form a source / drain isolation structure, and the source / drain isolation structure is used to isolate the first source / drain structure and the second source / drain structure. According to the standard process for preparing transistors, the first source / drain structure and the first source / drain metal are formed.

[0085] It should be noted that the "source / drain" mentioned in the embodiments of the present application is an abbreviation for "source and / or drain".

[0086] In some possible embodiments, S104 may include: removing the source / drain filling structure to expose the second source / drain region; growing a source / drain epitaxy in the second source / drain region to form a second source / drain structure; forming a second source / drain metal on the second source / drain structure.

[0087] It is understandable that after the second source-drain region is exposed, a second source-drain structure and a second source-drain metal can be formed on the source-drain isolation structure according to the standard process for fabricating transistors.

[0088] Next, taking the first transistor and the second transistor as gate-all-around field-effect transistors as an example, the semiconductor structure provided by the embodiments of the present application will be described. Figure 2 FIG. is a schematic diagram of the first structure of the semiconductor structure in the embodiments of the present application, where Figure 2 in (a) is the design layout of the semiconductor structure; Figure 2 in (b) is a cross-sectional view of the semiconductor structure taken along the cross-sectional direction of the gate structure (i.e., the A-A' direction); (c) is a cross-sectional view of the semiconductor structure taken along the cross-sectional direction of the source-drain structure (i.e., the B-B' direction); (d) is a cross-sectional view of the semiconductor structure taken along the cross-sectional direction of the active structure (i.e., the C-C' direction).

[0089] Figure 2 The semiconductor structure 10 shown can be prepared through Figures 3A to 3L the process shown, Figures 3A to 3L FIG. is a schematic diagram of the first process for preparing the semiconductor structure in the embodiments of the present application.

[0090] In one example, the first preparation process of the semiconductor structure may include the following steps:

[0091] The first step: providing a substrate 21 (see Figure 3A in (a)). The substrate 21 includes a first stack 211, a first sacrificial layer 212, a second stack 213, a second sacrificial layer 214, and a bottom substrate 215. Both the first stack 211 and the second stack 213 are formed by sequentially stacking Si material and SiGe1 material, and the first sacrificial layer 212 and the second sacrificial layer 214 are made of SiGe2 material.

[0092] The second step: etching the substrate 21 to form an active structure 22. The active structure 22 includes a first active structure 221 and a second active structure 222. The etched first sacrificial layer 212 is located between the first active structure 221 and the second active structure 222 (see Figure 3A in (b)).

[0093] Step 3: Deposit an insulating material on the bottom substrate 215 and the active structure 22 to form a shallow trench isolation (STI) structure 23. The STI structure 23 wraps the active structure 22 and covers the bottom substrate 215; at this time, the height of the STI structure 23 in the horizontal direction is greater than the height of the active structure 22. Then, through etching, a part of the STI structure 23 is removed until the first active structure 221 and the second active structure 222 are exposed; at this time, the second sacrificial layer 214 is still wrapped by the STI structure 23 (see Figure 3A in (c)).

[0094] Step 4: Deposit polysilicon (poly Si) in the first gate region and the second gate region to form a first dummy gate structure 241 and a second dummy gate structure 242; and form spacers 25 on the sidewalls of the first dummy gate structure 241 and the second dummy gate structure 242 (see Figure 3B in (a)).

[0095] Step 5: Etch a part of the spacers 25 until the first active structure 221 and the first sacrificial layer 212 are exposed (see Figure 3B in (b)).

[0096] Step 6: Remove the first active structure 221 in the first source / drain region through selective etching (see Figure 3B in (c)).

[0097] Step 7: Remove the first sacrificial layer 212 through selective etching to form a first gap 26 (see Figure 3C in (a)).

[0098] Step 8: Fill silicon nitride (SiN) in the first gap 26, the first source / drain region, and the second source / drain region, and perform chemical-mechanical planarization (CMP) on the silicon nitride in the first source / drain region and the second source / drain region (see Figure 3C in (b)).

[0099] Step 9: Remove the silicon nitride in the first source / drain region and the second source / drain region through etching, and retain the silicon nitride in the first gap 26 to form an intermediate dielectric isolation layer 27, which is used to isolate the first transistor 11 and the second transistor 12 (see Figure 3C in (c)).

[0100] Step 10: Horizontally etch SiGe1 in the first active structure 221 to form a groove, and deposit an insulating material in the groove to form a first inner spacer 281 (seeFigure 3D in (a) of FIG.

[0101] The eleventh step: anisotropic etching is performed to remove the second active structure 222 in the second source / drain region, so as to expose the second source / drain region (see Figure 3D in (b) of FIG.

[0102] The twelfth step: anisotropic etching is performed to remove the shallow trench isolation structure 23 and the second sacrificial layer 214 in the second source / drain region (see Figure 3D in (c) of FIG.

[0103] The thirteenth step: an insulating material is filled in the second source / drain region to form a source / drain filling structure 29, and the source / drain filling structure 29 can cover a part of the intermediate dielectric isolation layer 27 (see Figure 3E in (a) of FIG.

[0104] The fourteenth step: an insulating material different from the source / drain filling structure 29 is deposited on the source / drain filling structure 29 to form a source / drain isolation structure 30 (see Figure 3E in (b) of FIG.

[0105] The fifteenth step: source / drain epitaxy is grown in the first source / drain region to form a first source / drain structure 111 (see Figure 3E in (c) of FIG.

[0106] The sixteenth step: an insulating material is deposited in the first source / drain region to form a first interlayer dielectric (ILD) layer 112 (see Figure 3F in (a) of FIG.

[0107] The seventeenth step: a first source / drain metal 113 and a first dielectric layer 114 are formed according to a standard process (see Figure 3F in (b) of FIG.

[0108] The eighteenth step: a back-end interconnect process is performed to form a first metal interconnect layer 115 (see Figure 3F in (c) of FIG.

[0109] The nineteenth step: an insulating material is deposited on the first transistor 11 to form an insulating layer 13; the insulating layer 13 is bonded to the carrier wafer 14; then, the first transistor 11 is flipped so that the bottom substrate 215 faces upward; the bottom substrate 215 is removed until the shallow trench isolation structure 23 is exposed (see Figure 3G in (a) of FIG.

[0110] The twentieth step: the shallow trench isolation structure 23 is selectively etched to expose the second sacrificial layer 214 (see Figure 3G in (b) of FIG.

[0111] The twenty-first step: Deposit polysilicon in the region etched in the twentieth step to form a new second dummy gate structure 242 (see Figure 3G in (c)).

[0112] The twenty-second step: Remove the source / drain fill structure 29 (see Figure 3H in (a)).

[0113] The twenty-third step: Form the second inner spacer 282 in the second transistor 12 (see Figure 3H in (b)).

[0114] The twenty-fourth step: Form the second source / drain structure 121 and the second interlayer dielectric layer 122 (see Figure 3H in (c)).

[0115] The twenty-fifth step: Anisotropically etch to remove the first dummy gate structure 241 and the second dummy gate structure 242 to form a first groove (see Figure 3I in (a)).

[0116] The twenty-sixth step: Isotropically remove SiGe1 in the first active structure 221 and the second active structure 222 to form a nanosheet structure (see Figure 3I in (b)).

[0117] The twenty-seventh step: Deposit HK (high-K) dielectric on the surface of the nanosheet structure to form the first gate dielectric layer 116 and the second gate dielectric layer 126 (see Figure 3I in (c)).

[0118] The twenty-eighth step: Deposit lanthanum oxide on the surfaces of the first gate dielectric layer 116 and the second gate dielectric layer 126 to form a first dipole layer 117 outside the first gate dielectric layer 116 (see Figure 3J in (a)).

[0119] The twenty-ninth step: Deposit an insulating material with a preset height in the first groove to form a first isolation structure 31 (see Figure 3J in (b)).

[0120] The thirtieth step: Remove the lanthanum oxide on the surface of the second gate dielectric layer 126 by etching (see Figure 3J in (c)).

[0121] The thirty-first step: Deposit aluminum oxide on the surface of the second gate dielectric layer 126 to form a second dipole layer 127 (see Figure 3K in (a)).

[0122] The thirty-second step: Grow a work function metal on the surface of the second dipole layer 127 to form a second work function metal layer 128 (see Figure 3K in (b)).

[0123] The thirty-third step: Remove the first isolation structure 31 (see Figure 3K in (c)).

[0124] The thirty-fourth step: Deposit a metal material in the first gate region and the second gate region to form a first gate structure 119 and a second gate structure 129 (see Figure 3L in (a)).

[0125] The thirty-fifth step: Perform a gate cutting process on the first gate structure 119 and the second gate structure 129 to form a gate cut structure 32 (see Figure 3L in (b)).

[0126] The thirty-sixth step: Form a second source / drain metal 123, a second dielectric layer 124, and a second metal interconnect layer 125 (see Figure 3L in (c)).

[0127] Thus, the semiconductor structure 10 provided with a first dipole layer and a second dipole layer is formed according to the "common gate" method and the "etch-back" method.

[0128] In some embodiments, the semiconductor structure 10 is formed by using a blocking diffusion method, which can be prepared through the process shown in Figures 4A to 4C and is Figures 4A to 4C the second schematic diagram of the preparation process of the semiconductor structure in the embodiments of the present application.

[0129] In one example, the second preparation process of the semiconductor structure 10 may include the following steps:

[0130] The first step: Form a nanosheet structure according to the first step to the twenty-sixth step of the first preparation process of the semiconductor structure above (see Figure 4A in (a)).

[0131] The second step: Deposit HK dielectric on the surface of the nanosheet structure to form a first gate dielectric layer 116 and a second gate dielectric layer 126 (see Figure 4A in (b)).

[0132] The third step: Deposit an insulating material with a preset height in the first groove to form a second isolation structure 33 (see Figure 4A in (c)).

[0133] The fourth step: Deposit alumina on the surface of the second gate dielectric layer 126 to form a second dipole layer 127 (see Figure 4B in (a)).

[0134] The fifth step: Form a second work function metal layer 128 (see Figure 4B in (b)).

[0135] Step 6: Remove the second isolation structure 33 (see Figure 4B (c) in

[0136] Step 7: Deposit lanthanum oxide on the surfaces of the second work function metal layer 128 and the first gate dielectric layer 116 to form a first dipole layer 117 (see Figure 4C (a) in

[0137] Among them, due to the blocking effect of the second work function metal layer 128, the lanthanum oxide located in the second transistor will not diffuse to the second gate dielectric layer.

[0138] Step 8: Form other structures in the semiconductor structure 10 according to the first preparation process of the above semiconductor structure (see Figure 4C (b) in

[0139] Thus far, the semiconductor structure 10 provided with the first dipole layer and the second dipole layer is formed according to the common gate method and the blocking diffusion method.

[0140] In some embodiments, in the case where the semiconductor device includes four stacked transistors, among them, the first dipole layer and the second dipole layer are provided in the first stacked transistor, only the first dipole layer is provided in the second stacked transistor, only the second dipole layer is provided in the third stacked transistor, and neither the first dipole layer nor the second dipole layer is provided in the fourth stacked transistor. The common gate method is used to form multiple stacked transistors in the above semiconductor device, which can be prepared through the process shown in Figures 5A to 5I and Figures 5A to 5I is the first schematic diagram of the preparation process of the semiconductor device in the embodiment of the present application. It should be noted that in Figures 5A to 5I , Figure (a) shows the preparation process of the first stacked transistor, Figure (b) shows the preparation process of the second stacked transistor, Figure (c) shows the preparation process of the third stacked transistor, and Figure (d) shows the preparation process of the fourth stacked transistor.

[0141] Step 1: According to the first step to the twenty-seventh step in the first preparation process of the above semiconductor structure, form the first gate dielectric layer 116 and the second gate dielectric layer 126; then form an isolation structure 40 that wraps the first gate dielectric layer 116 (see Figure 5A ).

[0142] Step 2: According to the design layout of the semiconductor device, coat photoresist in the second stacked transistor and the fourth stacked transistor to form a first photoresist layer 41 (which can also be called a mask structure) (see Figure 5B ).

[0143] Step 3: Deposit aluminum oxide to form a second dipole layer 127 in the first and third stacked transistors (see Figure 5C ).

[0144] Step 4: Remove the first photoresist layer 41 in the second and fourth stacked transistors and the aluminum oxide material above the first photoresist layer 41 (see Figure 5D ).

[0145] Step 5: Isotropically etch to remove the isolation structure 40 (see Figure 5E ).

[0146] Step 6: Coat a photoresist on the third and fourth stacked transistors according to the design layout of the semiconductor device to form a second photoresist layer 42 (also referred to as a mask structure) (see Figure 5F ).

[0147] Step 7: Deposit lanthanum oxide to form a first dipole layer 117 in the first and second stacked transistors (see Figure 5G ).

[0148] Step 8: Remove the second photoresist layer 42 in the third and fourth stacked transistors and the lanthanum oxide material above the second photoresist layer 42 (see Figure 5H ).

[0149] Step 9: Prepare other structures in the stacked transistors according to the above common gate method (see Figure 5I ).

[0150] Thus, a semiconductor device including four types of stacked transistors is formed according to the common gate method.

[0151] Next, taking the first transistor and the second transistor as surround gate field effect transistors as an example, the semiconductor structure provided by the embodiment of the present application will be described. Figure 6 is the second structural schematic diagram of the semiconductor structure in the embodiment of the present application, where Figure 6 in (a) is the design layout of the semiconductor structure; Figure 6 in (b) is the cross-sectional view of the semiconductor structure taken along the cross-sectional direction of the gate structure (i.e., the A-A' direction); (c) is the cross-sectional view of the semiconductor structure taken along the cross-sectional direction of the source-drain structure (i.e., the B-B' direction); (d) is the cross-sectional view of the semiconductor structure taken along the cross-sectional direction of the active structure (i.e., the C-C' direction).

[0152] Figure 6 The semiconductor structure 10 shown can be prepared through the Figures 7A to 7H shown process, Figures 7A to 7HThis is the second schematic diagram of the preparation process of the semiconductor structure in the embodiments of this application.

[0153] In one example, the third preparation process of the semiconductor structure may include the following steps:

[0154] The first step: Form the first interlayer dielectric layer 112 according to the first step to the sixteenth step in the first preparation process of the semiconductor structure above; then, remove the first dummy gate structure to expose the first gate region (see (a) in Figure 7A ).

[0155] The second step: Remove the SiGe1 material in the first active structure 221 to form a nanosheet structure (see (b) in Figure 7A ).

[0156] The third step: Deposit HK material to form the first gate dielectric layer 116 (see (c) in Figure 7A ).

[0157] The fourth step: Isotropically deposit lanthanum oxide to form the first dipole layer 117 (see (a) in Figure 7B ).

[0158] The fifth step: Form the first gate structure 119 (see (b) in Figure 7B ).

[0159] The sixth step: Perform a gate cut-off process to form the gate cut-off structure 32 in the first transistor (see (c) in Figure 7B ).

[0160] The seventh step: Form the first source / drain metal 113 and the first dielectric layer 114 (see (a) in Figure 7C ).

[0161] The eighth step: Form the first metal interconnect layer 115 (see (b) in Figure 7C ).

[0162] The ninth step: Form the insulating layer 13; bond the insulating layer 13 to the carrier wafer 14; then, perform a flip-chip process on the first transistor 11 so that the bottom substrate 215 is placed upward; remove the bottom substrate 215 until the shallow trench isolation structure 23 is exposed (see (c) in Figure 7C ).

[0163] The tenth step: Selectively etch the shallow trench isolation structure 23 to expose the second sacrificial layer 214 (see (a) in Figure 7D ).

[0164] The eleventh step: Deposit polysilicon in the region etched in the tenth step to form a new second dummy gate structure 242 (see (b) in Figure 7D ).

[0165] The twelfth step: Remove the source-drain filling structure 29 (see (c) in Figure 7D .

[0166] The thirteenth step: Form the second inner sidewall 282 in the second transistor 12 (see (a) in Figure 7E .

[0167] The fourteenth step: Form the second source-drain structure 121 and the second interlayer dielectric layer 122 (see (b) in Figure 7E .

[0168] The fifteenth step: Anisotropically etch to remove the second dummy gate structure 242 to expose the second gate region (see (c) in Figure 7E .

[0169] The sixteenth step: Deposit an insulating material on the first gate structure 119 to form the gate isolation structure 34 (see (a) in Figure 7F ; The gate isolation structure 34 is used to isolate the first gate structure 119 and the second gate structure 129.

[0170] The seventeenth step: Remove the SiGe1 material in the second active structure 222 to form a nanosheet structure (see (b) in Figure 7F .

[0171] The eighteenth step: Deposit HK material to form the second gate dielectric layer 126 (see (c) in Figure 7F .

[0172] The nineteenth step: Isotropically deposit aluminum oxide to form the second dipole layer 127 (see (a) in Figure 7G .

[0173] The twentieth step: Form the second work function metal layer 128 (see (b) in Figure 7G .

[0174] The twenty-first step: Form the second gate structure 129 (see (c) in Figure 7G .

[0175] The twenty-second step: Perform a gate cut-off process to form the gate cut-off structure 32 in the second transistor (see (a) in Figure 7H .

[0176] The twenty-third step: Form the second source-drain metal 123 and the second dielectric layer 124 (see (b) in Figure 7H .

[0177] The twenty-fourth step: Form the second metal interconnect layer 125 (see (c) in Figure 7H .

[0178] Thus, the above semiconductor structure is formed according to the split-gate method.

[0179] In some embodiments, when there are four stacked transistors in a semiconductor device, a first dipole layer and a second dipole layer are provided in the first stacked transistor, only the first dipole layer is provided in the second stacked transistor, only the second dipole layer is provided in the third stacked transistor, and neither the first dipole layer nor the second dipole layer is provided in the fourth stacked transistor. The multiple stacked transistors in the above semiconductor device are formed by the common-gate method, and can be prepared through the Figures 8A to 8I process shown. Figures 8A to 8I This is the second schematic diagram of the preparation process of the semiconductor device in the embodiments of the present application. It should be noted that in Figures 8A to 8I , Fig. (a) shows the preparation process of the first stacked transistor, Fig. (b) shows the preparation process of the second stacked transistor, Fig. (c) shows the preparation process of the third stacked transistor, and Fig. (d) shows the preparation process of the fourth stacked transistor.

[0180] First step: According to the first to third steps in the third preparation process of the above semiconductor structure, a first gate dielectric layer 116 is formed (see Figure 8A ).

[0181] Second step: According to the design layout of the semiconductor device, photoresist is coated on the third stacked transistor and the fourth stacked transistor to form a third photoresist layer 43 (see Figure 8B ).

[0182] Third step: Lanthanum oxide is deposited isotropically to form a first dipole layer 117 (see Figure 8C ).

[0183] Fourth step: The third photoresist layer 43 in the third stacked transistor and the fourth stacked transistor, and the lanthanum oxide material on the third photoresist layer 43 are removed (see Figure 8D ).

[0184] Fifth step: A first transistor 11 in the stacked transistor is formed, and the first transistor 11 is flipped; then, a nanosheet structure and a second gate dielectric layer 126 in the second transistor 12 are formed (see Figure 8E ).

[0185] Sixth step: Photoresist is coated on the second stacked transistor and the fourth stacked transistor to form a fourth photoresist layer 44 (see Figure 8F ).

[0186] Seventh step: Aluminum oxide is deposited isotropically to form a second dipole layer 127 (see Figure 8G ).

[0187] Step 8: Remove the fourth photoresist layer 44 in the second stacked transistor and the fourth stacked transistor, and the alumina material on the fourth photoresist layer 44 (see Figure 8H ).

[0188] Step 9: Prepare other structures in the stacked transistor according to the above split-gate method (see Figure 8I ).

[0189] So far, a semiconductor device including four types of stacked transistors has been formed according to the split-gate method.

[0190] In the embodiments of the present application, the first dipole layer can be selectively provided or not provided in the first transistor and the second dipole layer can be selectively provided or not provided in the second transistor according to actual situations. In this way, the threshold voltages of the first transistor and the second transistor can be adjusted separately and flexibly.

[0191] Furthermore, the preparation method of the semiconductor structure described in the embodiments of the present application is compatible with mainstream device architectures, and can realize the front and back stacking of planar transistors, FinFETs, GAAFETs, and even vertical transistors (VTFETs) and CFETs, without the need for special process development for specific device architectures, with strong flexibility. Considering the iteration of semiconductor process nodes, it has strong extensibility, important industrial value, strong practicability, and broad expansion prospects.

[0192] Furthermore, the semiconductor structure provided in the embodiments of the present application can be detected using detection and analysis instruments, such as: scanning electron microscope (SEM), transmission electron microscope (TEM), scanning transmission electron microscopy (STEM), etc. Taking TEM as an example, the semiconductor structure provided in the embodiments of the present application can be detected by means of TEM slicing. For example, in the semiconductor structure prepared by the common-gate method, the first dipole layer, the second dipole layer, and the second work function metal layer can be observed; in the semiconductor structure prepared by the split-gate method, it can be observed that the first semiconductor material is attached to the outside of the second work function metal layer, and the second work function metal layer blocks the diffusion of the first semiconductor material into the second gate dielectric.

[0193] The embodiments of the present application provide a semiconductor device, including: the semiconductor structure as described in the above embodiments. The specific limitations of the semiconductor structure can be referred to the semiconductor structure shown in the above Figure 2 and Figure 6 , which will not be elaborated here.

[0194] An embodiment of the present application provides an electronic device, including: a circuit board and a semiconductor device as described in the above embodiment, and the semiconductor device is disposed on the circuit board. The semiconductor device includes the above semiconductor structure. For specific limitations of the semiconductor structure, reference can be made to the above Figure 2 and Figure 6 , which will not be elaborated here.

[0195] In the description of the present application, the descriptions referring to terms such as "one embodiment", "some embodiments", "example", "specific example", or "some examples" mean that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the embodiments of the present application. In the present application, the schematic representations of the above terms are not necessarily directed to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in any one or more embodiments or examples in a suitable manner. In addition, without conflict, those skilled in the art can combine different embodiments or examples described in the present application and the features of different embodiments or examples.

[0196] The above are only the preferred embodiments of the present application and are not used to limit the present application. For those skilled in the art, the present application can have various changes and modifications. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present application shall be included within the protection scope of the present application.

Claims

1. A method for preparing a semiconductor structure, characterized in that, The method includes: Forming an active structure on a substrate, the active structure including a first active structure and a second active structure; Forming a first transistor based on the first active structure; Flipping the wafer and thinning the substrate; Forming a second transistor based on the second active structure; the first transistor and the second transistor are stacked in a first direction; Wherein, a first dipole layer is disposed between a first gate dielectric layer and a first gate structure of the first transistor, and / or, a second dipole layer is disposed between a second gate dielectric layer and a second gate structure of the second transistor; the first dipole layer is formed of a first semiconductor material, and the second dipole layer is formed of a second semiconductor material.

2. The method according to claim 1, wherein Forming the first transistor based on the first active structure includes: depositing a semiconductor material in the first gate region and the second gate region to form a first dummy gate structure of the first transistor and a second dummy gate structure of the second transistor; the first dummy gate structure and the second dummy gate structure are formed in the same deposition process; Forming the second transistor based on the second active structure includes: removing the first dummy gate structure and the second dummy gate structure to form a first groove; depositing a metal material in the first groove to form a first gate structure of the first transistor and a second gate structure of the second transistor; the first gate structure and the second gate structure are formed in the same deposition process.

3. The method according to claim 2, characterized in that, After removing the first dummy gate structure and the second dummy gate structure to form the first groove, the method further includes: Depositing an insulating material on surfaces of the first active structure and the second active structure located in the first gate region and the second gate region to form a first gate dielectric layer and a second gate dielectric layer; Depositing the first semiconductor material on surfaces of the first gate dielectric layer and the second gate dielectric layer; Depositing an insulating material with a preset height in the first groove to form a first isolation structure; the first isolation structure wraps the first gate dielectric layer; Removing the first semiconductor material on the surface of the second gate dielectric layer to form the first dipole layer and expose the second gate dielectric layer; Depositing the second semiconductor material on the surface of the second gate dielectric layer to form the second dipole layer.

4. The method according to claim 2, wherein After removing the first dummy gate structure and the second dummy gate structure to form the first groove, the method further includes: Depositing an insulating material on surfaces of the first active structure and the second active structure located in the first gate region and the second gate region to form a first gate dielectric layer and a second gate dielectric layer; Depositing an insulating material with a preset height in the first groove to form a second isolation structure; the second isolation structure wraps the first gate dielectric layer; Depositing the second semiconductor material on the surface of the second gate dielectric layer to form the second dipole layer; Removing the second isolation structure to expose the first gate dielectric layer; Deposit the first semiconductor material on the surfaces of the first gate dielectric layer and the second dipole layer to form the first dipole layer; the first semiconductor material located outside the second dipole layer is isolated from the second active structure under the action of the second dipole layer.

5. The method according to claim 2, characterized in that, When the first dipole layer is not provided in the first transistor and the second dipole layer is provided in the second transistor; After removing the first pseudo-gate structure and the second pseudo-gate structure to form a first groove, the method further includes: Deposit an insulating material on the surfaces of the first active structure in the first gate region and the second active structure in the second gate region to form a first gate dielectric layer and a second gate dielectric layer; Deposit an insulating material with a preset height in the first groove to form a third isolation structure; the third isolation structure wraps the first gate dielectric layer; Deposit the second semiconductor material on the surface of the second gate dielectric layer to form the second dipole layer; Remove the third isolation structure to expose the first gate dielectric layer; Coat a photoresist in the first groove to form a first mask structure; Deposit the first semiconductor material on the first mask structure; Remove the first mask structure and the first semiconductor material.

6. The method according to claim 2, wherein When the first dipole layer is provided in the first transistor and the second dipole layer is not provided in the second transistor; After removing the first pseudo-gate structure and the second pseudo-gate structure to form a first groove, the method further includes: Deposit an insulating material on the surfaces of the first active structure in the first gate region and the second active structure in the second gate region to form a first gate dielectric layer and a second gate dielectric layer; Deposit an insulating material with a preset height in the first groove to form a fourth isolation structure; the fourth isolation structure wraps the first gate dielectric layer; Deposit a photoresist in the first groove and on the fourth isolation structure to form a second mask structure; the second mask structure wraps the second gate dielectric layer; Deposit the second semiconductor material on the second mask structure; Remove the second mask structure and the second semiconductor material to expose the second gate dielectric layer; Grow a work function metal on the surface of the second gate dielectric layer to form a second work function metal layer; Remove the fourth isolation structure to expose the first gate dielectric layer; Deposit the first semiconductor material on the surfaces of the first gate dielectric layer and the second work function metal layer to form the first dipole layer; wherein, the first semiconductor material located on the surface of the second work function metal layer is isolated from the second active structure under the action of the second work function metal layer.

7. The method according to claim 1, wherein Forming a first transistor based on the first active structure includes: depositing a semiconductor material in the first gate region and the second gate region to form a first dummy gate structure of the first transistor and a second dummy gate structure of the second transistor; the first dummy gate structure and the second dummy gate structure are formed in the same deposition process; removing the first dummy gate structure to expose the first gate region; depositing an insulating material on the surface of the first active structure located in the first gate region to form a first gate dielectric layer; depositing a metal material in the first gate region to form the first gate structure; Forming a second transistor based on the second active structure includes: removing the second dummy gate structure to expose the second gate region; depositing an insulating material with a preset height on the first gate structure to form a gate isolation structure; the gate isolation structure is used to isolate the first gate structure and the second gate structure; depositing an insulating material on the surface of the second active structure located in the second gate region to form a second gate dielectric layer; depositing a metal material in the second gate region to form the second gate structure.

8. The method according to claim 7, wherein, After forming the first gate dielectric layer, the method further includes: depositing the first semiconductor material on the surface of the first gate dielectric layer to form the first dipole layer; After forming the second gate dielectric layer, the method further includes: depositing the second semiconductor material on the surface of the second gate dielectric layer to form the second dipole layer.

9. The method according to claim 7, characterized in that, In the case where the first dipole layer is not provided in the first transistor and the second dipole layer is provided in the second transistor; After forming the first gate dielectric layer, the method further includes: coating a photoresist in the first gate region to form a third mask structure; the third mask structure wraps the first gate dielectric layer; depositing the first semiconductor material on the third mask structure; removing the third mask structure and the first semiconductor material; After forming the second gate dielectric layer, the method further includes: depositing the second semiconductor material on the surface of the second gate dielectric layer to form the second dipole layer.

10. The method according to claim 7, wherein In the case where the first dipole layer is provided in the first transistor and the second dipole layer is not provided in the second transistor; After forming the first gate dielectric layer, the method further includes: depositing the first semiconductor material on the surface of the first gate dielectric layer to form the first dipole layer; After forming the second gate dielectric layer, the method further includes: coating a photoresist in the second gate region to form a fourth mask structure; the fourth mask structure wraps the second gate dielectric layer; depositing the second semiconductor material on the fourth mask structure; removing the fourth mask structure and the second semiconductor material.

11. The method according to claim 1, characterized in that, Forming a first transistor based on the first active structure includes: Etch the active structure in the first source / drain region of the first transistor and the second source / drain region of the second transistor to form a second groove; Deposit an insulating material with a preset height in the second groove to form a source / drain fill structure; the source / drain fill structure fills the second source / drain region; Grow source / drain epitaxy in the first source / drain region to form a first source / drain structure; Form a first source / drain metal on the first source / drain structure.

12. The method according to claim 11, wherein Forming the second transistor based on the second active structure includes: Remove the source / drain fill structure to expose the second source / drain region; Grow source / drain epitaxy in the second source / drain region to form a second source / drain structure; Form a second source / drain metal on the second source / drain structure.

13. A semiconductor structure, characterized in that, Prepared by the method according to any one of claims 1 to 12, the semiconductor structure includes: A first transistor; A second transistor; the first transistor and the second transistor are stacked in a first direction; Wherein, a first dipole layer is provided between the first gate dielectric layer of the first transistor and the first gate structure of the first transistor, and / or, a second dipole layer is provided between the second gate dielectric layer of the second transistor and the second gate structure of the second transistor; the first dipole layer is formed of a first semiconductor material, and the second dipole layer is formed of a second semiconductor material.

14. A semiconductor device, characterized in that, Includes: The semiconductor structure according to claim 13.

15. An electronic device, characterized in that, Includes: A circuit board and the semiconductor device according to claim 14, the semiconductor device is disposed on the circuit board.

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