Semiconductor device

Abstract

This semiconductor device is provided with: an interlayer insulating film provided above a semiconductor substrate; a front surface electrode provided above the semiconductor substrate; a contact part for connecting the front surface electrode and the mesa part in the contact hole of the interlayer insulating film; and a lifetime adjustment region provided on the front surface side of the semiconductor substrate, the contact portion having a first contact portion provided in the transistor portion and a second contact portion provided in the diode portion, and the first contact portion being disposed above the second contact portion.

Description

Technical Field

[0001] The present invention relates to a semiconductor device. Background Art

[0002] There is known a structure in a semiconductor device having a transistor portion and a diode portion in which an electrode is connected to a semiconductor substrate through a trench-shaped contact portion (see, for example, Patent Document 1 and Patent Document 2).

[0003] Prior Art Documents Patent Documents Patent Document 1: WO2018 / 056233 Patent Document 2: Japanese Patent Application Laid-Open No. 2021-150483 Summary of the Invention

[0004] Technical Problem Preferably, reverse recovery loss is reduced in a semiconductor device having a transistor portion and a diode portion.

[0005] Technical Solution In a first aspect of the present invention, there is provided a semiconductor device including: a transistor portion; a diode portion; a plurality of trench portions provided on a front surface of a semiconductor substrate; a drift region of a first conductivity type provided in the semiconductor substrate; a base region of a second conductivity type provided above the drift region in the transistor portion; a first conductivity type emitter region and a second conductivity type contact region, both provided on the front surface of the semiconductor substrate in the transistor portion, and the doping concentration of the emitter region being higher than the doping concentration of the drift region, and the doping concentration of the contact region being higher than the doping concentration of the base region; a second conductivity type anode region provided above the drift region in the diode portion; a mesa portion of the semiconductor substrate provided between the plurality of trench portions; an interlayer insulating film provided above the semiconductor substrate; a front electrode provided above the semiconductor substrate; a contact portion connecting the front electrode and the mesa portion in a contact hole of the interlayer insulating film; and a lifetime adjustment region provided on a front surface side of the semiconductor substrate, the contact portion having a first contact portion provided in the transistor portion and a second contact portion provided in the diode portion, and the first contact portion being disposed at a position higher than the second contact portion.

[0006] The semiconductor device may include a second conductivity type second plug region provided below the second contact portion and having a doping concentration higher than the doping concentration of the contact region.

[0007] The second plug region may be provided to extend in a trench extending direction.

[0008] The second plug region may be intermittently provided in the trench extending direction.

[0009] The semiconductor device may include a first plug region of a second conductivity type, which is provided below the first contact portion and has a doping concentration higher than that of the contact region.

[0010] The first plug region may be intermittently provided in the trench extending direction.

[0011] The first plug region may be provided above the contact region and not above the emitter region.

[0012] The semiconductor device may include a barrier metal portion provided on the side surface of the contact hole. The barrier metal portion has a Ti layer.

[0013] The semiconductor device may include an accumulation region of a first conductivity type, which is provided above the drift region in the transistor portion and has a doping concentration higher than that of the drift region.

[0014] The front electrode may include an emitter electrode provided above the interlayer insulating film.

[0015] The front electrode may include a contact plug portion provided in the contact hole and connecting the emitter electrode to the mesa portion.

[0016] The diode portion may have the lifetime adjustment region.

[0017] The transistor portion may have the lifetime adjustment region.

[0018] The lifetime adjustment region of the transistor portion may be formed by irradiation with a particle beam.

[0019] The lifetime adjustment region may be provided so as to extend throughout the transistor portion and the diode portion in the trench arrangement direction.

[0020] The lifetime adjustment region may be provided so as to extend from the diode portion to a part of the transistor portion in the trench arrangement direction.

[0021] The doping concentration of the anode region may be higher than that of the base region.

[0022] The doping concentration of the anode region may be the same as that of the base region.

[0023] The first contact portion may be in contact with the front surface of the mesa portion.

[0024] The first contact portion may be disposed at a position lower than the front surface of the mesa portion.

[0025] The semiconductor device may include a boundary region provided between the transistor portion and the diode portion.

[0026] The lifetime adjustment region may be provided to extend from the diode portion to the boundary region in the trench arrangement direction.

[0027] The width of the boundary region in the trench arrangement direction may be 20 μm or more and 250 μm or less.

[0028] The contact portion of the boundary region may be a third contact portion, which is disposed at a position higher than the second contact portion and lower than the first contact portion.

[0029] The contact portion of the boundary region may be the second contact portion.

[0030] It should be noted that the above invention content does not list all the essential features of the present invention. In addition, sub - combinations of these feature groups can also form inventions separately. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 It is a top view showing an example of the semiconductor device 100.

[0032] Figure 2 It shows Figure 1 An enlarged view of an example of the region D in

[0033] Figure 3A It shows Figure 2 An example of the a - a cross - section in

[0034] Figure 3B It is near Figure 3A The contact hole 54 provided on the first table surface 61, the third table surface 63, and the fourth table surface 64 shown in

[0035] Figure 4A It shows Figure 2 An example of the b - b cross - section in

[0036] Figure 4B It is near Figure 4A The contact hole 54 provided on the first table surface 61, the third table surface 63, and the fourth table surface 64 shown in

[0037] Figure 4C It shows Figure 2 Another example of the b - b cross - section in

[0038] Figure 4D It is near Figure 4CEnlarged view near the contact holes 54 provided in the first face 61, the third face 63, and the fourth face 64 shown.

[0039] Figure 5A is a diagram showing Figure 2 another example of the a-a cross-section in

[0040] Figure 5B is a diagram showing Figure 2 another example of the b-b cross-section in

[0041] Figure 6 is a diagram showing Figure 1 an enlarged view of another example of region D in

[0042] Figure 7A is a diagram showing Figure 6 an example of the c-c cross-section in

[0043] Figure 7B is a diagram showing Figure 6 an example of the d-d cross-section in

[0044] Figure 8 is a diagram showing Figure 1 an enlarged view of another example of region D in

[0045] Figure 9A is a diagram showing Figure 8 an example of the e-e cross-section in

[0046] Figure 9B is Figure 9A an enlarged view near the first face 61, the second face 62, the third face 63, and the fourth face 64 shown.

[0047] Figure 9C is a diagram showing Figure 8 an example of the f-f cross-section in

[0048] Symbol Explanation 10 semiconductor substrate, 11 well region, 12 emission region, 14 base region, 15 contact region, 16 accumulation region, 18 drift region, 20 buffer region, 21 front face, 22 collector region, 23 back face, 24 collector electrode, 29 straight portion, 30 dummy trench portion, 31 Front end portion, 32 Dummy insulating film, 34 Dummy conductive portion, 38 Interlayer insulating film, 39 Straight portion, 40 Gate trench portion, 41 Front end portion, 42 Gate insulating film, 44 Gate conductive portion, 52 Emission electrode, 54 Contact hole, 60 Table surface portion, 61 First table surface portion, 62 Second table surface portion, 63 Third table surface portion, 64 Fourth table surface portion, 70 Transistor portion, 77 First contact portion, 80 Diode portion, 81 Extension region, 82 Cathode region, 84 Anode region, 87 Second contact portion, 90 Edge termination structure portion, 100 Semiconductor device, 130 Peripheral gate wiring, 131 Active side gate wiring, 160 Active portion, 162 End edge, 164 Gate pad, 200 Boundary region, 201 Adjustment region, 202 Non-adjustment region, 204 Lattice defect, 206 Lifetime adjustment region, 207 Third contact portion, 221 First plug region, 222 Second plug region, 250 Contact plug portion, 251 Plug, 252 Barrier metal portion Detailed implementation mode

[0049] Hereinafter, although the present invention is described by way of embodiments of the invention, the following embodiments do not limit the invention recited in the claims. In addition, all combinations of the features described in the embodiments are not necessarily essential to the technical solution of the invention.

[0050] In this specification, one side in the direction parallel to the depth direction of the semiconductor substrate is referred to as "upper", and the other side as "lower". One of the two main surfaces of the substrate, layer, or other component is referred to as the front surface, and the other as the back surface. The directions of "upper" and "lower" are not limited to the direction of gravity or the direction when actually mounting the semiconductor device.

[0051] In this specification, the right-angled coordinate axes of the X-axis, Y-axis, and Z-axis are sometimes used to explain technical matters. The rectangular coordinate system only determines the relative positions of the components and does not limit a specific direction. For example, the Z-axis direction is not limited to representing the height direction relative to the ground. It should be noted that the +Z-axis direction and the -Z-axis direction are opposite directions to each other. When not recording positive and negative and only recording the Z-axis direction, it refers to the direction parallel to the +Z-axis and the -Z-axis.

[0052] In this specification, the right-angled axes parallel to the front and back surfaces of the semiconductor substrate are set as the X-axis and the Y-axis. Additionally, the axis perpendicular to the front and back surfaces of the semiconductor substrate is set as the Z-axis. In this specification, the direction of the Z-axis is sometimes referred to as the depth direction. Also, in this specification, the direction parallel to the front and back surfaces of the semiconductor substrate and including the X-axis and the Y-axis is sometimes referred to as the horizontal direction.

[0053] Sometimes, the region from the center in the depth direction of the semiconductor substrate to the front surface of the semiconductor substrate is referred to as the front side. Similarly, sometimes the region from the center in the depth direction of the semiconductor substrate to the back surface of the semiconductor substrate is referred to as the back side.

[0054] In this specification, in the case of being referred to as "the same" or "equal", it may also include the case with errors caused by manufacturing deviations, etc. This error is, for example, within 10%.

[0055] In this specification, the conductivity type of the doped region doped with impurities is described as P-type or N-type. In this specification, impurities sometimes particularly refer to either an N-type donor or a P-type acceptor, and are sometimes referred to as dopants. In this specification, doping means introducing a donor or an acceptor into the semiconductor substrate to form a semiconductor with an N-type conductivity type or a semiconductor with a P-type conductivity type.

[0056] In this specification, the doping concentration refers to the concentration of donors or acceptors in the thermal equilibrium state. In this specification, the net doping concentration refers to the substantial concentration obtained by adding when setting the donor concentration as the concentration of positive ions and the acceptor concentration as the concentration of negative ions in the case including the polarity of charges. As an example, if the donor concentration is set as N D and the acceptor concentration is set as N A , then the substantial net doping concentration at any position becomes N D -NA In this specification, sometimes the net doping concentration is only referred to as the doping concentration.

[0057] A donor has the function of supplying electrons to a semiconductor. An acceptor has the function of obtaining electrons from a semiconductor. The donor and acceptor are not limited to the impurity itself. For example, a VOH defect formed by the combination of a vacancy (V), oxygen (O), and hydrogen (H) present in a semiconductor functions as a donor that supplies electrons. A hydrogen donor can be a donor formed by combining at least a vacancy (V) and hydrogen (H). Alternatively, an interstitial Si-H formed by the combination of interstitial silicon (Si-i) and hydrogen in a silicon semiconductor also functions as a donor that supplies electrons. In this specification, sometimes a VOH defect or interstitial Si-H is referred to as a hydrogen donor.

[0058] In this specification, the semiconductor substrate has N-type bulk donors distributed throughout. The bulk donors are donors formed by dopants that are contained substantially uniformly within an ingot during the manufacture of the ingot that is the basis of the semiconductor substrate. The bulk donors in this example are elements other than hydrogen. The dopant of the bulk donors is, for example, phosphorus, antimony, arsenic, selenium, or sulfur, but is not limited thereto. The bulk donor in this example is phosphorus. The bulk donors are also contained in the P-type region. The semiconductor substrate can be a wafer cut from a semiconductor ingot or a chip formed by singulating a wafer. The semiconductor ingot can be manufactured using any one of the Czochralski method (CZ method), magnetic field controlled Czochralski method (MCZ method), or floating zone method (FZ method). The ingot in this example is manufactured using the MCZ method. The oxygen concentration contained in the substrate manufactured using the MCZ method is 1×10 17 ~7×10 17 / cm 3 . The oxygen concentration contained in the substrate manufactured using the FZ method is 1×10 15 ~5×10 16 / cm 3 . When the oxygen concentration is high, there is a tendency for hydrogen donors to be easily generated. The bulk donor concentration can be the chemical concentration of the bulk donors distributed throughout the semiconductor substrate or a value between 90% and 100% of the chemical concentration. Additionally, an undoped substrate that does not contain dopants such as phosphorus can also be used as the semiconductor substrate. In this case, the bulk donor concentration (D0) of the undoped substrate is, for example, 1×10 10 / cm 3 or more and 5×10 12 / cm 3 or less. The bulk donor concentration (D0) of the undoped substrate is preferably 1×10 11 / cm 3 or more. The bulk donor concentration (D0) of the undoped substrate is preferably 5×10 12 / cm 3As follows. It should be noted that the concentrations in the present invention may be values at room temperature. As an example, they are values at 300K (Kelvin) (about 26.9°C) at room temperature.

[0059] When described as P+ type or N+ type in this specification, it means that the doping concentration is higher than that of P type or N type. When described as P- type or N- type, it means that the doping concentration is lower than that of P type or N type. In addition, when described as P++ type or N++ type in this specification, it means that the doping concentration is higher than that of P+ type or N+ type. Unless otherwise specified, the unit system in this specification is the SI unit system. Although the unit of length is sometimes expressed in cm, each calculation can be carried out after conversion to meters (m).

[0060] In this specification, the chemical concentration refers to the atomic density of impurities measured regardless of the state of electrical activation. The chemical concentration can be measured by, for example, secondary ion mass spectrometry (SIMS). The above net doping concentration can be measured by voltage-capacitance measurement (CV method). In addition, the carrier concentration measured by spreading resistance measurement (SR method) can be set as the net doping concentration. The carrier concentration measured by the CV method or SR method can be set as a value in the thermal equilibrium state. In addition, in the N-type region, the donor concentration is much larger than the acceptor concentration, so the carrier concentration in this region can also be set as the donor concentration. Similarly, in the P-type region, the carrier concentration in this region can also be set as the acceptor concentration. In this specification, sometimes the doping concentration in the N-type region is called the donor concentration, and sometimes the doping concentration in the P-type region is called the acceptor concentration.

[0061] When the concentration distribution of donors, acceptors, or net doping has a peak, the peak value can be set as the concentration of donors, acceptors, or net doping in this region. When the concentration of donors, acceptors, or net doping is almost uniform, etc., the average value of the concentration of donors, acceptors, or net doping in this region can be set as the concentration of donors, acceptors, or net doping. In this specification, in the concentration representation per unit volume, atoms / cm 3 or / cm 3 is used. This unit is used for the donor or acceptor concentration, or chemical concentration, in the semiconductor substrate. The atoms label can also be omitted.

[0062] The carrier concentration measured by the SR method can be lower than the donor or acceptor concentration. In the range where current flows during the measurement of spreading resistance, sometimes the carrier mobility of the semiconductor substrate is lower than the value in the crystalline state. Due to the disorder (disorder) of the crystal structure caused by lattice defects, etc., the carriers are scattered, resulting in a decrease in carrier mobility.

[0063] The concentration of donors or acceptors calculated based on the carrier concentration measured by the CV method or the SR method can be lower than the chemical concentration of the elements representing the donors or acceptors. As an example, in a silicon semiconductor, the donor concentration of phosphorus or arsenic that acts as a donor, or the acceptor concentration of boron that acts as an acceptor, is about 99% of their chemical concentration. On the other hand, in a silicon semiconductor, the donor concentration of hydrogen that acts as a donor is about 0.1% to 10% of the chemical concentration of hydrogen.

[0064] Figure 1 is a top view showing an example of the semiconductor device 100. In Figure 1 it shows the positions obtained by projecting each component onto the front side of the semiconductor substrate 10. In Figure 1 it shows only a part of the components of the semiconductor device 100 and omits other components.

[0065] The semiconductor device 100 includes a semiconductor substrate 10. The semiconductor substrate 10 is a substrate formed of a semiconductor material. As an example, the semiconductor substrate 10 is a silicon substrate. The semiconductor substrate 10 has an edge 162 in a top view. In this specification, the case simply referred to as a top view means the case of observing from the front side of the semiconductor substrate 10. The semiconductor substrate 10 of this example has two sets of edges 162 that are opposite to each other in a top view. In Figure 1 it, the X-axis and the Y-axis are parallel to a certain edge 162. In addition, the Z-axis is perpendicular to the front side of the semiconductor substrate 10.

[0066] An active portion 160 is provided on the semiconductor substrate 10. The active portion 160 is a region where a main current flows in the depth direction between the front side and the back side of the semiconductor substrate 10 when the semiconductor device 100 operates. An emission electrode is provided above the active portion 160, but it is omitted in Figure 1 it. The active portion 160 may refer to a region where the emission electrode overlaps in a top view. In addition, the region clamped by the active portion 160 in a top view may also be included in the active portion 160.

[0067] A transistor portion 70 including transistor elements such as an IGBT (Insulated Gate Bipolar Transistor) and a diode portion 80 including diode elements such as a freewheeling diode (FWD) are provided in the active portion 160. In Figure 1 the example, the transistor portion 70 and the diode portion 80 are alternately arranged along a predetermined first direction (the X-axis direction in this example) on the front side of the semiconductor substrate 10. The semiconductor device 100 of this example is a reverse conducting IGBT (RC-IGBT). In the X-axis direction, a boundary region is arranged between the transistor portion 70 and the diode portion 80, but it is omitted in Figure 1 it.

[0068] In Figure 1 , in the region where the transistor portion 70 is disposed, the symbol "I" is marked, and in the region where the diode portion 80 is disposed, the symbol "F" is marked. In this specification, a direction different from the first direction in a plan view is sometimes referred to as a second direction (in Figure 1 it is the Y-axis direction). The second direction may be a direction perpendicular to the first direction. The transistor portion 70 and the diode portion 80 may each have a long side in the second direction. That is, the length of the transistor portion 70 in the Y-axis direction is larger than the width in the X-axis direction. Similarly, the length of the diode portion 80 in the Y-axis direction is larger than the width in the X-axis direction. The second direction of the transistor portion 70 and the diode portion 80 may be the same as the long side direction of each of the trench portions and the mesa portions described later.

[0069] The diode portion 80 has an N+-type cathode region in the region in contact with the back surface of the semiconductor substrate 10. In this specification, the region where the cathode region is provided is referred to as the diode portion 80. That is, the diode portion 80 is the region that overlaps the cathode region in a plan view. In the back surface of the semiconductor substrate 10, a P+-type collector region may be provided in a region other than the cathode region. In this specification, sometimes the region where the diode portion 80 is extended along the Y-axis direction to the extended region 81 of the gate wiring described later is also included in the diode portion 80. A collector region is provided on the back surface of the extended region 81. The diode portion 80 has a P-type anode region on the front side of the semiconductor substrate 10.

[0070] The transistor portion 70 has a P+-type collector region in the region in contact with the back surface of the semiconductor substrate 10. In addition, the transistor portion 70 is periodically provided with an N-type emitter region, a P+-type contact region, a P-type base region, and a gate structure having a gate conductive portion and a gate insulating film on the front side of the semiconductor substrate 10.

[0071] The semiconductor device 100 may have one or more pads above the semiconductor substrate 10. The semiconductor device 100 of this example has a gate pad 164. The semiconductor device 100 may have pads such as an anode pad, a cathode pad, and a current detection pad as a temperature sensing portion of a PN junction diode. Each pad is disposed near the end edge 162. The vicinity of the end edge 162 refers to the region between the end edge 162 in a plan view and the emission electrode. When actually mounting the semiconductor device 100, each pad may be connected to an external circuit via wiring such as a wire.

[0072] A gate potential is applied to the gate pad 164. The gate pad 164 is electrically connected to the conductive portion of the gate trench portion of the active portion 160. The semiconductor device 100 includes a gate wiring that connects the gate pad 164 and the gate trench portion. In Figure 1 , the gate wiring is marked with diagonal hatching.

[0073] The gate wiring in this example has an outer peripheral gate wiring 130. The outer peripheral gate wiring 130 is disposed between the active portion 160 and the end edge 162 of the semiconductor substrate 10 in a plan view. The outer peripheral gate wiring 130 in this example surrounds the active portion 160 in a plan view. The region surrounded by the outer peripheral gate wiring 130 in a plan view may be set as the active portion 160. In addition, a well region is formed below the gate wiring. The well region is a P-type region having a concentration higher than that of the base region described later, and is formed from the front surface of the semiconductor substrate 10 to a position deeper than the base region. The region surrounded by the well region in a plan view may be set as the active portion 160.

[0074] The outer peripheral gate wiring 130 is connected to the gate pad 164. The outer peripheral gate wiring 130 is disposed above the semiconductor substrate 10. The outer peripheral gate wiring 130 may be a metal wiring including aluminum or the like, or a semiconductor such as polysilicon doped with impurities.

[0075] The semiconductor device 100 in this example further includes an active side gate wiring 131. The active side gate wiring 131 is provided in the active portion 160. By providing the active side gate wiring 131 in the active portion 160, the deviation of the wiring length measured from the gate pad 164 can be reduced for each region of the semiconductor substrate 10.

[0076] The outer peripheral gate wiring 130 and the active side gate wiring 131 are connected to the gate trench portion of the active portion 160. The outer peripheral gate wiring 130 and the active side gate wiring 131 are disposed above the semiconductor substrate 10. The outer peripheral gate wiring 130 and the active side gate wiring 131 may be wirings formed of a metal wiring including aluminum or the like, or a semiconductor such as polysilicon doped with impurities.

[0077] The active side gate wiring 131 may be connected to the outer peripheral gate wiring 130. The active side gate wiring 131 in this example extends from the outer peripheral gate wiring 130 on one side sandwiching the active portion 160 to the outer peripheral gate wiring 130 on the other side in a manner that substantially crosses the active portion 160 in the Y-axis direction. When the active portion 160 is divided by the active side gate wiring 131, the transistor portions 70 and the diode portions 80 may be alternately arranged in the X-axis direction in each divided region.

[0078] The semiconductor device 100 may include a temperature sensing portion (not shown), which is a PN junction diode formed of polysilicon or the like, and a current detection portion (not shown), which simulates the operation of the transistor portion provided in the active portion 160. The temperature sensing portion may dispose the anode pad and the cathode pad near the end edge 162. In addition, the current detection portion may dispose the current detection pad near the end edge 162.

[0079] When viewed from above, the semiconductor device 100 of this example has an edge terminal structure portion 90 between the active portion 160 and the end edge 162. The edge terminal structure portion 90 of this example is disposed between the peripheral gate wiring 130 and the end edge 162. The edge terminal structure portion 90 alleviates the electric field concentration on the front side of the semiconductor substrate 10. The edge terminal structure portion 90 may include at least one of a protection ring, a field plate, and a surface electric field reduction portion that is disposed in a ring shape surrounding the active portion 160.

[0080] Figure 2 is a magnified view showing an example of the region D in Figure 1 . The region D is a region including the transistor portion 70, the diode portion 80, and the active side gate wiring 131. Although it is omitted in Figure 1 , in the X-axis direction, a boundary region 200 is disposed between the transistor portion 70 and the diode portion 80. The boundary region 200 is a buffer structure for arranging structures different from the transistor portion 70 and the diode portion 80 side by side. The boundary region 200 is a region having a P+ type collector region in the region in contact with the back surface of the semiconductor substrate 10. The boundary region 200 of this example does not have an emitter region on the front surface of the semiconductor substrate 10.

[0081] The semiconductor device 100 of this example includes a gate trench portion 40, a dummy trench portion 30, a well region 11, an emitter region 12, a base region 14, a contact region 15, and an anode region 84 provided inside the front side of the semiconductor substrate 10. The gate trench portion 40 and the dummy trench portion 30 are each an example of a trench portion. In addition, the semiconductor device 100 of this example includes an emitter electrode 52 and an active side gate wiring 131 provided above the front surface of the semiconductor substrate 10. The emitter electrode 52 and the active side gate wiring 131 are provided separately from each other.

[0082] An interlayer insulating film is provided between the emitter electrode 52 and the front surface of the semiconductor substrate 10 and between the active side gate wiring 131 and the front surface of the semiconductor substrate 10, but it is omitted in Figure 2 . In the interlayer insulating film of this example, contact holes 54 are provided so as to penetrate the interlayer insulating film. In Figure 2 , each contact hole 54 is marked with oblique hatching.

[0083] The emission electrode 52 is disposed above the gate trench portion 40, dummy trench portion 30, well region 11, emission region 12, base region 14, contact region 15, and anode region 84. The emission electrode 52 is connected to the emission region 12, contact region 15, and base region 14 on the front surface of the semiconductor substrate 10 through contact holes 54. In addition, the emission electrode 52 is connected to the dummy conductive portion in the dummy trench portion 30 through a contact hole provided in the interlayer insulating film. The emission electrode 52 may be connected to the dummy conductive portion in the dummy trench portion 30 at the front end in the Y-axis direction of the dummy trench portion 30. The dummy conductive portion in the dummy trench portion 30 may not be connected to the emission electrode 52 and the gate conductive portion, or may be controlled to have a potential different from the potentials of the emission electrode 52 and the gate conductive portion.

[0084] The active-side gate wiring 131 is connected to the gate trench portion 40 through a contact hole provided in the interlayer insulating film. The active-side gate wiring 131 may be connected to the gate conductive portion of the gate trench portion 40 at the front end portion 41 in the Y-axis direction of the gate trench portion 40. The active-side gate wiring 131 is not connected to the dummy conductive portion in the dummy trench portion 30.

[0085] The emission electrode 52 is formed of a material containing metal. The emission electrode 52 is an example of a front electrode. In Figure 2 it, the range where the emission electrode 52 is provided is shown. For example, at least a part of the region of the emission electrode 52 is formed of aluminum or an alloy mainly composed of aluminum such as Al-Si, Al-Si-Cu and other metal alloys, copper or an alloy mainly composed of copper. The front electrode may have a barrier metal. In addition, the front electrode may have a contact plug portion in the contact hole. The contact plug portion has a barrier metal formed of titanium and titanium compounds etc. on the side surface of the contact hole, and a plug formed by embedding tungsten and / or copper etc. so as to be in contact with the barrier metal and the emission electrode 52. The contact plug portion connects the emission electrode 52 to the semiconductor substrate 10. The plug and the emission electrode 52 may be integrally formed.

[0086] The well region 11 is disposed overlapping the active-side gate wiring 131. The well region 11 is also disposed so as to extend with a predetermined width in a range where it does not overlap the active-side gate wiring 131. The well region 11 in this example is disposed separated from one end in the Y-axis direction of the contact hole 54 toward the active-side gate wiring 131 side. The well region 11 is a region of the second conductivity type having a doping concentration higher than the doping concentration of the base region 14. The base region 14 in this example is of P-type, and the well region 11 is of P+-type.

[0087] The transistor section 70, the diode section 80, and the boundary region 200 each have a plurality of trench sections arranged in a first direction. In the transistor section 70 of this example, one or more gate trench sections 40 and one or more dummy trench sections 30 are alternately provided in the first direction. In the diode section 80 of this example, a plurality of dummy trench sections 30 are provided in the first direction. In the diode section 80 of this example, no gate trench section 40 is provided. In the boundary region 200 of this example, a plurality of dummy trench sections 30 are provided in the first direction. In the boundary region 200 of this example, no gate trench section 40 is provided.

[0088] The gate trench section 40 of this example may have two linear portions 39 (portions of the trench that are linear in the second direction) extending in a second direction perpendicular to the first direction, and a front end portion 41 that connects the two linear portions 39. Figure 2 The second direction in [description] is the Y-axis direction.

[0089] Preferably, at least a part of the front end portion 41 is set to be curved in a plan view. By connecting the end portions of the two linear portions 39 in the Y-axis direction with the front end portion 41, it is possible to alleviate the electric field concentration at the end portions of the linear portions 39.

[0090] In the transistor section 70, the dummy trench sections 30 are provided between the respective linear portions 39 of the gate trench section 40. One dummy trench section 30 may be provided between the respective linear portions 39, or a plurality of dummy trench sections 30 may be provided. In the transistor section 70 of this example, two dummy trench sections 30 are provided between the respective linear portions 39. The dummy trench section 30 may have a linear shape extending in the second direction, or may have a linear portion 29 and a front end portion 31 similar to the gate trench section 40. Figure 2 The semiconductor device 100 shown only has the dummy trench section 30 having the front end portion 31, but may also have both a dummy trench section 30 having a linear shape without the front end portion 31 and a dummy trench section 30 having the front end portion 31.

[0091] The diffusion depth of the well region 11 may be deeper than the depths of the gate trench section 40 and the dummy trench section 30. The end portions of the gate trench section 40 and the dummy trench section 30 in the Y-axis direction are provided in the well region 11 in a plan view. That is, at the end portions of each trench section in the Y-axis direction, the bottom portion in the depth direction of each trench section is covered by the well region 11. Thereby, it is possible to alleviate the electric field concentration at the bottom portion of each trench section.

[0092] A mesa portion 60 is provided between the trench portions adjacent in the first direction. The mesa portion 60 refers to the region within the semiconductor substrate 10 that is clamped by the trench portions. The front surface of the mesa portion 60 in this example is the front surface of the semiconductor substrate 10. The depth position of the lower end of the mesa portion 60 is the same as the depth position of the lower end of the trench portion. The mesa portion 60 in this example is provided to extend along the trench in the second direction (Y-axis direction) on the front surface of the semiconductor substrate 10. The mesa portions 60 of the transistor portion 70, the mesa portions 60 of the diode portion 80, and the mesa portions 60 of the boundary region 200 may have different structures. When simply referred to as the mesa portion 60 in this specification, it respectively refers to the mesa portion 60 of the transistor portion 70, the mesa portion 60 of the diode portion 80, and the mesa portion 60 of the boundary region 200.

[0093] A base region 14 is provided in the mesa portions 60 of the transistor portion 70 and the boundary region 200, and a base region 14 and an anode region 84 are provided in the mesa portion 60 of the diode portion 80. In Figure 2 Although the base region 14 is shown disposed at one end portion in the second direction of each mesa portion, the base region 14 is also disposed at the other end portion of each mesa portion. In the mesa portion of the transistor portion 70, at least one of a first conductivity type emitter region 12 and a second conductivity type contact region 15 may be provided in the region clamped by the base region 14 in a top view. The emitter region 12 in this example is of N+ type, and the contact region 15 is of P+ type. The emitter region 12 and the contact region 15 may be provided between the base region 14 and the front surface of the semiconductor substrate 10 in the depth direction.

[0094] The mesa portion 60 of the transistor portion 70 has an emitter region 12 exposed on the front surface of the semiconductor substrate 10. The emitter region 12 is provided in contact with the gate trench portion 40. The mesa portion 60 in contact with the gate trench portion 40 may be provided with a contact region 15 exposed on the front surface of the semiconductor substrate 10.

[0095] The contact region 15 and the emitter region 12 in the mesa portion 60 are respectively provided from one trench portion in the X-axis direction to the other trench portion. As an example, the contact region 15 and the emitter region 12 of the mesa portion 60 are alternately arranged along the second direction (Y-axis direction) of the trench portion.

[0096] In another example, the contact region 15 and the emitter region 12 of the mesa portion 60 may be provided in a strip shape along the second direction (Y-axis direction) of the trench portion. For example, the emitter region 12 is provided in the region in contact with the trench portion, and the contact region 15 is provided in the region clamped by the emitter region 12. The emitter region 12 is not provided in the mesa portions 60 of the diode portion 80 and the boundary region 200 in this example.

[0097] On the front surface of the mesa portion 60 of the diode portion 80 in this example, a contact region 15 and an anode region 84 may be provided. The anode region 84 of the diode portion 80 may be disposed between the base regions 14 in the second direction (Y-axis direction), and the contact region 15 of the diode portion 80 may be disposed between the base region 14 and the anode region 84 in the second direction (Y-axis direction). The doping concentration of the anode region 84 may be the same as or different from the doping concentration of the base region 14. In this example, the doping concentration of the anode region 84 is the same as the doping concentration of the base region 14. The base region 14 and the anode region 84 in this example are P-type. The base region 14 and the anode region 84 can be formed by the same process, which is easy to manufacture.

[0098] On the front surface of the mesa portion 60 of the boundary region 200 in this example, a contact region 15 may be provided. The contact region 15 of the boundary region 200 may be clamped by the base region 14 in the second direction (Y-axis direction). Alternatively, on the front surface of the mesa portion 60 of the boundary region 200, an anode region 84 the same as that of the mesa portion 60 of the diode portion 80 may be provided. Alternatively, an N-type impurity region having the same doping concentration as the emitter region 12 or a doping concentration lower than that of the emitter region 12 may be provided on the mesa portion 60 of the boundary region 200. In this case, the gate trench portion 40 is not provided in the boundary region 200. In addition, the trench portion at the boundary position between the transistor portion 70 and the boundary region 200 is a dummy trench portion 30. On the mesa portion 60 of the boundary region 200, since the N-type impurity region does not contact the gate trench portion 40, an inversion layer is not formed and conduction does not occur.

[0099] The area ratio of the contact region 15 at the mesa portion 60 of the boundary region 200 may be greater than the area ratio of the contact region 15 at the mesa portion 60 of the diode portion 80. In this case, it is easy to extract holes in the semiconductor substrate 10 to the emitter electrode 52 via the mesa portion 60 of the boundary region 200.

[0100] Contact holes 54 are provided above each mesa portion 60. The contact holes 54 are disposed in a region clamped by the base region 14 or the anode region. The contact holes 54 in this example are provided above each of the regions of the contact region 15, the base region 14, and the emitter region 12. The contact holes 54 are not provided in the base region 14 and the well region 11. The contact holes 54 may be disposed at the center in the first direction (X-axis direction) of the mesa portion 60.

[0101] In the diode portion 80, an N+-type cathode region 82 is provided in a region adjacent to the back surface of the semiconductor substrate 10. On the back surface of the semiconductor substrate 10, a P+-type collector region 22 may be provided in a region where the cathode region 82 is not provided. The cathode region 82 and the collector region 22 are provided between the back surface 23 of the semiconductor substrate 10 and the buffer region 20. In Figure 2 it, the boundary between the cathode region 82 and the collector region 22 is shown by a dashed line.

[0102] The cathode region 82 is arranged separately from the well region 11 in the Y-axis direction. Thus, the distance between the P-type region (well region 11) with a relatively high doping concentration formed to a deep position and the cathode region 82 can be ensured, thereby improving the breakdown voltage. The end portion of the cathode region 82 in the Y-axis direction is arranged to be farther from the well region 11 than the end portion of the contact hole 54 in the Y-axis direction. In another example, the end portion of the cathode region 82 in the Y-axis direction can be arranged between the well region 11 and the contact hole 54.

[0103] Figure 3A is a diagram showing Figure 2 an example of the a-a cross-section in. The a-a cross-section is the XZ plane passing through the emitter region 12 and the cathode region 82. The semiconductor device 100 in this example has a semiconductor substrate 10, an interlayer insulating film 38, an emitter electrode 52, and a collector electrode 24 in this cross-section.

[0104] The interlayer insulating film 38 is provided on the front surface of the semiconductor substrate 10. The interlayer insulating film 38 is a film including at least one of insulating films such as silicate glass doped with impurities such as boron or phosphorus, thermal oxide films, and other insulating films. The contact hole 54 described in Figure 2 is provided in the interlayer insulating film 38.

[0105] The emitter electrode 52 is provided above the interlayer insulating film 38. The emitter electrode 52 is an example of a front electrode. The emitter electrode 52 can be connected to the semiconductor substrate 10 through the contact hole 54 in the interlayer insulating film 38. Alternatively, a contact plug portion can be provided in the contact hole 54 to connect the emitter electrode 52 and the semiconductor substrate 10. The contact plug portion can have a plug formed of tungsten or the like, and a titanium-containing barrier metal provided at a portion in contact with the semiconductor substrate 10. The barrier metal can have a titanium nitride layer, or can have a stacked structure of a titanium nitride layer and a titanium layer.

[0106] The collector electrode 24 is provided on the back surface 23 of the semiconductor substrate 10. The emitter electrode 52 and the collector electrode 24 are formed of a metal material such as aluminum. In this specification, the direction (Z-axis direction) connecting the emitter electrode 52 and the collector electrode 24 is referred to as the depth direction.

[0107] The semiconductor substrate 10 has an N-type drift region 18. The drift region 18 is provided in the transistor portion 70, the diode portion 80, and the boundary region 200, respectively.

[0108] In this example, among the plurality of stepped portions 60, there are a first stepped portion 61, a third stepped portion 63, and a fourth stepped portion 64. The first stepped portion 61 is provided in the transistor portion 70, the third stepped portion 63 is provided in the diode portion 80, and the fourth stepped portion 64 is provided in the boundary region 200.

[0109] On the first mesa surface 61 of the transistor section 70, an N+-type emitter region 12 and a P-type base region 14 are sequentially provided from the front surface 21 side of the semiconductor substrate 10. A drift region 18 is provided below the base region 14. An N+-type accumulation region 16 may be provided on the first mesa surface 61. The accumulation region 16 is disposed between the base region 14 and the drift region 18.

[0110] The emitter region 12 is exposed on the front surface 21 of the semiconductor substrate 10 and is provided in contact with the gate trench portion 40. The emitter region 12 may be in contact with the trench portions on both sides of the mesa portion 60. The doping concentration of the emitter region 12 is higher than that of the drift region 18.

[0111] The base region 14 is provided below the emitter region 12. The base region 14 of this example is provided in contact with the emitter region 12. The base region 14 may be in contact with the trench portions on both sides of the first mesa surface 61.

[0112] The accumulation region 16 is provided below the base region 14. The accumulation region 16 is an N+-type region with a doping concentration higher than that of the drift region 18. That is, the donor concentration of the accumulation region 16 is higher than that of the drift region 18. By providing a high-concentration accumulation region 16 between the drift region 18 and the base region 14, the carrier injection promotion effect (IE effect) can be improved and the conduction voltage can be reduced. The accumulation region 16 may be provided to cover the entire back surface of the base region 14 in the first mesa surface 61.

[0113] On the third mesa surface 63 of the diode section 80, an anode region 84 is provided in contact with the front surface 21 of the semiconductor substrate 10. The doping concentration of the anode region 84 may be the same as that of the base region 14 or lower than that of the base region 14. In this example, the doping concentration of the anode region 84 is the same as that of the base region 14. The base region 14 and the anode region 84 of this example are P-type. A drift region 18 is provided below the anode region 84. An accumulation region 16 may be provided below the anode region 84.

[0114] In the fourth mesa surface of the boundary region 200 of this example, a base region 14 is provided, and a contact region 15 is provided on the front side of the base region 14. The contact region 15 is clamped by the base region 14 in the second direction (Y-axis direction). Thus, in the turn-off operation, holes in the semiconductor substrate 10 are easily extracted to the emitter electrode 52 via the fourth mesa surface 64 of the boundary region 200. A drift region 18 is provided below the base region 14. In the fourth mesa surface 64, an accumulation region 16 may be provided below the base region 14.

[0115] It should be noted that in Figure 3A , the boundary region 200 is shown as having one fourth mesa surface 64, but it is not limited thereto. The boundary region 200 may be provided over one or several degrees of mesa surfaces 60 (fourth mesa surface 64).

[0116] In the transistor section 70, the diode section 80, and the boundary region 200, an N+-type buffer region 20 can be provided under the drift region 18. The doping concentration of the buffer region 20 is higher than that of the drift region 18. The buffer region 20 can have a concentration peak with a doping concentration higher than that of the drift region 18. The doping concentration of the concentration peak refers to the doping concentration at the apex of the concentration peak. Additionally, the doping concentration of the drift region 18 can use the average value of the doping concentration in a region where the doping concentration distribution is substantially flat.

[0117] The buffer region 20 can have two or more concentration peaks in the depth direction (Z-axis direction) of the semiconductor substrate 10. The concentration peaks of the buffer region 20 can be set at the same depth position as, for example, the chemical concentration peaks of hydrogen (protons) or phosphorus. The buffer region 20 can function as a field stop layer to prevent the depletion layer expanding from the lower end of the base region 14 from reaching the P+-type collector region 22 and the N+-type cathode region 82.

[0118] In the transistor section 70, a P+-type collector region 22 is provided under the buffer region 20. The acceptor concentration of the collector region 22 is higher than that of the base region 14. The collector region 22 can contain the same acceptor as the base region 14 or a different acceptor from the base region 14. The acceptor of the collector region 22 is, for example, boron or aluminum.

[0119] In the diode section 80, an N+-type cathode region 82 is provided under the buffer region 20. The donor concentration of the cathode region 82 is higher than that of the drift region 18. The donor of the cathode region 82 is, for example, hydrogen or phosphorus. It should be noted that the elements serving as donors and acceptors in each region are not limited to the above examples.

[0120] In the boundary region 200, a P+-type collector region 22 is provided under the buffer region 20. That is, the boundary region 200 can be regarded as a part of the transistor section 70. The collector region 22 of the boundary region 200 can have the same doping concentration as that of the boundary region 200 of the transistor section 70. The boundary position in the X-axis direction between the cathode region 82 and the collector region 22 can be set as the boundary position in the X-axis direction between the diode section 80 and the boundary region 200.

[0121] In another example, in the boundary region 200, a part or all of the collector region 22 can be replaced with the cathode region 82. When the cathode region 82 is provided on the back surface of the boundary region 200, the region where the contact regions 15 and the anode region 84 are alternately arranged in the region clamped by the anode region 84 can be set as the diode section 80, and the region where the contact regions 15 are arranged in the entire region clamped by the anode region 84 can be set as the boundary region 200. When the cathode region 82 is provided on the back surface of the boundary region 200, the boundary region 200 can also be regarded as a part of the diode section 80.

[0122] Of the two trench portions that are connected to the emission region 12 closest to the diode portion 80 in the X-axis direction, the trench portion on the diode portion 80 side may be a dummy trench portion 30. In this case, the dummy trench portion 30 can be set as the boundary position in the X-axis direction between the transistor portion 70 and the boundary region 200 (or the diode portion 80). The central position of the dummy trench portion 30 in the X-axis direction can be set as the boundary position in the X-axis direction between the transistor portion 70 and the boundary region 200 (or the diode portion 80).

[0123] An emission region 12 may be provided in the boundary region 200. In this case, the gate trench portion 40 is not provided in the boundary region 200. In addition, the trench portion at the boundary position between the transistor portion 70 and the boundary region 200 is the dummy trench portion 30. That is, no transistor operation occurs in the boundary region 200. A gate trench portion 40 may also be provided in the boundary region 200. In this case, the emission region 12 is not provided in the boundary region 200. That is, no transistor operation occurs in the boundary region 200.

[0124] The collector region 22 and the cathode region 82 are exposed on the back surface 23 of the semiconductor substrate 10 and are connected to the collector electrode 24. The collector electrode 24 may be in contact with the entire back surface 23 of the semiconductor substrate 10. The emitter electrode 52 and the collector electrode 24 are formed of a metal material such as aluminum.

[0125] The semiconductor device 100 of this example includes a lifetime adjustment region 206 that contains a lifetime inhibitor for adjusting the lifetime of carriers. The lifetime adjustment region 206 of this example is a region where the lifetime of charge carriers is locally small. Charge carriers are electrons or holes. Sometimes charge carriers are simply referred to as carriers. The lifetime adjustment region 206 of this example is formed by irradiating a particle beam. Here, in the case of simply referring to a particle beam, it includes a particle beam composed of charged particles such as helium ions and protons and an electron beam. The lifetime adjustment region 206 of this example is formed by injecting a particle beam from the front surface 21 side of the semiconductor substrate 10. The particle beam may also be injected from the back surface 23 side of the semiconductor substrate 10.

[0126] In this example, the concentration distribution of helium or the like in the depth direction of the semiconductor substrate 10 may have a shape that trails from the lifetime adjustment region 206 to the front surface 21 of the semiconductor substrate 10. That is, the concentration of helium or the like ( / cm 3)(It) can monotonically decrease from the lifetime adjustment region 206 to the front surface 21. The concentration of helium or the like on the front surface 21 can be greater than 0. On the other hand, in the direction from the lifetime adjustment region 206 toward the back surface 23, the concentration of helium or the like can also have a shape like a trailing tail. Among them, the concentration of helium or the like in the trailing tail toward the back surface 23 decreases more sharply than the concentration of helium charged particles in the trailing tail toward the front surface 21. The concentration of helium or the like on the back surface 23 is lower than the concentration of helium charged particles on the front surface 21. The concentration of helium or the like on the front surface 21 can be below the measurement limit or can be 0.

[0127] By irradiating the semiconductor substrate 10 with a particle beam to inject charged particles, lattice defects 204 such as vacancies are formed in the vicinity of the injection position. The lattice defects 204 generate recombination centers. The lattice defects 204 can be mainly single-atom vacancies (V), multi-atom vacancies (VV), etc., can be dislocations, can also be interstitial atoms, and can also be transition metals or the like. For example, the atoms adjacent to the vacancies have dangling bonds. In a broad sense, donors and acceptors can also be included in the lattice defects 204, but in this specification, the lattice defects 204 mainly composed of vacancies are sometimes referred to as vacancy-type lattice defects, vacancy-type defects, or simply lattice defects. In this specification, the lattice defects 204 are sometimes simply referred to as recombination centers or lifetime inhibitors as recombination centers that contribute to the recombination of carriers. The lifetime inhibitor can be formed by injecting helium ions into the semiconductor substrate 10. The helium chemical concentration can be set as the density of the lattice defects 204. It should be noted that since the lifetime inhibitor formed by injecting helium ions is sometimes hydrogen-capped by the hydrogen present in the buffer layer 20, the depth position of the density peak of the lifetime inhibitor sometimes does not coincide with the depth position of the helium chemical concentration peak. In addition to this, in the case of injecting hydrogen ions into the semiconductor substrate 10, the lifetime inhibitor can be formed in the passage region of the hydrogen ions closer to the injection surface side than the range of the hydrogen ions.

[0128] The lattice defects 204 are an example of a lifetime inhibitor. In Figure 3A Figure, the lattice defects 204 at the injection position of the charged particles are schematically shown by × marks. In the region where a large amount of lattice defects 204 remain, the carriers are captured by the lattice defects 204, so the lifetime of the carriers becomes short. By adjusting the lifetime of the carriers, characteristics such as the reverse recovery time and reverse recovery loss of the diode section 80 can be adjusted. In the depth direction of the semiconductor substrate 10, the position where the carrier lifetime exhibits a minimum value can be set as the depth position of the lifetime adjustment region 206.

[0129] It should be noted that when an electron beam, a particle beam, etc. used to form the lifetime adjustment region 206 pass through the gate trench portion 40, defects may be generated near the interface between the gate insulating film 42 and the semiconductor substrate 10. Further, if there is a metal such as Ti having a hydrogen storage effect near the gate trench portion 40, the hydrogen that is stored and diffused may block the hydrogen termination of the dangling bonds in the gate trench portion 40, causing the threshold voltage to vary.

[0130] In this example, the lifetime adjustment region 206 is disposed on the front surface 21 side of the semiconductor substrate 10. Here, the front surface 21 side of the semiconductor substrate 10 refers to the region from the central position in the depth direction of the semiconductor substrate 10 to the front surface 21 of the semiconductor substrate 10. The lifetime adjustment region 206 of this example is disposed at a position lower than the lower end of the trench portion. Further, when the lifetime adjustment region 206 is formed by irradiating a particle beam with strong transmission force such as an electron beam, lattice defects are formed substantially uniformly from the front surface 21 to the back surface 23 of the semiconductor substrate 10. In this case, however, it can also be regarded that the depth position of the lifetime adjustment region 206 is disposed on the front surface 21 side of the semiconductor substrate 10.

[0131] The lifetime adjustment region 206 can be provided in at least one of the transistor portion 70 and the diode portion 80. When the semiconductor device 100 has the boundary region 200, the lifetime adjustment region 206 can also be provided in the boundary region 200. The lifetime adjustment region 206 can be provided so as to extend in at least a part or the whole of the diode portion 80 in the first direction (X-axis direction). The lifetime adjustment region 206 can be provided so as to extend in at least a part or the whole of the transistor portion 70 in the first direction (X-axis direction). The lifetime adjustment region 206 can also be provided in the entire boundary region 200. In another example, the lifetime adjustment region 206 can also be provided in a part of the boundary region 200.

[0132] The lifetime adjustment region 206 of this example is provided so as to extend throughout the transistor portion 70 and the diode portion 80 in the first direction (X-axis direction). That is, the lifetime adjustment region 206 of this example is also provided so as to extend throughout the boundary region 200 in the first direction (X-axis direction).

[0133] As described above, the doping concentration of the anode region 84 in this example is the same as the doping concentration of the base region 14. By including the lifetime adjustment region 206, the reverse recovery loss of the diode portion 80 of the semiconductor device 100 of this example is reduced, and thus the doping concentration of the anode region 84 can be increased to the same level as the doping concentration of the base region 14. Thereby, the base region 14 and the anode region 84 can be formed by the same process, facilitating manufacturing.

[0134] In addition, the lifetime adjustment region 206 of this example is provided so as to extend throughout the transistor portion 70 in the first direction (X-axis direction), and thus hole injection from the contact region 15 of the transistor portion 70 can be suppressed. As a result, it can be provided so as to extend over a plurality of mesa portions 60 of the boundary region 200 in the first direction (X-axis direction), and the area of the ineffective region where transistor operation is not performed can be reduced.

[0135] On the front surface 21 side of the semiconductor substrate 10, one or more gate trench portions 40 and one or more dummy trench portions 30 are provided. Each trench portion is provided from the front surface 21 of the semiconductor substrate 10 through the base region 14 or the anode region 84 to below the base region 14 and the anode region 84. In a region where at least any one of the emitter region 12, the contact region 15, and the storage region 16 is provided, each trench portion also penetrates these doped regions. The method in which the trench portion penetrates the doped region is not limited to a method of manufacturing in the order of forming the trench portion after forming the doped region. A method of forming a doped region between the trench portions after forming the trench portion is also included in the method in which the trench portion penetrates the doped region.

[0136] As described above, the gate trench portion 40 and the dummy trench portion 30 are provided in the transistor portion 70. The dummy trench portion 30 is provided in the diode portion 80 and the boundary region 200 of this example, and the gate trench portion 40 is not provided. Among them, a gate trench portion 40 or a dummy trench portion 30 may be arranged at the boundary between the boundary region 200 and the transistor portion 70.

[0137] The gate trench portion 40 has a gate trench provided on the front surface 21 of the semiconductor substrate 10, a gate insulating film 42, and a gate conductive portion 44. The gate insulating film 42 is provided so as to cover the inner wall of the gate trench. The gate insulating film 42 may be formed by oxidizing or nitriding the semiconductor on the inner wall of the gate trench. The gate conductive portion 44 is provided at a position closer to the inside than the gate insulating film 42 inside the gate trench. That is, the gate insulating film 42 insulates the gate conductive portion 44 from the semiconductor substrate 10. The gate conductive portion 44 is formed of a conductive material such as polysilicon.

[0138] The gate conductive portion 44 may be provided longer than the base region 14 in the depth direction. In this cross section, the gate trench portion 40 on the front surface 21 of the semiconductor substrate 10 is covered with an interlayer insulating film 38. The gate conductive portion 44 is electrically connected to the gate wiring. When a predetermined gate voltage is applied to the gate conductive portion 44, a channel formed by an inversion layer of electrons is formed on the surface layer of the interface in the base region 14 that is in contact with the gate trench portion 40.

[0139] The dummy trench portion 30 may have the same structure as the gate trench portion 40 in this cross-section. The dummy trench portion 30 has a dummy trench provided on the front surface 21 of the semiconductor substrate 10, a dummy insulating film 32, and a dummy conductive portion 34. The dummy conductive portion 34 is electrically connected to the emission electrode 52. The dummy insulating film 32 is provided so as to cover the inner wall of the dummy trench. The dummy conductive portion 34 is provided inside the dummy trench and at a position closer to the inside than the dummy insulating film 32. The dummy insulating film 32 insulates the dummy conductive portion 34 from the semiconductor substrate 10. The dummy conductive portion 34 may be formed of the same material as the gate conductive portion 44. For example, the dummy conductive portion 34 is formed of a conductive material such as polysilicon. The dummy conductive portion 34 may have the same length as the gate conductive portion 44 in the depth direction.

[0140] In this example, the gate trench portion 40 and the dummy trench portion 30 on the front surface 21 of the semiconductor substrate 10 are covered with the interlayer insulating film 38. It should be noted that the bottoms of the dummy trench portion 30 and the gate trench portion 40 may be a curved surface protruding downward (curved in cross-section).

[0141] A first contact portion 77 is provided on the first stepped surface portion 61 in this example. On the first stepped surface portion 61, the region where the first stepped surface portion 61 is connected to the front electrode in the first contact portion 77 corresponds to the contact portion.

[0142] A second contact portion 87 where the front electrode is in contact with the front surface of the third stepped surface portion 63 is provided on the third stepped surface portion 63 in this example. The second contact portion 87 is the portion where the front electrode (i.e., the emission electrode 52 or the contact plug portion) is provided inside the stepped surface portion 60. By forming a groove in the front surface 21 of the semiconductor substrate 10 exposed by the contact hole 54 and filling the groove with the front electrode, the second contact portion 87 can be formed. In the second contact portion 87, the region where the third stepped surface portion 63 is connected to the front electrode corresponds to the contact portion. The first contact portion 77 is disposed at a position higher than the second contact portion 87.

[0143] The second contact portion 87 is provided on the fourth stepped surface portion 64 in this example. Alternatively, the first contact portion 77 may be provided on a part of the fourth stepped surface portion 64, and the second contact portion 87 may be provided on the other fourth stepped surface portion 64.

[0144] In this example, each contact portion refers to the interface where the front electrode is in contact with the stepped surface portion 60. The contact portion may include the surface of the front electrode and the surface of the stepped surface portion 60. Here, in the case of the first contact portion 77, the surface of the stepped surface portion 60 refers to the front surface of the stepped surface portion 60, that is, the front surface 21 of the semiconductor substrate 10. In the case of the second contact portion 87, the surface of the stepped surface portion 60 refers to the bottom surface of the contact hole 54 provided inside the stepped surface portion 60.

[0145] It should be noted that when a metal silicide layer is formed at the interface between the front electrode and the mesa portion 60, the metal silicide layer may be included in the front electrode. That is, the interface between the metal silicide layer and the mesa portion 60 can be set as the contact portion.

[0146] In this example, by providing the second contact portion 87 in the diode portion 80, the region with a high doping concentration near the front surface 21 of the semiconductor substrate 10 is removed, so that the second contact portion 87 is in contact with the region with a low doping concentration among the anode regions 84. Thereby, the reverse recovery loss of the diode portion 80 can be reduced.

[0147] Figure 3B It is in Figure 3A An enlarged view near the contact hole 54 provided in the first mesa portion 61, the third mesa portion 63, and the fourth mesa portion 64 shown. Figure 3B One first mesa portion 61, one third mesa portion 63, and one fourth mesa portion 64 are shown respectively, and the regions between the mesa portions are omitted.

[0148] The emission electrode 52 of this example is provided on the front surface of the interlayer insulating film 38. The contact plug portion 250 includes a plug 251 and a barrier metal portion 252. The plug 251 of this example contains tungsten. The barrier metal portion 252 is provided above the front surface 21 of the semiconductor substrate 10. The barrier metal portion 252 is provided at least on the bottom surface of the contact hole 54. The barrier metal portion 252 can be provided at each contact portion. The barrier metal portion 252 can be in contact with the semiconductor substrate 10. The barrier metal portion 252 can also be provided on the side surface of the contact hole 54. The plug 251 is buried into the contact hole 54 through the barrier metal portion 252. The plug 251 and the barrier metal portion 252 can be provided on the front surface of the interlayer insulating film 38 or not provided on the front surface of the interlayer insulating film 38.

[0149] The intrusion of the metal elements of the plug 251 and / or the ions contained in the external environment into the semiconductor substrate 10 is suppressed by the barrier metal portion 252. The barrier metal portion 252 can contain at least one metal element among titanium (Ti), cobalt (Co), nickel (Ni), tantalum (Ta), magnesium (Mg), vanadium (V), lanthanum (La), palladium (Pd), or zirconium (Zr). The barrier metal portion 252 can be a metal having a hydrogen storage effect. The barrier metal portion 252 of this example has a titanium (Ti) layer. The barrier metal portion 252 can contain a titanium nitride layer. The barrier metal portion 252 can also be a laminated film of a titanium layer and a titanium nitride layer.

[0150] The emission electrode 52 is provided above the barrier metal portion 252. The emission electrode 52 is also provided above the interlayer insulating film 38. The emission electrode 52 is formed of a material different from that of the barrier metal portion 252. As an example, the emission electrode 52 contains aluminum. The emission electrode 52 can be an alloy of aluminum and silicon.

[0151] Figure 3B Shows the depth Z1 of the first contact portion 77 and the depth Z2 of the second contact portion 87 in the depth direction (Z-axis direction) of the semiconductor substrate 10. In this example, the first contact portion 77 is provided on the first mesa surface 61, and the second contact portion 87 is provided on the third mesa surface 63 and the fourth mesa surface 64.

[0152] Here, the depths of the first contact portion 77 and the second contact portion 87 refer to the distance measured from the front surface 21 of the semiconductor substrate 10 at the deepest position at the interface where the semiconductor substrate 10 is in contact with the front electrode on the bottom surface of the contact hole 54. The depth Z2 of the second contact portion 87 can be greater than the depth Z1 of the first contact portion 77.

[0153] The first contact portion 77 of this example is in contact with the front surface 21 of the semiconductor substrate 10. Accordingly, the depth Z1 of the first contact portion 77 is zero. The first contact portion 77 can be arranged at a position deeper than the front surface 21 of the semiconductor substrate 10. In addition, the depth Z2 of the second contact portion 87 of this example is greater than the depth Z1 of the first contact portion 77. That is, the second contact portion 87 is arranged at a position farther from the front surface 21 of the semiconductor substrate 10 than the first contact portion 77.

[0154] In this example, by providing the first contact portion 77 in the transistor portion 70, the surface area (total area of the side surface and the bottom surface) of the contact hole 54 provided in the transistor portion 70 becomes smaller than the surface area of the contact hole 54 provided in the diode portion 80. Accordingly, in the contact hole 54 provided in the transistor portion 70, the area of the barrier metal portion 252 becomes relatively small, and the amount of the Ti layer in the barrier metal portion 252 also becomes relatively small. Thereby, it is possible to suppress the variation in the threshold voltage caused by the Ti layer having a hydrogen storage effect.

[0155] Figure 4A Is a diagram showing Figure 2 An example of the b-b cross section in. The b-b cross section is the XZ plane passing through the contact region 15 and the cathode region 82. In Figure 4A The contact region 15 is arranged in the b-b cross section of, instead of Figure 3A The emitter region 12 in the a-a cross section shown. In addition, a plug region of the second conductivity type is provided below the contact hole 54. Other structures are the same as those in the a-a cross section, and thus the description thereof is omitted here.

[0156] The first face 61 of this example has a first plug region 221 of P++ type, the first plug region 221 is disposed below the first contact portion 77, and the doping concentration is higher than the doping concentration of the contact region 15. The first plug region 221 can be grounded with the first contact portion 77. At least a part of the first plug region 221 is disposed in a manner that overlaps with the contact region 15 in a top view. It can be disposed in a manner that the entire first plug region 221 overlaps with the contact region 15. That is, the first plug region 221 is provided in any XZ cross-section passing through the contact region 15. The first plug region 221 can be provided in the XZ cross-section at the center in the Z-axis direction passing through the contact region 15.

[0157] In this example, from Figure 3A it can be seen that the first plug region 221 may not be provided in the XZ cross-section passing through the emitter region 12. That is, the first plug region 221 can be provided below the contact region 15 and not below the emitter region 12. For example, the first plug region 221 is not provided in the XZ cross-section at the center in the Z-axis direction passing through the emitter region 12. That is, the first plug region 221 does not overlap with the emitter region 12 in a top view, and the first plug region 221 is intermittently provided in the second direction (Y-axis direction). By providing each plug region, it is easy to extract holes in each face portion. Therefore, a reduction in withstand voltage can be suppressed. In another example, as long as the first plug region 221 does not completely obstruct the connection between the emitter region 12 and the first contact portion 77, it can be provided below the emitter region 12 and can also be provided to extend in the second direction (Y-axis direction).

[0158] The third face 63 may have a second plug region 222 of P++ type, the second plug region 222 is disposed below the second contact portion 87, and the doping concentration is higher than the doping concentration of the contact region 15. The second plug region 222 can be grounded with the second contact portion 87.

[0159] Alternatively, similar to the above first plug region 221, the second plug region 222 may not be provided in the XZ cross-section passing through the emitter region 12, and the second plug region 222 is intermittently provided below the contact region 15 in the second direction (Y-axis direction). Similar to the first plug region 221, the second plug region 222 of this example is intermittently provided in the second direction (Y-axis direction), and the second plug region 222 is not provided in the XZ cross-section at the center in the Z-axis direction passing through the emitter region 12. Thereby, injection of holes from the third face 63 into the drift region 18 can be suppressed, and reverse recovery loss can be reduced.

[0160] In another example, the intervals, widths, and positions intermittently provided in the second direction (Y-axis direction) of the second plugging region 222 of the third face 63 can be set in a manner different from the intervals, widths, and positions of the emission region 12 of the first face 61. For the second plugging region 222 of each third face 63, it can also be set in a manner different from the intervals, widths, and positions of the second plugging regions 222 of other third faces 63. The second plugging region 222 can be provided to extend in the second direction (Y-axis direction).

[0161] The fourth face 64 can have a second plugging region 222 below the second contact portion 87. The structure of the second plugging region 222 in the fourth face 64 is the same as that of the second plugging region 222 in the third face 63, so the description is omitted.

[0162] Figure 4B is at Figure 4A An enlarged view near the contact hole 54 provided in the first face 61, the third face 63, and the fourth face 64 shown. In this example, a first plugging region 221 is provided below the first contact portion 77, and a second plugging region 222 is provided below the second contact portion 87. Since other parts are the same as Figure 3B the same, the description is omitted. By providing each plugging region, holes can be easily extracted in each face. Therefore, the reduction of the tolerance can be suppressed.

[0163] Figure 4C is a diagram showing Figure 2 another example of the b-b cross-section in Figure 4D is at Figure 4C An enlarged view near the contact hole 54 provided in the first face 61, the third face 63, and the fourth face 64 shown. In this example, no first plugging region 221 and second plugging region 222 are provided below the contact region 15 and the anode region 84. That is, no plugging region is provided in the semiconductor device 100 of this example. Thereby, the injection of holes can be suppressed, and the reverse recovery loss can be reduced.

[0164] It should be noted that when no plugging region is provided, neither the first contact portion 77 nor the second contact portion 87 is provided with a contact plugging portion 250, that is, a plug 251 and a barrier metal portion 252. Similarly, no plug 251 and barrier metal portion 252 are provided at the position where the first contact portion 77 is in contact with the emission region 12.

[0165] Figure 5A is a diagram showing Figure 2 another example of the a-a cross-section in Figure 5B is a diagram showing Figure 2Another example of the cross-section taken along line b-b. In this example, different from the above example, a first contact portion 77 is provided on the fourth stepped surface portion 64 of the boundary region 200 instead of the second contact portion 87. Thus, a first plug region 221 is provided below the first contact portion 77 on the fourth stepped surface portion 64 of the boundary region 200.

[0166] The first plug region 221 of the fourth stepped surface portion 64 in this example can be arranged in the same configuration as the second plug region 222 of the fourth stepped surface portion 64 described using Figure 4A In such a configuration, the same effects as those of the above configuration can also be obtained.

[0167] Figure 6 It shows Figure 1 Another enlarged view of region D in Figure 7A It shows Figure 6 An example of the cross-section taken along line c-c in Figure 7B It shows Figure 6 An example of the cross-section taken along line d-d in . The difference between this example and the above example is that no boundary region 200 is provided between the transistor portion 70 and the diode portion 80.

[0168] In addition, the lifetime adjustment region 206 in this example is arranged to extend from the diode portion 80 over a part of the transistor portion 70 in the second direction (Y-axis direction). By providing the lifetime adjustment region 206 in at least a part of the transistor portion 70, the semiconductor device 100 in this example can reduce the area of the inactive region where transistor operation does not occur without providing a wide boundary region 200. An example of providing a wide boundary region 200 will be described later. In the transistor portion 70, the region where the lifetime adjustment region 206 is provided is set as the adjustment region 201, and the region where the lifetime adjustment region 206 is not provided is set as the non-adjustment region 202. The configuration of the diode portion 80 is the same as that of the above example, so the description thereof is omitted.

[0169] The adjustment region 201 in this example has a first contact portion 77 provided on the first stepped surface portion 61. The first contact portion 77 can be provided with respect to a part of the first stepped surface portion 61, or can be provided with respect to all of the first stepped surface portion 61. Alternatively, the second contact portion 87 can also be provided with respect to all of the first stepped surface portion 61. The first stepped surface portion 61 of the adjustment region 201 has the same structure as the above first stepped surface portion 61, so the description thereof is omitted.

[0170] The non-adjustment region 202 of this example has a first contact portion 77 provided on the second mesa 62. The non-adjustment region 202 is a region where the carrier lifetime at the same depth position as the lifetime adjustment region 206 is longer than the carrier lifetime of the lifetime adjustment region 206 of the diode portion 80. The non-adjustment region 202 may also be a region where charged particles such as helium for forming lifetime inhibitors such as lattice defects 204 are not implanted. The chemical concentration ( / cm 3 ) of charged particles such as helium in the non-adjustment region 202 may be the same as the chemical concentration at the center in the Z-axis direction of the drift region 18 of the charged particles.

[0171] The first contact portion 77 of this example is disposed at a position lower than the front surfaces of the first mesa 61 and the second mesa 62. The depth of the first contact portion 77 may be 1 / 2 or less of the depth of the second contact portion 87, or may be 1 / 4 or less of the depth. The first contact portion 77 may also be in contact with the front surface 21 of the semiconductor substrate 10, and the depth Z1 of the first contact portion 77 may be zero.

[0172] The doping concentration of the anode region 84 of this example may be the same as the doping concentration of the base region 14. Since the semiconductor device 100 of this example includes the lifetime adjustment region 206, the reverse recovery loss of the diode portion 80 is reduced, so that the doping concentration of the anode region 84 can be increased to the same level as that of the base region 14. Thus, the base region 14 and the anode region 84 can be formed by the same process, which is easy to manufacture. In another example, the doping concentration of the anode region 84 may be lower than the doping concentration of the base region 14, and the reverse recovery loss can be further reduced.

[0173] In addition, the second plug region 222 of this example is provided to extend in the second direction (Y-axis direction). Since the semiconductor device 100 of this example includes the lifetime adjustment region 206, the reverse recovery loss of the diode portion 80 is reduced, so that the second plug region 222 can be provided to extend, which can promote the extraction of holes and suppress the decrease in withstand voltage.

[0174] It should be noted that in another example, the plug region may be intermittently provided as described in Figure 3A 、 Figure 3B 、 Figure 4A and Figure 4B , or may not be provided as described in Figure 4C and Figure 4D .

[0175] Figure 8 is an enlarged view showing another example of the region D in Figure 1 . Figure 9A is a view showing an example of the e-e cross section in Figure 8 . Figure 9B is Figure 9AAn enlarged view near the second face 62, the third face 63, and the fourth face 64 shown. Figure 9C is a diagram showing Figure 8 an example of the f-f cross section in

[0176] In this example, the width of the boundary region 200 is greater than Figure 2 the width of the boundary region 200 shown. The width W of the boundary region 200 of this example in the first direction (X-axis direction) can be 20 μm or more and 250 μm or less, preferably 30 μm or more and 200 μm or less, and more preferably 50 μm or more and 100 μm or less.

[0177] In this example, the lifetime adjustment region 206 is provided to extend from the diode portion 80 to the boundary region 200 in the first direction (X-axis direction). That is, the lifetime adjustment region 206 of this example is not provided in the transistor portion 70. Alternatively, the semiconductor device 100 may not have the lifetime adjustment region 206.

[0178] In this example, by providing the boundary region 200 widely over a plurality of fourth faces 64, it is possible to suppress the influence of the transistor portion 70 on the characteristics of the diode portion 80. For example, it is possible to suppress the operation of the gate trench portion 40, the discharge or injection of holes in the contact region 15 from affecting the forward voltage and / or reverse recovery characteristics. Therefore, the transistor portion 70 may not be provided in the lifetime adjustment region 206 of this example.

[0179] In the boundary region 200 of this example, a third contact portion 207 is provided on the fourth face 64. As Figure 9B shown, the third contact portion 207 is arranged at a position higher than the second contact portion 87 and at a position lower than the first contact portion 77. That is, the depth Z3 of the third contact portion 207 is greater than the depth of the first contact portion 77 and less than the depth Z2 of the second contact portion 87. The depth Z3 of the third contact portion 207 can be a depth of 1 / 2 or less, or 1 / 4 or less, of the depth Z2 of the second contact portion 87. Thus, in this example, by providing the shallow third contact portion 207 in the boundary region 200, it is possible to reduce the amount of the Ti layer of the barrier metal portion 252 while promoting the extraction of holes to prevent latch-up.

[0180] In another example, as Figure 3A 、 Figure 3B 、 Figure 4A and Figure 4B described, the boundary region 200 may be provided with the first contact portion 77 or the second contact portion 87. In addition, in the example described using Figures 2 to 5B , the third contact portion 207 of this example may be provided in the boundary region 200.

[0181] In the boundary region 200 of this example, an anode region 84 is provided on the front surface of the fourth mesa 64, and the contact region 15 is not provided. That is, the structure of the front surface of the fourth mesa 64 is the same as the structure of the front surface of the third mesa 63. In addition, the doping concentration of the anode region 84 in this example is lower than the doping concentration of the base region 14. In another example, the doping concentration of the anode region 84 may be the same as the doping concentration of the base region 14.

[0182] In addition, in Figure 9A and Figure 9C , a first plug region 221 and a second plug region 222 are provided in the XZ cross-section passing through the contact region 15, and the first plug region 221 and the second plug region 222 are not provided in the XZ cross-section passing through the emitter region 12. Thus, the first plug region 221 and the second plug region 222 in this example are intermittently provided in the second direction (Y-axis direction). Thereby, the injection of holes is suppressed, and even if the width W of the lifetime adjustment region 206 is small, the reverse recovery loss can be reduced. It should be noted that, in another example, the plug region may be intermittently or continuously provided as described in Figure 3A , Figure 3B , Figure 4A and Figure 4B , or may not be provided as described in Figure 4C and Figure 4D .

[0183] As described above, although the present invention has been described by way of embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It is obvious to those skilled in the art that various changes or improvements can be made to the above embodiments. According to the description of the claims, the embodiments with such changes or improvements can also be included in the technical scope of the present invention.

[0184] It should be noted that, as long as the execution order of each process such as the actions, sequences, steps, and stages in the devices, systems, programs, and methods shown in the claims, the specification, and the drawings is not specifically indicated as "before...", "in advance", etc., and the result of the previous process is not used in the subsequent process, it can be implemented in any order. Even for convenience, the use of "first", "next", etc. to describe the action flow in the claims, the specification, and the drawings does not mean that it must be implemented in this order.

Claims

1. A semiconductor device, characterized in that, Comprising: A transistor section; A diode section; A plurality of trench sections provided on the front surface of a semiconductor substrate; A drift region of a first conductivity type provided in the semiconductor substrate; A base region of a second conductivity type provided above the drift region in the transistor section; A first conductivity type emitter region and a second conductivity type contact region, both provided on the front surface of the semiconductor substrate in the transistor section, and the doping concentration of the emitter region is higher than that of the drift region, and the doping concentration of the contact region is higher than that of the base region; A second conductivity type anode region provided above the drift region in the diode section; A mesa portion of the semiconductor substrate provided between the plurality of trench sections; An interlayer insulating film provided above the semiconductor substrate; A front electrode provided above the semiconductor substrate; A contact portion for connecting the front electrode to the mesa portion through a contact hole in the interlayer insulating film; and A lifetime adjustment region provided on the front side of the semiconductor substrate, The contact portion has a first contact portion provided in the transistor section and a second contact portion provided in the diode section, The first contact portion is disposed at a position higher than that of the second contact portion.

2. The semiconductor device according to claim 1, wherein The semiconductor device includes a second conductivity type second plug region provided below the second contact portion and having a doping concentration higher than that of the contact region.

3. The semiconductor device according to claim 2, wherein The second plug region is provided to extend in the trench extending direction.

4. The semiconductor device according to claim 2, wherein The second plug region is provided intermittently in the trench extending direction.

5. The semiconductor device according to claim 1, wherein The semiconductor device includes a second conductivity type first plug region provided below the first contact portion and having a doping concentration higher than that of the contact region.

6. The semiconductor device according to claim 5, wherein The first plug region is provided intermittently in the trench extending direction.

7. The semiconductor device according to claim 5, wherein The first plug region is provided above the contact region and not above the emitter region.

8. The semiconductor device according to claim 1, wherein The semiconductor device includes a barrier metal portion provided on the side surface of the contact hole, The barrier metal portion has a Ti layer.

9. The semiconductor device according to claim 1, wherein The semiconductor device includes a first conductivity type storage region in the transistor section provided above the drift region and having a doping concentration higher than that of the drift region.

10. The semiconductor device according to claim 1, wherein The front electrode includes an emitter electrode provided above the interlayer insulating film.

11. The semiconductor device according to claim 10, wherein The front electrode includes a contact plug portion which is disposed in the contact hole and connects the emission electrode to the mesa portion.

12. The semiconductor device according to claim 1, wherein the diode portion has the lifetime adjustment region.

13. The semiconductor device according to claim 1, wherein the transistor portion has the lifetime adjustment region.

14. The semiconductor device according to claim 13, wherein the lifetime adjustment region of the transistor portion is formed by irradiation with a particle beam.

15. The semiconductor device according to claim 13, wherein the lifetime adjustment region is disposed to extend over the entire transistor portion and the diode portion in the trench arrangement direction.

16. The semiconductor device according to claim 13, wherein the lifetime adjustment region is disposed to extend from the diode portion to a part of the transistor portion in the trench arrangement direction.

17. The semiconductor device according to claim 1, wherein the doping concentration of the anode region is lower than that of the base region.

18. The semiconductor device according to claim 1, wherein the doping concentration of the anode region is the same as that of the base region.

19. The semiconductor device according to claim 1, wherein the first contact portion is in contact with the front surface of the mesa portion.

20. The semiconductor device according to claim 1, wherein the first contact portion is disposed at a position lower than the front surface of the mesa portion.

21. The semiconductor device according to claim 1, wherein the semiconductor device includes a boundary region which is disposed between the transistor portion and the diode portion.

22. The semiconductor device according to claim 21, wherein the lifetime adjustment region is disposed to extend from the diode portion to the boundary region in the trench arrangement direction.

23. The semiconductor device according to claim 21, wherein the width of the boundary region in the trench arrangement direction is 20 μm or more and 250 μm or less.

24. The semiconductor device according to claim 21, wherein the contact portion of the boundary region is the third contact portion, the third contact portion is disposed at a position higher than the second contact portion and at a position lower than the first contact portion.

25. The semiconductor device according to claim 21, wherein the contact portion of the boundary region is the second contact portion.

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