Semiconductor device and power equipment

Abstract

The invention discloses a semiconductor device and power equipment. The semiconductor device comprises a substrate; the buffer layer is positioned on one side of the substrate; the channel layer is located on the side, away from the substrate, of the buffer layer; the barrier layer is located on the side, away from the buffer layer, of the channel layer; the groove penetrates through the barrier layer and the channel layer and extends into the buffer layer; the groove is filled with the ohmic contact layer; the source and drain electrode metal layer is located on the side, away from the substrate, of the ohmic contact layer, and the source and drain electrode metal layer comprises a source electrode and a drain electrode; the gate metal layer is located on the side, away from the channel layer, of the barrier layer, and the gate metal layer comprises a gate and an anode; the passivation layer comprises a first via hole and a second via hole, the orthographic projection of the first via hole on the substrate and the orthographic projection of the source electrode on the substrate are mutually overlapped, and the orthographic projection of the second via hole on the substrate and the orthographic projection of the anode on the substrate are mutually overlapped; the source electrode field plate layer is connected with the source electrode and the anode through the first via hole and the second via hole, and the source electrode field plate layer and the grid electrode are mutually insulated through the passivation layer.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular, to a semiconductor device and a power device. Background Art

[0002] The breakdown voltage characteristics of semiconductor power devices are mainly closely related to the bandgap width of semiconductor materials. Gallium oxide (Ga2O3), as a new type of wide-bandgap semiconductor material, has an ultra-wide bandgap width of 4.8 eV to 4.9 eV, an ultra-high critical breakdown field strength of 8 MV / cm, and a Baliga figure of merit as high as 3444, which is 10 times that of silicon carbide (SiC) and 3444 times that of silicon (Si). In semiconductor manufacturing processes, gallium oxide materials have the advantages of enabling 10 14 ~10 20 cm -3 controllable n-type doping, low-cost wafers, etc., and can be used to fabricate high-voltage power devices with ultra-low losses.

[0003] In power conversion circuits such as DC-DC converters and resonant converters, when the power transistor switches to the off state, the induced electromotive force across the inductor coil in the circuit will generate a large peak current and reverse voltage on the transistor in the circuit, thereby damaging the device. In metal-oxide-semiconductor field-effect transistors (MOSFETs) based on silicon (Si) and silicon carbide (SiC), due to the presence of a body diode, the stored charge can be released in the off state to protect the device.

[0004] High electron mobility transistors (HEMTs) based on gallium oxide materials have advantages such as high electron mobility and can be applied in fields such as radio frequency power. However, in high electron mobility transistors, due to the absence of a body diode, in practical applications, when the switching speed is too fast, the turn-off loss is very large, the device is easily damaged, and the efficiency decreases. If the scheme of externally anti-parallel connected freewheeling diodes is adopted, although it has the ability to release the reverse current, it increases the area and cost, and will also introduce additional parasitic inductance and capacitance, bringing new reliability problems. Summary of the Invention

[0005] Embodiments of the present disclosure provide a semiconductor device and a power device, which can have high electron mobility and high breakdown field strength while reducing the reverse conduction loss of the device, and solve the problems of large parasitic impedance, high cost, poor reliability, and high noise of externally anti-parallel diodes.

[0006] The semiconductor device and the power device provided by the embodiments of the present disclosure are specifically as follows: On the one hand, embodiments of the present disclosure provide a semiconductor device, including: A substrate; A buffer layer located on one side of the substrate; The channel layer is located on the side of the buffer layer away from the substrate; The barrier layer is located on the side of the channel layer away from the buffer layer; The trench penetrates through the barrier layer and the channel layer and extends into the buffer layer; The ohmic contact layer fills the trench; The source-drain metal layer is located on the side of the ohmic contact layer away from the substrate, and the source-drain metal layer includes a source and a drain; The gate metal layer is located on the side of the barrier layer away from the channel layer, and the gate metal layer includes a gate and an anode; The passivation layer includes a first via hole and a second via hole. Among them, the orthographic projection of the first via hole on the substrate overlaps with the orthographic projection of the source on the substrate, and the orthographic projection of the second via hole on the substrate overlaps with the orthographic projection of the anode on the substrate; The source field plate layer connects the source and the anode through the first via hole and the second via hole, and the source field plate layer is insulated from the gate through the passivation layer.

[0007] In some embodiments, in the above semiconductor device provided by the embodiments of the present disclosure, a δ-doped layer is further included, and the δ-doped layer is located between the channel layer and the barrier layer.

[0008] In some embodiments, in the above semiconductor device provided by the embodiments of the present disclosure, the material of the δ-doped layer includes at least one of Si and Sn, and (Al x Ga 1-x )2O3, 0.01 ≤ x ≤ 0.5.

[0009] In some embodiments, in the above semiconductor device provided by the embodiments of the present disclosure, the doping concentration of Si and / or Sn in the δ-doped layer is 10 18 cm -3 ~10 20 cm -3 .

[0010] In some embodiments, in the above semiconductor device provided by the embodiments of the present disclosure, the thickness of the channel layer is 1 nm to 5 nm.

[0011] In some embodiments, in the above semiconductor device provided by the embodiments of the present disclosure, the material of the buffer layer includes Ga2O3, and the material of the channel layer includes (Al y Ga 1-y )2O3, 0.1 ≤ y ≤ 0.5.

[0012] In some embodiments, in the above-mentioned semiconductor device provided by the embodiments of the present disclosure, the doping concentration of Si and / or Sn in the δ-doped layer is 10 16 cm -3 ~10 18 cm -3 。

[0013] In some embodiments, in the above-mentioned semiconductor device provided by the embodiments of the present disclosure, the thickness of the channel layer is 1 nm to 10 nm, and the material of the channel layer includes (Al y Ga 1-y )2O3, where 0.01 ≤ y ≤ 0.15.

[0014] In some embodiments, in the above-mentioned semiconductor device provided by the embodiments of the present disclosure, a p-type layer is further included, and the p-type layer is disposed between the gate and the barrier layer.

[0015] On the other hand, the embodiments of the present disclosure provide a power device including the above-mentioned semiconductor device provided by the embodiments of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 is a schematic structural diagram of a semiconductor device provided by an embodiment of the present disclosure; Figure 2 is Figure 1 the equivalent circuit diagram of the semiconductor device shown; Figure 3 is Figure 1 the off-state schematic diagram of the semiconductor device shown; Figure 4 is Figure 1 the on-state schematic diagram of the semiconductor device shown; Figure 5 is Figure 1 the schematic diagram of the semiconductor device shown switching from the on-state to the off-state; Figure 6 is Figure 1 the schematic diagram of the semiconductor device shown switching from the off-state to the on-state; Figure 7 is another schematic structural diagram of a semiconductor device provided by an embodiment of the present disclosure; Figure 8 is Figure 1 a schematic structural diagram of the semiconductor device shown during the manufacturing process; Figure 9 is Figure 1 another schematic structural diagram of the semiconductor device shown during the manufacturing process; Figure 10 is Figure 1 another schematic structural diagram of the semiconductor device shown during the manufacturing process; Figure 11 Another schematic structural diagram of the semiconductor device during the preparation process shown in Figure 1 Figure 1 Figure 12 Another schematic structural diagram of the semiconductor device during the preparation process shown in Figure 1 Figure 1 Figure 13 Another schematic structural diagram of the semiconductor device during the preparation process shown in Figure 1 Figure 1 Figure 14 Another schematic structural diagram of the semiconductor device during the preparation process shown in Figure 1 Figure 1 Figure 15 Another schematic structural diagram of the semiconductor device during the preparation process shown in Figure 1 Figure 1 Figure 16 Another schematic structural diagram of the semiconductor device during the preparation process shown in Figure 1 Figure 1 Detailed implementation manners

[0017] To make the objectives, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present disclosure. It should be noted that the implementation manners described in the present disclosure should not be construed as limited to the specific shapes of the regions shown in the present disclosure, but include deviations in terms of shapes caused by, for example, manufacturing. For example, a region illustrated or described as flat may typically have rough and / or non-linear features; the sharp corners illustrated may be rounded, etc. And the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. To keep the following description of the embodiments of the present disclosure clear and concise, detailed descriptions of known functions and known components are omitted in the present disclosure.

[0018] Unless otherwise defined, the technical terms or scientific terms used herein shall have the ordinary meanings as understood by those of ordinary skill in the art to which the present disclosure pertains. The "first", "second" and similar terms used in the specification and claims of the present disclosure do not denote any order, quantity or importance, but are only used to distinguish different components. The terms such as "including" or "comprising" mean that the elements or items appearing before this word cover the elements or items listed after this word and their equivalents, without excluding other elements or items. The terms such as "connected" or "coupled" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. The terms such as "inside", "outside", "above", "below", etc. are only used to represent relative positional relationships, and when the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0019] In the following description, when an element or layer is referred to as being "on" or "connected to" another element or layer, the element or layer can be directly on the other element or layer, directly connected to the other element or layer, or there can be intermediate elements or intermediate layers. When an element or layer is referred to as being "disposed on one side of" another element or layer, the element or layer can be directly on one side of the other element or layer, directly connected to the other element or layer, or there can be intermediate elements or intermediate layers. However, when an element or layer is referred to as being "directly on" or "directly connected to" another element or layer, there are no intermediate elements or layers. The term "and / or" includes any and all combinations of one or more of the associated listed items.

[0020] Figure 1 A semiconductor device structure provided by an embodiment of the present disclosure is shown. Figure 2 is Figure 1 the equivalent circuit diagram of the semiconductor device shown. As Figure 1 and Figure 2 shown, the semiconductor device of the present disclosure may include: A substrate 101. In some embodiments, the substrate 101 may employ a Fe\Mg-doped semi-insulating homogeneous gallium oxide (Ga2O3) substrate or a heterogeneous material substrate such as Si, sapphire, SiC, diamond, etc. Among them, the resistivity in the Fe\Mg semi-insulating gallium oxide (Ga2O3) can be , for example . The thickness of the substrate 101 can be 100 μm to 650 μm, such as 150 μm, 200 μm, 250 μm, 300 μm, 350 μm, 400 μm, 450 μm, 500 μm, 550 μm, 600 μm, etc.

[0021] A buffer layer 102, a channel layer 103, and a barrier layer 104 are sequentially disposed on the substrate 101. A trench V is provided in the buffer layer 102, the channel layer 103, and the barrier layer 104. The trench V can penetrate the barrier layer 104 and the channel layer 103 and extend into the buffer layer 102. The depth of the trench V can be 40 nm to 60 nm, such as 45 nm, 50 nm, 55 nm, etc.; an n-type heavily doped "n+" Ga2O3 can be regrown in the trench V as an ohmic contact layer 105. Optionally, to ensure the ohmic contact effect, the doping concentration of the n-type impurity in Ga2O3 can be , for example .

[0022] The source-drain metal layer 106 is located on the side of the ohmic contact layer 105 away from the substrate 101. The source-drain metal layer 106 may include a source electrode S and a drain electrode D. The source-drain metal layer 106 may be a multi-layer structure such as a titanium / gold (Ti / Au) stack, a titanium / aluminum / nickel / gold (Ti / Al / Ni / Au) stack, etc. In some embodiments, the source-drain metal layer 106 may also be a single-layer structure.

[0023] The gate metal layer 107 is located on the side of the barrier layer 104 away from the channel layer 103. The gate metal layer 107 may include a gate G and an anode SG. The materials of the gate metal layer 107 include but are not limited to platinum (Pt), nickel (Ni), gold (Au), copper (Cu), etc. The gate metal layer 107 may be a single-layer structure or a multi-layer structure.

[0024] The passivation layer 108 includes a first via hole H1 and a second via hole H2. Among them, the orthographic projection of the first via hole H1 on the substrate 101 overlaps with the orthographic projection of the source electrode S on the substrate 101 (for example, the orthographic projection of the first via hole H1 on the substrate 101 and the orthographic projection of the source electrode S on the substrate 101 only partially coincide, or the orthographic projection of the first via hole H1 on the substrate 101 is located within the orthographic projection of the source electrode S on the substrate 101, or the orthographic projection of the source electrode S on the substrate 101 is located within the orthographic projection of the first via hole H1 on the substrate 101). The orthographic projection of the second via hole H2 on the substrate 101 overlaps with the orthographic projection of the anode SG on the substrate 101 (for example, the orthographic projection of the second via hole H2 on the substrate 101 and the orthographic projection of the anode SG on the substrate 101 partially coincide, or the orthographic projection of the second via hole H2 on the substrate 101 is located within the orthographic projection of the anode SG on the substrate 101, or the orthographic projection of the anode SG on the substrate 101 is located within the orthographic projection of the second via hole H2 on the substrate 101). The material used for the passivation layer 108 may be materials such as silicon dioxide, silicon nitride, etc. The thickness of the passivation layer 108 may be 0.01 μm to 1 μm, such as 0.05 μm, 0.1 μm, 0.2 μm, 0.3 μm, 0.4 μm, 0.5 μm, 0.6 μm, 0.7 μm, 0.8 μm, 0.9 μm, etc.

[0025] The source field plate layer 109 can connect the source electrode S and the anode SG through the first via hole H1 and the second via hole H2, and the source field plate layer 109 is insulated from the gate G through the passivation layer 108. The material of the source field plate layer 109 may be the same as the material of the source-drain metal layer 106.

[0026] In the above semiconductor device provided by the embodiments of the present disclosure, the substrate 101, buffer layer 102, channel layer 103, barrier layer 104, ohmic contact layer 105, passivation layer 108, source electrode S, drain electrode D and gate electrode G constitute a high electron mobility transistor (HEMT). There is a Schottky contact between the anode SG and the barrier layer 104, and the anode SG is electrically connected to the source electrode S through the source field plate layer 109. In this way, the monolithic integration of the Schottky diode (SBD) and the high electron mobility transistor (HEMT) is realized. Therefore, the problems of large parasitic impedance, high cost, poor reliability and high noise of the externally anti-parallel diode can be solved, and the packaging difficulty is also reduced. Moreover, the presence of the source field plate layer 109 can also relieve the aggregation of the peak electric field and improve the breakdown voltage of the device; the heterojunction formed by the buffer layer 102 and the channel layer 103 can effectively separate the doped region and the channel region, avoid the scattering of ionized impurities, and greatly improve the two-dimensional electron gas (2DEG) at the interface between the two, which can reduce the reverse conduction loss while ensuring the advantages of high electron mobility, high breakdown voltage and high threshold voltage.

[0027] In some embodiments, Figure 3 Fig. shows a schematic diagram of the semiconductor device of the present disclosure in the off state. As Figure 3 can be seen, at this time, the gate-source voltage difference Vgs of the high electron mobility transistor (HEMT) is less than the threshold voltage Vth, and the drain-source voltage difference Vds is greater than 0V, and there is no current path. Figure 4 Fig. shows a schematic diagram of the semiconductor device of the present disclosure in the on state. As Figure 4 can be seen, at this time, the gate-source voltage difference Vgs of the high electron mobility transistor (HEMT) is greater than or equal to the threshold voltage Vth, and the drain-source voltage difference Vds is greater than 0V, and the current conducts forward from the drain electrode D to the source electrode S. Figure 5 Fig. shows a schematic diagram of the semiconductor device of the present disclosure switching from the on state to the off state. As Figure 5 can be seen, at this time, the gate-source voltage difference Vgs of the high electron mobility transistor (HEMT) is less than the threshold voltage Vth, and the turn-on voltage Von,SBD of the Schottky diode (SBD) is greater than the drain-source voltage difference Vds and less than 0V, and the semiconductor device conducts in the reverse direction through the integrated Schottky diode (SBD). Among them, Figure 5 the "-" in "-Von,SBD" indicates that the current direction is opposite to Figure 4 the current direction in the on state shown. Figure 6 Fig. shows a schematic diagram of the semiconductor device of the present disclosure switching from the off state to the on state. As Figure 6 can be seen, at this time, the gate-source voltage difference Vgs of the high electron mobility transistor (HEMT) is greater than the threshold voltage Vth, and the turn-on voltage Von,SBD of the Schottky diode (SBD) is greater than the drain-source voltage difference Vds and less than 0V, and the semiconductor device conducts in the reverse direction through the integrated Schottky diode (SBD) and flows from the source electrode S to the drain electrode D.

[0028] In some embodiments, in the above semiconductor device provided by the embodiments of the present disclosure, such as Figure 1 shown, it may further include a δ-doped layer 110 (which may also be referred to as a delta-doped layer or a delta doping layer). The δ-doped layer 110 is located between the channel layer 103 and the barrier layer 104. In the related art, for a high electron mobility transistor (HEMT) to achieve high mobility, generally, the thickness of the channel layer 103 needs to be set above 200 nm. Limited by the short-channel effect, it is not suitable for fabricating high-frequency devices with a small gate length. By providing a δ-doped layer 110 between the channel layer 103 and the barrier layer 104, the impurity ions are fixed in the lattice, and the electrons provided enter the adjacent channel layer, forming a two-dimensional electron gas with a high concentration, thereby improving the electron mobility and making it suitable for high-frequency devices.

[0029] In some embodiments, the doping material of the δ-doped layer 110 includes at least one of Si and Sn. The main material of the δ-doped layer 110 may be (Al x Ga 1-x )2O3, where 0.01 ≤ x ≤ 0.5. Specifically, x may be 0.1, 0.2, 0.3, 0.4, etc. The thickness of the δ-doped layer 110 may be 1 nm to 5 nm, such as 2 nm, 3 nm, 4 nm, etc. By reducing the doping concentration of Si and / or Sn in the δ-doped layer 110, and / or increasing the thickness of the channel layer 103, the threshold voltage of the high electron mobility transistor (HEMT) can be gradually changed from a negative value to a positive value, that is, the high electron mobility transistor (HEMT) can be changed from a depletion type to an enhancement type. Optionally, in the depletion-type high electron mobility transistor (HEMT) of the present disclosure, the thickness of the channel layer 103 may be 1 nm to 5 nm (such as 2 nm, 3 nm, 4 nm, etc.), and the doping concentration of Si and / or Sn in the δ-doped layer 110 is 10 18 cm -3 ~10 20 cm -3 , such as 10 19 cm -3 ; in the enhancement-type high electron mobility transistor (HEMT) of the present disclosure, the thickness of the channel layer 103 is 1 nm to 10 nm, such as 2 nm, 3 nm, 4 nm, 5 nm, 6 nm, 7 nm, 8 nm, 9 nm, etc., and the doping concentration of Si and / or Sn in the δ-doped layer 110 is 10 16 cm -3 ~10 18 cm -3 , such as 10 17 cm -3 .

[0030] In some embodiments, in the above semiconductor device provided by the embodiments of the present disclosure, the material of the buffer layer 102 includes Ga2O3, and the material of the channel layer 103 includes (Aly Ga 1-y )2O3, the crystal phase of Ga2O3 is the same as that of (Al y Ga 1-y )2O3, 0.1 ≤ y ≤ 0.5, and specific y can be 0.3, 0.4, etc. Ga2O3 can be in crystal phases such as α, β, γ, δ, ε(κ), etc. Correspondingly, (Al y Ga 1-y )2O3 adopts the same crystal phases as Ga2O3, such as α, β, γ, δ, ε(κ), etc. The crystal phase of Ga2O3 being the same as that of (Al y Ga 1-y )2O3 is equivalent to being able to homoepitaxially grow (Al y Ga 1-y )2O3 on Ga2O3. Thus, it can ensure better film quality and is beneficial to generating a high-density two-dimensional electron gas at the Ga2O3 / (Al y Ga 1-y )2O3 interface; and in the (Al y Ga 1-y )2O3 of the channel layer 103, when the Al component concentration is 0.1 ≤ y ≤ 0.5, it can also increase the concentration of the two-dimensional electron gas, thereby increasing the saturation current density of the high electron mobility transistor HEMT, which is suitable for depletion-mode high electron mobility transistor HEMT.

[0031] In some embodiments, during the epitaxial growth of the channel layer 103, it can be regulated by MOCVD or MBE to reduce the doping concentration in the channel layer 103, thereby effectively reducing the concentration of the two-dimensional electron gas at the interface between the channel layer 103 and the buffer layer 102, making the two-dimensional electron gas easier to deplete and achieving an enhancement-mode operation (threshold voltage greater than 0V). Optionally, in the (Al y Ga 1-y )2O3 of the channel layer 103 included in the enhancement-mode high electron mobility transistor HEMT, the Al component concentration is 0.01 ≤ y ≤ 0.15, and specific y can be 0.02, 0.03, 0.04, 0.05, 0.06, 0.07, 0.08, 0.09, 0.1, 0.11, 0.12, 0.13, 0.14, etc.

[0032] In some embodiments, Figure 7 Another structural schematic diagram of the semiconductor device provided by the embodiments of the present disclosure is given. As Figure 7As shown, the semiconductor device of the present disclosure may further include a p-type layer 111 disposed between the gate G and the barrier layer 104. By introducing a layer of p-type material, such as p-type NiO, Cu2O, etc., under the gate G, it can help deplete the carriers in the channel under the gate G, thereby enabling an enhancement-mode operation. Further, the threshold voltage can be adjusted by controlling the concentration and thickness of the p-type layer 111 under the gate G. The higher the concentration and the thicker the thickness of the p-type layer 111, the threshold voltage of the device will gradually shift to the right, causing the threshold voltage to change from less than 0V to greater than 0V, which is equivalent to the high electron mobility transistor (HEMT) changing from depletion mode to enhancement mode.

[0033] On the other hand, the embodiments of the present disclosure also provide a method for manufacturing a semiconductor device. The following takes the Figure 1 manufacturing process of the semiconductor device shown as an example for illustrative description.

[0034] First step, as Figure 8 shown, an unintentionally doped buffer layer 102 is epitaxially grown on the substrate 101 by methods such as MOCVD, MBE, pulsed laser deposition (PLD), etc. Optionally, the substrate 101 is an Fe-doped Ga2O3 substrate, the buffer layer 102 is β-phase Ga2O3, the thickness of the buffer layer 102 is 100 nm to 600 nm, such as 200 nm, 300 nm, 400 nm, 500 nm, etc. The Ga2O3 contained in the substrate 101 can have the same crystal phase as the Ga2O3 contained in the buffer layer 102, such as α-phase, β-phase, etc.

[0035] Second step, as Figure 9 shown, a channel layer 103, a δ-doped layer 110, and a barrier layer 104 are sequentially epitaxially grown on the buffer layer 102. Among them, the material of the channel layer 103 includes β-phase (Al y Ga 1-y )2O3, the material of the δ-doped layer 110 includes (Al x Ga 1-x )2O3, the material of the barrier layer 104 includes (Al z Ga 1-z )2O3. Among them, the crystal phases of (Al x Ga 1-x )2O3 and (Al z Ga 1-z )2O3 can be the same as that of (Al y Ga 1-y) The crystal phases of (Al

[0036] The third step is as Figure 10 shown. Deposit 500 nm thick SiO2 as a hard mask by means of PECVD or ICP-CVD, etc. Define the ohmic contact regions of the source S and the drain D through lithography, and etch away the SiO2 in the regions to be made into ohmic contacts through ICP-RIE and CF4 gas. Then, use ICP etching of BCl3 and Ar gas to etch out a trench V with a depth of 40 nm to 60 nm. Regrow n-type heavily doped Ga2O3 as the ohmic contact layer 105 in the ohmic contact regions where the trench V is located, and wet-etch away the Ga2O3 except for the ohmic contact regions where the trench V is located through BOE solution. The crystal phase of the n-type heavily doped Ga2O3 can be the same as or different from that of (Al y Ga 1-y )2O3.

[0037] The fourth step is as Figure 11 shown. Evaporate the source-drain metal layer 106 on the ohmic contact layer 105 by electron beam evaporation, and perform rapid annealing to enhance the ohmic contact quality; and use an ICP-RIE device to perform mesa isolation based on dry etching of BCl3 / Ar to separately prepare the source S and the drain D.

[0038] The fifth step is as Figure 12 shown. Evaporate the gate metal layer 107 on the barrier layer 104 by electron beam evaporation as a Schottky contact, and use an ICP-RIE device to perform mesa isolation based on dry etching of BCl3 / Ar to separately prepare the gate G and the anode SG.

[0039] The sixth step is as Figure 13 shown. Deposit a layer of silicon oxide, silicon nitride, etc. as the passivation layer 108 through PECVD, and perform dry etching on the passivation layer 108 to form a first via hole H1 overlapping with the source S and a second via hole H2 overlapping with the anode SG.

[0040] In some embodiments, as Figure 14 shown, the present disclosure may also first deposit a layer of silicon oxide, silicon nitride, etc. as the first passivation layer 1081 through PECVD, and perform dry etching on the first passivation layer 1081 to form a third via hole H3 for preparing the gate G and a first sub-via hole H21 for preparing the anode SG. Then, as Figure 15As shown, a gate G is formed in the third via hole H3, and an anode SG is formed in the first sub-via hole H21. After that, as Figure 16 shown, a second passivation layer 1082 is formed to cover the gate G and have a second sub-via hole H21 at the anode SG. At the same time, a first via hole H1 penetrating the second passivation layer 1082 is also provided at the source S. Among them, the second sub-via hole H21 and the first sub-via hole H21 together constitute a second via hole H2. The material of the second passivation layer 1082 can be the same as that of the first passivation layer 1081.

[0041] The seventh step, as Figure 1 shown, the source field plate layer 109 is used to connect the anode SG and the source S, so as to realize the integration of the Schottky diode SBD in the high electron mobility transistor HEMT.

[0042] Based on the same inventive concept, the embodiments of the present disclosure provide a power device including the above semiconductor device provided by the embodiments of the present disclosure. Since the principle of solving problems of this power device is similar to that of the above semiconductor device, therefore, the implementation of this power device provided by the embodiments of the present disclosure can refer to the implementation of the above semiconductor device provided by the embodiments of the present disclosure, and the repeated parts will not be described again.

[0043] In some embodiments, the above power device provided by the embodiments of the present disclosure may include but are not limited to: radio frequency amplifiers, mixers, radars, satellites, power supplies, automotive electronics, energy-saving lamps, home appliances, etc. Of course, in addition to including semiconductor devices, the power device provided by the present disclosure may also include other structures. For example, when the power device is a radar, it further includes: a transmitter, an antenna, a receiver, etc.; when the power device is a mixer, it may further include: input ports and output ports, etc.

[0044] As can be seen from the above, in the semiconductor device of the present disclosure, a gallium oxide high electron mobility transistor with a source field plate layer is integrated in an anti-parallel manner with a Schottky diode, providing an additional low-resistance path for the reverse current to flow through at the Schottky diode when the high electron mobility transistor is reverse turned off, realizing low conduction loss and uniform reverse current distribution. This semiconductor device has a two-dimensional electron gas (2DEG) at the (Al x Ga 1-x )2O3 / Ga2O3 interface, which can reduce the reverse conduction loss while ensuring advantages such as high electron mobility, high breakdown voltage, and high threshold voltage. Since it is a monolithic integrated anti-parallel diode in the high electron mobility transistor, it can solve the problems of large parasitic impedance, high cost, poor reliability, and high noise of the external anti-parallel diode.

[0045] Although the preferred embodiments of the present disclosure have been described, additional changes and modifications can be made to these embodiments by those skilled in the art once they learn the basic creative concept. Therefore, the appended claims are intended to be interpreted to include the preferred embodiments as well as all changes and modifications that fall within the scope of the present disclosure.

[0046] Obviously, those skilled in the art can make various changes and modifications to the embodiments of the present disclosure without departing from the spirit and scope of the embodiments of the present disclosure. Thus, if these modifications and variations of the embodiments of the present disclosure fall within the scope of the claims of the present disclosure and their equivalent technologies, the present disclosure also intends to include these modifications and variations.

Claims

1. A semiconductor device, characterized in that, Comprising: A substrate; A buffer layer located on one side of the substrate; A channel layer located on the side of the buffer layer away from the substrate; A barrier layer located on the side of the channel layer away from the buffer layer; A trench penetrating through the barrier layer and the channel layer and extending into the buffer layer; An ohmic contact layer filling the trench; A source-drain metal layer located on the side of the ohmic contact layer away from the substrate, the source-drain metal layer including a source and a drain; A gate metal layer located on the side of the barrier layer away from the channel layer, the gate metal layer including a gate and an anode; A passivation layer including a first via and a second via, wherein a positive projection of the first via on the substrate overlaps with a positive projection of the source on the substrate, and a positive projection of the second via on the substrate overlaps with a positive projection of the anode on the substrate; A source field plate layer, the source field plate layer connecting the source and the anode through the first via and the second via, and the source field plate layer being insulated from the gate through the passivation layer.

2. The semiconductor device according to claim 1, wherein, Further comprising a δ-doping layer located between the channel layer and the barrier layer.

3. The semiconductor device according to claim 2, wherein The material of the delta-doped layer includes at least one of Si and Sn, and (Al x Ga 1-x )2O3, 0.01≤x≤0.

5.

4. The semiconductor device according to claim 3, characterized in that, The doping concentration of Si and / or Sn in the δ-doped layer is 10 18 cm -3 ~10 20 cm -3 。 5. The semiconductor device according to any one of claims 2 to 4, characterized in that, The thickness of the channel layer is 1 nm to 5 nm.

6. The semiconductor device according to any one of claims 1 to 4, characterized in that, The material of the buffer layer includes Ga2O3, and the material of the channel layer includes (Al y Ga 1-y )2O3, where 0.1 ≤ y ≤ 0.

5.

7. The semiconductor device according to claim 3, wherein The doping concentration of Si and / or Sn in the δ-doped layer is 10 16 cm -3 ~10 18 cm -3 。 8. The semiconductor device according to any one of claims 2, 3, and 7, characterized in that, The thickness of the channel layer is 1 nm to 10 nm, and the material of the channel layer includes (Al y Ga 1-y )2O3, where 0.01 ≤ y ≤ 0.

15.

9. The semiconductor device according to any one of claims 2, 3, and 7, characterized in that, Further comprising a p-type layer disposed between the gate and the barrier layer.

10. A power device, characterized in that, Comprising the semiconductor device according to any one of claims 1 to 9.

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