Semiconductor device and forming method thereof

Abstract

A semiconductor device and a method of forming the same wherein the semiconductor device has a substrate of a first conductivity type, an epitaxial layer formed on the substrate and having the first conductivity type, a first element, and a second element electrically connected to the first element. The first element comprises a first gate trench structure and a first shielding part, and the substrate serves as a drain electrode of the first element. The second element includes a second gate trench structure, a planar gate structure and a second shielding portion. The first and second gate trench structures extend into the epitaxial layer from a top surface of the epitaxial layer. The planar gate structure is on the top surface of the epitaxial layer. The first shielding part is located below the first gate trench structure and is in contact with the bottom of the first gate trench structure. The second shielding part is located below the second gate trench structure and is in contact with the bottom of the second gate trench structure. The first shielding portion and the second shielding portion have a second conductivity type.

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a method of forming the same, and more particularly to a semiconductor device that integrates elements with different driving current directions on the same substrate and a method of forming the same. Background Art

[0002] The semiconductor industry has continuously improved the integration density of different electronic components by continuously reducing the minimum element size so that more components can be integrated in a given area. For example, a vertical-diffused metal oxide semiconductor (VDMOS) uses a vertical structure design to reduce the cell pitch and improve the functional density. It uses the back side of the wafer as the drain and fabricates the sources and gates of multiple transistors on the front side of the wafer. Therefore, the driving current develops from a planar direction flow to a vertical direction flow, and the semiconductor device achieves high reverse breakdown voltage and low on-resistance, and is widely used in power switching elements.

[0003] As the requirements for the electrical performance of semiconductor devices continue to increase, the integrated element types and functions also increase accordingly to meet the application requirements. For example, a driving element with a different current driving method (e.g., having a driving current flowing in a planar direction) and a VDMOS element (having a driving current flowing in a vertical direction) can be integrated through a packaging method. In the packaging structure, additional wire bonding or additional traces need to be formed for electrical connection to achieve element integration. However, these additional wire bonds or traces will generate parasitic inductance between the driving element and the VDMOS element in the packaging structure. If the parasitic inductance is too high, the entire circuit or system cannot operate at high frequencies. Therefore, although current existing semiconductor devices are generally suitable and sufficient to meet their intended purposes, they are not entirely satisfactory in all aspects. Summary of the Invention

[0004] Some embodiments of the present invention provide a semiconductor device, which can integrate MOS elements with different driving current directions on the same substrate. The semiconductor device has a substrate of a first conductivity type, an epitaxial layer formed on the aforementioned substrate and having a first conductivity type, a first element, and a second element, wherein the second element is disposed at a distance from the first element and is electrically connected to the first element. The first element includes a first gate trench structure and a first shielding portion. The first gate trench structure extends from the top surface of the epitaxial layer into the epitaxial layer, wherein the substrate serves as a drain of the first element. The first shielding portion is located below the first gate trench structure and contacts the bottom of the first gate trench structure, and the first shielding portion has a second conductivity type. The second element includes a second gate trench structure, a planar gate structure, and a second shielding portion. The second gate trench structure extends from the top surface of the epitaxial layer into the epitaxial layer, and the planar gate structure is located on the top surface of the epitaxial layer. The second shielding portion is located below the second gate trench structure and contacts the bottom of the second gate trench structure, and the second shielding portion has a second conductivity type.

[0005] Some embodiments of the present invention provide a method for forming a semiconductor device, including providing a substrate having a first conductivity type; forming an epitaxial layer on the substrate, the epitaxial layer having a first conductivity type; forming a first element and a second element at a first region and a second region of the epitaxial layer respectively, the second element being disposed at a distance from the first element and being electrically connected to the first element. The first element includes a first gate trench structure extending from the top surface of the epitaxial layer into the epitaxial layer, wherein the substrate serves as a drain of the first element; and a first shielding portion located below the first gate trench structure and contacting the bottom of the first gate trench structure, and the first shielding portion has a second conductivity type. The second element includes a second gate trench structure extending from the top surface of the epitaxial layer into the epitaxial layer; a planar gate structure located on the top surface of the epitaxial layer; and a second shielding portion located below the second gate trench structure and contacting the bottom of the second gate trench structure, and the second shielding portion has a second conductivity type. Description of the Drawings

[0006] Figures 1 to 10 are cross-sectional schematic views of a semiconductor device according to some embodiments of the present invention at various intermediate manufacturing stages.

[0007] Reference Numerals:

[0008] 10: Semiconductor device

[0009] 10-1: First element

[0010] 10-2: Second element

[0011] 10-3: Third element

[0012] 100: Substrate

[0013] 100a, 102a, 1021a: Top surface

[0014] 1121b: Bottom surface

[0015] 101: Masking layer

[0016] 1011: First masking portion

[0017] 1012: Second masking portion

[0018] 102: Epitaxial layer

[0019] 1021: First epitaxial portion

[0020] 1022: Second epitaxial portion

[0021] 1041, 1043: Current spreading layer

[0022] 105: Substrate region

[0023] 106, 1061, 1062: Well region

[0024] 108, 1081, 1082, 1083: First heavily doped portion

[0025] 109, 1091, 1092, 1093: Second heavily doped portion

[0026] 1081s, 1082s, 1093s: Sidewall

[0027] 110: Protection ring

[0028] 112G - 1: First gate trench structure

[0029] 112G - 2: Second gate trench structure

[0030] 112G - 3: Third gate trench structure

[0031] 1121: Bottom conductive portion

[0032] 1122: Top conductive portion

[0033] 1123: Insulating layer

[0034] 113: Capping layer

[0035] 114, 1142, 1143: Planar gate structure

[0036] 116, 1161, 1162, 1163: Contact

[0037] A1: First region

[0038] A2: Second region

[0039] A3: The third region

[0040] A G : The peripheral region

[0041] D1: The first direction

[0042] D2: The second direction

[0043] D3: The third direction Detailed implementation manners

[0044] The following invention provides many embodiments or examples for implementing different elements of the provided semiconductor device. Specific examples of each element and its configuration are described below to simplify the description of the embodiments of the present invention. Of course, these are merely examples and are not intended to limit the embodiments of the present invention. For example, when it is mentioned in the description that the first element is formed on the second element, it may include embodiments where the first and second elements are in direct contact, and may also include embodiments where additional elements are formed between the first and second elements such that they are not in direct contact. In addition, the embodiments of the present invention may repeat reference numerals and / or letters in different examples. Such repetition is for the sake of simplicity and clarity and is not intended to indicate the relationship between the different embodiments discussed.

[0045] Furthermore, in the following description, spatially relative terms such as "under", "below", "beneath", "above", "over" and other similar terms may be used to simplify the description of the relationship between one element or component and other elements or other components as shown in the figures. Such spatially relative terms include not only the directions depicted in the figures but also different orientations of the semiconductor device during use or operation. The semiconductor device can be oriented in other directions, and the spatially relative descriptions used herein can be interpreted accordingly.

[0046] Some variations of the embodiments are described below. In the embodiments shown in different figures and descriptions, like element symbols are used to denote like elements. It can be understood that additional steps can be provided before, during, and after the method, and some of the recited steps can be replaced or deleted for other embodiments of the method.

[0047] Embodiments of the present invention provide a semiconductor device and a method of forming the same, which can integrate metal-oxide-semiconductor (MOS) elements with different driving current directions on the same substrate to fabricate a semiconductor device. In some embodiments below, an example of a semiconductor device is illustrated by integrating complementary MOS (CMOS) elements with a driving current flowing in a planar direction and vertical-diffused MOS (VDMOS) elements with a driving current flowing in a vertical direction on a substrate, and both the CMOS elements and the VDMOS elements have trench gates.

[0048] Figures 1 to 10 FIG. is a cross-sectional schematic view of a semiconductor device according to some embodiments of the present invention at various intermediate manufacturing stages.

[0049] Referring to Figure 1 , according to some embodiments, a substrate 100 of a first conductivity type is provided. The substrate 100 may be a bulk semiconductor substrate, such as a semiconductor wafer. The substrate 100 may be made of silicon or other semiconductor materials, such as a silicon wafer. Alternatively, the substrate 100 may comprise other elemental semiconductor materials, such as germanium. Furthermore, in some embodiments, the substrate 100 may include compound semiconductors, such as silicon carbide (SiC), gallium nitride, gallium arsenide, indium arsenide, or indium phosphide. In some embodiments, the substrate 100 may include alloy semiconductors, such as silicon germanium, silicon carbide germanium, gallium arsenide phosphide, or gallium indium phosphide. In some embodiments, the substrate 100 may also include a silicon on insulator (SOI) or other suitable substrate. The SOI substrate may be formed by separation by implanted oxygen (SIMOX) process, wafer bonding process, other applicable means, or a combination of the foregoing. In some embodiments, the substrate 100 may be composed of different semiconductor materials, such as silicon, silicon germanium, silicon carbide, etc.

[0050] In an example applied to a semiconductor device including a VDMOS element, such as a vertical trench gate MOSFET, the substrate 100 is, for example, a wafer doped with a dopant of a first conductivity type. This substrate 100 of the first conductivity type can serve as the drain region of the VDMOS element. In this embodiment, the first conductivity type is n-type, but the present invention is not limited thereto. In some other embodiments, the first conductivity type may also be p-type.

[0051] Next, an epitaxial growth process is performed on the substrate 100 to form an epitaxial layer 102 (Figure 2 ), and a shielding layer including a plurality of separated shielding portions is formed in the epitaxial layer 102. The epitaxial layer 102 has the same conductivity type as the substrate 100, and the shielding layer 101 includes dopants of a conductivity type opposite to that of the epitaxial layer 102. In some embodiments, for example (but not limited to) applications using a silicon-based substrate for the manufacturing process, the epitaxial layer 102 can be formed by continuous epitaxial growth, and then dopants can be implanted into the epitaxial layer 102 through an implantation process to form the shielding layer 101. In some embodiments, for example (but not limited to) applications using a silicon carbide substrate for the manufacturing process, the epitaxial growth can be carried out in stages to form the epitaxial layer 102, and the shielding layer 101 is formed between the stage growths. In this example, the epitaxial layer 102 is formed in a two-stage epitaxial growth manner.

[0052] As Figure 1 shown, according to some embodiments, an epitaxial growth process is performed on the top surface 100a of the substrate 100 to form a first epitaxial portion 1021 of the epitaxial layer 102. The substrate 100 and the first epitaxial portion 1021 have the same conductivity type, for example, the first conductivity type. In this example, the substrate 100 and the first epitaxial portion 1021 are n-type. Furthermore, the doping concentration of the first epitaxial portion 1021 of the epitaxial layer 102 is less than the doping concentration of the substrate 100.

[0053] In this example, a first element (such as a VDMOS element) is formed at a first region A1 of the epitaxial layer 102, a second element (such as an NMOS element) is formed at a second region A2, and a third element (such as a PMOS element) is formed at a third region A3. The NMOS element and the PMOS element are electrically connected to form a CMOS element. Accordingly, a semiconductor device having a VDMOS element and a CMOS element is integrally formed on the same substrate.

[0054] After the first epitaxial portion 1021 is formed, dopants are implanted into the first epitaxial portion 1021 through an implantation process to form a first shielding portion 1011 at the first region A1 and a second shielding portion 1012 at the second region A2 and the third region A3. In this example, as Figure 1 shown, the first shielding portion 1011 and the second shielding portion 1012 extend in a first direction D1 (such as the Y direction) and are spaced apart from each other by a distance in a second direction D2 (such as the X direction).

[0055] In some embodiments, the separated first masking portion 1011 and second masking portion 1012 have a conductivity type different from that of the first epitaxial portion 1021, such as a second conductivity type. In this example, the first masking portion 1011 and the second masking portion 1012 are p-type, and can also be referred to as p-type masking portions. The dopant of the first masking portion 1011 and the second masking portion 1012 can be aluminum (Al), or other suitable dopants. In some embodiments, the doping concentration of the first masking portion 1011 and the second masking portion 1012 is, for example (but not limited to), in the range of about 1E16 atoms / cm 3 to about 1E18 atoms / cm 3 range.

[0056] After that, referring to Figure 2 , according to some embodiments, on the top surface 1021a of the first epitaxial portion 1021, epitaxial growth continues in the third direction D3 (such as the Z direction) to form a second epitaxial portion 1022. The second epitaxial portion 1022 covers the masking layer 101 including the first masking portion 1011 and the second masking portion 1012. The second epitaxial portion 1022 also has the first conductivity type, such as n-type. In this example, the first epitaxial portion 1021 and the second epitaxial portion 1022 together constitute an epitaxial layer 102. The thickness of the epitaxial layer 102 (along the third direction D3) can be adjusted according to the operating voltage required for the actual semiconductor device application.

[0057] In some embodiments, the above epitaxial growth process can be carried out by metal organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), hydride vapor phase epitaxy (HVPE), liquid phase epitaxy (LPE), chloride vapor phase epitaxy (Cl-VPE), other suitable process methods, or a combination of the foregoing methods to form the epitaxial layer 102.

[0058] After that, a plurality of doping regions required for each element are formed in the epitaxial layer 102.

[0059] Referring to Figure 3, in some embodiments of forming a VDMOS device at the first region A1 of the epitaxial layer 102, dopants having the same conductivity type as the epitaxial layer 102 are implanted at the first region A1 of the epitaxial layer 102 to form a current spreading layer (CSL) 1041. Furthermore, the current spreading layer 1041 extends downward from the top surface 102a of the epitaxial layer 102 and contacts the first shielding portion 1011. In this example, the first region A1 of the epitaxial layer 102 includes two first shielding portions 1011 spaced apart in the second direction D2, and the current spreading layer 1041 also extends between the two first shielding portions 1011. As Figure 3 shown, the bottom surface of the current spreading layer 1041 is, for example, substantially coplanar with the bottom surface of the first shielding portion 1011.

[0060] In this example, the current spreading layer 1041 has a first conductivity type, for example, n-type. Furthermore, the doping concentration of the current spreading layer 1041 is greater than the doping concentration of the epitaxial layer 102, so that when the subsequently manufactured VDMOS device operates, it can enhance the flow of electrons from the source electrode through the space between the two first shielding portions 1011 to the drain electrode (substrate 100), thereby reducing the resistance of the VDMOS device.

[0061] Furthermore, in some embodiments of forming a PMOS device at the third region A3 of the epitaxial layer 102, another current spreading layer 1043 can also be formed at the third region A3 of the epitaxial layer 102. The current spreading layer 1043 also has a first conductivity type, for example, n-type. The current spreading layer 1043 can serve as the channel region of the PMOS device formed at the third region A3. Furthermore, the doping concentration of the current spreading layer 1043 can be greater than the doping concentration of the epitaxial layer 102 to further improve the threshold voltage of the subsequently manufactured PMOS device. In this example, the current spreading layer 1043 extends downward from the top surface 102a of the epitaxial layer 102 and contacts the second shielding portion 1012.

[0062] According to some embodiments of the present invention, the current spreading layers 1041 and 1043 can be formed in the same process, and can be formed by implanting dopants having a first conductivity type (for example, n-type) into the epitaxial layer 102 simultaneously through, for example, an ion implantation process.

[0063] According to some embodiments, the above-mentioned current diffusion layer 1041 and current diffusion layer 1043 can be formed by a deposition process, a photolithographic patterning process, an etching process, and an implantation process. For example, in one example, an oxide hardmask material layer (not shown) can be deposited above the top surface 102a of the epitaxial layer 102, and then a patterned photoresist corresponding to the positions of the current diffusion layer 1041 and current diffusion layer 1043 is formed on this oxide hardmask material layer, and the oxide hardmask material layer is etched according to this patterned photoresist to form an oxide hardmask. After that, the patterned photoresist is removed, and the epitaxial layer 102 is doped according to the formed oxide hardmask to form the current diffusion layer 1041 and current diffusion layer 1043 in the epitaxial layer 102. After that, the oxide hardmask is removed.

[0064] Referring to Figure 4 , according to some embodiments, a base region 105 is formed in the current diffusion layer 1041 of the first region A1. This base region 105 is doped downward from the top surface 102a of the epitaxial layer 102 and extends in the current diffusion layer 1041, for example, along the first direction D1. Furthermore, this base region 105 has a different conductivity type from the current diffusion layer 1041.

[0065] In this example, dopants of the second conductivity type, such as p-type dopants, are implanted at the current diffusion layer 1041 to form the base region 105. Furthermore, in this example, the position of the base region 105 is, for example, roughly corresponding to the upper part between the two first shielding portions 1011. And the bottom surface of the base region 105 is spaced apart from the top surface of the first shielding portion 1011 by a distance in the third direction D3. Furthermore, according to some embodiments, the base region 105 can be formed by the deposition process, the photolithographic patterning process, the etching process, and the implantation process as described above.

[0066] Referring to Figure 5 , according to some embodiments, a well region 106 is formed in the epitaxial layer 102. The depth of the well region 106 is greater than the depth of the base region 105. For example, a well region 1061 is formed in the epitaxial layer 102 of the first region A1, and the well region 1061 extends downward from the top surface 102a of the epitaxial layer 102 to connect to the first shielding portion 1011. Similarly, a well region 1062 is formed in the epitaxial layer 102 of the second region A2, and the well region 1062 extends downward from the top surface 102a of the epitaxial layer 102 to connect to the second shielding portion 1012.

[0067] Furthermore, according to some embodiments, the well regions 1061 and 1062 contain dopants of a conductivity type opposite to that of the epitaxial layer 102. Dopants of the second conductivity type, such as p-type dopants, can be implanted into the epitaxial layer 102 through an implantation process to form the well regions 1061 and 1062. As Figure 5 shown, in this example, the well region 1061 of the first region A1 is adjacent to the current diffusion layer 1041, and the well region 1062 of the second region A2 is adjacent to the current diffusion layer 1042. In this example, the well region 1062 of the second conductivity type (e.g., p-type) can serve as the channel region of the NMOS device (i.e., the second device) formed at the second region A2.

[0068] After that, according to some embodiments of the present invention, several heavily doped portions required for forming devices in each region (such as the first region A1, the second region A2, and the third region A3) are formed, including a plurality of first heavily doped portions 108 and a plurality of second heavily doped portions 109 of different conductivity types, to serve as the source regions, drain regions, and base regions of the devices to be fabricated (such as the VDMOS device, the NMOS device and the PMOS device included in the CMOS device).

[0069] Referring to Figure 6 , according to some embodiments, a plurality of first heavily doped portions 108 of the first conductivity type are formed. The first heavily doped portions 108 (such as including the first heavily doped portions 1081, 1082, and 1083) can be formed by implanting dopants of the first conductivity type into the substrate region 105, the current diffusion layer 1043, and the well region 1062 simultaneously through, for example, an ion implantation process. In this example, these first heavily doped portions 108 have the same first conductivity type as the epitaxial layer 102, such as n-type.

[0070] Specifically, in some embodiments of forming a VDMOS device at the first region A1, a first heavily doped portion 1081 of the first conductivity type (e.g., n-type) is formed in the substrate region 105 to serve as a source region of the VDMOS device. This first heavily doped portion 1081 extends not only downward from the top surface 102a of the epitaxial layer 102 but also along the first direction D1. Furthermore, the depth of the first heavily doped portion 1081 in the vertical direction (e.g., the third direction D3) is less than the depth of the substrate region 105 in the vertical direction (e.g., the third direction D3).

[0071] Furthermore, in some embodiments where NMOS components are formed in the second region A2, two first heavily doped portions 1082 of a first conductivity type (e.g., n-type) are formed in the well region 1062 to serve as a source region and a drain region of the NMOS component. The first heavily doped portions 1082 extend downward from the top surface 102a of the epitaxial layer 102 and are spaced apart by a distance in the first direction D1. The depth of the first heavily doped portions 1082 in the vertical direction (e.g., the third direction D3) is also less than the depth of the well region 1062 in the vertical direction (e.g., the third direction D3).

[0072] Furthermore, in some embodiments where PMOS components are formed in the third region A3, a first heavily doped portion 1083 of a first conductivity type (e.g., n-type) is formed in the current diffusion layer 1043 to serve as the bulk region of the PMOS component. This bulk region can be adjacent to a second heavily doped portion 1093 (such as one of those in Figure 7 ), which is to be formed subsequently as a source region.

[0073] The method of forming the above-mentioned first heavily doped portion 108 is, for example, similar to the methods of forming the current diffusion layer 1041, the current diffusion layer 1043, and the well region 1062. In some embodiments, the doping concentration of the first heavily doped portion 108 is greater than the doping concentrations of the current diffusion layer 1041 and the current diffusion layer 1043. In some embodiments, the doping concentration of the first heavily doped portion 108 is, for example (but not limited to), in the range of about 1E18 atoms / cm 3 to about 1E21 atoms / cm 3 .

[0074] After that, referring to Figure 7 , according to some embodiments, second heavily doped portions 109 required for forming components are formed in each region. The second heavily doped portions 109 (such as including second heavily doped portions 1091, 1092, and 1093) can be formed by, for example, simultaneously implanting dopants of a second conductivity type into the source region (i.e., the first heavily doped portion 1081), the current diffusion layer 1043, and the well region 1062 through an ion implantation process. In this example, these second heavily doped portions 109 have the same second conductivity type as the masking layer 101, such as p-type.

[0075] Specifically, in some embodiments where a VDMOS device is formed in the first region A1, a second heavily doped portion 1091 of the second conductivity type (e.g., p-type) is formed in the source region 1081 to serve as the base region of the VDMOS device. Although not shown in the figures, these second heavily doped portions 1091 in the source region (i.e., the first heavily doped portion 1081) extend downward to contact the underlying substrate region 105. Therefore, the depth of the second heavily doped portion 1091 in the vertical direction (e.g., the third direction D3) is approximately equal to the depth of the first heavily doped portion 1081 in the vertical direction (e.g., the third direction D3).

[0076] Furthermore, in some embodiments where an NMOS device is formed in the second region A2, a second heavily doped portion 1092 of the second conductivity type (e.g., p-type) is formed in the well region 1062 to serve as the base region of the NMOS device. As Figure 7 shown, the second heavily doped portion 1092 serving as the base region of the NMOS device is adjacent to the first heavily doped portion 1082 serving as the source region of the NMOS device.

[0077] Furthermore, in some embodiments where a PMOS device is formed in the third region A3, two second heavily doped portions 1093 of the second conductivity type (e.g., p-type) are formed in the current diffusion layer 1043 to serve as a source region and a drain region of the PMOS device. As Figure 7 shown, the second heavily doped portion 1093 serving as the source region of the PMOS device is adjacent to the first heavily doped portion 1083 serving as the base region of the PMOS device.

[0078] In addition, according to some embodiments, a plurality of guard rings 110 are also formed at the periphery of the regions (e.g., the first region A1, the second region A2, and the third region A3) where these devices are formed. For example, in the peripheral region A G of the epitaxial layer 102, dopants of the second conductivity type are implanted into the epitaxial layer 102 through an ion implantation process to form the guard ring 110, so as to prevent the fabricated devices from being affected by noise.

[0079] The above-mentioned second heavily doped portion 109 and the guard ring 110 can be formed in the same process and have approximately the same ion implantation depth. The formation method of the second heavily doped portion 109 and the guard ring 110 is, for example, similar to the formation methods of the current diffusion layer 1041, the current diffusion layer 1043, and the well region 1062. In some embodiments, the doping concentration of the second heavily doped portion 109 and the guard ring 110 is greater than the doping concentration of the shielding layer 101. In some embodiments, the doping concentration of the second heavily doped portion 109 and the guard ring 110 is, for example (but not limited to), between approximately 1E18 atoms / cm 3 and approximately 1E21 atoms / cm3 between the ranges.

[0080] According to some embodiments, after forming the above-mentioned multiple first heavily doped portions 108, multiple second heavily doped portions 109, and the guard ring 110, a high-temperature annealing process is performed to activate the dopants in each region / layer / portion in the epitaxial layer 102. After the high-temperature annealing process, the junctions of these doped regions / layers / portions in the epitaxial layer 102 are finalized. The temperature of the high-temperature annealing process can depend on the material actually selected for the substrate 100. In some embodiments using a silicon-based substrate 100, for example (but not limited to), the high-temperature annealing process is performed in a temperature range of approximately 1000 °C to approximately 1200 °C. In some embodiments using a silicon carbide substrate 100, for example (but not limited to), the high-temperature annealing process is performed in a temperature range of approximately 1600 °C to approximately 1700 °C.

[0081] After that, referring to Figure 8 , according to some embodiments of the present invention, gate trench structures of each element are formed in each region. In this example, a first gate trench structure 112G-1 of a first element (such as a VDMOS element) is formed at the first region A1, a second gate trench structure 112G-2 of a second element (such as an NMOS element) is formed at the second region A2, and a third gate trench structure 112G-3 of a third element (such as a PMOS element) is formed at the third region A3.

[0082] In some embodiments, the gate trench structures of all elements of the semiconductor device are fabricated simultaneously. Specifically, the aforementioned first gate trench structure 112G-1, second gate trench structure 112G-2, and third gate trench structure 112G-3 are formed in the same process to simplify the process of the semiconductor device in the embodiment. These gate trench structures, for example, extend from the top surface of the epitaxial layer 102 downward into the epitaxial layer 102. Furthermore, in some embodiments, the formed gate trench structures are split-gate trench structures.

[0083] As Figure 8As shown, in some examples where a trench gate VDMOS device is formed at the first region A1, each first gate trench structure 112G-1 includes a bottom conductive portion 1121, a top conductive portion 1122 above the bottom conductive portion 1121, and an insulating layer 1123 that electrically isolates the bottom conductive portion 1121 from the top conductive portion 1122. The insulating layer 1123 covers the sidewalls of the bottom conductive portion 1121 and the top conductive portion 1122 and is located between the bottom conductive portion 1121 and the top conductive portion 1122 to electrically isolate the bottom conductive portion 1121 from the top conductive portion 1122.

[0084] Furthermore, in this example, two first gate trench structures 112G-1 extend in the first direction D1 and are spaced apart from each other in the second direction D2, where the first heavily doped portion 1081, the second heavily doped portion 1091, and the substrate region 105 are located between the two first gate trench structures 112G-1. In this example, the opposing sidewalls 1081s of the first heavily doped portion 1081 and the opposing sidewalls of the substrate region 105 contact the insulating layer 1123 of the first gate trench structure 112G-1.

[0085] It should be noted that, in some embodiments, the bottom of the first gate trench structure 112G-1 contacts the first shielding portion 1011. More specifically, the bottom conductive portion 1121 of the first gate trench structure 112G-1 directly contacts (or is physically in contact with) the first shielding portion 1011 and is electrically connected to the first shielding portion 1011. Furthermore, in some embodiments, the bottom conductive portion 1121 of the first gate trench structure 112G-1 is electrically connected to the source of the first device (such as a VDMOS device) (i.e., the first heavily doped portion 1081).

[0086] The manufacturing method of the above-mentioned first gate trench structure 112G-1 can be, for example (but not limited to), through a deposition process, a photolithographic patterning process, and an etching process, and is formed on the current diffusion layer 1041 ( Figure 7) Grooves are formed therein. These grooves extend in the first direction D1, and the bottom of the grooves exposes the first masking portion 1011. Then, an insulating material is formed on the sidewalls and the bottom surface of the grooves, and part of the insulating material can be removed by etch-back to form the lower portion of the insulating layer 1123 and expose the first masking portion 1011. Then, a conductive material can be deposited and the conductive material can be etched to form the bottom conductive portion 1121, wherein the bottom surface 1121b of the bottom conductive portion 1121 directly contacts the first masking portion 1011. Then, an insulating material can be formed again in the remaining space of the grooves to form the upper portion of the insulating layer 1123 on the upper sidewalls of the grooves and on the bottom conductive portion 1121, wherein the upper portion of the insulating layer 1123 covers the bottom conductive portion 1121. Then, another conductive material can be deposited and the conductive material can be etched to form the top conductive portion 1122 above the bottom conductive portion 1121, and the top conductive portion 1122 is separated from the bottom conductive portion 1121 by the insulating layer 1123. Furthermore, in this example, the top conductive portion 1122 is relatively recessed in the grooves, and a capping layer 113 (for example, including an oxide or other suitable insulating material) is deposited on the top conductive portion 1122 to cover the top conductive portion 1122, wherein the top surface of the capping layer 113 is substantially coplanar with the top surface 102a of the epitaxial layer 102.

[0087] According to some embodiments, the bottom conductive portion 1121 may include polysilicon, titanium, titanium nitride, other suitable conductive materials, or a combination of the foregoing materials. The top conductive portion 1122 may include polysilicon or other suitable conductive materials. And the bottom conductive portion 1121 and the top conductive portion 1122 may include the same or different conductive materials. In some embodiments, the insulating layer 1123 may be silicon oxide, or other suitable semiconductor oxide materials, or a combination of the foregoing materials. Furthermore, the insulating layer 1123 can be formed by a deposition process, an oxidation process, a combination of the foregoing, or other suitable processes. In an example where the epitaxial layer 102 includes silicon carbide, the silicon carbide on the side surface and the bottom surface of the grooves can be oxidized by a high-temperature process (for example, using a high-temperature furnace tube) to form silicon oxide as part of the insulating layer 1123 on the side surface and the bottom surface of the grooves, and an oxide layer is formed on the bottom conductive portion 1121 by deposition to cover the top surface of the bottom conductive portion 1121, so that the subsequently formed top conductive portion 1122 can be electrically isolated from the bottom conductive portion 1121.

[0088] Furthermore, as Figure 8As shown, in some examples where an NMOS device is formed in the second region A2 and a PMOS device is formed in the third region A3, the second gate trench structure 112G-2 and the third gate trench structure 112G-3 have the same configuration as the first gate trench structure 112G-1. Each of the second gate trench structure 112G-2 and the third gate trench structure 112G-3 also includes a bottom conductive portion 1121, a top conductive portion 1122 above the bottom conductive portion 1121, and an insulating layer 1123 that electrically isolates the bottom conductive portion 1121 and the top conductive portion 1122. The materials and manufacturing methods of the related components of the second gate trench structure 112G-2 and the third gate trench structure 112G-3 may refer to those of the first gate trench structure 112G-1 described above, and will not be repeated here.

[0089] Furthermore, in this example, the second gate trench structure 112G-2 and the third gate trench structure 112G-3 also extend in the first direction D1 and are spaced apart from each other in the second direction D2. The first heavily doped portion 1082, the second heavily doped portion 1092, and the well region 1062 in the second region A2 are located between two second gate trench structures 112G-2, and the opposite sidewalls of the first heavily doped portion 1082, the second heavily doped portion 1092, and the well region 1062 contact the second gate trench structure 112G-2. For example, the opposite sidewalls 1082s of the first heavily doped portion 1082 in the figure respectively contact the insulating layer 1123 of the second gate trench structure 112G-2. Similarly, the first heavily doped portion 1083, the second heavily doped portion 1093, and the current diffusion layer 1043 in the third region A3 are located between two third gate trench structures 112G-3, and the opposite sidewalls of the first heavily doped portion 1083, the second heavily doped portion 1093, and the current diffusion layer 1043 contact the third gate trench structure 112G-3. For example, the opposite sidewalls 1093s of the second heavily doped portion 1093 in the figure respectively contact the insulating layer 1123 of the third gate trench structure 112G-3.

[0090] It should be noted that, in some embodiments, the bottoms of the second gate trench structure 112G-2 and the third gate trench structure 112G-3 contact the second shielding portion 1012. More specifically, the bottom conductive portion 1121 of each of the second gate trench structure 112G-2 and the third gate trench structure 112G-3 directly contacts (or is referred to as physically contacting) the second shielding portion 1012 and is electrically connected to the second shielding portion 1012.

[0091] According to some embodiments of the present invention, since the shielding layer 101 in the semiconductor device, including the first shielding portion 1011 and the second shielding portion 1012, is formed in the same process, the first shielding portion 1011 and the second shielding portion 1012 may have substantially the same horizontal height and also have substantially the same depth (along the third direction D3) in the epitaxial layer. And since the aforementioned first gate trench structure 112G-1, second gate trench structure 112G-2, and third gate trench structure 112G-3 are also formed by the same process and these gate trench structures all extend to the corresponding shielding portions below, the first gate trench structure 112G-1, second gate trench structure 112G-2, and third gate trench structure 112G-3 have substantially the same vertical depth in the epitaxial layer 102.

[0092] After that, referring to Figure 9 , according to some embodiments, a planar gate structure 114 is further formed in the region of the non-vertical semiconductor element. For example, a planar gate structure 1142 of a second element (such as an NMOS element) is formed at the second region A2, and a planar gate structure 1143 of a third element (such as a PMOS element) is formed at the third region A3.

[0093] In some embodiments, the top conductive portion 1122 of the second gate trench structure 112G-2 at the second region A2 is electrically connected to the upper planar gate structure 1142, and the bottom conductive portion 1121 of the second gate trench structure 112G-2 is electrically connected to the lower second shielding portion 1012.

[0094] In some embodiments, the top conductive portion 1122 of the third gate trench structure 112G-3 at the third region A3 is electrically connected to the upper planar gate structure 1143, and the bottom conductive portion 1121 of the third gate trench structure 112G-3 is electrically connected to the lower second shielding portion 1012.

[0095] In some embodiments, each of the planar gate structures 1142 and 1143 includes a gate dielectric layer and a gate electrode located on the gate dielectric layer. To clearly show the relevant configuration of the planar gate and the underlying doped regions, Figure 9 the gate dielectric layers in the planar gate structures 1142 and 1143 are omitted in

[0096] The above gate dielectric layer may be silicon oxide or other suitable dielectric materials. The above gate electrode may include polysilicon or other suitable conductive materials. A dielectric material layer (not shown) may be formed on the epitaxial layer 102 through a deposition process (such as physical vapor deposition (PVD) process, chemical vapor deposition (CVD) process, atomic layer deposition (ALD) process), or a thermal oxidation process. Thereafter, a conductive material (not shown) is deposited on the dielectric material layer, and the above deposition process may be a physical vapor deposition process, a chemical vapor deposition process, or other suitable processes. Then, through a photolithography process and an etching process, the above dielectric material layer and the above conductive material may be patterned to form the gate dielectric layer and the gate electrode of the planar gate structures 1142 and 1143.

[0097] Furthermore, as Figure 9 shown, in some examples of forming NMOS devices at the second region A2, the first heavily doped portions 1082 serving as source regions and drain regions are spaced apart in the first direction D1 and respectively correspond to opposite sides of the planar gate structure 1142. More specifically, two second gate trench structures 112G-2 are spaced apart in the second direction D2, and the planar gate structure 1142 and the first heavily doped portions 1082 (serving as source regions and drain regions) are located between the second gate trench structures 112G-2. The first heavily doped portions 1082 extend between the second gate trench structures 112G-2. For example, the opposite sidewalls 1082s of the first heavily doped portions 1082 respectively contact the second gate trench structures 112G-2. In some embodiments, one set of opposite sidewalls of the planar gate structure 1142 extends in the first direction D1, and the other set of opposite sidewalls of the planar gate structure 1142 respectively correspond to the first heavily doped portions 1082 serving as source regions and drain regions.

[0098] Therefore, according to some embodiments of the present invention, the second device (such as an NMOS device) formed at the second region A2 not only has the planar gate structure 1142 but also has the second gate trench structure 112G-2. Therefore, in the embodiments, the non-vertical semiconductor devices integrated with the first device (such as a VDMOS device) each have multiple gates and multiple channels. For example, the tri-gate structures shown in the second device (such as an NMOS device) in this example include two second gate trench structures 112G-2 and one planar gate structure 1142, and thus have three channels.

[0099] Similarly, a third element (e.g., a PMOS element) formed at the third region A3 has a planar gate structure 1143 and a third gate trench structure 112G-3. Thus, the third element integrated with the first element (e.g., a VDMOS element) in the embodiment also has multiple gates and multiple channels. For example, the three gate structures shown in this example (including two third gate trench structures 112G-3 and one planar gate structure 1143) can form three channels.

[0100] After that, referring to Figure 10 , according to some embodiments, after forming the planar gate structures 1142 and 1143, an interlayer dielectric layer is formed over the epitaxial layer 102 to cover the epitaxial layer 102, the multiple first heavily doped portions 108 and the second heavily doped portion 109, the well region 1062, the guard ring 110, the first gate trench structure 112G-1, the second gate trench structure 112G-2, the third gate trench structure 112G-3, the planar gate structure 1142, and the planar gate structure 1143. Then, a plurality of contacts 116 are formed in the interlayer dielectric layer.

[0101] To clearly show the relevant configurations of the planar gate structure 114, the contacts 116, and the underlying doped regions, Figure 10 the gate dielectric layers in the planar gate structures 1142 and 1143 (only the gate electrodes are shown) are omitted from the illustration, and the interlayer dielectric layer is also omitted from the illustration.

[0102] In some embodiments, the interlayer dielectric layer can be silicon oxide, or other suitable low-k dielectric materials, or a combination of the foregoing materials. In some embodiments, the material of the interlayer dielectric layer is different from the material of the insulating layer 1123 of the gate trench structure. In some other embodiments, the material of the interlayer dielectric layer is the same as the material of the insulating layer 1123 of the gate trench structure. Furthermore, the interlayer dielectric layer can be deposited over the epitaxial layer 102 by a deposition process. In some embodiments, the above deposition process can be a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD) process, other suitable processes, or a combination of the foregoing.

[0103] Thereafter, according to some embodiments, some portions of the interlayer dielectric layer may be removed through a photolithography patterning process and an etching process to form contact holes (not shown), wherein the bottom of the contact holes exposes the corresponding underlying conductive portions, such as source regions, drain regions, and substrate regions. The above-mentioned photolithography patterning process includes photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, cleaning, and drying (e.g., hard baking), other suitable processes, or a combination of the foregoing processes. In some embodiments, the above-mentioned etching process may be a dry etching process, a wet etching process, a plasma etching process, a reactive ion etching process, other suitable processes, or a combination of the foregoing processes.

[0104] Thereafter, according to some embodiments, suitable conductive materials are filled into the contact holes in each region to form the contacts 116.

[0105] As Figure 10 shown, in some embodiments, the contact 1161 of the first element 10-1 (e.g., a VDMOS element) located in the first region A1 is electrically connected to the first heavily doped portion 1081 (source region) and the second heavily doped portion 1091 (base region). In some embodiments, since the second heavily doped portion 1091 is connected to the underlying substrate region 105, the source and the base of the first element 10-1 are electrically connected, and during device operation, the first heavily doped portion 1081 and the second heavily doped portion 1091 are at the same potential. In other words, these contacts 1161 of the first element 10-1 are all electrically connected to the source.

[0106] Furthermore, in some embodiments, the contacts 1162 of the second element 10-2 (e.g., an NMOS element) located in the second region A2 are electrically connected to the first heavily doped portion 1082 (e.g., having n+ dopants) serving as the source region and the drain region, respectively, and are electrically connected to the second heavily doped portion 1092 (e.g., having p+ dopants) serving as the base region. Since the second heavily doped portion 1092 serving as the base region of the NMOS element is adjacent to the first heavily doped portion 1082 serving as the source region, the source and the base of the second element 10-2 are electrically connected, and during device operation, the first heavily doped portion 1082 serving as the source region and the second heavily doped portion 1092 serving as the base region are at the same potential.

[0107] Similarly, in some embodiments, the contacts 1163 of the third element 10-3 (e.g., a PMOS element) located in the third region A3 are electrically connected to the first heavily doped portion 1083 (e.g., having n+ dopants) serving as the base region and to the second heavily doped portion 1093 (e.g., having p+ dopants) serving as the source and drain regions, respectively. Since the first heavily doped portion 1083 serving as the base region of the PMOS element is adjacent to the second heavily doped portion 1093 serving as the source region, the source and the base of the third element 10-3 are electrically connected, and during device operation, the second heavily doped portion 1093 serving as the source region and the first heavily doped portion 1083 serving as the base region are at the same potential.

[0108] Furthermore, the above-mentioned contact 116 may be a single-layer or multi-layer structure. In some embodiments, the contact 116 includes a contact barrier layer and a contact conductive layer. The contact barrier layer is formed on the sidewalls and bottom of the contact hole to be a barrier liner, and the contact conductive layer fills the remaining space in the contact hole. In the diagrams of this example, as Figure 2 shown, only the single-layer structure of the contact 116 is shown to simplify the diagrams. Furthermore, in some examples, the top surface of the contact 116 (including the top surface of the contact barrier layer and the top surface of the contact conductive layer, if any) is substantially coplanar with the top surface of the interlayer dielectric layer (not shown).

[0109] In some examples, a barrier material (not shown) may be formed on the interlayer dielectric layer by a deposition process, and the barrier material is deposited isotropically in the contact hole; then a conductive material (not shown) is deposited above the barrier material layer, and the conductive material fills the remaining space in the contact hole. Subsequently, for example, by etching or other suitable means, the excess portions of the conductive material and the barrier material above the interlayer dielectric layer are removed to form the contact barrier layer and the contact conductive layer in the contact hole, thereby fabricating the above-mentioned contact 116.

[0110] Materials that can be used as the contact barrier layer of the contact 116 include, for example, titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), cobalt (Co), cobalt tungsten phosphide (CoWP), ruthenium (Ru), aluminum oxide (Al2O3), magnesium oxide (MgO), aluminum nitride (AlN), tantalum pentoxide (Ta2O5), silicon dioxide (SiO2), hafnium dioxide (HfO2), zirconium dioxide (ZrO2), magnesium fluoride (MgF2), calcium fluoride (CaF2), other suitable barrier materials, or combinations of the foregoing materials. In some embodiments, the above-mentioned contact barrier layer can be formed by a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process, a physical vapor deposition (PVD) process, other suitable processes, or combinations of the foregoing processes.

[0111] In some embodiments, the conductive material of the contact conductive layer that can serve as the contact 116 includes tungsten (W), aluminum (Al), copper (Cu), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), nickel silicide (NiSi), cobalt silicide (CoSi), tantalum carbide (TaC), tantalum silicide nitride (TaSiN), tantalum carbide nitride (TaCN), titanium aluminide (TiAl), titanium aluminide nitride (TiAlN), other suitable metals, or a combination of the foregoing materials. Furthermore, in some embodiments, the above-mentioned contact conductive layer can be formed by a chemical vapor deposition process, an atomic layer deposition process, a physical vapor deposition process, other suitable processes, or a combination of the foregoing processes.

[0112] In some embodiments, the contacts 116 of all the components of the semiconductor device 10 are fabricated simultaneously. Specifically, the contact 1161 of the first component 10-1 (such as a VDMOS component) in the first region A1, the contact 1162 of the second component 10-2 (such as an NMOS component) in the second region A2, and the contact 1163 of the third component 10-3 (such as a PMOS component) in the third region A3 are formed in the same process to simplify the process of the semiconductor device 10 of the embodiment.

[0113] After the contacts 116 are formed, subsequent processes of other components of the semiconductor device 10 are carried out. According to some embodiments, a metal layer (not shown) is formed above the interlayer dielectric layer and the contacts 116. The metal layer covers the contacts 116 and is physically and electrically in contact with the contacts 116. Therefore, the metal layer is electrically connected to, for example, the first heavily doped portion 108, the second heavily doped portion 109, the substrate region 105, and the well region 1062 through the contacts 116.

[0114] In some embodiments, the above-mentioned metal layer may include copper, silver, gold, aluminum, tungsten, other suitable metal materials, or a combination of the foregoing materials. In some embodiments, the material of the metal layer is the same as that of the contact member 116. In some other embodiments, the material of the metal layer is different from that of the contact member 116. According to some embodiments, the metal layer can be formed on the contact member 116 through a deposition process. In some embodiments, the above-mentioned deposition process can be a physical vapor deposition process, a chemical vapor deposition process, other suitable processes, or a combination of the foregoing. After forming the above-mentioned metal layer, the process of the semiconductor device 10 is completed.

[0115] According to some embodiments, the semiconductor device 10 may include a first element 10-1 such as a VDMOS element, a second element 10-2 such as an NMOS element, and a third element 10-3 such as a PMOS element, wherein the NMOS element and the PMOS element are electrically connected to form a complementary metal oxide semiconductor (CMOS) element. The CMOS element can be used as a switching element to control the VDMOS element to turn on or off the operation of the VDMOS element. In a non-limiting example, in the CMOS element, the drains of the NMOS element and the PMOS element are interconnected, and the gate of the VDMOS element is electrically connected to the drain of the CMOS element.

[0116] In summary, the semiconductor device of the embodiments proposed by the present invention can implement elements with different driving current flow directions on the same substrate, such as a semiconductor device including a VDMOS element (with a driving current flowing in the vertical direction) and a CMOS element (with a driving current flowing in the planar direction). In the application of high-power devices, the VDMOS element is a high-power element, and the CMOS element can be used as a driver for the VDMOS element. The semiconductor device of the embodiments has many advantages. For example, compared with the excessive parasitic inductance generated by the traditional packaging method of combining different functional elements, the integrated (monolithic) semiconductor device proposed by the embodiments can effectively reduce the parasitic inductance between the VDMOS element and the driving circuit of the CMOS element (control element). The reduction of parasitic inductance can increase the operating frequency of the entire circuit or the entire system. Additionally, in some embodiments where silicon carbide epitaxy is used to fabricate the semiconductor device, the element operation can be performed at a higher temperature.

[0117] Furthermore, according to some embodiments of the present invention, each component in the semiconductor device includes a discrete gate trench structure. For the VDMOS component of the semiconductor device of the embodiment, the discrete gate of the first gate trench structure 112G-1 can reduce the parasitic capacitance between the gate and the drain, and improve the switching speed of the VDMOS component. For the CMOS component of the semiconductor device of the embodiment, the second gate trench structure 112G-2 and the third gate trench structure 112G-3 fabricated simultaneously with the first gate trench structure 112G-1 can simplify the process and increase the number of channels of the CMOS component. For example, in the above example, the NMOS component formed in the second region A2 and the PMOS component formed in the third region A3 each have three gates and three channels. Compared with the CMOS component with a traditional planar gate, the CMOS component of the embodiment can construct more channels in the same area, improve the channel density, generate a larger current during component operation, and thus improve the operation speed.

[0118] Furthermore, for the semiconductor device according to some embodiments of the present invention, the shielding layer 101 can provide good protection for the components. For example, the first shielding portion 1011 formed in the first region A1, which is located at the bottom of the first gate trench structure 112G-1 of the VDMOS component, can prevent the gate insulating layer in the gate trench structure from being damaged by a high-intensity electric field. For example, the second shielding portion 1012 formed in the second region A2 and the third region A3, which is located below the CMOS component and covers the bottoms of the relevant well regions and gate trench structures (including the second gate trench structure 112G-2 and the third gate trench structure 112G-3) of the CMOS component, can thus serve as a good isolation layer for the CMOS component in the epitaxial layer 102.

[0119] Furthermore, for a conventional planar CMOS device (without a gate trench structure), pins are disposed on the top surface of the epitaxial layer. The accumulated charges in the isolation layer buried inside the epitaxial layer can only be led out through the well region between the isolation layer and the surface pins, and there is no conductor directly connecting the isolation layer and the surface pins. Therefore, the path for leading out the accumulated charges is relatively long, and the ability to remove charges is weak. For the semiconductor device according to some embodiments of the present invention, the bottom (such as the bottom conductive portion 1121) of the gate trench structure (such as the first gate trench structure 112G-1, the second gate trench structure 112G-2, and the third gate trench structure 112G-3) of each component is in direct contact with and electrically connected to the shielding layer 101. The shielding layer 101 contains dopants of a second conductivity type (such as p-type), and the shielding layer 101 can be grounded through a connection line (not shown). Therefore, when operating the semiconductor device of the embodiment, if charges accumulate at the bottom conductive portion 1121, the shielding layer 101 in direct contact with the bottom conductive portion 1121 can quickly lead out the accumulated charges. Therefore, the semiconductor device of the embodiment has a better ability to remove charge interference.

[0120] According to the manufacturing method proposed in some embodiments, as described in the above exemplary steps, for components in different regions, such as forming a first component (such as a VDMOS component) in the first region A1, a second component (such as an NMOS component) in the second region A2, and a third component (such as a PMOS component) in the third region A3 as described above, since many related components of the CMOS component of the embodiment can be fabricated simultaneously with the components of the VDMOS component, only slight modification of the process steps is required, such as adding two additional masks to fabricate the well region 1062 ( Figure 5 ) of the NMOS component and fabricating the planar gate structure 114 ( Figure 9 ) of the NMOS component / PMOS component, the semiconductor device of the embodiment can be fabricated. The process is simple and compatible with the existing process.

Claims

1. A semiconductor device, characterized in that, Comprising: A substrate having a first conductivity type; An epitaxial layer located on the substrate, and the epitaxial layer has the first conductivity type; A first element, comprising: A first gate trench structure extending from the top surface of the epitaxial layer into the epitaxial layer, wherein the substrate serves as a drain of the first element; and A first shielding portion located below the first gate trench structure and in contact with the bottom of the first gate trench structure, and the first shielding portion has a second conductivity type; and A second element spaced apart from the first element and electrically connected to the first element, the second element comprising: A second gate trench structure extending from the top surface of the epitaxial layer into the epitaxial layer; A planar gate structure located on the top surface of the epitaxial layer; and A second shielding portion located below the second gate trench structure and in contact with the bottom of the second gate trench structure, and the second shielding portion has the second conductivity type.

2. The semiconductor device according to claim 1, wherein The first gate trench structure and the second gate trench structure are respectively a split gate trench structure, and the split gate trench comprises: A bottom conductive portion; A top conductive portion located on the bottom conductive portion; and An insulating layer covering the sidewalls of the bottom conductive portion and the top conductive portion and located between the bottom conductive portion and the top conductive portion to electrically isolate the bottom conductive portion from the top conductive portion.

3. The semiconductor device according to claim 2, wherein, The bottom conductive portion of the first gate trench structure physically contacts and electrically connects to the first shielding portion, and the bottom conductive portion of the second gate trench structure physically contacts and electrically connects to the second shielding portion.

4. The semiconductor device according to claim 1, wherein The first gate trench structure and the second gate trench structure have the same vertical depth in the epitaxial layer.

5. The semiconductor device according to claim 1, wherein, The first shielding portion and the second shielding portion have the same horizontal height.

6. The semiconductor device according to claim 1, wherein, The first gate trench structure and the second gate trench structure extend in a first direction, and the second element is spaced apart from the first element in a second direction different from the first direction. The second element further comprises: A source region and a drain region respectively corresponding to opposite sides of the planar gate structure, and the source region and the drain region are spaced apart in the first direction.

7. The semiconductor device according to claim 6, wherein, The second element has two of the second gate trench structures spaced apart in the second direction, the planar gate structure, the source region and the drain region are located between the two second gate trench structures, one set of opposite sidewalls of the planar gate structure extends in the first direction, and the source region and the drain region correspond to the other set of opposite sidewalls of the planar gate structure and extend between the two second gate trench structures.

8. The semiconductor device according to claim 1, wherein, The first element further comprises: A current diffusion layer located in the epitaxial layer and in contact with the first shielding portion, and the current diffusion layer has the first conductivity type, wherein the doping concentration of the current diffusion layer is greater than that of the epitaxial layer; A base region located in the current diffusion layer and extending downward from the top surface of the epitaxial layer, and the base region has the second conductivity type; and A first heavily doped portion formed in the base region and extending downward from the top surface of the epitaxial layer, the first heavily doped portion has the first conductivity type and serves as a source region of the first element.

9. The semiconductor device according to claim 8, wherein The first element has two of the first gate trench structures spaced apart in a second direction and two of the first shielding portions corresponding to below the two first gate trench structures, wherein the current diffusion layer extends between the two first shielding portions, and a bottom surface of the current diffusion layer is coplanar with bottom surfaces of the two first shielding portions.

10. The semiconductor device according to claim 1, characterized in that, The second element further includes: a well region extending downward from the top surface of the epitaxial layer to contact the second shielding portion, a sidewall of the well region contacting the second gate trench structure, and the well region having the second conductivity type, wherein the planar gate structure is correspondingly located above the well region; and a first heavily doped portion formed in the well region and extending downward from the top surface of the epitaxial layer, and the first heavily doped portion having the first conductivity type to respectively serve as a source region and a drain region of the second element.

11. The semiconductor device according to claim 1, wherein, It further includes: a third element spaced apart from the first element, and the third element being electrically connected to the second element, the third element including: a third gate trench structure extending from the top surface of the epitaxial layer into the epitaxial layer.

12. The semiconductor device according to claim 11, wherein The second shielding portion below the second gate trench structure continuously extends below the third gate trench structure and is in direct contact with and electrically connected to a bottom of the third gate trench structure.

13. The semiconductor device according to claim 12, wherein, The third element further includes: a current diffusion layer located in the epitaxial layer and in contact with the second shielding portion, and the current diffusion layer having the first conductivity type, wherein a doping concentration of the current diffusion layer is greater than a doping concentration of the epitaxial layer; a second heavily doped portion extending downward from the top surface of the epitaxial layer, and the second heavily doped portion having the second conductivity type to respectively serve as a source region and a drain region of the third element.

14. The semiconductor device according to claim 13, wherein The second shielding portion directly contacts and covers the bottom surface of the current diffusion layer.

15. The semiconductor device according to claim 11, wherein, The second element is an NMOS element, the third element is a PMOS element, the second element and the third element constitute a complementary metal oxide semiconductor element, and the complementary metal oxide semiconductor element serves as a switching element for controlling the first element.

16. A method for forming a semiconductor device, characterized in that It includes: providing a substrate having a first conductivity type; forming an epitaxial layer on the substrate, the epitaxial layer having the first conductivity type; forming a first element and a second element at a first region and a second region of the epitaxial layer respectively, the second element being spaced apart from and electrically connected to the first element, wherein the first element includes: a first gate trench structure extending from the top surface of the epitaxial layer into the epitaxial layer, wherein the substrate serves as a drain of the first element; and a first shielding portion located below the first gate trench structure and in contact with a bottom of the first gate trench structure, and the first shielding portion having a second conductivity type; wherein the second element includes: a second gate trench structure extending from the top surface of the epitaxial layer into the epitaxial layer; a planar gate structure located on the top surface of the epitaxial layer; and a second shielding portion located below the second gate trench structure and in contact with a bottom of the second gate trench structure, and the second shielding portion having the second conductivity type.

17. The method for forming a semiconductor device according to claim 16, wherein, The first shielding portion and the second shielding portion are formed in the same process.

18. The method for forming a semiconductor device according to claim 16, wherein, The first gate trench structure and the second gate trench structure are formed in the same process.

19. The method for forming a semiconductor device according to claim 16, wherein, After forming the first shielding portion and the second shielding portion, it further includes: Forming a current diffusion layer in the epitaxial layer at the first region, the current diffusion layer extending downward from the top surface of the epitaxial layer to contact the first shielding portion, the current diffusion layer having the first conductivity type, wherein the doping concentration of the current diffusion layer is greater than the doping concentration of the epitaxial layer; Forming a base region in the current diffusion layer, the base region being doped downward from the top surface of the epitaxial layer and extending in the current diffusion layer, and the base region having the second conductivity type; and Forming a well region at the second region, and the well region extending downward from the top surface of the epitaxial layer to contact the second shielding portion.

20. The method for forming a semiconductor device according to claim 19, wherein, After forming the base region and the well region, it further includes: Simultaneously forming a first heavily doped portion in the base region at the first region and the well region at the second region, the first heavily doped portion having the first conductivity type, to serve as the source region of the first element and the source region and drain region of the second element; and Simultaneously forming a second heavily doped portion in the base region at the first region and the well region at the second region, the second heavily doped portion having the second conductivity type, to serve as the base region of the first element and the second element.

21. The method for forming a semiconductor device according to claim 20, wherein, After forming the current diffusion layer, the base region, the well region, the first heavily doped portion and the second heavily doped portion, the first gate trench structure and the second gate trench structure are respectively formed at the first region and the second region.

22. The method for forming a semiconductor device according to claim 16, wherein, The formed first gate trench structure and second gate trench structure are respectively a split gate trench structure.

23. The method of forming a semiconductor device according to claim 16, wherein, It further includes: Forming a third element in a third region of the epitaxial layer, the third element being spaced apart from the first element and the second element, and the third element being electrically connected to the second element, wherein the second shielding portion under the second gate trench structure continuously extends to the third region.

24. The method for forming a semiconductor device according to claim 23, wherein, The third element includes: A third gate trench structure extending from the top surface of the epitaxial layer into the epitaxial layer, and the bottom of the third gate trench structure contacts the second shielding portion.

25. The method for forming a semiconductor device according to claim 24, wherein, The first gate trench structure, the second gate trench structure and the third gate trench structure are formed in the same process.

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