Semiconductor device and forming method thereof

Abstract

In an embodiment, a semiconductor device may include a plurality of first nanostructures. A plurality of first nanostructures extend between the first source / drain regions. The semiconductor device may also include a plurality of second nanostructures over the plurality of first nanostructures. A second plurality of nanostructures extends between the second source / drain regions. The device may further include a first gate stack around the plurality of first nanostructures. The device may additionally include a second gate stack over the first gate stack and disposed around the plurality of second nanostructures. The device may also include a vertical interconnect structure extending through the first gate stack and the second gate stack. The device may also include a front side contact electrically coupled to a front side of the vertical interconnect structure and a back side contact electrically coupled to a back side of the vertical interconnect structure. The embodiment of the invention relates to a semiconductor device and a forming method thereof.

Description

Technical Field

[0001] Embodiments of the present application relate to semiconductor devices and methods of forming the same. Background Art

[0002] Semiconductor devices are used in a variety of electronic applications such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically fabricated by successively depositing insulating or dielectric layers, conductive layers, and semiconductor layers over a semiconductor substrate; and patterning the individual material layers using lithography to form circuit components and elements thereon.

[0003] The semiconductor industry continues to improve the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continuously reducing the minimum feature size, which allows more components to be integrated into a given area. As the semiconductor industry further advances towards increased device density, higher performance, and lower cost, challenges from manufacturing and design have led to stacked device configurations such as stacked transistors, which include complementary field effect transistors (CFETs). However, as the minimum feature size decreases, additional components are introduced. Summary of the Invention

[0004] Some embodiments of the present application provide a semiconductor device, including: a plurality of first nanostructures extending between a first source / drain region; a plurality of second nanostructures located above the plurality of first nanostructures and extending between a second source / drain region; a first gate stack located around the plurality of first nanostructures; a second gate stack located above the first gate stack and disposed around the plurality of second nanostructures; a vertical interconnect structure extending through the first gate stack and the second gate stack; a front-side contact electrically coupled to a front side of the vertical interconnect structure; and a back-side contact electrically coupled to a back side of the vertical interconnect structure.

[0005] Some other embodiments of the present application provide a method of forming a semiconductor device, including: forming a first transistor and a second transistor vertically stacked over a semiconductor substrate; removing a first gate stack of the first transistor and a second gate stack of the second transistor, the removing forming a first trench; forming a first dielectric layer in the first trench; depositing a conductive material over the first dielectric layer; etching a second trench in the conductive material; forming a second dielectric layer in the second trench, the conductive material being located between the first dielectric layer and the second dielectric layer; and forming a front-side conductive contact on a front side of the conductive material, the front-side conductive contact being electrically coupled to the conductive material and a source / drain of the second transistor.

[0006] Some further embodiments of the present application provide a method of forming a semiconductor device, including: forming a multi-layer stack above a semiconductor substrate, the multi-layer stack including alternating semiconductor nanostructures and pseudo-nanostructures; forming lower source / drain regions, wherein lower semiconductor nanostructures of the semiconductor nanostructures extend between the lower source / drain regions; forming upper source / drain regions above the lower source / drain regions, wherein upper semiconductor nanostructures of the semiconductor nanostructures extend between the upper source / drain regions; replacing the pseudo-nanostructures with a lower gate stack surrounding the lower semiconductor nanostructures and an upper gate stack surrounding the upper semiconductor nanostructures; etching a first trench through the upper gate stack and the lower gate stack; forming a bottom dielectric layer in a bottom of the first trench; forming a conductive interconnect on the bottom dielectric layer in the first trench; forming a second trench in the conductive interconnect; forming a dielectric material in the second trench; forming a front-side conductive contact on a front side of the conductive interconnect; and forming a back-side conductive contact on a back side of the conductive interconnect, the front-side conductive contact and the back-side conductive contact being electrically coupled to the conductive interconnect. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Aspects of embodiments of the present disclosure are best understood from the following detailed description when read with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, for the sake of clarity of discussion, the dimensions of the various components may be arbitrarily increased or decreased.

[0008] Figure 1 A perspective view of an exemplary stacked transistor in accordance with some embodiments is shown.

[0009] Figure 2 、 Figure 3 、 Figure 4 、 Figure 5A 、 Figure 5B 、 Figure 6A 、 Figure 6B 、 Figure 6C 、 Figure 7A 、 Figure 7B 、 Figure 8A 、 Figure 8B 、 Figure 9A 、 Figure 9B 、 Figure 9C 、 Figure 10A 、 Figure 10B 、 Figure 10C 、 Figure 11A 、 Figure 11B 、 Figure 12A 、 Figure 12B 、 Figure 13A 、 Figure 13B 、Figure 14A , Figure 14B , Figure 14C , Figure 15A and Figure 15B are views of intermediate stages in the fabrication of stacked transistors according to some embodiments.

[0010] Figure 16A and Figure 16B are views of intermediate stages in the fabrication of stacked transistors according to some embodiments.

[0011] Figure 17A and Figure 17B are views of intermediate stages in the fabrication of stacked transistors according to some embodiments. DETAILED DESCRIPTION

[0012] The following disclosure provides many different embodiments or examples for implementing different features of the embodiments of the present disclosure. Specific examples of components and arrangements are described below to simplify the embodiments of the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include embodiments where the first component and the second component are in direct contact, and may also include embodiments where additional components may be formed between the first component and the second component such that the first component and the second component may not be in direct contact. In addition, the embodiments of the present disclosure may repeat reference numerals and / or characters in various examples. This repetition is for the purpose of simplicity and clarity, and in itself does not indicate the relationship between the various embodiments and / or configurations discussed.

[0013] In addition, for ease of description, spatially relative terms such as "below", "beneath", "lower", "above", "upper", etc. may be used herein to describe the relationship of one element or component to another (or other) element or component as shown in the figures. Except for the orientation depicted in the figures, the spatially relative terms are intended to include different orientations of the device during use or operation. The device may be oriented otherwise (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein may be interpreted accordingly.

[0014] Stacked transistors (such as CFETs) and methods of forming the same are provided. In various embodiments, the stacked transistor includes two vertically stacked transistors and a vertical interconnect structure extending through the stacked transistor. The vertical interconnect structure allows for backside interconnect wiring and can reduce the need and size of frontside interconnects. The vertical interconnect structure extends through the stacked transistor in a cut metal gate region of the transistor. Additionally, the vertical interconnect structure may include a cut region to reduce capacitance and increase the speed of the device. In some embodiments, the vertical interconnect structure may couple the drain regions of the stacked transistors.

[0015] The vertical interconnect structure includes a metal interconnect structure and a bottom dielectric structure that reduces the aspect ratio of the metal interconnect structure and avoids seams or voids in the metal interconnect structure. Additionally, the disclosed embodiments include a backside planarization process to expose the metal interconnects of the vertical interconnect structure without causing the metal interconnects to protrude from the backside. Thus, the disclosed embodiments provide a vertical interconnect structure without metal protruding from the backside. Accordingly, the disclosed embodiments allow for improved process integration, increased routing flexibility, and increased device performance.

[0016] Figure 1 An example of a stacked transistor 10 (including FETs (transistors) 10U and 10L) according to some embodiments is shown. Figure 1 is a three - dimensional view, and some components of the stacked transistor are omitted for clarity of illustration.

[0017] The stacked transistor includes a plurality of vertically stacked FETs. For example, the stacked transistor can include a lower nanostructure FET 10L of a first device type (e.g., n - type / p - type) and an upper nanostructure FET 10U of a second device type (e.g., p - type / n - type). When the stacked transistor is a CFET, the second device type of the upper nanostructure FET 10U is opposite to the first device type of the lower nanostructure FET 10L. The nanostructure FETs 10U and 10L include semiconductor nanostructures 26 (including a lower semiconductor nanostructure 26L and an upper semiconductor nanostructure 26U), where the semiconductor nanostructure 26 serves as the channel region for the nanostructure FETs. The lower semiconductor nanostructure 26L is for the lower nanostructure FET 10L, and the upper semiconductor nanostructure 26U is for the upper nanostructure FET 10U. In other embodiments, the stacked transistor can also be applicable to other types of transistors (e.g., finFETs, etc.).

[0018] The gate dielectric 78 surrounds the respective semiconductor nanostructures 26. Gate electrodes 80 (including a lower gate electrode 80L and an upper gate electrode 80U) are located above the gate dielectric 78. Source / drain regions 62 (including a lower source / drain region 62L and an upper source / drain region 62U) are provided on opposite sides of the gate dielectric 78 and the respective gate electrodes 80. Each of the source / drain regions 62 can refer to a source or a drain, individually or jointly depending on the context. Isolation components (not shown) can be formed to separate the desired source / drain regions 62 and / or the desired gate electrodes 80.

[0019] Figure 1Also shown are reference cross-sections used in the subsequent figures. Cross-section A-A' is a vertical cross-section parallel to the longitudinal axis of the semiconductor nanostructure 26 of the stacked transistor 10 and in the current direction between the source / drain regions 62 of the stacked transistor 10, for example. Cross-section B-B' is a vertical cross-section perpendicular to cross-section A-A' and along the longitudinal axis of the gate electrode 80 of the stacked transistor 10.

[0020] Figures 2 to 15B Shows a variation view of an intermediate stage in the formation of a stacked transistor (as schematically shown in Figure 1 ) according to some embodiments. Figure 2 Shows a perspective view similar to Figure 1 . Figure 3 , Figure 4 and Figure 5A show cross-sectional views along a cross-section similar to the reference cross-section A-A' in Figure 1 . Figure 5B Shows a cross-sectional view along a cross-section similar to the reference cross-section B-B' in Figure 1 .

[0021] In Figure 2 , a wafer is provided, the wafer including a substrate 20. The substrate 20 can be a semiconductor substrate, such as a bulk semiconductor, which can be doped (e.g., with p-type or n-type dopants) or undoped. Other substrates can also be used, such as multi-layer or gradient substrates. In some embodiments, the semiconductor material of the substrate 20 can include silicon, germanium, carbon-doped silicon, III-V compound semiconductors; etc. or combinations thereof.

[0022] Semiconductor strips 28 are formed extending upward from the semiconductor substrate 20. Each of the semiconductor strips 28 includes a semiconductor strip 20' (a patterned portion of the semiconductor substrate 20, also referred to as a semiconductor fin 20') and a multi-layer stack 22. The stacked components of the multi-layer stack 22 are hereinafter referred to as nanostructures. Specifically, the multi-layer stack 22 includes a pseudo-nanostructure 24A, a pseudo-nanostructure 24B, a lower semiconductor nanostructure 26L, and an upper semiconductor nanostructure 26U. The pseudo-nanostructure 24A and the pseudo-nanostructure 24B can also be collectively referred to as the pseudo-nanostructure 24, and the lower semiconductor nanostructure 26L and the upper semiconductor nanostructure 26U can also be collectively referred to as the semiconductor nanostructure 26.

[0023] The pseudo-nanostructure 24A is formed of a first semiconductor material, and the pseudo-nanostructure 24B is formed of a second semiconductor material different from the first semiconductor material. The first semiconductor material and the second semiconductor material can be selected from the candidate semiconductor materials of the substrate 20. The first semiconductor material and the second semiconductor material have a high etch selectivity with respect to each other. Thus, in a subsequent process, the pseudo-nanostructure 24B can be removed at a rate faster than the pseudo-nanostructure 24A.

[0024] The semiconductor nanostructure 26 (including the lower semiconductor nanostructure 26L and the upper semiconductor nanostructure 26U) is formed of one or more third semiconductor materials. The third semiconductor material can be selected from the candidate semiconductor materials of the substrate 20. The lower semiconductor nanostructure 26L and the upper semiconductor nanostructure 26U can be formed of the same semiconductor material or can be formed of different semiconductor materials. Additionally, the first and second semiconductor materials of the pseudo-nanostructure 24 have a high etch selectivity to the third semiconductor material of the semiconductor nanostructure 26. Thus, the pseudo-nanostructure 24 can be selectively removed in subsequent process steps without significantly removing the semiconductor nanostructure 26. In some embodiments, the pseudo-nanostructure 24A is formed of or includes silicon germanium, the semiconductor nanostructure 26 is formed of silicon, and the pseudo-semiconductor nanostructure 24B can be formed of germanium or silicon germanium having a higher percentage of germanium atoms than the pseudo-nanostructure 24A.

[0025] The lower semiconductor nanostructure 26L will provide the channel region of the lower nanostructure FET for the CFET. The upper semiconductor nanostructure 26U will provide the channel region of the upper nanostructure FET for the CFET. The semiconductor nanostructure 26 closely located above / below (e.g., in contact with) the pseudo-nanostructure 24B can be used for isolation and can or cannot be used as the channel region for the CFET. The pseudo-nanostructure 24B will subsequently be replaced with an isolation structure that defines the boundary between the lower nanostructure FET and the upper nanostructure FET.

[0026] To form the semiconductor strip 28, layers of a first semiconductor material, a second semiconductor material, and a third semiconductor material (arranged as shown and described above) may be deposited over the semiconductor substrate 20. The layers of the first semiconductor material, the second semiconductor material, and the third semiconductor material may be grown by a process such as vapor phase epitaxy (VPE) or molecular beam epitaxy (MBE), and deposited by a process such as chemical vapor deposition (CVD) process or atomic layer deposition (ALD) process, etc. Then, a patterning process may be applied to the layers of the first semiconductor material, the second semiconductor material, and the third semiconductor material, and the semiconductor substrate 20 to define the semiconductor strip 28, which includes a semiconductor fin 20', a pseudo-nanostructure 24, and a semiconductor nanostructure 26. The semiconductor fin and nanostructure may be patterned by any suitable method. For example, the patterning process may include one or more lithography processes, including double patterning or multiple patterning processes. Generally, double patterning or multiple patterning processes combine lithography and self-alignment processes, thereby allowing the creation of patterns with, for example, a pitch smaller than that obtainable using a single, direct lithography process. For example, in one embodiment, a sacrificial layer is formed over the substrate and patterned using a lithography process. A spacer is formed adjacent to the patterned sacrificial layer using a self-alignment process. Then the sacrificial layer is removed, and then the remaining spacer may be used as an etch mask for the patterning process to etch the layers of the first semiconductor material, the second semiconductor material, and the third semiconductor material, and the semiconductor substrate 20. The etching may be implemented by any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), etc. or a combination thereof. The etching may be anisotropic.

[0027] Also as Figure 2 shown, a shallow trench isolation (STI) region 32 is formed between the substrate 20 and adjacent semiconductor strips 28. The STI region 32 may include a dielectric liner and a dielectric material over the dielectric liner. Each of the dielectric liner and the dielectric material may include an oxide such as silicon oxide, a nitride such as silicon nitride, etc. or a combination thereof. The formation of the STI region 32 may include: depositing a dielectric layer; and implementing a planarization process such as a chemical mechanical polishing (CMP) process, a mechanical polishing process, etc. to remove an excess portion of the dielectric material. The deposition process may include ALD, high density plasma CVD (HDP-CVD), flowable CVD (FCVD), etc. or a combination thereof. In some embodiments, the STI region 32 includes silicon oxide formed by an FCVD process, followed by an annealing process. Then, the dielectric layer is recessed to define the STI region 32. The dielectric layer may be recessed such that an upper portion of the semiconductor strip 28 (including the multilayer stack 22) protrudes above the remaining STI region 32. Although Figure 2 shown that the top surface of the STI region 32 is flat, the top surface of the STI region 32 may be concave (seeFigure 5B and Figure 7B a more detailed view of), depending on the etching process used to recess the STI region 32.

[0028] After forming the STI region 32, a dummy gate stack 42 can be formed above and along the sidewalls of the upper portion of the semiconductor strip 28 (the portion protruding above the STI region 32). Forming the dummy gate stack 42 can include forming a dummy dielectric layer 36 on the semiconductor strip 28. The dummy dielectric layer 36 can be formed of or include, for example, silicon oxide, silicon nitride, combinations thereof, etc., and can be deposited or thermally grown according to acceptable techniques. A dummy gate layer 38 is formed above the dummy dielectric layer 36. The dummy gate layer 38 can be deposited, for example, by physical vapor deposition (PVD), CVD, or other techniques, and then planarized, such as by a CMP process. The material of the dummy gate layer 38 can be conductive or non-conductive, and can be selected from the group including amorphous silicon, polysilicon (poly-Si), poly-silicon germanium (poly-SiGe), etc. A mask layer 40 including, for example, silicon nitride, silicon oxynitride, etc. is formed above the planarized dummy gate layer 38. Next, the mask layer 40 can be patterned by photolithography and etching processes to form a mask, and then the mask is used to etch and pattern the dummy gate layer 38, and possibly etch and pattern the dummy dielectric layer 36. The remaining portions of the mask layer 40, the dummy gate layer 38, and the dummy dielectric layer 36 form the dummy gate stack 42.

[0029] In Figure 3 , gate spacers 44 and source / drain recesses 46 are formed. First, the gate spacers 44 are formed above the multi-layer stack 22 and on the exposed sidewalls of the dummy gate stack 42. The gate spacers 44 can be formed by conformally forming one or more dielectric layers and then anisotropically etching the dielectric layers. Suitable dielectric materials can include silicon oxide, silicon nitride, silicon oxynitride, carbon oxynitride, etc., which can be formed by deposition processes such as CVD, ALD, etc.

[0030] Subsequently, source / drain recesses 46 are formed in the semiconductor strip 28. The source / drain recesses 46 are formed by etching and can extend through the multi-layer stack 22 and into the semiconductor strip 20'. The bottom surface of the source / drain recesses 46 can be above, below, or flush with the top surface of the STI region 32. In the etching process, the gate spacers 44 and the dummy gate stack 42 mask some portions of the semiconductor strip 28. The etching can include a single etching process or multiple etching processes. When the source / drain recesses 46 reach the desired depth, a timed etching process can be used to stop the etching of the source / drain recesses 46.

[0031] InFigure 4 In this case, an internal spacer 54 and a dielectric isolation layer 56 are formed. Forming the internal spacer 54 and the dielectric isolation layer 56 may include an etching process of laterally etching the pseudo-nanostructures 24A and removing the pseudo-nanostructures 24B. The etching process may be isotropic and may be selective to the material of the pseudo-nanostructures 24, such that the pseudo-nanostructures 24 are etched at a rate faster than that of the semiconductor nanostructures 26. The etching process may also be selective to the material of the pseudo-nanostructures 24B, such that the pseudo-nanostructures 24B are etched at a rate faster than that of the pseudo-nanostructures 24A. In this way, the pseudo-nanostructures 24B can be completely removed between the lower semiconductor nanostructures 26L (collectively) and the upper semiconductor nanostructures 26U (collectively) without completely removing the pseudo-nanostructures 24A. In some embodiments, where the pseudo-nanostructures 24B are formed of germanium or silicon germanium with a high germanium atom percentage, the pseudo-nanostructures 24A are formed of silicon germanium with a low germanium atom percentage, and the semiconductor nanostructures 26 are formed of silicon without germanium, the etching process may include a dry etching process using chlorine gas, with or without plasma. Since the pseudo-gate stack 42 wraps the sidewalls of the semiconductor nanostructures 26 (see Figure 2 ), the pseudo-gate stack 42 can support the upper semiconductor nanostructures 26U such that the upper semiconductor nanostructures 26U do not collapse when the pseudo-nanostructures 24B are removed. Additionally, although the sidewalls of the pseudo-nanostructures 24A are shown as being straight after etching, the sidewalls may be concave or convex.

[0032] The internal spacer 54 is formed on the sidewalls of the recessed pseudo-nanostructures 24A, and the dielectric isolation layer 56 is formed between the upper semiconductor nanostructures 26U (collectively) and the lower semiconductor nanostructures 26L (collectively). As will be described in more detail subsequently, source / drain regions will be formed in the source / drain trenches 46, and the pseudo-nanostructures 24A will be replaced with corresponding gate structures. The internal spacer 54 serves as an isolation component between the subsequently formed source / drain regions and the subsequently formed gate structures. Additionally, the internal spacer 54 can be used to prevent damage to the subsequently formed source / drain regions by subsequent etching processes, such as the etching process for forming the gate structures. On the other hand, the dielectric isolation layer 56 is used to isolate the upper semiconductor nanostructures 26U (collectively) from the lower semiconductor nanostructures 26L (collectively). Additionally, the intermediate semiconductor nanostructures (the semiconductor nanostructures 26 in contact with the dielectric isolation layer 56) and the dielectric isolation layer 56 can define the boundaries of the lower nanostructure FETs and the upper nanostructure FETs.

[0033] The internal spacer 54 and the dielectric isolation layer 56 can be formed by: conformally depositing an insulating material in the source / drain recess 46, on the sidewalls of the pseudo-nanostructure 24, and between the upper semiconductor nanostructure 26U and the lower semiconductor nanostructure 26L; and then etching the insulating material. The insulating material can be a hard dielectric material, such as a carbon-containing dielectric material, such as silicon carbonitride, silicon oxycarbide, silicon oxynitride, etc. Other low dielectric constant (low-k) materials with a k value less than about 3.5 can be utilized. The insulating material can be formed by a deposition process, such as ALD, CVD, etc. The etching of the insulating material can be anisotropic or isotropic. The insulating material (when etched) has a portion that remains in the sidewalls of the pseudo-nanostructure 24A (thus forming the internal spacer 54), and has a portion that remains between the upper semiconductor nanostructure 26U and the lower semiconductor nanostructure 26L (thus forming the dielectric isolation layer 56).

[0034] Similarly, as Figure 4 shown, a lower epitaxial source / drain region 62L and an upper epitaxial source / drain region 62U are formed. The lower epitaxial source / drain region 62L is formed in the lower portion of the source / drain recess 46. The lower epitaxial source / drain region 62L contacts the lower semiconductor nanostructure 26L and does not contact the upper semiconductor nanostructure 26U. The internal spacer 54 electrically insulates the lower epitaxial source / drain region 62L from the pseudo-nanostructure 24A, which will be replaced with a replacement gate in a subsequent process.

[0035] The lower epitaxial source / drain region 62L is epitaxially grown and has a conductivity type suitable for the device type (p-type or n-type) of the lower nanostructure FET. When the lower epitaxial source / drain region 62L is an n-type source / drain region, the corresponding material can include silicon or carbon-doped silicon, which is doped with an n-type dopant such as phosphorus, arsenic, etc. When the lower epitaxial source / drain region 62L is a p-type source / drain region, the corresponding material can include silicon or silicon germanium, which is doped with a p-type dopant such as boron, indium, etc. The lower epitaxial source / drain region 62L can be in-situ doped and can or cannot be implanted with the corresponding p-type or n-type dopant. During the epitaxy of the lower epitaxial source / drain region 62L, the exposed surface (e.g., sidewalls) of the upper semiconductor nanostructure 26U can be masked to prevent unwanted epitaxial growth on the upper semiconductor nanostructure 26U. After the growth of the lower epitaxial source / drain region 62L, the mask on the upper semiconductor nanostructure 26U can then be removed.

[0036] Due to the epitaxial process used to form the lower epitaxial source / drain region 62L, the upper surface of the lower epitaxial source / drain region 62L has facets that laterally extend outward beyond the sidewalls of the multi-layer stack 22. In some embodiments, adjacent lower epitaxial source / drain regions 62L remain separated after the epitaxial process is completed. In other embodiments, these facets cause adjacent lower epitaxial source / drain regions 62L of the same FET to merge.

[0037] A first contact etch stop layer (CESL) 66 and a first ILD 68 are formed over the lower epitaxial source / drain region 62L. The first CESL 66 can be formed of a dielectric material having a high etch selectivity with respect to the etch of the first ILD 68, such as silicon nitride, silicon oxide, silicon oxynitride, etc., which can be formed by any suitable deposition process, such as CVD, ALD, etc. The first ILD 68 can be formed of a dielectric material, which can be deposited by any suitable method, such as CVD, plasma enhanced CVD (PECVD), or FCVD. Suitable dielectric materials for the first ILD 68 can include phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), silicon oxide, etc.

[0038] The forming process can include: depositing a conformal CESL layer; depositing the material for the first ILD 68; and subsequent planarization processes and then an etch-back process. In some embodiments, the first ILD 68 is first etched, leaving the first CESL 66 unetched. Then an anisotropic etch process is implemented to remove the portion of the first CESL 66 that is above the recessed first ILD 68. After the recessing, the sidewalls of the upper semiconductor nanostructure 26U are exposed.

[0039] Then, an upper epitaxial source / drain region 62U is formed in the upper portion of the source / drain recess 46. The upper epitaxial source / drain region 62U can grow epitaxially from the exposed surface of the upper semiconductor nanostructure 26U. The material of the upper epitaxial source / drain region 62U can be selected from the same group of candidate materials used to form the lower source / drain region 62L, depending on the desired conductivity type of the upper epitaxial source / drain region 62U. In an embodiment where the stacked transistor is a CFET, the conductivity type of the upper epitaxial source / drain region 62U can be opposite to that of the lower epitaxial source / drain region 62L. For example, the upper epitaxial source / drain region 62U can be doped oppositely to the lower epitaxial source / drain region 62L. Optionally, the conductivity types of the upper epitaxial source / drain region 62U and the lower epitaxial source / drain region 62L can be the same. The upper epitaxial source / drain region 62U can be in-situ doped with an n-type or p-type dopant and / or can be implanted with an n-type or p-type dopant. Adjacent upper source / drain regions 62U can remain separated after the epitaxial process or can be merged.

[0040] After forming the upper epitaxial source / drain region 62U, a second CESL 70 and a second ILD 72 are formed. The materials and the formation methods can be respectively similar to those of the first CESL 66 and the first ILD 68, and will not be discussed in detail herein. The formation process can include: depositing layers for the second CESL 70 and the second ILD 72; and performing a planarization process to remove the excess portions of the corresponding layers. After the planarization process, the top surfaces of the second ILD 72, the gate spacers 44, and the mask 40 (if present) or the dummy gate layer 38 are substantially coplanar (within the process variation range). Thus, the top surface of the mask 40 (if present) or the dummy gate layer 38 is exposed through the second ILD 72. In the illustrated embodiment, the mask 40 remains after the removal process. In other embodiments, the mask 40 is removed, such that the top surface of the dummy gate layer 38 is exposed through the second ILD 72.

[0041] Figure 5A and Figure 5B Different cross-sections of a replacement gate process for replacing the dummy gate stack 42 and the dummy nanostructure 24A with a gate stack 90 are shown. Figure 5A Shows along Figure 1 the reference line A-A'; and Figure 5B shows along Figure 1Cross-sectional view of reference line B-B'. The replacement gate process includes first removing the remaining portions of the dummy gate stack 42 and the dummy nanostructures 24A. The dummy gate stack 42 is removed in one or more etching processes, thereby defining a recess between the gate spacers 44 and exposing the upper portion of the semiconductor strip 28. Then, the remaining portions of the dummy nanostructures 24A are removed by etching such that the recess extends between the semiconductor nanostructures 26. In the etching process, the dummy nanostructures 24A are etched at a rate faster than the semiconductor nanostructures 26, the dielectric isolation layer 56, and the inner spacers 54. The etching can be isotropic. For example, when the dummy nanostructures 24A are formed of silicon germanium and the semiconductor nanostructures 26 are formed of silicon, the etching process can include a wet etching process using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), etc.

[0042] Then, a gate dielectric 78 is deposited in the recess between the gate spacers 44 and on the exposed semiconductor nanostructures 26. The gate dielectric 78 is conformally formed on the exposed surfaces of the recess (the removed dummy gate stack 42 and the dummy nanostructures 24A) including the semiconductor nanostructures 26 and the gate spacers 44. In some embodiments, the gate dielectric 78 wraps all (e.g., four) sides of the semiconductor nanostructures 26. Specifically, the gate dielectric 78 can be formed on the top surface of the semiconductor fin 20'; on the top surface, sidewalls, and bottom surface of the semiconductor nanostructures 26; and on the sidewalls of the gate spacers 44. The gate dielectric 78 can include oxides such as silicon oxide or metal oxide, silicates such as metal silicate, combinations thereof, multilayers thereof, etc. The gate dielectric 78 can include a high dielectric constant (high-k) material having a k value greater than about 7.0, such as metal oxides or silicates of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. The gate dielectric 78 can be deposited using a conformal deposition process such that the portion of the gate dielectric 78 located on the STI region 32 can have the same profile as the upper surface of the STI region 32 (e.g., the concave profile as Figure 5B shown). The method of forming the gate dielectric 78 can include molecular beam deposition (MBD), ALD, PECVD, etc. and subsequent planarization processes (e.g., CMP) to remove the portion of the gate dielectric 78 located above the second ILD 72. Although a single-layer gate dielectric 78 is shown, the gate dielectric 78 can include multiple layers, such as an interface layer and an upper high-k dielectric layer.

[0043] A lower gate electrode 80L is formed on a gate dielectric 78 surrounding a lower semiconductor nanostructure 26L. For example, the lower gate electrode 80L wraps around the lower semiconductor nanostructure 26L. The lower gate electrode 80L can be formed of a metal-containing material such as tungsten, titanium, titanium nitride, tantalum, tantalum nitride, tantalum carbide, aluminum, ruthenium, cobalt, combinations thereof, multilayers thereof, etc. Although a single-layer gate electrode is shown, the lower gate electrode 80L can include any number of work function adjustment layers, any number of barrier layers, any number of glue layers, and filling materials.

[0044] The lower gate electrode 80L is formed of a material suitable for the device type of the lower nanostructure FET. For example, the lower gate electrode 80L can include one or more work function adjustment layers formed of a material suitable for the device type of the lower nanostructure FET. In some embodiments, the lower gate electrode 80L includes an n-type work function adjustment layer, which can be formed of titanium aluminum, titanium aluminum carbide, tantalum aluminum, tantalum carbide, combinations thereof, etc. In some embodiments, the lower gate electrode 80L includes a p-type work function adjustment layer, which can be formed of titanium nitride, tantalum nitride, combinations thereof, etc. Additionally or alternatively, the lower gate electrode 80L can include a dipole-inducing element suitable for the device type of the lower nanostructure FET. Acceptable dipole-inducing elements include lanthanum, aluminum, scandium, ruthenium, zirconium, erbium, magnesium, strontium, and combinations thereof.

[0045] The lower gate electrode 80L can be formed by: conformally depositing one or more gate electrode layers; and recessing the gate electrode layers. The conformal deposition process for depositing the lower gate electrode 80L can produce a portion of the lower gate electrode 80L on the STI region 32 having the same profile as the upper surface of the STI region 32 (e.g., a concave profile as Figure 5B shown). Any acceptable etching process can be implemented, such as dry etching, wet etching, etc. or a combination thereof, to recess the gate electrode layers. The etching can be isotropic. Etching the lower gate electrode 80L can expose the upper semiconductor nanostructure 26U.

[0046] In some embodiments, an isolation layer (not explicitly shown) can be optionally formed on the lower gate electrode 80L. The isolation layer serves as an isolation component between the lower gate electrode 80L and the subsequently formed upper gate electrode 80U. The isolation layer can be formed by: conformally depositing a dielectric material (e.g., silicon oxide, silicon nitride, silicon oxynitride, carbon oxynitride, combinations thereof, etc.); and subsequently recessing the dielectric material to expose the upper semiconductor nanostructure 26U.

[0047] Then, an upper gate electrode 80U is formed on the above-described isolation layer (if present) or the lower gate electrode 80L. The upper gate electrode 80U is disposed between the upper semiconductor nanostructures 26U. In some embodiments, the upper gate electrode 80U wraps the upper semiconductor nanostructures 26U. The upper gate electrode 80U can be formed of the same candidate materials and candidate processes used to form the lower gate electrode 80L. The upper gate electrode 80U is formed of a material suitable for the device type of the upper nanostructure FET. For example, the upper gate electrode 80U can include one or more work function adjustment layers (e.g., an n-type work function adjustment layer and / or a p-type work function adjustment layer) formed of a material suitable for the device type of the upper nanostructure FET. Although a single-layer upper gate electrode 80U is shown, the upper gate electrode 80U can include any number of work function adjustment layers, any number of barrier layers, any number of glue layers, and filling materials. In some embodiments, the upper gate electrode 80U can be formed of a material different from that of the lower gate electrode 80L. In some embodiments, the interface between the upper gate electrode 80U and the lower gate electrode 80L is visible.

[0048] Furthermore, a removal process is implemented to make the top surface of the upper gate electrode 80U flush with the top surface of the second ILD 72. The removal process used to form the gate dielectric 78 can be the same removal process as that used to form the upper gate electrode 80U. In some embodiments, a planarization process such as chemical mechanical polishing (CMP), an etch-back process, a combination thereof, etc. can be utilized. After the planarization process, the top surfaces of the upper gate electrode 80U, the gate dielectric 78, the second ILD 72, and the gate spacer 44 are substantially coplanar (within the process variation range). Each corresponding pair of the gate dielectric 78 and the gate electrode 80 (including the upper gate electrode 80U and / or the lower gate electrode 80L) can be collectively referred to as a "gate structure" 90 (including the upper gate structure 90U and the lower gate structure 90L). Each gate structure 90 extends along three sides (e.g., the top surface, the sidewalls, and the bottom surface) of the channel region of the semiconductor nanostructure 26 (see Figure 1 ). The lower gate structure 90L can also extend along the sidewalls and / or the top surface of the semiconductor fin 20'.

[0049] Figure 6A , Figure 6B , Figure 6C , Figure 7A , Figure 7B , Figure 8A , Figure 8B , Figure 9A , Figure 9B , Figure 9C , Figure 10A , Figure 10B , Figure 10C , Figure 11A , Figure 11B , Figure 12A ,Figure 12B , Figure 13A , Figure 13B , Figure 14A , Figure 14B , Figure 14C , Figure 15A and Figure 15B illustrate a process of cutting a metal gate electrode and subsequent processes for forming contacts and front - side and back - side interconnect structures. Unless otherwise specified, the drawings with reference numerals having the letter "A" are cross - sectional views along the reference line A - A' of Figure 1 . The drawings with reference numerals having the letter "B" are cross - sectional views along the reference line B - B' of Figure 1 . Figure 6C is a plan view, Figure 9C is a perspective view, and Figure 10C and Figure 14C are cross - sectional views along the reference line C - C' of Figure 1 .

[0050] Figure 6A , Figure 6B and Figure 6C illustrate cutting the gate electrodes 80 (80U and 80L) according to some embodiments. After cutting the gate electrodes 80, the gate electrodes 80 will be separated into individual and electrically isolated gate structures 90. Although a single gate cut is shown, it should be understood that the gate structures 90 can be separated into multiple parts of the gate structures 90 by additional simultaneous cutting processes.

[0051] In Figure 6A and Figure 6B , a hard mask 102, a cushion layer 104, and a hard mask 106 are formed over the gate electrodes 80 and the ILD 72. The material of the hard mask 102 can be the same as or different from some of the materials in the CESL 66. In some embodiments, the hard mask layer 102 can be formed of a dielectric material having a high etch selectivity with respect to the etching of the second ILD 72, such as silicon nitride, silicon oxide, silicon oxynitride, etc., which can be formed by any suitable deposition process, such as CVD, ALD, etc. In some embodiments, the cushion layer 104 is formed of a metal - containing material, such as TiN, TaN, etc. The cushion layer 104 can also be formed of a dielectric material such as silicon oxide. The material of the hard mask 106 can be the same as or different from some of the materials in the CESL 66. In some embodiments, the hard mask layer 106 can be formed of a dielectric material having a high etch selectivity with respect to the etching of the first ILD 72, such as silicon nitride, silicon oxide, silicon oxynitride, etc., which can be formed by any suitable deposition process, such as CVD, ALD, etc.

[0052] After forming the hard masks 102 / 106 and the cushion layer 104, a photoresist layer (not shown) can be formed and patterned. In some embodiments, a bottom anti-reflective coating (BARC, not shown) can also be formed between the hard mask layer 106 and the patterned photoresist. In some embodiments, the patterned photoresist is used as an etching mask to etch the hard mask layer 106. The opening extends into the hard mask layer 106 and exposes the top surface of the cushion layer 104. Then the patterned photoresist can be removed.

[0053] In addition, in Figure 6A and Figure 6B the cushion layer 104, the underlying hard mask 102, the gate electrode 80, the ILDs 68 and 72, the CESLs 70 and 66, and the isolation region 32 are etched to form a trench 110 that extends through the gate electrode 80 to expose the substrate 20. In some embodiments, the etching can be stopped to only partially etch into the isolation region 32. In some embodiments, the etching can still continue until a portion of the substrate 20 is removed. The etching can include multiple cycles using various etchants that are effective for removing different materials in the gate structure 90. In some embodiments, the bottom of the trench 110 can be disposed in the isolation region 32 and can not penetrate the substrate 20. In some embodiments, the etching is performed using process gases selected from but not limited to Cl2, BCl3, Ar, CH4, CF4, and combinations thereof.

[0054] In Figure 6B 's cross-sectional view, the trench 110 is formed to have a depth D1 from the bottom to the top and a width W1 at the bottom of the trench 110. In some embodiments, the aspect ratio (D1 / W1) of the trench 110 in this cross-section is in the range from 10 to 30.

[0055] Figure 6C A plan view shows the trench 110 (with regions or portions 1110A and 110B) extending through the gate structure 90 between adjacent nanostructures 26. Figure 6C The reference line A - A' of Figure 6A shows the Figure 6C 's cross-sectional view, and Figure 6B 's reference line B - B' shows the

[0056] In the illustrated embodiment, the trench 110 extends through three gate structures 90, and in other embodiments, the trench 110 can extend through more or fewer gate structures 90. The region 110B of the trench 110 will be used for the subsequently formed vertical interconnect structures 124 / 128 / 130, and the region 110A of the trench 110 does not contain the vertical interconnect structure. As Figure 6C shown, the region 110B is wider than the region 110A.

[0057] In Figure 7A and Figure 7B , a dielectric layer 120 (which may also be referred to as the bottom dielectric layer 120) is formed in the bottom of the trench 110. The bottom dielectric layer 120 partially fills the trench 110 and reduces the aspect ratio of the trench 110. After the bottom dielectric layer 120 is formed, the remaining trench 110 has a depth D2 from the top surface of the bottom dielectric layer 120 to the top, and has a width W2 at the top surface of the bottom dielectric layer 120. In some embodiments, after the bottom dielectric layer 120 is formed in the cross-section of Figure 7B , the aspect ratio (D2 / W2) of the trench 110 is in the range from 5 to 8.

[0058] The bottom dielectric layer 120 may be formed of a dielectric material, such as silicon nitride, silicon oxide, silicon oxynitride, etc., which may be formed by any suitable deposition process, such as CVD, ALD, etc. In some embodiments, the dielectric constant (k value) of the bottom dielectric layer 120 is in the range from 4 to 7. The bottom dielectric layer 120 may be a single layer or may include multiple layers, including layers of different material compositions. For example, the bottom dielectric layer 120 may include a silicon nitride layer and a silicon oxide layer above the silicon nitride layer. In some embodiments, the bottom dielectric layer 120 is formed to have a thickness in the range from 50 nm to 100 nm. The bottom dielectric layer 120 may be selectively grown or formed in the trench 110 to have a desired thickness, or may fill the trench 110 and be etched back to the bottom dielectric layer 120 to a desired thickness.

[0059] In Figure 8A and Figure 8B , a liner 122 and a vertical interconnect 124 are formed in the remaining trench 110 on the bottom dielectric layer 120. In some embodiments, the liner 122 is a dielectric material and may include silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxynitride, etc., which may be formed by a deposition process such as CVD, ALD, etc. The liner 122 may include multiple layers, such as a diffusion barrier layer, an adhesion layer, etc. The diffusion barrier layer or the adhesion layer may include titanium, titanium nitride, tantalum, tantalum nitride, etc. After the liner 122 is formed, a conductive material is formed in the opening to fill and overfill the remaining trench 110. The conductive material may be formed by a deposition process such as ALD, CVD, PVD, etc. In some embodiments, the conductive material is cobalt, tungsten, palladium, nickel, aluminum, molybdenum, copper, silver, gold, etc. or a combination thereof. A planarization process, such as CMP, may be implemented to remove the excess material from the top surfaces of the ILD 72 and the gate electrode 80. The remaining conductive material forms the vertical interconnect 124 in the trench. The metal resistivity of the vertical interconnect 124 is less than 48 micro-ohm centimeters (μΩ·cm).

[0060] By having a bottom dielectric layer 120, the aspect ratio of the trench 110 is reduced, enabling the formation of the conductive material of the vertical interconnect 124 while avoiding seams or voids in the conductive material. In addition, because the vertical interconnect 124 extends through the stacked transistors in the cut metal gate region of the transistor, no additional wiring spacers are required for the vertical interconnect, thereby reducing the overall size of the structure.

[0061] Figure 9A , Figure 9B and Figure 9C Cutting of the vertical interconnect 124 to form a trench in the vertical interconnect 124 and filling the trench with a dielectric material is shown in accordance with some embodiments. The trench in the vertical interconnect 124 (not shown unfilled) can be formed in a manner similar to the trench 110 described above, and will not be repeated here. For example, the trench can be formed using photolithography and etching steps to form a trench extending into the vertical interconnect 124. Cutting of the vertical interconnect 124 reduces the capacitance of the vertical interconnect 124, which can enable higher operating speeds for the device.

[0062] After forming the trenches, the trenches are filled with a dielectric material, such as a dielectric liner 128 and a dielectric filler 130 on the dielectric liner 128. In some embodiments, the dielectric liner 128 may include silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxynitride, etc., which may be formed by a deposition process such as CVD, ALD, etc. After forming the dielectric liner 128, a dielectric filler 130 is formed in the opening to fill and possibly overfill the remaining trenches. In some embodiments, the dielectric filler 130 may include silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxynitride, etc., which may be formed by a deposition process such as CVD, ALD, etc. In a specific embodiment, the dielectric liner 128 is silicon nitride and the dielectric filler is silicon oxide. A planarization process, such as CMP, may be performed to remove excess dielectric material from the top surfaces of the vertical interconnects 124, the ILD 72, and the gate electrode 80. The remaining dielectric liner 128 and dielectric filler 130 form a cut interconnect region 128 / 130 in the trench.

[0063] By replacing some of the conductive material of vertical interconnect 124 with the dielectric material of the cut dielectric region, the capacitance of vertical interconnect 124 is reduced, which may enable higher operating speeds for the device.

[0064] Figure 10A , Figure 10B and Figure 10CIt shows that a metal-semiconductor alloy region 138 and source / drain contact 140 are formed in the second ILD 72 to be electrically coupled to the upper epitaxial source / drain region 62U and / or the vertical interconnect 124. As an example of forming the source / drain contact 140, openings are formed through the second ILD 72 and the second CESL 70 using acceptable lithography and etching techniques. A liner (not shown separately) (such as a diffusion barrier layer, an adhesion layer, etc.) and a conductive material are formed in the openings. The liner may include titanium, titanium nitride, tantalum, tantalum nitride, etc. The conductive material may be cobalt, tungsten, copper, copper alloy, silver, gold, aluminum, nickel, etc. A removal process may be implemented to remove excess material from the gate spacer 44 and the top surface of the second ILD 72. The remaining liner and conductive material form the source / drain contact 140 in the openings.

[0065] As shown along Figure 1 reference line C-C’ of Figure 10C what is shown, the source / drain contact 140 may be a butt contact, and the vertical interconnect 124 and the upper epitaxial source / drain region 62U are connected by a single source / drain contact 140. In some embodiments, the source / drain contact 140 extends through the CESL 70 into the ILD 68. Additionally, in some embodiments, the source / drain contact 140 extends along the sidewalls and the top surface of the upper epitaxial source / drain region 62U. The vertical interconnect 124 may couple the upper epitaxial source / drain region 62U with the lower epitaxial source / drain region 62L and subsequent backside contacts and interconnect structures together.

[0066] Optionally, a metal-semiconductor alloy region 138 is formed at the interface between the source / drain region 62 and the source / drain contact 140. The metal-semiconductor alloy region 138 can be a silicide region formed of a metal silicide (e.g., titanium silicide, cobalt silicide, nickel silicide, etc.), a germanide region formed of a metal germanide (e.g., titanium germanide, cobalt germanide, nickel germanide, etc.), a siligermanide region formed of a metal silicide and a metal germanide, etc. The metal-semiconductor alloy region 138 can be formed by depositing a metal in the opening for the source / drain contact 140 and then performing a thermal annealing process prior to the material of the source / drain contact 140. The metal can be any metal capable of reacting with the semiconductor material (e.g., silicon, silicon germanium, germanium, etc.) of the source / drain region 62 to form a low-resistance metal-semiconductor alloy, such as nickel, cobalt, titanium, tantalum, platinum, tungsten, other noble metals, other refractory metals, rare earth metals, or alloys thereof. The metal can be deposited by a deposition process such as ALD, CVD, PVD, etc. After the thermal annealing process, a cleaning process, such as wet cleaning, can be performed to remove any residual metal from the opening for the source / drain contact 140 (such as from the surface of the metal-semiconductor alloy region 138). Then, the material of the source / drain contact 140 can be formed on the metal-semiconductor alloy region 138.

[0067] The ESL 134 and the third ILD 136 are formed. In some embodiments, the ESL 134 can include a dielectric material having a high etch selectivity with respect to the etch of the third ILD 136, such as aluminum oxide, aluminum nitride, silicon oxycarbide, etc. The third ILD 136 can be formed using flowable CVD, ALD, etc., and the material can include PSG, BSG, BPSG, USG, etc., which can be deposited by any suitable method, such as CVD, PECVD, etc.

[0068] In some embodiments, a planarization process such as CMP, etch-back process, a combination thereof, etc. is utilized. After the planarization process, the top surfaces of the third ILD 136, the ESL 134, and the source / drain contact 140 are substantially coplanar (within the process variation range).

[0069] A gate contact (not shown separately) can be formed to contact the upper gate electrode 80U. As an example of forming the gate contact, an opening for the gate contact is formed through the third ILD 106 and the ESL 104. The opening can be formed using acceptable lithography and etching techniques. A liner (not shown separately) (such as a diffusion barrier layer, an adhesion layer, etc.) and a conductive material are formed in the opening. The liner can include titanium, titanium nitride, tantalum, tantalum nitride, etc. The conductive material can be cobalt, tungsten, copper, copper alloy, silver, gold, aluminum, nickel, etc. A planarization process, such as CMP, can be implemented to remove excess material from the top surface of the third ILD 106. The remaining liner and conductive material form the gate contact in the opening. The gate contact can be formed in different processes or can be formed in the same process.

[0070] Figure 11A and Figure 11B The formation of the front-side interconnect structure 154 is shown. The front-side interconnect structure 154 includes a dielectric layer 156 and a layer of conductive components 158 in the dielectric layer 156. The dielectric layer 156 can include a low-k dielectric layer formed of a low-k dielectric material. The dielectric layer 156 can also include a passivation layer formed of a non-low-k and dense dielectric material, such as undoped silicate glass (USG), silicon oxide, silicon nitride, etc. or a combination thereof above the low-k dielectric material. The dielectric layer 156 can also include a polymer layer.

[0071] The conductive components 158 can include wires and vias, which can be formed using a damascene process. The conductive components 158 can include metal wires and metal vias, which include a diffusion barrier layer and a copper-containing material above the diffusion barrier layer. The conductive components 158 can be electrically coupled to the contacts 140 and other underlying conductive components to provide wiring and interconnection. There can also be aluminum pads located above the metal wires and vias and electrically connected to the metal wires and vias. As will be discussed below, contacts to the lower gate structure 90L and the lower source / drain regions 62L can be made through the back side of the device (e.g., the side opposite the front-side interconnect structure 154).

[0072] Figures 12A to 15B A cross-sectional view showing an intermediate step of forming a back-side vertical interconnect contact according to some embodiments is shown. Referring Figure 12A and Figure 12B , the orientation of the device can be flipped. For example, a carrier substrate (not explicitly shown) can be bonded to the front-side interconnect structure 154 by dielectric-to-dielectric bonding, and the device can be flipped to expose the back side of the device (e.g., the side of the substrate 20 opposite the front-side interconnect structure 154).

[0073] In Figure 13A and Figure 13BIn the embodiment of the present invention, a substrate removal process may then be performed on the back side of the device (e.g., on substrate 20). In some embodiments, the process may include, for example, a combination of CMP and / or etch-back processes. The planarization process and / or etching process may remove substrate 20, exposing semiconductor strips 20', and may also simultaneously expose STI regions 32 and / or bottom dielectric layer 120. Removing lower portions of semiconductor substrate 20 and semiconductor strips 20' advantageously improves electrical performance by improving isolation between subsequently formed backside gate contacts and / or backside source / drain contacts. For example, by removing semiconductor substrate 20, issues regarding backside contact shorts through semiconductor substrate 20 / semiconductor strips 20' may be addressed.

[0074] After the lower portions of the semiconductor strips 20' are removed, a backside dielectric layer 160, such as a backside oxide layer 160, is formed over the backside of the device filling the openings in the STI regions 32 where the semiconductor strips 20' were removed. In some embodiments, the backside dielectric layer 160 is made of silicon oxide or the like. The backside dielectric layer 160, together with the bottom dielectric layer 120, enables a subsequent planarization process to remove these layers to expose the vertical interconnects 124 at the backside of the device without causing protrusions or bumps at the vertical interconnects 124.

[0075] Figure 14A , Figure 14B and Figure 14C The planarization of the back side of the device is shown to expose the vertical interconnects 124. In some embodiments, the planarization process includes multiple CMP steps or processes, wherein the first CMP process is performed at Figure 13A and Figure 13B The second CMP process stops at the reference line P1 in Figure 13A and Figure 13B The first CMP process may stop at the semiconductor strip 20 ′, and the second CMP process may stop at the vertical interconnect 124 .

[0076] In some embodiments, one or both of the CMP processes include a high dielectric flux (SiO x or Si x N y ) and a Cerium Oxide or Silicon Oxide based CMP slurry with high oxide / silicon removal rate selectivity. This high selectivity allows for precise CMP stops on semiconductor strips 20'. After the planarization process, the backside surfaces of vertical interconnects 124, pads 122, STI regions 32, and semiconductor strips 20' are substantially coplanar (within process variation).

[0077] After the planarization process is completed, the remaining semiconductor strip 20’ has a height H1. In some embodiments, the height H1 ranges from 20 nm to 60 nm. Additionally, after the planarization process is completed, the vertical interconnect 124 has a top width W3 and a bottom width W4 along the Figure 1 reference line C-C’ in Figure 14C . In some embodiments, the top width W3 is greater than the bottom width W4. In some embodiments, the top width W3 ranges from 30 nm to 50 nm. In some embodiments, the bottom width W4 ranges from 20 nm to 30 nm.

[0078] In Figure 15A and Figure 15B , a backside interconnect structure 170 is formed. In some embodiments, a backside ESL 172 is deposited over the backside of the device (such as over the vertical interconnect 124, STI region 32, and semiconductor strip 20’). The backside ESL 172 can be formed using a material and process similar to the frontside ESL 134 described above, and a detailed description of the backside ESL 172 is not repeated here. The backside ESL 172 can provide etch control during the formation of the backside vertical interconnect contacts. For example, the backside ESL 172 can provide endpoint control for patterning the backside vertical interconnect contact openings that expose the vertical interconnect 124.

[0079] The backside interconnect structure 170 includes a dielectric layer 174 and a layer of conductive components 176 in the dielectric layer 174. The dielectric layer 174 can include a low-k dielectric layer formed of a low-k dielectric material. The dielectric layer 174 can also include a passivation layer formed of a non-low-k and dense dielectric material, such as USG, silicon oxide, silicon nitride, etc. or a combination thereof over the low-k dielectric material. The dielectric layer 174 can also include a polymer layer.

[0080] The conductive components 176 can include wires and vias, which can be formed using a damascene process. The conductive components 176 can include metal wires and metal vias, which include a diffusion barrier layer and a copper-containing material over the diffusion barrier layer. The conductive components 176 can be electrically coupled to the vertical interconnect 124 and other underlying conductive components such as gate contacts and source / drain contacts (not shown separately) to provide routing and interconnection. There can also be aluminum pads located over the metal wires and vias and electrically connected to the metal wires and vias.

[0081] Figure 16A and Figure 16B show a cross-sectional view of an intermediate stage in the formation of a stacked transistor (as schematically shown in Figure 1 ). In Figure 16A and Figure 16B , the same reference numerals represent those described above inFigures 2 to 15B the same components formed by the same processes described in, unless otherwise specified. In Figure 16A and Figure 16B the vertical interconnect 124 includes two portions 124A and 124B, each of which is composed of a different conductive material, rather than a single conductive material throughout the vertical interconnect 124. Figure 16A shows a cross-sectional view along a cross-section similar to the reference cross-section A-A' in Figure 1 . Figure 16B shows a cross-sectional view along a cross-section similar to the reference cross-section B-B' in Figure 1 .

[0082] Figure 16A and Figure 16B show a device in an intermediate processing stage similar to the intermediate structure in Figure 9A , Figure 9B and Figure 9C , where the same reference numerals denote the same components formed by the same processes.

[0083] In Figure 16A and Figure 16B the vertical interconnect 124 is formed of a plurality of conductive materials 124A and 124B. In some embodiments, the conductive material composition of the lower portion 124A is different from that of the upper portion 124B. In some embodiments, the lower portion 124A and the upper portion 124B are formed by different deposition processes. In some embodiments, the conductive materials of the portions 124A and 124B may each include cobalt, tungsten, palladium, nickel, aluminum, molybdenum, copper, silver, gold, etc. or combinations thereof. In some embodiments, the interface between the lower portion 124A and the upper portion 124B is visible.

[0084] Figure 17A and Figure 17B show a cross-sectional view of an intermediate stage in the formation of a stacked transistor (as schematically shown in Figure 1 ). In Figure 17A and Figure 17B the same reference numerals denote the same components formed by the same processes as described above in Figures 2 to 15B , unless otherwise specified. In Figure 17A and Figure 17B portions of the liner 122 and the bottom dielectric layer 120 are retained on the back side of the device, through which conductive vias are formed to make electrical connections to the vertical interconnect 124 from the back side. Figure 17A shows a cross-sectional view along a cross-section similar to the reference cross-section A-A' in Figure 1 . Figure 17B shows a cross-sectional view along a cross-section similar to the reference cross-section B-B' in Figure 1Cross-sectional views of reference cross-section B-B' and similar cross-sections.

[0085] Figure 17A and Figure 17B show devices in an intermediate processing stage of an intermediate structure similar to Figure 15A and Figure 15B where like reference numerals represent like elements formed by the same process.

[0086] In the embodiments of Figure 17A and Figure 17B during removal of the backside dielectric layer 160 (see, e.g., Figures 13A to 14B ), the removal stops at the semiconductor strip 20' (see, e.g., Figure 13A and Figure 13B reference line P1 in). In this embodiment, the remaining portions of the bottom dielectric layer 120 and the liner 122 are not removed, and a backside conductive via 184 is formed through the bottom dielectric layer 120 and the liner 122 to provide a backside electrical connection to the vertical interconnect 124. The backside conductive via 184 can be formed of a material and process similar to the conductive components in the interconnects 154 and 170 and will not be described again here.

[0087] After forming the conductive via 184, processing similar to that described in Figure 15A and Figure 15B can be implemented to achieve the structures in Figure 17A and Figure 17B .

[0088] In an embodiment, a semiconductor device can include a plurality of first nanostructures. The plurality of first nanostructures extend between first source / drain regions. The semiconductor device can also include a plurality of second nanostructures located above the plurality of first nanostructures. The plurality of second nanostructures extend between second source / drain regions. The device can further include a first gate stack around the plurality of first nanostructures. The device can additionally include a second gate stack located above the first gate stack and disposed around the plurality of second nanostructures. The device can also include a vertical interconnect structure extending through the first gate stack and the second gate stack. The device can also include a front-side contact electrically coupled to the front side of the vertical interconnect structure and a back-side contact electrically coupled to the back side of the vertical interconnect structure.

[0089] The described embodiments may also include one or more of the following features. A semiconductor device, wherein a vertical interconnect structure extends through more than two gate stacks. A semiconductor device, wherein the vertical interconnect structure electrically couples one of a first source / drain region to one of a second source / drain region. The semiconductor device may include a dielectric liner on a sidewall of the vertical interconnect structure. The vertical interconnect structure has a conductive material. The semiconductor device may include a backside dielectric layer on a backside of the vertical interconnect structure. A backside contact extends through the backside dielectric layer. A semiconductor device, wherein an outer sidewall of the backside dielectric layer is co-terminus with an outer sidewall of the dielectric liner. A semiconductor device, wherein the vertical interconnect structure may include a first region extending from a front side of the vertical interconnect structure into the vertical interconnect structure. The first region has a dielectric material. A semiconductor device, wherein the front side contact is a butt contact that electrically couples the vertical interconnect structure to one of the second source / drain regions. A semiconductor device, wherein the vertical interconnect structure may include a lower portion and an upper portion. The lower portion has a different material composition than the upper portion. Each of the lower portion and the upper portion is conductive. The semiconductor device may include a front side interconnect structure electrically coupled to the front side contact and a backside interconnect structure electrically coupled to the backside contact.

[0090] In an embodiment, a method may include forming a first transistor and a second transistor over a semiconductor substrate. The first transistor and the second transistor are vertically stacked. The method may also include removing a first gate stack of the first transistor and a second gate stack of the second transistor. Removing forms a first trench. The method may further include: forming a first dielectric layer in the first trench; depositing a conductive material over the first dielectric layer; etching a second trench in the conductive material; forming a second dielectric layer in the second trench. The conductive material is located between the first dielectric layer and the second dielectric layer, and a front side conductive contact is formed on a front side of the conductive material. The front side conductive contact is electrically coupled to the conductive material and a source / drain of the second transistor.

[0091] The described embodiments may also include one or more of the following features. The method may include forming a backside conductive contact on a backside of the conductive material. The method may include: removing the semiconductor substrate to expose the backside of the conductive material; and forming a backside conductive contact on the backside of the conductive material. The method may include: removing the semiconductor substrate and exposing the backside of the shallow trench isolation (STI) region; forming an oxide layer on the backside of the STI region; performing a first planarization step to remove at least a portion of the oxide layer and the first dielectric layer in the first trench; performing a second planarization step to remove the remaining portion of the first dielectric layer in the first trench and expose the backside of the conductive material in the first trench; and forming a backside conductive contact on the exposed backside of the conductive material. The method may include: removing the semiconductor substrate and exposing the backside of the shallow trench isolation (STI) region; forming an oxide layer on the backside of the STI region; performing a first planarization step to remove at least a portion of the oxide layer and the first dielectric layer in the first trench; and forming a backside conductive contact through the remaining portion of the first dielectric layer in the first trench. The backside conductive contact is electrically coupled to the backside of the conductive material. The method may include: after forming the first dielectric layer in the first trench, depositing a dielectric liner on sidewalls and a bottom surface of the first trench above the first dielectric layer. The conductive material is located on the dielectric liner. The method, wherein an outer sidewall of the first dielectric layer is co-terminal with an outer sidewall of the dielectric liner.

[0092] In an embodiment, the method may include forming a multi-layer stack above the semiconductor substrate. The multi-layer stack has alternating semiconductor nanostructures and pseudo-nanostructures. The method may also include forming lower source / drain regions, wherein lower semiconductor nanostructures of the semiconductor nanostructures extend between the lower source / drain regions. The method may further include forming upper source / drain regions above the lower source / drain regions, wherein upper semiconductor nanostructures of the semiconductor nanostructures extend between the upper source / drain regions. The method may additionally include replacing the pseudo-nanostructures with a lower gate stack around the lower semiconductor nanostructures and an upper gate stack around the upper semiconductor nanostructures. The method may further include: etching a first trench through the upper gate stack and the lower gate stack; forming a bottom dielectric layer in a bottom of the first trench; forming a conductive interconnect on the bottom dielectric layer in the first trench; forming a second trench in the conductive interconnect; forming a dielectric material in the second trench; forming a frontside conductive contact on a front side of the conductive interconnect; and forming a backside conductive contact on a back side of the conductive interconnect. The frontside conductive contact and the backside conductive contact are electrically coupled to the conductive interconnect.

[0093] The described embodiments may also include one or more of the following features. A method, wherein the front-side conductive contact is electrically coupled to one of the conductive interconnect and the upper source / drain region. The method may include removing a semiconductor substrate to expose a back side of the conductive interconnect.

[0094] Each embodiment provides a stacked transistor of two vertically stacked transistors and a vertical interconnect structure extending through the stacked transistors. The vertical interconnect structure allows back-side interconnect wiring and can reduce the need and size of front-side interconnects. The vertical interconnect structure extends through the stacked transistors in a cut metal gate region of the transistors. Additionally, the vertical interconnect structure may include a cut region to reduce some of the conductive material of the vertical interconnect replaced with a dielectric material to reduce capacitance and enable a higher operating speed for the device. In some embodiments, the vertical interconnect structure may couple drain regions of the stacked transistors.

[0095] The vertical interconnect structure includes a metal interconnect structure and a bottom dielectric structure that reduces the aspect ratio of the metal interconnect structure and avoids seams or voids in the metal interconnect structure. Additionally, the disclosed embodiments include a back-side planarization process to expose the metal interconnect of the vertical interconnect structure without causing the metal interconnect to protrude from the back side. Thus, the disclosed embodiments provide a vertical interconnect structure without metal protruding from the back side. Accordingly, the disclosed embodiments allow for improved process integration, increased wiring flexibility, and increased device performance.

[0096] Some embodiments of the present application provide a semiconductor device, comprising: a plurality of first nanostructures extending between a first source / drain region; a plurality of second nanostructures located above the plurality of first nanostructures and extending between a second source / drain region; a first gate stack located around the plurality of first nanostructures; a second gate stack located above the first gate stack and disposed around the plurality of second nanostructures; a vertical interconnect structure extending through the first gate stack and the second gate stack; a front-side contact electrically coupled to a front side of the vertical interconnect structure; and a back-side contact electrically coupled to a back side of the vertical interconnect structure.

[0097] In some embodiments, the vertical interconnect structure extends through more than two gate stacks. In some embodiments, the vertical interconnect structure electrically couples one of the first source / drain regions to one of the second source / drain regions. In some embodiments, the semiconductor device further comprises: a dielectric liner located on the sidewalls of the vertical interconnect structure, the vertical interconnect structure comprising a conductive material. In some embodiments, the semiconductor device further comprises a backside dielectric layer located on the backside of the vertical interconnect structure, the backside contact extending through the backside dielectric layer. In some embodiments, the outer sidewalls of the backside dielectric layer are co-terminus with the outer sidewalls of the dielectric liner. In some embodiments, the vertical interconnect structure includes a first region extending from the front side of the vertical interconnect structure into the vertical interconnect structure, the first region comprising a dielectric material. In some embodiments, the front side contact is a butt contact that electrically couples the vertical interconnect structure to one of the second source / drain regions. In some embodiments, the vertical interconnect structure includes a lower portion and an upper portion, the lower portion having a different material composition than the upper portion, and each of the lower portion and the upper portion being conductive. In some embodiments, the semiconductor device further comprises: a front side interconnect structure electrically coupled to the front side contact; and a backside interconnect structure electrically coupled to the backside contact.

[0098] Some other embodiments of the present application provide a method of forming a semiconductor device, comprising: forming a first transistor and a second transistor vertically stacked above a semiconductor substrate; removing a first gate stack of the first transistor and a second gate stack of the second transistor, the removal forming a first trench; forming a first dielectric layer in the first trench; depositing a conductive material over the first dielectric layer; etching a second trench in the conductive material; forming a second dielectric layer in the second trench, the conductive material being located between the first dielectric layer and the second dielectric layer; and forming a front side conductive contact on the front side of the conductive material, the front side conductive contact being electrically coupled to the conductive material and the source / drain of the second transistor.

[0099] In some embodiments, the method further includes: forming a backside conductive contact on a backside of the conductive material. In some embodiments, the method further includes: removing the semiconductor substrate to expose the backside of the conductive material; and forming a backside conductive contact on the backside of the conductive material. In some embodiments, the method further includes: removing the semiconductor substrate and exposing a backside of a shallow trench isolation (STI) region; forming an oxide layer on the backside of the shallow trench isolation region; performing a first planarization step to remove at least a portion of the oxide layer and the first dielectric layer in the first trench; performing a second planarization step to remove a remaining portion of the first dielectric layer in the first trench and expose the backside of the conductive material in the first trench; and forming a backside conductive contact on the exposed backside of the conductive material. In some embodiments, the method further includes: removing the semiconductor substrate and exposing a backside of a shallow trench isolation region; forming an oxide layer on the backside of the shallow trench isolation region; performing a first planarization step to remove at least a portion of the oxide layer and the first dielectric layer in the first trench; and forming a backside conductive contact through a remaining portion of the first dielectric layer in the first trench, the backside conductive contact being electrically coupled to the backside of the conductive material. In some embodiments, the method further includes: after forming the first dielectric layer in the first trench, depositing a dielectric liner on sidewalls and a bottom surface of the first trench above the first dielectric layer, the conductive material being located on the dielectric liner. In some embodiments, an outer sidewall of the first dielectric layer is co-terminus with an outer sidewall of the dielectric liner.

[0100] Some other embodiments of the present application provide a method for forming a semiconductor device, including: forming a multi-layer stack above a semiconductor substrate, the multi-layer stack including alternating semiconductor nanostructures and pseudo-nanostructures; forming a lower source / drain region, wherein a lower semiconductor nanostructure of the semiconductor nanostructures extends between the lower source / drain regions; forming an upper source / drain region above the lower source / drain region, wherein an upper semiconductor nanostructure of the semiconductor nanostructures extends between the upper source / drain regions; replacing the pseudo-nanostructures with a lower gate stack around the lower semiconductor nanostructure and an upper gate stack around the upper semiconductor nanostructure; etching a first trench through the upper gate stack and the lower gate stack; forming a bottom dielectric layer at the bottom of the first trench; forming a conductive interconnect on the bottom dielectric layer in the first trench; forming a second trench in the conductive interconnect; forming a dielectric material in the second trench; forming a front-side conductive contact on a front side of the conductive interconnect; and forming a back-side conductive contact on a back side of the conductive interconnect, the front-side conductive contact and the back-side conductive contact being electrically coupled to the conductive interconnect.

[0101] In some embodiments, the front-side conductive contact is electrically coupled to one of the conductive interconnect and the upper source / drain region. In some embodiments, the method further includes: removing the semiconductor substrate to expose the back side of the conductive interconnect.

[0102] The features of several embodiments are outlined above, so that those skilled in the art can better understand various aspects of the embodiments of the present disclosure. Those skilled in the art should understand that they can easily use the embodiments of the present disclosure as a basis to design or modify other processes and structures for performing the same purposes and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also be aware that such equivalent structures do not depart from the spirit and scope of the embodiments of the present disclosure, and they can make various changes, substitutions, and alterations herein without departing from the spirit and scope of the embodiments of the present disclosure.

Claims

1. A semiconductor device, comprising: a plurality of first nanostructures extending between a first source / drain region; a plurality of second nanostructures located above the plurality of first nanostructures and extending between a second source / drain region; a first gate stack located around the plurality of first nanostructures; a second gate stack located above the first gate stack and disposed around the plurality of second nanostructures; a vertical interconnect structure extending through the first gate stack and the second gate stack; a front-side contact electrically coupled to a front side of the vertical interconnect structure; and a back-side contact electrically coupled to a back side of the vertical interconnect structure.

2. The semiconductor device according to claim 1, wherein, The vertical interconnect structure extends through more than two gate stacks.

3. The semiconductor device according to claim 1, wherein The vertical interconnect structure electrically couples one of the first source / drain regions to one of the second source / drain regions.

4. The semiconductor device according to claim 1, further comprising: a dielectric liner located on a sidewall of the vertical interconnect structure, the vertical interconnect structure comprising a conductive material.

5. The semiconductor device according to claim 4, further comprising a back-side dielectric layer located on the back side of the vertical interconnect structure, the back-side contact extending through the back-side dielectric layer.

6. The semiconductor device according to claim 5, wherein, An outer sidewall of the back-side dielectric layer is co-terminus with an outer sidewall of the dielectric liner.

7. The semiconductor device according to claim 1, wherein The vertical interconnect structure includes a first region extending from a front side of the vertical interconnect structure into the vertical interconnect structure, the first region including a dielectric material.

8. The semiconductor device according to claim 1, wherein, The front-side contact is a butt contact that electrically couples the vertical interconnect structure to one of the second source / drain regions.

9. A method of forming a semiconductor device, comprising: forming a first transistor and a second transistor vertically stacked above a semiconductor substrate; removing a first gate stack of the first transistor and a second gate stack of the second transistor, the removing forming a first trench; forming a first dielectric layer in the first trench; depositing a conductive material above the first dielectric layer; etching a second trench in the conductive material; forming a second dielectric layer in the second trench, the conductive material being located between the first dielectric layer and the second dielectric layer; and forming a front-side conductive contact on a front side of the conductive material, the front-side conductive contact being electrically coupled to the conductive material and a source / drain of the second transistor.

10. A method of forming a semiconductor device, comprising: forming a multi-layer stack above a semiconductor substrate, the multi-layer stack including alternating semiconductor nanostructures and pseudo-nanostructures; forming lower source / drain regions, wherein lower semiconductor nanostructures of the semiconductor nanostructures extend between the lower source / drain regions; forming upper source / drain regions above the lower source / drain regions, wherein upper semiconductor nanostructures of the semiconductor nanostructures extend between the upper source / drain regions; Replace the pseudo-nanostructure with a lower gate stack around the lower semiconductor nanostructure and an upper gate stack around the upper semiconductor nanostructure; Etch a first trench through the upper gate stack and the lower gate stack; Form a bottom dielectric layer in the bottom of the first trench; Form a conductive interconnect on the bottom dielectric layer in the first trench; Form a second trench in the conductive interconnect; Form a dielectric material in the second trench; Form a front-side conductive contact on the front side of the conductive interconnect; and Form a back-side conductive contact on the back side of the conductive interconnect, the front-side conductive contact and the back-side conductive contact being electrically coupled to the conductive interconnect.

Images