Dielectric layer removing method, gate structure forming method and semiconductor structure
By uniformly etching dielectric layers across gate regions using controlled etching and specific material compositions, the method addresses thickness disparities and chemical infiltration issues, enhancing semiconductor device reliability and performance.
Patent Information
- Application Number
- CN202510373037.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-27
- Publication Date
- 2025-07-15
AI Technical Summary
In the prior art, the thickness of the dielectric oxide layer in the large block gate region is greater than that in the small block gate region, resulting in the inability to completely remove in the gate etching process, forming a chemical erosion path, affecting device performance and reliability.
By accurately controlling the difference in dielectric layer thickness between large block gate regions and small block gate regions, dry etching, wet etching or non-plasma gas-phase reaction etching is used, combined with photoresist layer protection, ensuring the consistent dielectric layer thickness and eliminating chemical erosion paths.
The dielectric layer thickness is consistent, leakage current is reduced, carrier mobility is improved, device corrosion resistance is enhanced, device failure risk is reduced, and electrical performance and reliability are improved.
Smart Images
Figure CN120322016A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor manufacturing technology, and particularly to a method for removing a dielectric layer, a method for forming a gate structure, and a semiconductor structure. Background Art
[0002] In the existing semiconductor manufacturing technology, the gate region is usually divided into a large gate region and a small gate region. Due to the limitations of the manufacturing process, the thickness of the dielectric oxide layer in the large gate region is often greater than that in the small gate region. This thickness difference exists before the gate dry etching process, posing significant challenges to the subsequent etching process. In the gate etching process, the final over-etching step usually adopts a high selectivity method to ensure that the underlying substrate is not damaged. However, although this high-selectivity etching process can effectively protect the underlying substrate, it cannot completely remove the dielectric oxide layer outside the large gate region.
[0003] As Figure 4 shown, the figure shows two main devices: "Core device" and "Input / Output device (IO device)", which are located on the same substrate. The figure points out that the dielectric oxide layer remaining in the large gate region cannot be covered by the sidewall protection layer, forming obvious voids, which constitute "chemical attack paths". During the manufacturing process, chemicals may enter and damage the device through these paths. Due to the complexity and high-precision requirements of the semiconductor manufacturing process, any minor defect may lead to the failure of the entire device. In the prior art, the dielectric oxide layer outside the small gate region has been completely removed. However, there is an obvious residue of the dielectric oxide layer outside the large gate region. This residue phenomenon not only affects the overall performance of the device but also may cause the remaining dielectric oxide layer not covered by the sidewall protection layer to be vulnerable to chemical attack in subsequent processes, thus triggering gate defect problems.
[0004] To solve this technical problem, it is urgent to develop a new etching process or improve the existing process to effectively remove the dielectric oxide layer outside the large gate region while maintaining the protection of the underlying substrate. Summary of the Invention
[0005] To solve all or part of the above prior art problems, the present invention provides a method for removing a dielectric layer, a method for forming a gate structure, and a semiconductor structure. By implementing the method for removing the dielectric layer, the problem of uneven dielectric layer thickness between the large gate region and the small gate region is effectively solved.
[0006] To achieve the above object, the present invention provides the following technical solutions:
[0007] A method for removing a dielectric layer, comprising the following steps:
[0008] S1. Provide a substrate, the substrate includes a first region and a second region, and the first region and the second region are isolated by an isolation structure;
[0009] S2. Form a first dielectric layer on the first region and a second dielectric layer on the second region, and the thickness of the second dielectric layer is greater than that of the first dielectric layer;
[0010] S3. Etch the second dielectric layer on the non-gate region of the second region, and the etching depth is the difference in thickness between the second dielectric layer and the first dielectric layer.
[0011] The formation steps of the first dielectric layer and the second dielectric layer in step S2 include:
[0012] S2.1 Form a dielectric layer with a second thickness on the surface of the substrate;
[0013] S2.2 Coat a photoresist on the surface of the dielectric layer in the second region, and remove the dielectric layer on the surface of the first region by etching. The remaining dielectric layer in the second region is the second dielectric layer;
[0014] S2.3 Form the first dielectric layer with a first thickness on the surface of the first region, and the second thickness is greater than the first thickness.
[0015] Step S3 specifically includes:
[0016] S3.1 Form a photoresist layer on the surface of the first region and on the surface of the second dielectric layer on the gate region in the second region;
[0017] S3.2 Etch the unshielded region by the photoresist layer, and the etching depth is the difference in thickness between the second dielectric layer and the first dielectric layer;
[0018] S3.3 Remove the remaining photoresist layer.
[0019] In step S3.2, the etching process is any one of dry etching, wet etching or non-plasma gas-phase reaction etching.
[0020] In step S3.3, the photoresist layer is removed by wet stripping or a photoresist remover device.
[0021] The material of the first dielectric layer is a silicon oxide layer, which is formed by an in-situ steam oxidation process.
[0022] The material of the second dielectric layer is a silicon oxide layer, which is formed by an in-situ steam oxidation process.
[0023] The present invention also provides a method for forming a gate structure, which is further implemented on the basis of the above-mentioned method and includes the following steps:
[0024] S4. A polysilicon layer and a hard mask layer are sequentially formed on the surface of the substrate, and the polysilicon layer and the hard mask layer are patterned through an etching process;
[0025] S5. The first dielectric layer in the non-gate region and the second dielectric layer in the non-gate region are removed through an etching process, and only the part at the bottom of the gate region is retained, thereby forming a gate structure;
[0026] It further includes the step: S6. A sidewall structure is formed on the gate structure.
[0027] The present invention also provides a semiconductor structure, which is prepared by using the above-mentioned method for removing a dielectric layer or the above-mentioned method for forming a gate structure.
[0028] The present invention has at least the following beneficial effects:
[0029] 1) By keeping the thickness of the dielectric layer in the non-gate region consistent, the problem of uneven dielectric layer thickness between the large gate region and the small gate region is effectively solved. The consistent dielectric layer thickness helps to reduce the uneven electric field distribution, thereby reducing the leakage current and increasing the carrier mobility. Specifically, a uniform electric field distribution can make the current flow more smoothly in the device, reduce the generation of leakage current caused by electric field concentration, and then improve the switching speed and current transmission efficiency of the device, significantly enhancing the electrical performance of the device, enabling it to achieve the best performance under specific working conditions, and meeting the requirements of high performance for semiconductor devices.
[0030] 2) This method eliminates the chemical etching path caused by the difference in dielectric layer thickness. In the prior art, the dielectric layer remaining outside the large gate region cannot be covered by the sidewall protection layer, forming obvious voids, and these voids constitute the "chemical etching path". During the manufacturing process, chemicals may enter through these paths and damage the device. However, the present invention ensures that the thickness of the dielectric layer in the non-gate region of the second region is the same as that of the first region by precisely controlling the etching depth, thereby eliminating these voids, enhancing the anti-etching ability of the device, effectively reducing the risk of device failure, improving the reliability and stability of the device, extending the service life of the device, and reducing the production cost and maintenance cost caused by device failure. Description of the Drawings
[0031] To more clearly illustrate the technical solutions in the specific embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following described drawings are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.
[0032] Figure 1 It is a flowchart of a method for removing a dielectric layer according to an embodiment of the present invention.
[0033] Figure 2 It is a schematic diagram of a method for removing a dielectric layer according to an embodiment of the present invention.
[0034] Figure 3 It is a schematic diagram of a method for forming a gate structure according to an embodiment of the present invention. Figure 4 It is a schematic diagram of the residual dielectric oxide layer in the large gate region and the chemical etching path in the background technology.
[0035] Reference numerals: 1, the first region; 2, the second region; 3, the isolation structure; 4, the first dielectric layer; 5, the second dielectric layer; 6, the photoresist layer; 7, the polysilicon layer; 8, the hard mask layer; 9, the sidewall structure. Specific Embodiments
[0036] The following will clearly and completely describe the technical solutions in the specific embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, rather than all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope of protection of the present invention.
[0037] In the embodiments of the present invention, with reference to Figures 1 to 3 as shown, a method for removing a dielectric layer is provided. This method is particularly applicable to the dielectric layer processing of the large gate region and the small gate region in semiconductor devices. The specific steps are as follows:
[0038] S1. Provide a substrate, which is divided into multiple regions, including the first region 1 and the second region 2. These regions are isolated by the isolation structure 3 to ensure the independence of different regions. Among them, the second region 2 corresponds to the large gate region, and the first region 1 corresponds to the small gate region;
[0039] S2. Form a first dielectric layer 4 on the first region 1 and a second dielectric layer 5 on the second region 2. As Figure 2 shown in a, due to different process conditions or design requirements, the thickness of the second dielectric layer 5 is greater than the thickness of the first dielectric layer 4;
[0040] S3. Etch the second dielectric layer 5 on the non-gate region in the second region 2, and control the etching depth to be the thickness part by which the second dielectric layer 5 exceeds the first dielectric layer 4, as Figure 2 shown in c, so as to achieve the uniformization of the dielectric layer thickness in the non-gate regions of the two regions.
[0041] In this embodiment, the first region 1 is defined as a low-voltage device region, usually called the core device region (Coredevice), and this region is specifically used to form the corresponding structures of the core devices. The second region 2 is a high-voltage device region, usually called the input / output device region (IO device), and this region is used to construct the corresponding structures of the input / output devices. Through the above steps, the present invention can effectively solve the problem of uneven dielectric layer thickness between the large gate region and the small gate region, so as to ensure that the devices in each region can achieve the best performance under their specific working conditions.
[0042] Specifically, the formation steps of the first dielectric layer 4 and the second dielectric layer 5 in step S2 specifically include:
[0043] S2.1 Uniformly deposit an initial dielectric layer with a second thickness on the substrate surface.
[0044] S2.2 Coat a photoresist on the surface of the initial dielectric layer in the second region 2, and perform exposure and development processes so that the initial dielectric layer on the surface of the first region 1 is exposed. Then, remove the exposed initial dielectric layer on the surface of the first region 1 through an etching process. Due to the protection of the photoresist, the remaining initial dielectric layer in the second region 2 is the second dielectric layer 5 with the second thickness;
[0045] S2.3 Re-form a first dielectric layer 4 with a first thickness on the surface of the first region 1, and the second thickness is greater than the first thickness.
[0046] By first forming an initial dielectric layer with a uniform thickness and then selectively removing and re-forming it, the thickness difference between the dielectric layers in the first region 1 and the second region 2 can be precisely controlled to meet the specific requirements of different regions for the dielectric layer thickness.
[0047] Step S3 specifically includes the following steps:
[0048] S3.1 Form a photoresist layer 6 on the surface of the first region 1 and on the surface of the second dielectric layer 5 on the gate region in the second region 2, as Figure 2 shown in b;
[0049] S3.2 Etch the non-gate region in the second region 2 that is not shielded by the photoresist layer 6, and control the etching depth to be the thickness difference between the second dielectric layer 5 and the first dielectric layer 4, as Figure 2As shown in c. The etching process can be dry etching, wet etching or non-plasma gas-phase reaction etching. In this embodiment, dry etching is specifically used for etching.
[0050] S3.3 Remove the remaining photoresist layer 6, as Figure 2 shown in d. The removal of the photoresist layer 6 can be achieved by wet stripping, using a photoresist removal device, or other suitable removal techniques. In this embodiment, wet stripping is specifically used for removal.
[0051] By forming the photoresist layer 6 in a specific area and performing selective etching, the etching position can be precisely controlled to ensure that the thickness of the dielectric layer in the non-gate region of the second region 2 is the same as that in the first region 1. When the dielectric layer in the non-gate region is removed subsequently, the thickness of the dielectric layer to be removed on the two regions is the same, effectively solving the problem of residual dielectric layer outside the large gate region in the prior art. This method eliminates the possible chemical erosion problem in the subsequent process caused by the difference in dielectric layer thickness, enhances the erosion resistance and reliability of the device, and effectively reduces the risk of device failure.
[0052] In this embodiment, the material of the first dielectric layer 4 is a silicon oxide layer, which is formed by an in-situ steam oxidation process. This process promotes the growth of the oxide layer by reacting steam with the silicon substrate under specific temperature and humidity conditions, thus ensuring the uniformity and compactness of the dielectric layer. The second dielectric layer 5 is also a silicon oxide layer, and the in-situ steam oxidation process is selected for its formation. The thermal oxidation process forms a high-quality dielectric layer by reacting oxygen with the silicon substrate in a high-temperature environment, while the in-situ steam oxidation process provides milder conditions, which helps to control the thickness and characteristics of the dielectric layer. The selection and use of these two processes can effectively improve the electrical performance and stability of the dielectric layer, meeting the requirements of high-performance devices.
[0053] The present invention also provides a method for forming a gate structure, which is further implemented based on the above method for removing the dielectric layer, and includes the following steps:
[0054] S4. Form a polysilicon layer 7 and a hard mask layer 8 on the substrate surface in sequence, as Figure 3 shown in a. The hard mask layer 8 can generally use silicon nitride or silicon oxide material, and can be a single-layer structure or a combination of multiple-layer structures. The polysilicon layer 7 and the hard mask layer 8 are patterned by an etching process.
[0055] S5. Remove the first dielectric layer 4 in the non-gate region and the second dielectric layer 5 in the non-gate region through an etching process, and only retain the part at the bottom of the gate region, as Figure 3 shown in b, thereby completing the formation of the gate structure.
[0056] S6. Form a sidewall structure 9 on the gate structure, as Figure 3As shown in c, the formation of the semiconductor structure is completed. The spacer structure 9 is generally composed of silicon nitride or other insulating materials, which is used to protect the gate structure from damage in subsequent process steps and provide a certain degree of spatial isolation.
[0057] Through the above steps, the formed gate structure has better electrical properties and mechanical stability, which helps to improve the overall performance of the device, reduce leakage current, increase carrier mobility, and reduce the risk of device failure.
[0058] The present invention also provides a semiconductor structure prepared by using the method for removing the dielectric layer or the method for forming the gate structure described above.
[0059] In summary, the semiconductor manufacturing method of the present invention significantly improves the performance, process stability, and economic benefits of the device by achieving the uniformity of the dielectric layer thickness in the non-gate region and the improved method for forming the gate structure. These improvements are of great significance for modern semiconductor manufacturing, and help to promote the progress of technology and the development of the industry.
[0060] It should be noted that for those of ordinary skill in the art, without departing from the principle of the present invention, several improvements and modifications can be made to the present invention, and these improvements and modifications also fall within the scope of protection of the claims of the present invention.
Claims
1. A method for removing a dielectric layer, characterized in that, Including the following steps: S1. Provide a substrate, the substrate including a first region (1) and a second region (2), the first region (1) and the second region (2) being isolated by an isolation structure (3); S2. Form a first dielectric layer (4) on the first region (1), and form a second dielectric layer (5) on the second region (2), the thickness of the second dielectric layer (5) being greater than the thickness of the first dielectric layer (4); S3. Etch the second dielectric layer (5) on the non-gate region of the second region (2), the etching depth being the difference in thickness between the second dielectric layer (5) and the first dielectric layer (4).
2. The method according to claim 1, wherein The formation steps of the first dielectric layer (4) and the second dielectric layer (5) in step S2 include: S2.1 Form a dielectric layer with a second thickness on the surface of the substrate; S2.2 Coat a photoresist on the surface of the dielectric layer in the second region (2), and remove the dielectric layer on the surface of the first region (1) by etching, and the remaining dielectric layer in the second region (2) is the second dielectric layer (5); S2.3 Form the first dielectric layer (4) with a first thickness on the surface of the first region (1), the second thickness being greater than the first thickness.
3. The method according to claim 1, wherein Step S3 specifically includes: S3.1 Form a photoresist layer (6) on the surface of the first region (1) and on the surface of the second dielectric layer (5) in the gate region of the second region (2); S3.2 Etch the region not shielded by the photoresist layer (6), the etching depth being the difference in thickness between the second dielectric layer (5) and the first dielectric layer (4); S3.3 Remove the remaining photoresist layer (6).
4. The method according to claim 3, wherein In step S3.2, the etching process is any one of dry etching, wet etching, or non-plasma gas-phase reaction etching.
5. The method according to claim 3, characterized in that, In step S3.3, the photoresist layer (6) is removed using wet stripping or a photoresist remover device.
6. The method according to claim 1, wherein The material of the first dielectric layer (4) is a silicon oxide layer, formed by an in-situ steam oxidation process.
7. The method according to claim 1, wherein The material of the second dielectric layer (5) is a silicon oxide layer, formed by an in-situ steam oxidation process.
8. A method for forming a gate structure, characterized in that Further implemented based on the method according to any one of claims 1-7, including the following steps: S4. Sequentially form a polysilicon layer (7) and a hard mask layer (8) on the surface of the substrate, and perform patterning on the polysilicon layer (7) and the hard mask layer (8) through an etching process; S5. Remove the first dielectric layer (4) in the non-gate region and the second dielectric layer (5) in the non-gate region through an etching process, only retaining the part at the bottom of the gate region, thereby forming a gate structure.
9. The method according to claim 8, wherein Also including the step: S6. Form a sidewall structure (9) on the gate structure.
10. A semiconductor structure, characterized in that, Prepared by using the method for removing a dielectric layer according to any one of claims 1-7 or the method for forming a gate structure according to any one of claims 8-9.