Hybrid substrate, preparation method thereof and semiconductor device
The mixed substrate solution addresses the performance and area inefficiencies of SOI-based semiconductor devices by creating a hybrid substrate with both SOI and bulk silicon regions, enabling efficient formation and reduced area usage for logic and RF components.
Patent Information
- Application Number
- CN202510471617.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-15
- Publication Date
- 2025-07-15
AI Technical Summary
In the prior art, when logic devices and radio frequency devices are formed on SOI substrates, logic devices occupy a large area and have no obvious advantages in performance, making it difficult to take into account both performance and cost.
By preparing a hybrid substrate on the SOI substrate, including removing part of the top silicon layer and the insulating layer, forming a doped layer and forming an isolation region therein, forming an SOI region and a bulk silicon region of the hybrid substrate, for use in logic devices and radio frequency devices, respectively.
The performance optimization of logic devices and RF devices is achieved, reducing the area of logic devices, reducing costs, and improving the overall performance of semiconductor devices.
Smart Images
Figure CN120322018A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of semiconductor technology, and more particularly to a hybrid substrate, a method for preparing the same, and a semiconductor device. Background Art
[0002] Currently, for semiconductor devices integrating logic devices and radio frequency devices, the logic devices and radio frequency devices are usually formed together on a SOI (Silicon On Insulator) substrate. By introducing an insulating layer (BOX), the SOI substrate can effectively reduce the parasitic capacitance between the device and the substrate, thereby improving the switching speed of the circuit and reducing the power consumption. For radio frequency devices, forming them on a SOI substrate has good radio frequency performance; while for logic devices, forming them on a SOI substrate occupies a larger area compared to forming on a bulk silicon substrate and has no obvious performance advantages.
[0003] Therefore, improvements are needed to at least partially solve the above problems. Summary of the Invention
[0004] A series of simplified concepts are introduced in the Summary of the Invention section, which will be further elaborated in the Detailed Description section. The Summary of the Invention section of the present invention does not mean to attempt to define the key features and essential technical features of the claimed technical solution, nor does it mean to attempt to determine the protection scope of the claimed technical solution.
[0005] To at least partially solve the above problems, according to a first aspect of the present invention, there is provided a method for preparing a hybrid substrate, which includes:
[0006] Providing a SOI substrate, wherein the SOI substrate includes a bottom silicon layer, an insulating layer located above the bottom silicon layer, and a top silicon layer located above the insulating layer, and the SOI substrate has a first region and a second region;
[0007] Removing the top silicon layer in the first region and the insulating layer in the first region to expose the bottom silicon layer in the first region;
[0008] Forming a doped layer on the upper part of the exposed bottom silicon layer in the first region;
[0009] Forming isolation regions in the doped layer.
[0010] Exemplarily, the removing the insulating layer in the first region and the top silicon layer in the first region to expose the bottom silicon layer in the first region includes:
[0011] A patterned first mask layer is formed above the SOI substrate, wherein the first mask layer exposes the top silicon layer located in the first region;
[0012] Using the first mask layer as a mask, etch the top silicon layer located in the first region and the insulating layer located in the first region until the bottom silicon layer located in the first region is exposed.
[0013] Exemplarily, forming a doped layer on the upper part of the exposed bottom silicon layer located in the first region includes:
[0014] A patterned second mask layer is formed above the second region, wherein the second mask layer exposes the bottom silicon layer located in the first region;
[0015] Using the second mask layer as a mask, form the doped layer on the upper part of the exposed bottom silicon layer located in the first region through an ion implantation process and / or a diffusion process; or,
[0016] Forming a doped layer on the upper part of the exposed bottom silicon layer located in the first region includes:
[0017] Using the first mask layer as a mask, form the doped layer on the upper part of the exposed bottom silicon layer located in the first region through an ion implantation process.
[0018] Exemplarily, forming isolation regions in the doped layer includes:
[0019] A patterned third mask layer is formed above the first region and above the second region, wherein the third mask layer exposes a part of the doped layer;
[0020] Oxidize the exposed part of the doped layer to form the isolation regions.
[0021] Exemplarily, forming isolation regions in the doped layer includes:
[0022] A patterned third mask layer is formed above the first region and above the second region, wherein the third mask layer exposes at least a part of the doped layer;
[0023] Etch the exposed part of the doped layer to form isolation trenches in the doped layer;
[0024] Deposit isolation material, wherein the isolation material fills the isolation trenches and covers the third mask layer;
[0025] Remove the isolation material located above the third mask layer and retain the isolation material located in the isolation trenches.
[0026] Exemplarily, removing the isolation material above the third mask layer and retaining the isolation material in the isolation trench includes:
[0027] Grinding the isolation material through a CMP process until the third mask layer above the second region is exposed;
[0028] Removing the isolation material above the third mask layer in the first region through a dry etching process or a wet etching process, wherein the upper surface of the remaining isolation material is not higher than the upper surface of the third mask layer in the first region.
[0029] Exemplarily, the lower surface of the isolation region is not higher than the lower surface of the doped layer.
[0030] According to a second aspect of the present invention, there is provided a hybrid substrate, which includes:
[0031] A bottom silicon layer, the bottom silicon layer having a first part and a second part, the first part having a doped layer and an isolation region formed thereon, the isolation region being located in the doped layer;
[0032] An insulating layer, the insulating layer being located above the second part;
[0033] A top silicon layer, the top silicon layer being located above the insulating layer.
[0034] Exemplarily, the upper surface of the isolation region is not lower than the upper surface of the doped layer;
[0035] The lower surface of the isolation region is not higher than the lower surface of the doped layer.
[0036] According to a third aspect of the present invention, there is provided a semiconductor device, which includes the hybrid substrate as described above;
[0037] The semiconductor device further includes logic devices and radio frequency devices, the logic devices being formed on the doped layer, and the radio frequency devices being formed on the top silicon layer.
[0038] According to the hybrid substrate, its preparation method, and the semiconductor device of the present invention, the hybrid substrate has both an SOI region and a bulk silicon region at the same time. The SOI region and the bulk silicon region can be respectively used to form logic devices and radio frequency devices. The hybrid substrate can combine the advantages of an SOI substrate and a bulk silicon substrate to optimize performance and cost. Description of the Drawings
[0039] The following drawings of the present application are hereby incorporated as part of the present application for understanding the present application. The embodiments of the present application are shown in the drawings and described to explain the device and principle of the present application. In the drawings,
[0040] Figure 1 is a schematic flow chart of a method for preparing a hybrid substrate according to an embodiment of the present application;
[0041] Figures 2A - 2F is a cross-sectional schematic view of each step of a method for preparing a hybrid substrate according to an embodiment of the present application;
[0042] Figure 3 is a cross-sectional schematic view of a hybrid substrate according to an embodiment of the present application;
[0043] Figures 4A - 4F is a cross-sectional schematic view of each step of a method for preparing a hybrid substrate according to another embodiment of the present application;
[0044] Figure 5 is a cross-sectional schematic view of a hybrid substrate according to another embodiment of the present application.
[0045] Description of reference numerals:
[0046] 100 - SOI substrate, 110 - first region, 120 - second region, 101 - bottom silicon layer, 1011 - first part, 1022 second part, 102 - insulating layer, 103 - top silicon layer, 200 - first mask layer, 300 - second mask layer, 400 - doping layer, 500 - third mask layer, 600 - isolation region, 700 - isolation material, 800 - isolation region. Detailed Description
[0047] In the following description, numerous specific details are given to provide a more thorough understanding of the present application. However, it is obvious to those skilled in the art that the present application can be implemented without one or more of these details. In other instances, some well-known technical features are not described to avoid confusion with the present application.
[0048] It should be understood that the present application can be implemented in different forms and should not be construed as limited to the embodiments presented herein. On the contrary, these embodiments are provided to make the disclosure thorough and complete, and to fully convey the scope of the present application to those skilled in the art. In the drawings, for clarity, the dimensions and relative dimensions of layers and regions may be exaggerated. The same reference numerals denote the same elements throughout.
[0049] It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Thus, without departing from the teachings of the present application, the first element, component, region, layer, or part discussed below may be referred to as the second element, component, region, layer, or part.
[0050] Spatial relationship terms such as "under", "below", "beneath", "underneath", "above", "on top", etc. may be used herein for convenience in describing the relationship of one element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientation shown in the figures, spatial relationship terms are intended to also include different orientations of the device during use and operation.
[0051] The purpose of the terms used herein is only to describe specific embodiments and is not a limitation of the present application. As used herein, the singular forms "a", "an", and "the" are also intended to include the plural forms unless the context clearly dictates otherwise. It should also be understood that the terms "comprising" and / or "including", when used in this specification, specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. As used herein, the term "and / or" includes any and all combinations of the associated listed items.
[0052] Embodiments of the invention are described herein with reference to cross-sectional views that are schematic illustrations of ideal embodiments (and intermediate structures) of the present application. Thus, it is contemplated that variations in the shapes shown, for example, due to manufacturing techniques and / or tolerances. Accordingly, the embodiments of the present application should not be limited to the specific shapes shown herein, but include shape deviations due to, for example, manufacturing. Thus, the figures shown are substantially schematic in nature, and their shapes are not intended to show the actual shape of the device and are not intended to limit the scope of the present application.
[0053] Refer to the attached Figure 1 An exemplary illustration is given of a method for preparing a hybrid substrate according to an embodiment of the present application. The preparation method includes:
[0054] S10: Provide an SOI (Silicon On Insulator) substrate. Among them, the SOI substrate includes a bottom silicon layer, an insulating layer located above the bottom silicon layer, and a top silicon layer located above the insulating layer. The SOI substrate has a first region and a second region;
[0055] S20: Remove the top silicon layer and the insulating layer in the first region to expose the bottom silicon layer in the first region;
[0056] S30: Form a doped layer on the upper part of the exposed bottom silicon layer in the first region;
[0057] S40: Form isolation regions in the doped layer.
[0058] According to the method for preparing a hybrid substrate of the present invention, in the formed hybrid substrate, the first region is equivalent to a bulk silicon substrate, and the second region is an SOI substrate. That is, the hybrid substrate simultaneously has an SOI region (the second region) and a bulk silicon region (the first region), and the SOI region and the bulk silicon region can be respectively used to form logic devices and radio frequency devices. The hybrid substrate can combine the advantages of an SOI substrate and a bulk silicon substrate to achieve optimization of performance and cost.
[0059] The following refers to the atta Figures 2A - 2F A method for preparing a hybrid substrate according to an embodiment of the present application (i.e., the above steps S10 - S40) will be described in detail.
[0060] In step S10, refer to the atta Figure 2A , provide an SOI substrate 100.
[0061] Specifically, the SOI substrate 100 includes a bottom silicon layer 101, an insulating layer 102 located above the bottom silicon layer 101, and a top silicon layer 103 located above the insulating layer 102. Exemplarily, both the bottom silicon layer 101 and the top silicon layer 103 are undoped single-crystalline silicon, and the insulating layer 102 is a silicon dioxide layer. The SOI substrate 100 has a first region 110 and a second region 120. It should be noted that the first region 110 and the second region 120 are artificially defined regions. The first region 110 is a bulk silicon region, which can be used to form logic devices after subsequent processing steps, and the second region 120 is an SOI region, which can be used to form radio frequency devices. In some embodiments, the first region 110 and the second region 120 can be arranged side by side. That is, from a top-down perspective, both the first region 110 and the second region 120 can be strip-shaped and arranged in parallel side by side. Exemplarily, the first region 110 and the second region 120 can be arranged alternately side by side. That is, the first region 110 is located between two adjacent second regions 120, and the second region 120 is located between two adjacent first regions 110. In some embodiments, the second region 120 can be disposed around the outside of the first region 110. That is, from a top-down perspective, the first region 110 can be rectangular, circular, or other suitable shapes, and the second region 120 surrounds the first region 110 in a circumferential direction. In some embodiments, the first region 110 can be disposed around the outside of the second region 120. That is, from a top-down perspective, the second region 120 can be rectangular, circular, or other suitable shapes, and the first region 110 surrounds the second region 120 in a circumferential direction. In this step, there is no difference in the structures of the first region 110 and the second region 120 themselves. Both the first region 110 and the second region 120 include the bottom silicon layer 101, the insulating layer 102, and the top silicon layer 103.
[0062] Exemplarily, the radio frequency devices include, but are not limited to, radio frequency transmitters, radio frequency receivers, radio frequency switches, low-noise amplifiers, power amplifiers, mixers, voltage-controlled oscillators, phase shifters, resonators, filters, antennas, modulators, demodulators, etc.
[0063] Exemplarily, the logic devices include, but are not limited to, transistors, diodes, capacitors, memory cells, transistors, resistors, etc. Exemplarily, the logic devices can simultaneously include n-channel metal-oxide-semiconductor (NMOS) field-effect transistors and p-channel metal-oxide-semiconductor (PMOS) field-effect transistors.
[0064] In step S20, refer to the appendix Figure 2B , remove the top silicon layer 103 located in the first region 110 and the insulating layer 102 located in the first region 110, exposing the bottom silicon layer 101 located in the first region 110.
[0065] Specifically, first, a patterned first mask layer 200 is formed above the SOI substrate 100 (i.e., above the top silicon layer 103 in the first region 110 and the second region 120). The first mask layer 200 covers the top silicon layer 103 in the second region 120 and exposes the top silicon layer 103 in the first region 110. In this embodiment, the first mask layer 200 may include a silicon dioxide layer, and the first mask layer 200 is patterned through a photolithography and etching process. The first mask layer 200 may also be any other type of mask patterned through any suitable process.
[0066] Then, using the first mask layer 200 as a mask, the top silicon layer 103 in the first region 110 and the insulating layer 102 in the first region 110 are etched until the bottom silicon layer 101 in the first region 110 is exposed. Exemplarily, the top silicon layer 103 in the first region 110 and the insulating layer 102 in the first region 110 can be etched through a dry etching process. Exemplarily, the dry etching process includes but is not limited to plasma etching, reactive ion etching, etc.
[0067] In step S30, referring to the appendix Figure 2C , a doped layer 400 is formed on the upper part of the exposed bottom silicon layer 101 in the first region 110.
[0068] Specifically, first, a patterned second mask layer 300 is formed above the second region 120. Among them, the second mask layer 300 exposes the bottom silicon layer 101 in the first region 110. In this embodiment, the patterned second mask layer 300 is located above the first mask layer 200, covers the first mask layer 200, and exposes the bottom silicon layer 101 in the first region 110. Exemplarily, the second mask layer 300 may be a photoresist layer. A second mask layer 300 can be formed integrally above the first region 110 and the second region 120 first, and then patterned so that it is only located above the second region 120 (e.g., above the first mask layer 200). In some other embodiments, the first mask layer 200 can be removed first, and then a patterned second mask layer 300 is re-formed. At this time, the patterned second mask layer 300 is at least above the top silicon layer 103 in the second region 120, covers the top silicon layer 103 in the second region 120, and exposes the bottom silicon layer 101 in the first region 110.
[0069] Then, using the second mask layer 300 as a mask, a doped layer 400 is formed on the upper part of the exposed bottom silicon layer 101 in the first region 110 through an ion implantation process. It should be noted that in this application, the "upper part" refers to the upper side region inside it, and the "above" refers to the upper side region outside it. Exemplarily, N-type ions (such as phosphorus, arsenic, antimony, etc.) or P-type ions (such as boron, etc.) can be implanted through an ion implantation process on the upper part of the exposed bottom silicon layer 101 in the first region 110 to form an N-type or P-type doped layer 400. It should be noted that after ion implantation, crystal damage can be repaired and doped ions can be activated through a Rapid Thermal Annealing (RTA) process. After forming the doped layer 400, the resistance value of the bottom silicon layer 101 in the first region 110 can be effectively reduced, making its performance reach or approach that of a conventional bulk silicon substrate. Exemplarily, the depth of the doped layer 400 is less than or equal to the thickness of the bottom silicon layer 101, and the depth of the doped layer 400 is greater than or equal to one-fourth, one-third, one-half, or other appropriate values of the thickness of the bottom silicon layer 101. This application does not make specific limitations in this regard. In some embodiments, the doped layer 400 can be formed on the upper part of the exposed bottom silicon layer 101 in the first region 110 through a diffusion process. It should be noted that when forming the doped layer 400 on the upper part of the exposed bottom silicon layer 101 in the first region 110 through a diffusion process, the second mask layer 300 also needs to further cover the side surfaces of the insulating layer 102 and the top silicon layer 103 between the first region 110 and the second region 120.
[0070] In this embodiment, after forming the doped layer 400, the second mask layer 300 is removed.
[0071] In some other embodiments, in step S30, the second mask layer 300 may not be formed. Instead, directly using the first mask layer 200 formed in step S20 as a mask, a doped layer 400 is formed on the upper part of the exposed bottom silicon layer 101 in the first region 110 through an ion implantation process. It should be noted that after ion implantation, crystal damage can be repaired and doped ions can be activated through a Rapid Thermal Annealing (RTA) process. After forming the doped layer 400, the first mask layer 200 is removed.
[0072] In step S40, refer to the appendix Figures 2D - 2F , an isolation region 600 is formed in the doped layer 400.
[0073] Specifically, first, refer to the appendix Figure 2D, a patterned third mask layer 500 is formed above the first region 110 and above the second region 120, wherein the third mask layer 500 exposes a portion of the doped layer 400. Exemplarily, the third mask layer 500 may include a silicon oxide layer and a silicon nitride layer located on the silicon oxide layer. In some embodiments, the third mask layer 500 may include only a silicon nitride layer. Exemplarily, a layer of the third mask layer 500 may be deposited integrally above the first region 110 and above the second region 120 by a CVD (Chemical Vapor Deposition) process or other suitable deposition process, and then patterned by photolithography and etching processes to expose a portion of the doped layer 400. The patterned third mask layer 500 is used to define the position of the isolation region 600.
[0074] Then, refer to the attached Figure 2E , oxidize the exposed portion of the doped layer 400 to form the isolation region 600. Exemplarily, the substrate structure obtained in the previous step (i.e., the substrate structure shown in the attached Figure 2D ) can be placed in a high-temperature oxidation furnace and subjected to high-temperature oxidation in an oxidation atmosphere such as oxygen or water vapor. The surface of the doped layer 400 not covered by the third mask layer 500 will be oxidized to generate silicon dioxide, forming the isolation region 600. The oxidation temperature is usually between 900 - 1100 °C, and the oxidation time depends on the required thickness of the isolation region 600. Exemplarily, the bottom surface of the isolation region 600 is not higher than the bottom surface of the doped region, that is, the bottom surface of the isolation region 600 can be flush with the bottom surface of the doped region or slightly lower than the bottom surface of the doped region. The isolation region 600 can be used to define the device boundary, form isolation between devices, and prevent leakage and crosstalk between devices.
[0075] Then, refer to the attached Figure 2F , remove the third mask layer 500 and the second mask layer 300, thus obtaining a hybrid substrate. Among them, the first region 110 is equivalent to a bulk silicon substrate, and the second region 120 is a SOI substrate, that is, the hybrid substrate has both a SOI region (the second region 120) and a bulk silicon region (the first region 110), and the SOI region and the bulk silicon region can be used to form logic devices and RF devices respectively. In the related art, the logic devices formed on the SOI substrate can only be led out from the front side, occupying a relatively large area; while the logic devices formed on the bulk silicon region of the hybrid substrate of the present application can not only be led out from the front side, but also be led out from the back side (i.e., the lower side of the bottom silicon layer 101), which can significantly reduce the occupied area, is beneficial to the miniaturization of semiconductor devices, and can reduce costs while meeting performance requirements. That is, the hybrid substrate can combine the advantages of the SOI substrate and the bulk silicon substrate to achieve performance and cost optimization.
[0076] Refer to the attached Figure 3An exemplary description is given of a hybrid substrate according to an embodiment of the present application. The hybrid substrate is formed by the above steps S10 - S40 (i.e., the steps shown in Appendix Figures 2A - 2F ). The hybrid substrate includes a bottom silicon layer 101, an insulating layer 102, and a top silicon layer 103.
[0077] The bottom silicon layer has a first portion 1011 and a second portion 1012. A doped layer 400 and an isolation region 600 are formed on the upper part of the first portion, and the isolation region 600 is located in the doped layer 400. The insulating layer 102 is located above the second portion, and the top silicon layer 103 is located above the insulating layer 102.
[0078] Exemplarily, the doped layer 400 can be N - type or P - type. The depth of the doped layer 400 is less than or equal to the thickness of the bottom silicon layer 101, and the depth of the doped layer 400 is greater than or equal to one - quarter, one - third, one - half, or other appropriate values of the thickness of the bottom silicon layer 101. The present application does not make specific limitations in this regard. Exemplarily, the material of the isolation region 600 can be silicon dioxide. The isolation region 600 can be used to define device boundaries, form isolation between devices, and prevent leakage and crosstalk between devices. The material of the insulating layer 102 can be silicon dioxide.
[0079] Exemplarily, the upper surface of the isolation region 600 is not lower than the upper surface of the doped layer 400, and the lower surface of the isolation region 600 is not lower than the lower surface of the doped layer 400. Through such a setting, the isolation region 600 can have a better isolation effect. In this embodiment, the upper surface of the isolation region 600 is flush with the upper surface of the doped layer 400, and the lower surface of the isolation region 600 is flush with the lower surface of the doped layer 400.
[0080] Next, a detailed description is given of the preparation method of a hybrid substrate according to another embodiment of the present application. It should be noted that for the preparation method of this embodiment, steps S10 - S30 are the same as those of the above - mentioned embodiment (see Appendix Figures 2A - 2C ), and will not be repeated here.
[0081] In step S40, see Appendix Figures 4A - 4F , an isolation region 800 is formed in the doped layer 400.
[0082] Specifically, first, see Appendix Figure 4A, a patterned third mask layer 500 is formed above the first region 110 and above the second region 120, wherein the third mask layer 500 exposes at least a part of the doped layer 400. Exemplarily, the third mask layer 500 may include a silicon oxide layer and a silicon nitride layer located on the silicon oxide layer. In some embodiments, the third mask layer 500 may only include a silicon nitride layer. Exemplarily, a layer of the third mask layer 500 may be deposited integrally above the first region 110 and above the second region 120 by a CVD process or other suitable deposition process, and then patterned by photolithography and etching processes to expose at least a part of the doped layer 400. The patterned third mask layer 500 is used to define the position of the isolation region 800.
[0083] Then, referring to the atta Figure 4B , the exposed part of the doped layer 400 is etched to form isolation trenches in the doped layer 400. Exemplarily, the exposed part of the doped layer 400 may be etched using the third mask layer 500 as a mask by a dry etching process or a wet etching process to form isolation trenches. Exemplarily, the dry etching process includes but is not limited to plasma etching, reactive ion etching, etc. Exemplarily, the depth of the isolation trenches is greater than or equal to the thickness of the doped layer 400.
[0084] Then, referring to the atta Figure 4C , an isolation material 700 is deposited. The isolation material 700 fills the isolation trenches and covers the third mask layer 500. Exemplarily, the isolation material 700 may be deposited integrally above the first region 110 and the second region 120 by a High-Density Plasma Chemical Vapor Deposition (HDPCVD) process. Exemplarily, the isolation material 700 may be silicon oxide, silicon oxynitride, or other suitable dielectric materials.
[0085] In some embodiments, in step S40, when patterning the third mask layer 500 by photolithography and etching processes, it may be made to expose at least a part of the first mask layer 200 at the same time, and the exposed first mask layer 200 is etched until a part of the top silicon layer 103 is exposed; then, while etching the exposed part of the doped layer 400, the exposed part of the top silicon layer 103 is etched to form isolation trenches in the top silicon layer 103 synchronously; then, while depositing the isolation material 700, the isolation trenches are filled synchronously. The isolation material 700 deposited in the isolation trenches can be used as the isolation region in the top silicon layer 103 subsequently.
[0086] Then, referring to the atta Figures 4D - 4E, the isolation material 700 above the third mask layer 500 is removed, and the isolation material 700 in the isolation trenches is retained. The retained isolation material 700 constitutes the isolation region 800 in the doped layer 400.
[0087] Specifically, first refer to the appendix Figure 4D , the isolation material 700 is polished by a CMP (Chemical Mechanical Polishing) process until the third mask layer 500 above the second region 120 is exposed. That is, the third mask layer 500 serves as the stop layer for the CMP process.
[0088] Then refer to the appendix Figure 4E , the isolation material 700 above the third mask layer 500 in the first region 110 is removed by a dry etching process or a wet etching process. Among them, the upper surface of the remaining isolation material 700 is not higher than the upper surface of the third mask layer 500 in the first region 110. Exemplarily, a patterned fourth mask layer can be formed above the isolation material 700 and the exposed third mask layer 500. The fourth mask layer covers the third mask layer 500 and exposes the isolation material 700 in the first region 110. Then, using the fourth mask layer as a mask, the isolation material 700 is etched by a dry etching process or a wet etching process until the third mask layer 500 in the first region 110 is exposed. In some other embodiments, the fourth mask layer may not be formed, and the isolation material 700 is directly etched using the third mask layer 500 as a mask by a dry etching process or a wet etching process until the third mask layer 500 in the first region 110 is exposed. The upper surface of the etched remaining isolation material 700 can be flush with or slightly lower than the upper surface of the third mask layer 500 in the first region 110. The etched remaining isolation material 700 constitutes the isolation region 800 in the doped layer 400.
[0089] Then, refer to the appendix Figure 4F, the third mask layer 500 and the second mask layer 300 are removed, thus obtaining a hybrid substrate. Among them, the first region 110 is equivalent to a bulk silicon substrate, and the second region 120 is an SOI substrate. That is, the hybrid substrate simultaneously has an SOI region (the second region 120) and a bulk silicon region (the first region 110), and the SOI region and the bulk silicon region can be respectively used to form logic devices and radio frequency devices. In the related art, the logic devices formed on the SOI substrate can only be led out from the front side, occupying a relatively large area; while the logic devices formed on the bulk silicon region of the hybrid substrate of the present application can not only be led out from the front side, but also be led out from the back side (that is, the lower side of the bottom silicon layer 101), which can significantly reduce the occupied area, is beneficial to the miniaturization of semiconductor devices, and can reduce costs while meeting performance requirements. That is, the hybrid substrate can combine the advantages of the SOI substrate and the bulk silicon substrate to achieve the optimization of performance and cost.
[0090] Refer to the attached Figure 5 An exemplary description is given of a hybrid substrate according to another embodiment of the present application. This hybrid substrate is formed through the above steps S10-S40 (that is, the steps shown in the attached Figures 2A - 2C 、 Figures 4A - 4F . This hybrid substrate includes a bottom silicon layer 101, an insulating layer 102, and a top silicon layer 103.
[0091] The bottom silicon layer has a first part 1011 and a second part 1012. A doping layer 400 and an isolation region 800 are formed on the upper part of the first part, and the isolation region 800 is located in the doping layer 400. The insulating layer 102 is located above the second part, and the top silicon layer 103 is located above the insulating layer 102.
[0092] Exemplarily, the doping layer 400 can be N-type or P-type. The depth of the doping layer 400 is less than or equal to the thickness of the bottom silicon layer 101, and the depth of the doping layer 400 is greater than or equal to one-fourth, one-third, one-half or other appropriate values of the thickness of the bottom silicon layer 101. The present application does not make specific limitations on this. Exemplarily, the material of the isolation region 800 can be silicon dioxide, silicon nitride, etc. The isolation region 800 can be used to define the device boundary, form isolation between devices, and prevent leakage and crosstalk between devices. The material of the insulating layer 102 can be silicon dioxide.
[0093] Exemplarily, the upper surface of the isolation region 800 is not lower than the upper surface of the doping layer 400, and the lower surface of the isolation region 800 is not lower than the lower surface of the doping layer 400. Through such a setting, the isolation region 800 can have a better isolation effect. In this embodiment, the upper surface of the isolation region 800 is higher than the upper surface of the doping layer 400, and the lower surface of the isolation region 600 is flush with the lower surface of the doping layer 400.
[0094] The present application also provides a semiconductor device, which includes the hybrid substrate as described above. The semiconductor device further includes a logic device and a radio frequency device. The logic device is formed on the doped layer 400, and the radio frequency device is formed on the top silicon layer 103. It should be noted that the logic device may also be partially formed on the isolation region 600 (isolation region 800).
[0095] Exemplarily, the radio frequency device includes, but is not limited to, a radio frequency transmitter, a radio frequency receiver, a radio frequency switch, a low noise amplifier, a power amplifier, a mixer, a voltage controlled oscillator, a phase shifter, a resonator, a filter, an antenna, a modulator, a demodulator, etc.
[0096] Exemplarily, the logic device includes, but is not limited to, a transistor, a diode, a capacitor, a storage unit, a transistor, a resistor, etc. Exemplarily, the logic device may simultaneously include an n-channel metal oxide semiconductor (NMOS) field effect transistor and a p-channel metal oxide semiconductor (PMOS) field effect transistor.
[0097] In the semiconductor device according to the present application, its hybrid substrate has both an SOI region and a bulk silicon region, and the SOI region and the bulk silicon region form a logic device and a radio frequency device respectively. In the related art, the logic device formed on the SOI substrate can only be led out from the front side, occupying a relatively large area; while the logic device formed on the bulk silicon region of the hybrid substrate of the present application can not only be led out from the front side, but also be led out from the back side (i.e., the lower side of the bottom silicon layer 101), which can significantly reduce the occupied area, is beneficial to the miniaturization of the semiconductor device, and can reduce the cost while meeting the performance requirements.
[0098] Although example embodiments have been described herein with reference to the accompanying drawings, it should be understood that the above example embodiments are merely exemplary and are not intended to limit the scope of the present application thereto. Those of ordinary skill in the art can make various changes and modifications therein without departing from the scope and spirit of the present application. All such changes and modifications are intended to be included within the scope of the present application as claimed in the appended claims.
[0099] In several embodiments provided by the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of the units is only a logical function division, and there may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another device, or some features can be ignored or not executed.
[0100] In the specification provided herein, a number of specific details are set forth. It will be appreciated, however, that embodiments of the present application may be practiced without these specific details. In some instances, well-known methods, structures and techniques have not been shown in detail so as not to obscure an understanding of the present specification.
[0101] Similarly, it should be understood that in order to streamline the present application and assist in understanding one or more of the various inventive aspects, in the description of the exemplary embodiments of the present application, the various features of the present application are sometimes grouped together in a single embodiment, figure, or description thereof. However, the methods of the present application should not be construed as reflecting an intention that the claimed present application requires more features than are expressly recited in each claim. Rather, as reflected by the corresponding claims, the inventive point lies in that the corresponding technical problems can be solved by features less than all the features of a single disclosed embodiment. Therefore, the claims following the detailed description are hereby expressly incorporated into the detailed description, where each claim itself serves as a separate embodiment of the present application.
[0102] Those skilled in the art will appreciate that, except where features are mutually exclusive, any combination may be employed of all the features disclosed in this specification (including the accompanying claims, abstract and drawings) and all the processes or units of any method or apparatus so disclosed. Each feature disclosed in this specification (including the accompanying claims, abstract and drawings), unless otherwise expressly stated, may be replaced by alternative features serving the same, equivalent or similar purpose.
[0103] In addition, those skilled in the art will be able to understand that although some of the embodiments described herein include certain features included in other embodiments but not others, the combination of features of different embodiments means that it is within the scope of the present application and forms different embodiments. For example, in the claims, any one of the claimed embodiments may be used in any combination.
[0104] It should be noted that the above embodiments illustrate rather than limit the present application, and alternative embodiments may be designed by those skilled in the art without departing from the scope of the appended claims.
Claims
1. A method for preparing a hybrid substrate, characterized in that, Comprising: Providing an SOI substrate, wherein the SOI substrate includes a bottom silicon layer, an insulating layer located above the bottom silicon layer, and a top silicon layer located above the insulating layer, and the SOI substrate has a first region and a second region; Removing the top silicon layer located in the first region and the insulating layer located in the first region to expose the bottom silicon layer located in the first region; Forming a doped layer on the upper part of the exposed bottom silicon layer located in the first region; Forming isolation regions in the doped layer.
2. The preparation method according to claim 1, characterized in that The removing the top silicon layer located in the first region and the insulating layer located in the first region to expose the bottom silicon layer located in the first region includes: Forming a patterned first mask layer above the SOI substrate, wherein the first mask layer exposes the top silicon layer located in the first region; Using the first mask layer as a mask, etching the top silicon layer located in the first region and the insulating layer located in the first region until the bottom silicon layer located in the first region is exposed.
3. The preparation method according to claim 2, characterized in that The forming a doped layer on the upper part of the exposed bottom silicon layer located in the first region includes: Forming a patterned second mask layer above the second region, wherein the second mask layer exposes the bottom silicon layer located in the first region; Using the second mask layer as a mask, forming the doped layer on the upper part of the exposed bottom silicon layer located in the first region through an ion implantation process; or, The forming a doped layer on the upper part of the exposed bottom silicon layer located in the first region includes: Using the first mask layer as a mask, forming the doped layer on the upper part of the exposed bottom silicon layer located in the first region through an ion implantation process.
4. The preparation method according to claim 1, characterized in that The forming isolation regions in the doped layer includes: Forming a patterned third mask layer above the first region and above the second region, wherein the third mask layer exposes a part of the doped layer; Oxidizing the exposed part of the doped layer to form the isolation regions.
5. The preparation method according to claim 1, characterized in that The forming isolation regions in the doped layer includes: Forming a patterned third mask layer above the first region and above the second region, wherein the third mask layer exposes at least a part of the doped layer; Etching the exposed part of the doped layer to form isolation trenches in the doped layer; Depositing an isolation material, wherein the isolation material fills the isolation trenches and covers the third mask layer; Removing the isolation material located above the third mask layer and retaining the isolation material located in the isolation trenches.
6. The preparation method according to claim 5, characterized in that The removing the isolation material located above the third mask layer and retaining the isolation material located in the isolation trenches includes: The isolation material is polished by a CMP process until the third mask layer located above the second region is exposed; The isolation material located above the third mask layer in the first region is removed by a dry etching process or a wet etching process, wherein the upper surface of the remaining isolation material is not higher than the upper surface of the third mask layer in the first region.
7. The manufacturing method according to any one of claims 1-6, characterized in that The lower surface of the isolation region is not higher than the lower surface of the doped layer.
8. A hybrid substrate, characterized in that, Comprising: A bottom silicon layer having a first part and a second part, a doped layer and an isolation region are formed on the upper part of the first part, and the isolation region is located in the doped layer; An insulating layer located above the second part; A top silicon layer located above the insulating layer.
9. The hybrid substrate according to claim 8, characterized in that The upper surface of the isolation region is not lower than the upper surface of the doped layer; The lower surface of the isolation region is not higher than the lower surface of the doped layer.
10. A semiconductor device, characterized in that, Comprising the hybrid substrate according to claim 8 or 9; The semiconductor device further includes a logic device and a radio frequency device, the logic device is formed on the doped layer, and the radio frequency device is formed on the top silicon layer.