Booster comprising circuit for reducing overvoltage stresses on discharge protection device

Abstract

An apparatus comprising: a boosted voltage generator configured to generate a boosted voltage at an output; a first field effect transistor (FET) including a drain / source terminal coupled to the output terminal of the boost voltage generator; a discharge circuit coupled to a source / drain terminal of the first FET, where the discharge circuit is configured to discharge the output terminal of the boost voltage generator via the first FET in response to an effective discharge signal; and a gate voltage boost circuit configured to generate a gate voltage for a gate of the first FET, where the gate voltage boost circuit is configured to boost the gate voltage in response to an effective discharge signal. Another embodiment may include a current injection circuit configured to generate a current and inject the current into the discharge circuit in place of or in addition to the gate voltage boost circuit.

Description

Cross - Reference to Related Applications This patent application claims the benefit of priority to pending U.S. non - provisional application No. 18 / 080,607, filed on December 13, 2022, which has been assigned to the assignee of the present invention, and the content thereof is hereby incorporated by reference in its entirety as if fully set forth herein and for all applicable purposes. Technical Field Broadly speaking, aspects of the present disclosure relate to integrated circuits (ICs) including boost converters. Specifically, aspects of the present disclosure relate to boost converters including circuitry for reducing over - voltage stress on discharge protection devices. Background Art Integrated circuits (ICs) may include boost converters to generate a boosted voltage that is higher than an input voltage (e.g., the supply voltage on a voltage rail Vdd used by the boost converter). For example, if the supply voltage is 0.9 volts (V), the boost converter may generate a boosted voltage between 0.9 V and 1.8 V. To keep devices such as field - effect transistors (FETs) small for processing speed and IC footprint considerations, typically, the devices are implemented with a maximum rated voltage that has a certain tolerance margin higher than the supply voltage Vdd (e.g., 1.2 V, where 0.9 V is Vdd and 0.3 V is the tolerance margin). A boosted voltage that is twice the supply voltage Vdd may be higher than the rated voltage of such devices. Therefore, it is meaningful to protect such devices from over - voltage stress caused by the boosted voltage. Summary of the Invention A simplified summary of one or more embodiments is given below to provide a basic understanding of these embodiments. This summary is not an exhaustive overview of all contemplated embodiments and is neither intended to identify key or critical elements of all embodiments nor to describe the scope of any or all embodiments. Its sole purpose is to present some concepts of one or more embodiments in a simplified form as a prelude to the more detailed description that follows. One aspect of the present disclosure relates to an apparatus. The apparatus includes: a boosted - voltage generator configured to generate a boosted voltage at an output; a first field - effect transistor (FET) including a drain / source terminal coupled to the output of the boosted - voltage generator; a discharge circuit coupled to the source / drain terminal of the first FET, wherein the discharge circuit is configured to discharge the output of the boosted - voltage generator via the first FET in response to a discharge signal becoming active; and a gate - voltage boost circuit configured to generate a gate voltage for the first FET, wherein the gate - voltage boost circuit is configured to boost the gate voltage in response to the active discharge signal. Another aspect of the present disclosure relates to a method for reducing the boosted voltage at the output of a boost voltage generator. The method includes: discharging the output of the boost voltage generator via a first field effect transistor (FET) in response to a discharge signal becoming active; and boosting the gate voltage applied to the gate of the first FET in response to the active discharge signal. Another aspect of the present disclosure relates to a device including: a boost voltage generator configured to generate a boosted voltage at an output; a first field effect transistor (FET) including a drain / source terminal coupled to the output of the boost voltage generator; a discharge circuit coupled to the source / drain terminal of the first FET, wherein the discharge circuit is configured to discharge the output of the boost voltage generator via the first FET in response to a discharge signal becoming active; and a current injection circuit configured to generate a current and inject the current into the discharge circuit. Another aspect of the present disclosure relates to a method for reducing the boosted voltage at the output of a boost voltage generator. The method includes: discharging the output of the boost voltage generator via a first FET and a second FET in response to an active discharge signal applied to the gate of the second FET; generating an injection current; and combining the injection current with the drain-to-source current of the first FET to form a discharge current through the second FET. Another aspect of the present disclosure relates to a wireless communication device. The wireless communication device includes: at least one antenna; a transceiver coupled to the at least one antenna, wherein the transceiver includes: a booster including: a boost voltage generator configured to generate a boosted voltage at an output, a first field effect transistor (FET) including a drain / source terminal coupled to the output of the boost voltage generator, a discharge circuit coupled to the source / drain terminal of the first FET, wherein the discharge circuit is configured to discharge the output of the boost voltage generator via the first FET in response to a discharge signal becoming active; and a gate voltage booster circuit configured to generate a gate voltage for the gate of the first FET, wherein the gate voltage booster circuit is configured to generate the gate voltage at a boosted level in response to the active discharge signal; and an analog-to-digital converter (ADC) configured to use the boosted voltage; and an integrated circuit (IC) including one or more signal processing cores coupled to the transceiver. Another aspect of the present disclosure relates to a wireless communication device. The wireless communication device includes: at least one antenna; a transceiver coupled to the at least one antenna, wherein the transceiver includes: a booster including: a boost voltage generator configured to generate a boost voltage at an output, a first field effect transistor (FET) including a drain / source terminal coupled to the output of the boost voltage generator, a discharge circuit coupled to the source / drain terminal of the first FET, wherein the discharge circuit is configured to discharge the output of the boost voltage generator via the first FET in response to a discharge signal becoming active; and a current injection circuit configured to generate a current and inject the current into the discharge circuit, and an analog-to-digital converter (ADC) configured to use the boost voltage; and an integrated circuit (IC) including one or more signal processing cores coupled to the transceiver. To achieve the above and related purposes, one or more implementations include the features fully described and particularly pointed out in the claims below. The following description and the drawings set forth in detail certain illustrative aspects of one or more implementations. However, these aspects merely indicate some of the various ways in which the principles of the various implementations may be employed, and the description of the implementations is intended to include all such aspects and their equivalents. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 A schematic diagram of an example booster according to one aspect of the present disclosure is shown.

[0013] Figure 2 A schematic diagram of another example booster according to another aspect of the present disclosure is shown.

[0014] Figure 3 A schematic diagram / block diagram of another example booster according to another aspect of the present disclosure is shown.

[0015] Figure 4 A schematic diagram / block diagram of another example booster according to another aspect of the present disclosure is shown.

[0016] Figure 5 A schematic diagram / block diagram of another example booster according to another aspect of the present disclosure is shown.

[0017] Figure 6A A schematic diagram / block diagram of another example booster according to another aspect of the present disclosure is shown.

[0018] Figure 6B A graph depicting an example timing relationship between the gate voltage of an overvoltage protection field effect transistor (FET) and a discharge signal according to another aspect of the present disclosure is shown.

[0019] Figure 7 Shows a schematic diagram / block diagram of another example boost converter according to another aspect of the present disclosure.

[0020] Figure 8 Shows a schematic diagram / block diagram of another example boost converter according to another aspect of the present disclosure.

[0021] Figure 9 Shows a schematic diagram / block diagram of another example boost converter according to another aspect of the present disclosure.

[0022] Figure 10 Shows a schematic diagram / block diagram of another example boost converter according to another aspect of the present disclosure.

[0023] Figure 11 Shows a schematic diagram / block diagram of another example boost converter according to another aspect of the present disclosure.

[0024] Figure 12 Shows a schematic diagram / block diagram of another example boost converter according to another aspect of the present disclosure.

[0025] Figure 13 Shows a flowchart of an example method for reducing the boost voltage at the output of a boost voltage generator according to another aspect of the present disclosure.

[0026] Figure 14 Shows a flowchart of another example method for reducing the boost voltage at the output of a boost voltage generator according to another aspect of the present disclosure.

[0027] Figure 15 Shows a block diagram of an example wireless communication device according to another aspect of the present disclosure. Detailed Description

[0028] The following detailed description presented in connection with the accompanying drawings is intended as a description of various configurations and is not intended to represent the only configuration in which the concepts described herein can be implemented. The detailed description includes specific details for a thorough understanding of the various concepts. However, it will be apparent to those skilled in the art that these concepts may be practiced without these specific details. In some instances, well-known structures and components are shown in block diagram form to avoid obscuring such concepts.

[0029] Figure 1FIG. 0 shows a schematic diagram of an example boost converter 100 according to an aspect of the present disclosure. In this example, the boost converter 100 can be implemented as a switched-capacitor bootstrap converter. As further discussed herein, the switched-capacitor bootstrap converter generates a boosted voltage that is the sum of the supply voltage Vdd and the input voltage Vin, where Vin can vary, for example, between 0V and Vdd. The boost converter 100 can also be implemented in an integrated circuit (IC).

[0030] The boost converter 100 can be configured to generate a boosted voltage Vbst based on the input voltage Vin, where the boosted voltage Vbst is substantially equal to the sum of the upper supply voltage rail Vdd and the input voltage Vin. The boosted voltage Vbst is applied to the gate of a field-effect transistor (FET) to turn on the FET, thereby transferring the input voltage Vin to the load. The boost converter 100 includes a discharge circuit for resetting or reducing the gate voltage of the FET to zero (0) volts (V) or some other voltage level in preparation for a subsequent cycle of turning on the FET.

[0031] Specifically, the boost converter 100 includes a boosted voltage generator or charging circuit 110, a discharge circuit 120, an FET M11 (which can be implemented as an n-channel metal oxide semiconductor FET (NMOS FET)), and a capacitive load C L denoted as the load.

[0032] The boosted voltage generator 110 includes a set of switching devices SW11, SW12, SW13, and SW14 and a boost capacitor Cb. The switching device SW11 is coupled between the upper voltage rail Vdd and the node n1. The boost capacitor Cb is coupled between the node n1 and the node n2. The switching device SW12 is coupled between the node n2 and the lower voltage rail (e.g., ground). The switching device SW13 is coupled between the node n2 and an input terminal configured to receive the input voltage Vin. The switching device SW14 is coupled between the node n1 and the gate of the FET M11.

[0033] The discharge circuit 120 includes a switching device SW15 coupled between the gate of the FET M11 and the lower voltage rail. The FET M11 includes a drain coupled to the Vin input terminal and a source coupled to an output terminal that generates an output voltage Vout. The load C L is coupled between the output terminal and the lower voltage rail.

[0034] The boost converter 100 can operate according to two phases. These two phases can be cycled or repeated. In the first phase, the boost capacitor Cb is charged to have a potential Vdd across the capacitor Cb, while the gate of the FET M11 is coupled to the lower voltage rail; and in the second phase, a boosted voltage Vbst is generated at the gate of the FET M11 to turn on the FET M11 and allow the input voltage Vin to pass through to the load CL An output voltage Vout is formed at both ends.

[0035] More specifically, in the first stage, the switching devices SW11, SW12, and SW15 are closed, and the switching devices SW13 and SW14 are open. Closing the switching device SW11 couples the upper voltage rail Vdd to the first terminal of the boost capacitor Cb (at node n1), and closing the switching device SW12 couples the second terminal of the boost capacitor Cb (at node n2) to the lower voltage rail. Assuming that the voltage at the upper voltage rail can also be referred to as Vdd, and the voltage or potential at the lower voltage rail is zero (0) V or ground, the boost capacitor Cb is charged to a potential substantially equal to Vdd. The closed switching device SW15 couples the gate of M11 to ground to discharge any residual boost voltage Vbst from the previous cycle, and turns off the FET M11 during the first stage. During the first stage, the open switching devices SW13 and SW14 isolate the Vin input terminal and the gate of the FET M11 from the boost voltage generator 110, respectively.

[0036] During the second stage, the switching devices SW11, SW12, and SW15 are open, and the switching devices SW13 and SW14 are closed. Closing the switching device SW13 applies the input voltage Vin to the second terminal of the boost capacitor Cb (at node n2), and closing the switching device SW14 couples the first terminal of the boost capacitor Cb to the gate of the FET M11. In this configuration, the boost voltage Vbst generated at the gate of the FET M11 is substantially equal to Vdd + Vin. The open switching devices SW11 and SW12 isolate the boost capacitor Cb from the upper voltage rail and the lower voltage rail, respectively, and the open switching device SW15 isolates the gate of the FET M11 from the lower voltage rail. The boost voltage Vbst at the gate of the FET M11 turns on the FET M11 with a gate-to-source voltage (Vgs) substantially equal to Vdd. The turned-on FET M11 transfers the input voltage Vin to the output terminal to form an output voltage Vout (substantially equal to the input voltage Vin) across the load C L An output voltage Vout (substantially equal to the input voltage Vin) is formed at both ends.

[0037] As described above, the boost converter 100 may be implemented in an IC. In such an embodiment, the switching devices SW11 to SW15 may be implemented as FETs. Generally, such FETs SW11 to SW15 are designed to operate reliably at the maximum voltage between any two terminals of Vdd. For example, each of the FETs SW11 to SW15 may have a reliability limit that is a certain tolerance higher than Vdd. For example, if Vdd is 0.9V, the reliability limit of such FETs SW11 to SW15 may be 1.2V. However, the input voltage Vin may be as high as Vdd. And, as discussed, the boost voltage Vbst may be as high as Vdd + Vin or 2Vdd. As shown, the boost voltage Vbst is across the FET SW15 of the discharge circuit 120. Therefore, when the input voltage Vin is relatively high (e.g., Vin > 0.4Vdd), the FET SW15 may be subject to overvoltage stress (e.g., a voltage higher than its reliability limit).

[0038] Figure 2 A schematic diagram of another example boost converter 200 according to another aspect of the present disclosure is shown. In this example, the boost converter 200 may be implemented as a charge pump boost converter. As further discussed herein, the charge pump boost converter generates a boost voltage Vbst that is substantially twice the supply voltage Vdd (e.g., the input voltage is the supply voltage Vdd of the boost converter 200). The boost voltage Vbst is applied across the load. The boost converter 200 also includes a discharge circuit for resetting or reducing the voltage across the load in preparation for a subsequent cycle of generating the boost voltage Vbst and applying it across the load. Similarly, the boost converter 200 may be implemented in an integrated circuit (IC).

[0039] Specifically, the boost converter 200 includes a boost voltage generator or charging circuit 210, a discharge circuit 220, and a load represented by a capacitive load C L The boost voltage generator 210 includes a set of switching devices SW21, SW22, SW23, and SW24 and a boost capacitor Cb. The switching device SW21 is coupled between the upper voltage rail Vdd and the node n1. The boost capacitor Cb is coupled between the node n1 and the node n2. The switching device SW22 is coupled between the upper voltage rail Vdd and the node n2. The switching device SW23 is coupled between the node n2 and the lower voltage rail (e.g., ground). The switching device SW24 is coupled between the node n1 and the load C L between. The discharge circuit 220 includes a switching device SW25 that is coupled across or in parallel with the load C L in parallel.

[0040] The booster 200 can operate according to two phases. These two phases can be cycled or repeated. In the first phase, the boost capacitor Cb is charged to have a potential Vdd across the two terminals of the capacitor Cb, while the discharge circuit 220 shorts the load C L ; and in the second phase, a boosted voltage Vbst is generated across the load C L .

[0041] More specifically, in the first phase, the switching devices SW21, SW23, and SW25 are closed, while the switching devices SW22 and SW24 are open. Closing the switching device SW21 couples the upper voltage rail Vdd to the first terminal of the boost capacitor Cb (at node n1), and closing the switching device SW23 couples the second terminal of the boost capacitor Cb (at node n2) to the lower voltage rail. Assuming the voltage at the upper voltage rail can also be referred to as Vdd, and the voltage or potential at the lower voltage rail is zero (0) V or ground, the boost capacitor Cb is charged to a potential substantially equal to Vdd. Closing the switching device SW25 shorts the load C L to reduce any residual boosted voltage Vbst from the previous cycle to ground.

[0042] During the second phase, the switching devices SW21, SW23, and SW25 are open, and the switching devices SW22 and SW24 are closed. Closing the switching device SW22 applies Vdd to the second terminal of the boost capacitor Cb (at node n2), and closing the switching device SW24 couples the first terminal of the boost capacitor Cb to the load C L . In this configuration, the boosted voltage generated across the load C L is substantially equal to 2Vdd. The open switching devices SW21 and SW23 isolate the boost capacitor Cb from the upper voltage rail and the lower voltage rail respectively, and the open switching device SW25 removes the short across the load C L . L

[0043] As discussed above, the booster 200 can also be implemented in an IC, where the switching devices SW21 to SW25 are implemented as FETs. Similarly, such FETs SW21 to SW25 can be designed to operate reliably at the maximum voltage across any two terminals of Vdd, where the reliability limit is higher than Vdd by a certain tolerance margin. However, as discussed, the boosted voltage Vbst can be substantially equal to 2Vdd. As shown, the boosted voltage Vbst is across the FET SW25 of the discharge circuit 220. Accordingly, since the boosted voltage Vbst is substantially equal to 2Vdd, the FET SW25 may suffer from overvoltage stress (e.g., a voltage higher than its reliability limit).

[0044] Figure 3 ​FIG. / BLOCK DIAGRAM SHOWING ANOTHER EXAMPLE BOOST CONVERTER 300 IN ACCORDANCE WITH ANOTHER ASPECT OF THE PRESENT DISCLOSURE. THE BOOST CONVERTER 300 INCLUDES A BOOST VOLTAGE GENERATOR 310 AND A DISCHARGE CIRCUIT 320. THE BOOST VOLTAGE GENERATOR 310 IS CONFIGURED TO GENERATE AND OUTPUT A BOOST VOLTAGE Vbst BASED ON AN INPUT VOLTAGE Vin, WHERE THE BOOST VOLTAGE Vbst CAN BE AS HIGH AS 2Vdd. FOR EXAMPLE, IF THE BOOST VOLTAGE GENERATOR 310 IS IMPLEMENTED AS A BOOST SWITCH BOOST VOLTAGE GENERATOR 110, THE BOOST VOLTAGE Vbst CAN BE SUBSTANTIALLY EQUAL TO Vdd + Vin, WHERE Vin CAN BE AS HIGH AS Vdd. IF THE BOOST VOLTAGE GENERATOR 310 IS IMPLEMENTED AS A CHARGE PUMP BOOST VOLTAGE GENERATOR 210, THE BOOST VOLTAGE Vbst CAN BE SUBSTANTIALLY EQUAL TO 2Vdd. IT SHOULD BE UNDERSTOOD THAT THE BOOST VOLTAGE GENERATOR 310 CAN BE IMPLEMENTED AS OTHER TYPES OF BOOST VOLTAGE GENERATORS.

[0045] THE DISCHARGE CIRCUIT 320 INCLUDES A FET M31 (E.G., AN NMOS FET) THAT INCLUDES: A DRAIN COUPLED TO THE OUTPUT OF THE BOOST VOLTAGE GENERATOR 310 TO RECEIVE THE BOOST VOLTAGE Vbst THEREFROM; A SOURCE COUPLED TO A LOWER VOLTAGE RAIL (E.G., GROUND); AND A GATE CONFIGURED TO RECEIVE AN ENABLE DISCHARGE SIGNAL Vdsch TO TURN ON THE FET M31 DURING A SECOND OPERATING PHASE. AS DISCUSSED WITH REFERENCE TO THE BOOST CONVERTERS 100 AND 200, THE FET M31 MAY BE SUBJECTED TO OVER-VOLTAGE STRESS DUE TO THE BOOST VOLTAGE Vbst.

[0046] Figure 4 FIG. / BLOCK DIAGRAM SHOWING ANOTHER EXAMPLE BOOST CONVERTER 400 IN ACCORDANCE WITH ANOTHER ASPECT OF THE PRESENT DISCLOSURE. THE BOOST CONVERTER 400 IS SIMILAR TO THE PREVIOUSLY DISCUSSED BOOST CONVERTER 300, BUT INCLUDES AN OVER-VOLTAGE PROTECTION DEVICE TO PREVENT OVER-VOLTAGE STRESS OF THE DISCHARGE CIRCUIT.

[0047] SPECIFICALLY, THE BOOST CONVERTER 400 INCLUDES A BOOST VOLTAGE GENERATOR 410, AN OVER-VOLTAGE PROTECTIVE FIELD-EFFECT TRANSISTOR (FET) M41, AND A DISCHARGE CIRCUIT 420. THE BOOST VOLTAGE GENERATOR 410 IS CONFIGURED TO GENERATE AND OUTPUT A BOOST VOLTAGE Vbst BASED ON AN INPUT VOLTAGE Vin, WHERE THE BOOST VOLTAGE Vbst CAN BE AS HIGH AS 2Vdd. THE OVER-VOLTAGE PROTECTIVE FET M41 (E.G., AN NMOS FET) INCLUDES A DRAIN COUPLED TO THE OUTPUT OF THE BOOST VOLTAGE GENERATOR 410 (WHERE THE BOOST VOLTAGE Vbst IS GENERATED), A SOURCE COUPLED TO THE DISCHARGE CIRCUIT 420, AND A GATE CONFIGURED TO RECEIVE A POWER SUPPLY VOLTAGE AT A HIGH VOLTAGE RAIL Vdd.

[0048] The discharge circuit 420 includes an FET M42 (e.g., an NMOS FET) that includes: a drain coupled to the source of the overvoltage protection FET M41, a source coupled to the lower voltage rail (e.g., ground), and a gate configured to receive a discharge signal Vdsch. During a first operation phase, the discharge signal Vdsch becomes active to turn on the FET M42, thereby reducing the boost voltage Vbst by discharging the output of the boost voltage generator 410 to ground via the overvoltage protection FET M41. Turning on the FET M42 causes the overvoltage protection FET M41 to also turn on because its gate-to-source voltage Vgs is substantially Vdd, which can be higher than its threshold voltage Vth. During a second operation phase, the discharge signal Vdsch is deactivated to turn off the FET M42 while the boost voltage generator 410 outputs the boost voltage Vbst for its intended use (e.g., for turning on an FET or supplying the boost voltage Vbst to a load).

[0049] As represented by the thick gate line, the overvoltage protection FET M41 can be implemented with a thicker gate oxide compared to the gate oxide of the FET M42 of the discharge circuit 420. The thicker gate oxide FET M41 allows a voltage of up to 2Vdd across its terminals (e.g., its drain-to-source voltage Vds can be up to 2Vdd) without being affected by overvoltage stress (e.g., due to the thicker oxide layer, its reliability limit can be higher than 2Vdd). Thus, the FET M42 of the discharge circuit 420 is not affected by overvoltage stress because most of the boost voltage Vbst is across the overvoltage protection FET M41.

[0050] One drawback of this approach is that the overvoltage protection FET M41 is implemented with a thicker gate oxide than the gate oxide of the FET M42. Since the overvoltage protection FET M41 is different from the FET M42, additional process steps (e.g., different mask sets) should be implemented to form the thicker gate oxide FET M41. This complicates the manufacturing of the IC. Additionally, in some technology nodes, the formation of such a thicker gate oxide FET M41 may not be available or feasible. Therefore, it is desirable to implement the overvoltage protection FET in the same manner as the FET M42 of the discharge circuit 420 (e.g., the same gate oxide thickness).

[0051] Figure 5FIG. shows a schematic diagram / block diagram of another example boost converter 500 according to another aspect of the present disclosure. As discussed in more detail herein, the boost converter 500 includes a gate voltage boost circuit configured to generate a boosted gate voltage for an overvoltage protection field effect transistor (FET) in response to an active discharge signal Vdsch. The boosted gate voltage ensures that the voltage between any two terminals of the overvoltage protection field effect transistor (FET) does not cause overvoltage stress to the FET. In doing so, the overvoltage protection FET does not need to be implemented with a thicker oxide and can be implemented with a thinner oxide according to other FETs (e.g., FETs of the discharge circuit) in the integrated circuit (IC).

[0052] Specifically, the boost converter 500 includes a boost voltage generator 510, an overvoltage protection FET M51, a discharge circuit 520, and a gate voltage boost circuit 530. The boost voltage generator 510 is configured to generate a boost voltage Vbst based on an input voltage Vin, where the boost voltage Vbst can be up to 2Vdd. The overvoltage protection FET M51 (e.g., an NMOS FET) includes a drain coupled to the output terminal of the boost voltage generator 510 where the boost voltage Vbst is generated, a source coupled to the discharge circuit 520, and a gate configured to receive a gate voltage Vg.

[0053] The discharge circuit 520 includes an FET M52 (e.g., an NMOS FET) that includes a drain coupled to the source of the overvoltage protection FET M51, a source coupled to a lower voltage rail (e.g., ground), and a gate configured to receive a discharge signal Vdsch. The gate voltage boost circuit 530 includes an input terminal configured to receive the discharge signal Vdsch and is configured to generate a boosted gate voltage Vg for the overvoltage protection FET M51 in response to the discharge signal Vdsch becoming active. When the discharge signal Vdsch is not active, the gate voltage boost circuit 530 can be configured to generate a gate voltage Vg at a non-boosted voltage level (e.g., Vdd).

[0054] During a first operating phase, the discharge signal Vdsch becomes active to turn on the FET M52 to discharge the output terminal of the boost voltage generator 510 to ground via the overvoltage protection FET M51, such that the boosted voltage Vbst is reduced to, for example, 0V. Moreover, in response to the active discharge signal Vdsch, the gate voltage boost circuit 530 boosts the gate voltage Vg for the overvoltage protection FET M51 such that the voltage across any two of its terminals is at or below a threshold (e.g., at or below Vdd).

[0055] For example, the gate voltage booster circuit 530 can boost the gate voltage Vg from Vdd to 2Vdd. During the initial discharge stage (the time when overvoltage stress occurs), the discharge current can be considered relatively constant. Regardless of whether the discharge current is constant, at a given discharge current, when the gate voltage Vg is boosted, the source voltage Vs of the overvoltage protection FET M51 also exhibits a similar voltage increase t. If the boost voltage Vbst (which is also the drain voltage Vd of the overvoltage protection FET M51) is 2Vdd, the voltage difference between any two terminals is not greater than Vdd. For example, if Vd is 2Vdd, Vg is 2Vdd, and Vs is Vdd, then: the gate-to-drain voltage Vgd of the overvoltage protection FET M51 is basically 0V (e.g., Vg - Vd = 2Vdd - 2Vdd = 0V); the gate-to-source voltage Vgs of the overvoltage protection FET M51 is basically Vdd (e.g., Vg - Vs = 2Vdd - Vdd = Vdd); and the drain-to-source voltage Vds of the overvoltage protection FET M51 is basically Vdd (e.g., Vd - Vs = 2Vdd - Vdd = Vdd). In this case, the overvoltage protection FET M51 is not affected by overvoltage stress.

[0056] During the second operation stage, the discharge signal Vdsch is deactivated (disabled) to turn off the FET M52, so that the boost voltage Vbst generated by the boost voltage generator 510 can be used for its intended purpose (e.g., providing the boost voltage Vbst to a load C L or turning on a FET (e.g., FET M11)). In response to the deactivated discharge signal Vdsch, the gate voltage booster circuit 530 reduces the gate voltage Vg to its non-boost level (e.g., at Vdd).

[0057] Figure 6A A schematic diagram / block diagram of another example booster 600 according to another aspect of the present disclosure is shown. The booster 600 can be a more detailed implementation example of the booster 500. Specifically, the booster 600 includes a boost voltage generator 610, an overvoltage protection field effect transistor (FET) M61, a discharge circuit 620, and a gate voltage booster circuit 630.

[0058] The boost voltage generator 610 is configured to generate a boosted voltage Vbst based on an input voltage Vin, where the boosted voltage Vbst can be up to 2Vdd. The overvoltage protection FET M61 (e.g., an NMOS FET) includes a drain coupled to the output of the boost voltage generator 610 where the boosted voltage Vbst is generated, a source coupled to the discharge circuit 620, and a gate configured to receive a gate voltage Vg. The discharge circuit 620 includes an FET M63 (e.g., a p-channel metal oxide semiconductor FET (PMOS FET)) serially coupled between the upper voltage rail Vdd and the lower voltage rail (e.g., ground) with an FET M62 (e.g., an NMOS FET). That is, the FET M63 includes a source coupled to the upper voltage rail Vdd, a gate configured to receive a discharge signal Vdsch, and a drain coupled to the drain of the FET M62 and the source of the overvoltage protection FET M61. The FET M62 includes a source coupled to the lower voltage rail and a gate configured to receive the discharge signal Vdsch.

[0059] The gate voltage boost circuit 630 includes a capacitor C0 coupled between the gate of the FET M63 and the gate of the overvoltage protection FET M61. Additionally, the gate voltage boost circuit 630 includes a resistor R0 coupled between the upper voltage rail Vdd and the gate of the overvoltage protection FET M61. Further, the gate voltage boost circuit 630 includes an FET M64 (e.g., a PMOS FET) coupled between the upper voltage rail Vdd and the gate of the overvoltage protection FET M61. That is, the FET M64 includes a source coupled to the upper voltage rail Vdd, a gate coupled to the output of the boost voltage generator 610, and a drain coupled to the gate of the overvoltage protection FET M61.

[0060] Figure 6B A graph depicting an example timing relationship between the gate voltage Vg of the overvoltage protection FET M61 and the discharge signal Vdsch according to another aspect of the present disclosure is shown. The x-axis or horizontal axis represents time. The upper and lower parts of the y-axis or vertical axis represent the gate voltage Vg and the discharge signal Vdsch. The discharge signal Vdsch can switch between a non-active state (e.g., at 0V) and an active state (e.g., at Vdd). The gate voltage Vg can vary between a non-boosted level (e.g., at Vdd) and a boosted level (e.g., >Vdd). The operation of the gate boost circuit 630 is as follows:

[0061] The time interval from t1 to t2 is the discharge phase, and the time interval t2 - t3 is the non-discharge phase, where the boosted voltage Vbst is used for its intended purpose (e.g., to a load C LProvide a boosted voltage Vbst or turn on the FET (e.g., FET M11)). As shown, before time t1, the discharge signal is not active (e.g., at 0V), and in response, the gate voltage boost circuit 630 generates a gate voltage Vg at its non-boost level (e.g., Vdd). Specifically, the resistor R0 of the gate boost circuit 630 transfers the Vdd potential from the upper voltage rail Vdd to the gate of the overvoltage protection FET M61. The discharge signal Vdsch at 0V turns off FET M62 and turns on FET M63 to apply Vdd to the source of the overvoltage protection FET M61 to turn off M61 (since the gate-to-source voltage (Vgs) of M61 is substantially 0V (e.g., Vg = Vdd, Vs = Vdd → Vgs = Vdd - Vdd = 0V)). Thus, enabling M63 to charge the source voltage Vs of M61 to Vdd can turn off M61 and also avoid overvoltage stress during this phase (e.g., before t1 / discharge).

[0062] At the start of the discharge phase at time t1, the discharge signal Vdsch becomes active (e.g., by transitioning from 0V to Vdd). The discharge signal Vdsch at Vdd turns off FET M63 and turns on FET M62 to effect the discharge of the boosted voltage Vbst. In response, the gate voltage boost circuit 630 boosts the gate voltage Vg above its non-boosted voltage level. Specifically, the capacitor C0 of the gate voltage boost circuit 630 couples the rising edge of the discharge signal Vdsch to the gate of the overvoltage protection FET M61 to form a pulse in the gate voltage Vg, thereby effecting its boost. The peak and width of the gate voltage Vg pulse are controlled by FET M64 based on the boosted voltage Vbst, which acts as a voltage-controlled resistor.

[0063] For example, if the boosted voltage Vbst is relatively large (e.g., ~2Vdd), then the boosted voltage Vbst applied to the gate of FET M64 causes FET M64 to exhibit a relatively high resistance. In this way, the gate of the overvoltage protection FET M61 is well isolated from the upper voltage rail Vdd, allowing the gate voltage Vg to achieve a relatively high peak (e.g., ~2Vdd). Additionally, the high resistance of FET M64 results in a relatively large time constant for the gate voltage Vg pulse to achieve a relatively large width. The larger pulse width ensures that the overvoltage protection FET M61 is not affected by overvoltage stress during the discharge phase.

[0064] On the other hand, if the boosted voltage Vbst is relatively small (e.g., 0.5Vdd), the boosted voltage Vbst applied to the gate of FET M64 causes FET M64 to exhibit a relatively low resistance. In this way, the gate of the overvoltage protection FET M61 is more vulnerable to the upper voltage rail Vdd, thereby suppressing the gate voltage Vg from achieving a relatively high peak value (e.g., ~1.5Vdd). In addition, the low resistance of FET M64 makes the time constant of the gate voltage Vg pulse relatively small to achieve a relatively small width, thereby accelerating the discharge of the boosted voltage Vbst. By the end of the discharge phase at time t2, the gate voltage Vg has returned to its non-boosted level (e.g., at Vdd), and when the discharge signal Vdsch becomes and remains deactivated during the time interval t2 to t3, the gate voltage Vg remains at this level during the non-discharge phase.

[0065] Figure 7 FIG. / BLOCK DIAGRAM showing another example booster 700 according to another aspect of the present disclosure. As discussed in more detail herein, the booster 700 includes a current injection circuit configured to supply current to a discharge circuit to unload or reduce the drain-to-source current I of an overvoltage protection field effect transistor (FET). ds The current injection circuit provides current based on the drain-to-source voltage (Vds) of the overvoltage protection FET. Thus, if Vds is relatively high (e.g., close to the overvoltage stress condition), the current injection circuit provides a relatively high current to the discharge circuit to unload more drain-to-source current I from the overvoltage protection FET ds , reduce its drain-to-source voltage (Vds), and keep the overvoltage protection FET free from overvoltage stress.

[0066] Specifically, the booster 700 includes a boosted voltage generator 710, an overvoltage protection FET M71, a discharge circuit 720, and a current injection circuit 740. The boosted voltage generator 710 is configured to generate a boosted voltage Vbst based on an input voltage Vin, where the boosted voltage Vbst can be up to 2Vdd. The overvoltage protection FET M71 (e.g., an NMOS FET) includes a drain coupled to the output of the boosted voltage generator 710 where the boosted voltage Vbst is generated, a source coupled to the discharge circuit 720, and a gate configured to receive a gate voltage Vg (e.g., at ~Vdd).

[0067] The discharge circuit 720 includes a FET M72 (e.g., an NMOS FET) that includes a drain coupled to the source of the overvoltage protection FET M71, a source coupled to the lower voltage rail (e.g., ground), and a gate configured to receive a discharge signal Vdsch. The current injection circuit 740 includes an input terminal configured to receive the drain voltage Vd and the source voltage Vs of the overvoltage protection FET M71, and an output terminal for providing an injection current I inj to the discharge circuit 720 based on the drain-to-source voltage Vds of the overvoltage protection FET M71. As discussed in further and more detailed embodiments herein, one of the input terminals also serves as the output terminal of the current injection circuit 740.

[0068] During a first operating phase, the discharge signal Vdsch becomes active to turn on the FET M72 to discharge the output terminal of the boost voltage generator 710 to ground via the overvoltage protection FET M71, so as to reduce the boost voltage Vbst to, for example, 0V. The FET M72 turns on, thereby causing the source voltage Vs of the overvoltage protection FET M71 to decrease towards ground. If the boost voltage Vbst is relatively high (e.g., ~2Vdd), the drain-to-source voltage Vds of the overvoltage protection FET M71 increases towards 2Vdd as its source voltage Vs decreases due to the discharge circuit 720. The current injection circuit 740 senses the increase in the drain-to-source voltage Vds of the overvoltage protection FET M71 and provides the injection current I inj to the discharge circuit 720.

[0069] If the discharge current I dsch through the discharge circuit 720 is substantially constant, the drain-to-source current I ds of the overvoltage protection FET M71 is unloaded or reduced by the injection current I inj (e.g., I ds +I inj =I dsch →I ds =I dsch -I inj ). This reduction in I ds lowers the drain-to-source voltage Vds of the overvoltage protection FET M71. Or put another way, the injection current I inj increases the source voltage Vs to reduce the drain-to-source voltage Vds of the overvoltage protection FET M71 and prevent overvoltage stress on the FET M71. If the boost voltage Vbst is relatively small, which translates to a relatively small drain-to-source voltage Vds for the overvoltage protection FET M71, the current injection circuit 740 generates a relatively small injection current I inj based on Vds, because a smaller injection current I injTo maintain the overvoltage protection FET M71 from being affected by overvoltage stress conditions.

[0070] During the second operating phase, the discharge signal Vdsch is deactivated to turn off the FET M72, so that the boost voltage Vbst generated by the boost voltage generator 710 can be used for its intended purpose (e.g., to supply the boost voltage Vbst to a load C L or turn on a FET (e.g., FET M11)). Therefore, when the discharge path is cut off, the I ds and the injection current I inj of the overvoltage protection FET M71 are substantially zero (0) amperes (A). The source voltage Vs of M71 is charged to Vbst - Vth or Vdd (whichever is smaller), which prevents the FET M71 from being affected by overvoltage stress.

[0071] Figure 8 A schematic / block diagram of another example boost converter 800 according to another aspect of the present disclosure is shown. The boost converter 800 may be an example more detailed implementation of the boost converter 700. Specifically, the boost converter 800 includes a boost voltage generator 810, an overvoltage protection field effect transistor (FET) M81, a discharge circuit 820, and a current injection circuit 840.

[0072] The boost voltage generator 810 is configured to generate a boost voltage Vbst based on an input voltage Vin, where the boost voltage Vbst can be up to 2Vdd. The overvoltage protection FET M81 (e.g., an NMOS FET) includes a drain coupled to the output of the boost voltage generator 810 where the boost voltage Vbst is generated, a source coupled to the discharge circuit 820, and a gate configured to receive a gate voltage Vg (e.g., at ∼Vdd). The discharge circuit 820 includes a FET M82 (e.g., an NMOS FET) that includes a drain coupled to the source of the overvoltage protection FET M81, a source coupled to a lower voltage rail (e.g., ground), and a gate configured to receive a discharge signal Vdsch.

[0073] The current injection circuit 840 includes a FET M85 (e.g., an NMOS FET) that includes a drain coupled to the upper voltage rail Vdd, a gate coupled to the drain of the overvoltage protection FET M81, and a source coupled to the source of the overvoltage protection FET M81. The FET M85 is configured to generate an injection current I inj (e.g., its drain - source current).

[0074] During the first operation stage, the discharge signal Vdsch is asserted to turn on the FET M82 to discharge the output of the boost voltage generator 810 to the ground via the overvoltage protection FET M81 so as to reduce the boost voltage Vbst to, for example, 0V. The FET M82 is turned on, causing the source voltage Vs of the overvoltage protection FET M81 to decrease toward the ground. If the boost voltage Vbst is relatively high (e.g., ~2Vdd), the drain-to-source voltage Vds of the overvoltage protection FET M81 increases toward 2Vdd as its source voltage Vs decreases due to the discharge circuit 820. The gate-to-source voltage Vgs of the FET M85 is substantially the same as the drain-to-source voltage Vds of the overvoltage protection FET M81, senses the increase in Vds of the overvoltage protection FET M81, and injects an injection current I based on Vds. inj Provided to the discharge circuit 820.

[0075] In the initial discharge stage (when overvoltage stress occurs), the discharge current I dsch can be considered to be relatively constant. If the discharge current I dsch Basically constant, the drain-to-source current I ds The injected current I inj Unload or reduce (for example, I ds +I inj =I dsch →I ds =I dsch -I inj ). ds This reduction in Vds reduces the Vds of the overvoltage protection FET M81. Or in other words, the injected current I inj The source voltage Vs is increased to reduce the drain-to-source voltage Vds of the overvoltage protection FET M81 to prevent overvoltage stress on the FET M81. If the boost voltage Vbst is relatively small, which translates into a relatively small drain-to-source voltage Vds for the overvoltage protection FET M81, the FET M85 generates a relatively small injection current I based on Vds. inj , because a smaller injection current I is required inj To maintain the overvoltage protection FET M81 from overvoltage stress condition.

[0076] During the second operation phase, the discharge signal Vdsch is deasserted to turn off the FET M82 so that the boost voltage Vbst generated by the boost voltage generator 810 can be used according to its intended purpose (eg, to supply power to the load C L Provides a boost voltage Vbst or turns on a FET (e.g., FET M11). Therefore, when the discharge path is cut off, the Ids and the injected current I inj is substantially 0 A. The source voltage Vs of M81 is charged to Vbst - Vth or Vdd (whichever is smaller), which prevents the FET M81 from suffering overvoltage stress.

[0077] Figure 9 A schematic / block diagram of another example boost converter 900 according to another aspect of the present disclosure is shown. The boost converter 900 combines the gate boost circuit 530 of the boost converter 500 and the current injection circuit 740 of the boost converter 700 to prevent overvoltage stress on an overvoltage protection field - effect transistor (FET).

[0078] Specifically, the boost converter 900 includes a boost voltage generator 910, an overvoltage protection FET M91, a discharge circuit 920, and a gate voltage boost circuit 930. The boost voltage generator 910 is configured to generate a boost voltage Vbst based on the input voltage Vin, where the boost voltage Vbst can be up to 2Vdd. The overvoltage protection FET M91 (e.g., an NMOS FET) includes a drain coupled to the output of the boost voltage generator 910 where the boost voltage Vbst is generated, a source coupled to the discharge circuit 920, and a gate configured to receive a gate voltage Vg. The discharge circuit 920 includes an FET M92 (e.g., an NMOS FET) that includes a drain coupled to the source of the overvoltage protection FET M91, a source coupled to a lower voltage rail (e.g., ground), and a gate configured to receive a discharge signal Vdsch.

[0079] The gate voltage boost circuit 930 includes an input configured to receive the discharge signal Vdsch and is configured to generate a boosted gate voltage Vg for the overvoltage protection FET M91 in response to the discharge signal Vdsch becoming active. When the discharge signal Vdsch is not active, the gate voltage boost circuit 930 can be configured to generate a gate voltage Vg at a non - boosted voltage level (e.g., Vdd). The detailed operation of the gate voltage boost circuit 930 has been discussed with reference to the gate voltage boost circuit 530 of the boost converter 500.

[0080] The current injection circuit 940 includes an input configured to receive the drain voltage Vd and the source voltage Vs of the overvoltage protection FET M91, and an output for providing an injected current I inj based on the drain - to - source voltage Vds of the overvoltage protection FET M91 to the discharge circuit 920. The detailed operation of the current injection circuit 940 has been discussed with reference to the current injection circuit 740 of the boost converter 700.

[0081] Figure 10A schematic diagram / block diagram of another exemplary boost converter 1000 according to another aspect of the present disclosure is shown. The boost converter 1000 may be a more detailed embodiment example of the boost converter 900. Specifically, the boost converter 1000 includes a boost voltage generator 1010, an overvoltage protection field effect transistor (FET) M101, a discharge circuit 1020, a gate voltage boost circuit 1030, and a current injection circuit 1040.

[0082] The boost voltage generator 1010 is configured to generate a boost voltage Vbst based on an input voltage Vin, where the boost voltage Vbst may be up to 2Vdd. The overvoltage protection FET M101 (e.g., an NMOS FET) includes a drain coupled to the output terminal of the boost voltage generator 1010 where the boost voltage Vbst is generated, a source coupled to the discharge circuit 1020, and a gate configured to receive a gate voltage Vg. The discharge circuit 1020 includes an FET M103 (e.g., a PMOS FET) serially coupled between the upper voltage rail Vdd and the lower voltage rail (e.g., ground) with an FET M102 (e.g., an NMOS FET). That is, the FET M103 includes a source coupled to the upper voltage rail Vdd, a gate configured to receive a discharge signal Vdsch, and a drain coupled to the drain of the FET M102 and the source of the overvoltage protection FET M101. The FET M102 includes a source coupled to the lower voltage rail and a gate configured to receive the discharge signal Vdsch.

[0083] The gate voltage boost circuit 1030 includes a capacitor C0 coupled between the gate of the FET M103 and the gate of the overvoltage protection FET M101. Additionally, the gate voltage boost circuit 1030 includes a resistor R0 coupled between the upper voltage rail Vdd and the gate of the overvoltage protection FET M101. Further, the gate voltage boost circuit 1030 includes an FET M104 (e.g., a PMOS FET) coupled between the upper voltage rail Vdd and the gate of the overvoltage protection FET M101. That is, the FET M104 includes a source coupled to the upper voltage rail Vdd, a gate coupled to the output terminal of the boost voltage generator 1010, and a drain coupled to the gate of the overvoltage protection FET M101. The detailed operation of the gate voltage boost circuit 1030 has been discussed previously with reference to the gate voltage boost circuit 630 of the boost converter 600.

[0084] The current injection circuit 1040 includes a FET M105 (e.g., an NMOS FET) that includes a drain coupled to an upper voltage rail Vdd, a gate coupled to the drain of an overvoltage protection FET M101, and a source coupled to the source of the overvoltage protection FET M101. The FET M105 is configured to generate an injection current I based on the drain-to-source voltage Vds of the overvoltage protection FET M101 inj (e.g., its drain-to-source current). The detailed operation of the current injection circuit 1040 has been previously discussed with reference to the current injection circuit 840 of the boost converter 800.

[0085] Figure 11 A schematic / block diagram of another example boost converter 1100 in accordance with another aspect of the present disclosure is shown. The boost converter 1100 may be similar to the boost converter 1000 and have an example detailed implementation of a boost voltage generator. Specifically, the boost converter 1100 includes a boost voltage generator 1110, an overvoltage protection field effect transistor (FET) M111, a discharge circuit 1120, a gate voltage boost circuit 1130, and a current injection circuit 1140.

[0086] The boost voltage generator 1110 is configured to generate a boost voltage Vbst based on an input voltage Vin. The overvoltage protection FET M111 (e.g., an NMOS FET) includes a drain coupled to the boost voltage output of the boost voltage generator 1110 (where the boost voltage Vbst is generated), a source coupled to the discharge circuit 1120, and a gate configured to receive a gate voltage Vg. The discharge circuit 1120 includes a FET M113 (e.g., a PMOS FET) serially coupled between an upper voltage rail Vdd and a lower voltage rail (e.g., ground) with a FET M112 (e.g., an NMOS FET). That is, the FET M113 includes a source coupled to the upper voltage rail Vdd, a gate configured to receive a complementary clock signal and a drain coupled to the drain of the FET M112 and the source of the overvoltage protection FET M111. The FET M112 includes a source coupled to the lower voltage rail and a gate configured to receive a complementary clock signal that serves as a discharge signal Vdsch, as previously discussed.

[0087] The gate voltage boosting circuit 1130 includes a capacitor C0 coupled between the gate of FET M113 and the gate of overvoltage protection FET M111. Additionally, the gate voltage boosting circuit 1130 includes a resistor R0 coupled between the upper voltage rail Vdd and the gate of overvoltage protection FET M111. Further, the gate voltage boosting circuit 1130 includes a FET M114 (e.g., PMOS FET) coupled between the upper voltage rail Vdd and the gate of overvoltage protection FET M111. That is, FET M114 includes a source coupled to the upper voltage rail Vdd, a gate coupled to the boosted voltage output of the boosted voltage generator 1110, and a drain coupled to the gate of overvoltage protection FET M111. The detailed operation of the gate voltage boosting circuit 1130 has been discussed previously with reference to the gate voltage boosting circuit 630 of the booster 600.

[0088] The current injection circuit 1140 includes a FET M115 (e.g., NMOS FET) that includes a drain coupled to the upper voltage rail Vdd, a gate coupled to the drain of overvoltage protection FET M111, and a source coupled to the source of overvoltage protection FET M111. FET M115 is configured to generate an injection current I inj (e.g., the drain-to-source current of FET M115) based on the drain-to-source voltage Vds of overvoltage protection FET M111. The detailed operation of the current injection circuit 1140 has been discussed previously with reference to the current injection circuit 840 of the booster 800.

[0089] The boosted voltage generator 1110 includes a first FET M210 (e.g., PMOS FET) and a second FET M211 (e.g., NMOS FET) coupled in series between the upper voltage rail Vdd and node n2. That is, the first FET M210 includes a source coupled to the upper voltage rail Vdd, a gate configured to receive a non-complementary clock signal CLK, and a drain coupled to the drain of the second FET M211. The second FET M211 includes a gate coupled to the gate of the first FET M210 and is also configured to receive the non-complementary clock signal CLK. The second FET M211 includes a source coupled to node n2.

[0090] The boost voltage generator 1110 further includes a third FET M212 (e.g., a PMOS FET) serially coupled between the upper voltage rail Vdd and the lower voltage rail, a boost capacitor Cb, and a fourth FET M213 (e.g., an NMOS FET). That is, the third FET M212 includes a drain / source coupled to the upper voltage rail Vdd, a gate coupled to the boost voltage output terminal of the boost voltage generator 1110, and a source / drain coupled to the node n1. The boost capacitor Cb is coupled between the node n1 and n2. And, the third FET M213 includes a drain coupled to the node n2, a gate configured to receive a complementary clock signal and a source coupled to the lower voltage rail.

[0091] Regarding the terms "drain / source" and "source / drain", the FET M212 can be a symmetric device having a gate and two terminals. The terminal with the higher voltage of the PMOS FET M212 is typically referred to as the source, and the terminal with the lower voltage is referred to as the drain. However, for the PMOS FET M212, in one configuration, the voltage Vdd is higher than the voltage at the node n1. Thus, in this configuration, the source of the PMOS FET M212 is coupled to Vdd and the drain of the PMOS FET M212 is coupled to the node n1. In another configuration, the voltage at the node n1 is higher than Vdd. Thus, in this configuration, the source of the PMOS FET M212 is coupled to the node n1 and the drain of the PMOS FET M212 is coupled to Vdd. The same explanation applies to "drain / source" and "source / drain" for the FET M222 further described herein.

[0092] Additionally, the boost voltage generator 1110 includes a fifth FET M214 (e.g., a PMOS FET) coupled between the node nl and the boost voltage output terminal of the boost voltage generator 1110. That is, the fifth FET M214 includes a source coupled to the node nl, a gate coupled to the drains of the first FET M210 and the second FET M211, and a drain coupled to the output terminal of the boost voltage generator 1110. The boost voltage generator 1110 further includes a sixth FET M215 (e.g., an NMOS FET), which includes a drain coupled to the gate of the fifth FET M214, a gate coupled to the output terminal of the boost voltage generator 1110, and a source coupled to the node n2.

[0093] In addition, the boost voltage generator 1110 includes a seventh FET M216 (e.g., an NMOS FET) and an eighth FET (e.g., an NMOS FET) serially coupled between node n2 and the sampled voltage (Vsmpl) output terminal. That is, the seventh FET M216 includes a drain coupled to node n2, a gate coupled to the boost voltage output terminal of the boost voltage generator 1110, and a source coupled to the source of the eighth FET M217, where the sources of FETs M216 and M217 serve as the input terminal for the input voltage Vin. The eighth FET M217 includes a gate coupled to the boost voltage output terminal of the boost voltage generator 1110, and a drain serving as the sampled voltage (Vsmpl) output terminal.

[0094] In operation, when the non-complementary clock signal CLK and the complementary clock signal are low (e.g., 0V) and high (e.g., Vdd), respectively, the discharge circuit 1120 discharges the output terminal of the boost voltage generator 1110, while the gate boost circuit 1130 and the current injection circuit 1140 protect the overvoltage protection FET M111, as previously discussed. For the boost voltage generator 1110, the discharge circuit 1120 that reduces the boost voltage Vbst turns on the FET M212 to apply Vdd to the first terminal of the boost capacitor Cb (at node n1). The high complementary clock signal turns on the FET M213 to apply the ground potential to the second terminal of the boost capacitor Cb (at node n2). Also, the low non-complementary clock signal CLK turns on the FET M210 to apply Vdd to the gate of the FET M214 to turn it off, thereby isolating the boost capacitor Cb from the output terminal of the boost voltage generator 1110. Thus, during this stage, the boost capacitor Cb is charged to the Vdd potential, and the output terminal of the boost voltage generator 1110 is discharged to ground. The grounding of the boost voltage output terminal of the boost voltage generator 1110 also turns off the FETs M215, M216, and M217.

[0095] When the non-complementary clock signal CLK and the complementary clock signal are high and low, respectively, the high non-complementary clock signal CLK turns on the FET M211 and couples the gate of M214 to the second terminal of the boost capacitor Cb (at node n2). This has the effect of turning on the FET M214. The Vdd at the first terminal of the boost capacitor Cb (at node n1) is routed to the gates of the FETs M215, M216, and M217 to turn on these FETs. The low complementary clock signal turns off the FET M213 to isolate the second terminal of the boost capacitor Cb (at node n2) from ground. The low complementary clock signal The discharge circuit 1120, the gate voltage boost circuit 1130, and the current injection circuit 1140 are also disabled. When the FET M216 is turned on, it routes the input voltage Vin to the second terminal of the boost capacitor Cb (at node n2), so that the boost voltage Vbst becomes the sum of Vdd and the input voltage Vin (e.g., each bootstrap switch operation). The turn-on of the FET M217 causes the input voltage Vin to be sampled and generates an output of the sampled voltage (Vsmpl).

[0096] Figure 12 A schematic / block diagram of another example boost converter 1200 according to another aspect of the present disclosure is shown. The boost converter 1200 may be similar to the boost converter 1000 and has another example detailed implementation of a boost voltage generator. Specifically, the boost converter 1200 includes a boost voltage generator 1210, an overvoltage protection field-effect transistor (FET) M121, a discharge circuit 1220, a gate voltage boost circuit 1230, and a current injection circuit 1240.

[0097] The boost voltage generator 1210 is configured to generate a boost voltage Vbst based on an input voltage Vin (e.g., according to a charge pump operation, where Vin is Vdd). The overvoltage protection FET M121 (e.g., an NMOS FET) includes a drain coupled to the output of the boost voltage generator 1210 (where the boost voltage Vbst is generated), a source coupled to the discharge circuit 1220, and a gate configured to receive a gate voltage Vg. The discharge circuit 1220 includes an FET M123 (e.g., a PMOS FET) serially coupled between the upper voltage rail Vdd and the lower voltage rail (e.g., ground) with an FET M122 (e.g., an NMOS FET). That is, the FET M123 includes a source coupled to the upper voltage rail Vdd, a gate configured to receive a complementary clock signal and a drain coupled to the drain of the FET M122 and the source of the overvoltage protection FET M121. The FET M122 includes a source coupled to the lower voltage rail and a gate configured to receive a complementary clock signal which serves as a discharge signal Vdsch as previously discussed.

[0098] The gate voltage boosting circuit 1230 includes a capacitor C0 coupled between the gate of FET M123 and the gate of overvoltage protection FET M121. Additionally, the gate voltage boosting circuit 1230 includes a resistor R0 coupled between the upper voltage rail Vdd and the gate of overvoltage protection FET M121. Further, the gate voltage boosting circuit 1230 includes a FET M124 (e.g., PMOS FET) coupled between the upper voltage rail Vdd and the gate of overvoltage protection FET M121. That is, FET M124 includes a source coupled to the upper voltage rail Vdd, a gate coupled to the output of the boost voltage generator 1210, and a drain coupled to the gate of overvoltage protection FET M121. The detailed operation of the gate voltage boosting circuit 1230 has been previously discussed with reference to the gate voltage boosting circuit 630 of the booster 600.

[0099] The current injection circuit 1240 includes a FET M125 (e.g., NMOS FET) that includes a drain coupled to the upper voltage rail Vdd, a gate coupled to the drain of overvoltage protection FET M121, and a source coupled to the source of overvoltage protection FET M121. FET M125 is configured to generate an injection current I inj (e.g., its drain-to-source current) based on the drain-to-source voltage Vds of overvoltage protection FET M121. The detailed operation of the current injection circuit 1240 has been previously discussed with reference to the current injection circuit 840 of the booster 800.

[0100] The boost voltage generator 1210 includes a first FET M220 (e.g., NMOS FET) and a first capacitor C1 coupled in series between the upper voltage rail Vdd and the input of a complementary clock signal The boost voltage generator 1210 further includes a second FET M221 (e.g., NMOS FET) and a second capacitor C2 coupled in series between the upper voltage rail Vdd and the output of an inverter 1232. The inverter 1232 includes an input configured to receive the complementary clock signal and thereby outputs a non-complementary clock signal CLK.

[0101] More specifically, the first FET M220 includes a source coupled to the upper voltage rail Vdd, a gate coupled to the first terminal of the second capacitor C2, and a drain coupled to the first terminal of the first capacitor C1. Similarly, the second FET M221 includes a source coupled to the upper voltage rail Vdd, a gate coupled to the first terminal of the first capacitor C1, and a drain coupled to the first terminal of the second capacitor C2. As described above, the first capacitor C1 includes a terminal coupled to the complementary clock signal the second terminal of the input of, and the second capacitor C2 includes a second terminal coupled to the output of the inverter 1232.

[0102] The boost voltage generator 1210 further includes a third FET M222 (e.g., a PMOS FET) that includes a source / drain coupled to the first terminal of the second capacitor C2, a gate coupled to the upper voltage rail Vdd, and a drain / source coupled to the first terminal (at the output of the boost voltage generator 1210) of the third capacitor C3. The third capacitor C3 includes a second terminal coupled to the lower voltage rail.

[0103] In operation, when the non-complementary clock signal CLK and the complementary clock signal are low (e.g., 0V) and high (e.g., Vdd), respectively, the discharge circuit 1220 discharges the output of the boost voltage generator 1210, while the gate boost circuit 1230 and the current injection circuit 1240 protect the overvoltage protection FET M121, as previously discussed. The high complementary clock signal is applied to the gate of the FET M221 via the first capacitor C1, and turns on the FET M221 to apply Vdd to the first terminal of the second capacitor C2. In addition, the low non-complementary clock signal CLK generated by the inverter 1232 applies the ground potential (0V) to the second terminal of the second capacitor C2. This charges the second capacitor C2 to approximately the Vdd potential. At this stage, the source-to-gate voltage Vsg of the FET M222 is substantially 0V; and thus it is turned off.

[0104] When the non-complementary clock signal CLK and the complementary clock signal are high and low, respectively, the low complementary clock signal turns off the FET M221, and the high non-complementary clock signal CLK generated by the inverter 1232 is applied to the second terminal of the second capacitor C2. This causes the voltage at the first terminal of the second capacitor C2 to substantially become 2Vdd. When the source-to-gate voltage Vsg of the FET M222 is now substantially Vdd, the FET M222 turns on and generates a boosted voltage Vbst across the third capacitor C3 (at the output of the boost voltage generator 1210). In addition, the low complementary clock signal also disables the discharge circuit 1220, the gate voltage boost circuit 1230, and the current injection circuit 1240.

[0105] Figure 13FIG. 1300 is a flowchart illustrating an example method 1300 for reducing a boost voltage at an output of a boost voltage generator according to another aspect of the present disclosure. Method 1300 includes discharging an output of the boost voltage generator via a first field effect transistor (FET) in response to a discharge signal becoming active (block 1310). An example of a unit for discharging an output of the boost voltage generator via a first field effect transistor (FET) in response to a discharge signal becoming active includes any of the discharge circuits described herein.

[0106] Method 1300 further includes boosting a gate voltage applied to a gate of the first FET in response to the active discharge signal (block 1320). An example of a unit for boosting a gate voltage applied to a gate of the first FET in response to the active discharge signal includes any of the gate boosting circuits described herein.

[0107] Figure 14 FIG. 1400 is a flowchart illustrating another example method 1400 for reducing a boost voltage at an output of a boost voltage generator according to another aspect of the present disclosure. Method 1400 includes discharging an output of the boost voltage generator via a first FET and a second FET in response to an active discharge signal applied to a gate of the second field effect transistor (FET) (block 1410). An example of a unit for discharging an output of the boost voltage generator via a first field effect transistor (FET) and a second FET in response to an active discharge signal includes any of the discharge circuits described herein.

[0108] Method 1400 further includes generating an injection current (block 1420). An example of a unit for generating an injection current includes any of the current injection circuits described herein. Additionally, method 1400 includes combining the injection current with a drain-to-source current of the first FET to form a discharge current through the second FET (block 1430). An example of a unit for combining the injection current with a drain-to-source current of the first FET to form a discharge current through the second FET includes any coupling of a current injection circuit with a corresponding overvoltage protection FET described herein.

[0109] Figure 15 FIG. 1500 is a block diagram illustrating an example wireless communication device 1500 according to another aspect of the present disclosure. The wireless communication device 1500 may be a smart phone, a desktop computer, a laptop computer, a tablet device, an Internet of Things (IoT), a wearable wireless device (e.g., a wireless watch), and other types of wireless devices.

[0110] Specifically, wireless communication device 1500 includes an integrated circuit (IC) 1510, which may be implemented as a system on a chip (SOC). IC 1510 includes one or more signal processing cores 1520, which are configured to generate transmit (Tx) baseband (BB) signals and process receive (Rx) baseband (BB) signals.

[0111] Wireless communication device 1500 may also include a transceiver 1550 and at least one antenna 1560 (e.g., an antenna array). Transceiver 1550 is coupled to one or more signal processing cores 1520 to receive Tx BB signals therefrom and provide Rx BB signals thereto. Transceiver 1550 is configured to convert the Tx BB signal into a transmit (Tx) radio frequency (RF) signal and convert the receive (Rx) RF signal into an Rx BB signal. More specifically, transceiver 1550 includes: a digital-to-analog converter (DAC) 1552, which is configured to convert the Tx BB signal into an analog signal; an analog-to-digital converter (ADC) 1556, which is configured to convert the RX BB signal into a digital signal using a boosted voltage generated by booster 1554 described herein; and a front end 1558, which is configured to up-convert the Tx BB signal to a Tx RF signal and down-convert the Rx RF signal to an Rx BB signal.

[0112] Transceiver 1550 is coupled to at least one antenna 1560 to provide thereto a Tx RF signal for electromagnetic radiation into the wireless medium for wireless transmission and to receive an Rx RF signal electromagnetically picked up by at least one antenna 1560 from the wireless medium.

[0113] An overview of aspects of the present disclosure is provided below:

[0114] Aspect 1: An apparatus, comprising: a boosted voltage generator configured to generate a boosted voltage at an output; a first field effect transistor (FET) including a drain / source terminal coupled to the output of the boosted voltage generator; a discharge circuit coupled to the source / drain terminal of the first FET, wherein the discharge circuit is configured to discharge the output of the boosted voltage generator via the first FET in response to a discharge signal becoming active; and a gate voltage boost circuit configured to generate a gate voltage for the gate of the first FET, wherein the gate voltage boost circuit is configured to boost the gate voltage in response to an active discharge signal.

[0115] Aspect 2: The apparatus according to aspect 1, wherein the gate voltage boost circuit includes a capacitor having a first terminal coupled to the gate of the first FET and a second terminal configured to receive the discharge signal.

[0116] Aspect 3: The apparatus according to aspect 1 or 2, wherein the discharge circuit includes a second FET, the second FET including a drain / source terminal coupled to the source / drain terminal of the first FET, a source / drain terminal coupled to a lower voltage rail, and a gate configured to receive the discharge signal.

[0117] Aspect 4: The apparatus according to aspect 3, wherein the discharge circuit further includes a third FET, the third FET including a source / drain terminal coupled to an upper voltage rail, a gate configured to receive the discharge signal, and a drain / source terminal coupled to the drain / source terminal of the second FET.

[0118] Aspect 5: The apparatus according to any one of aspects 1-4, wherein the gate voltage boosting circuit further includes a resistor coupled between the upper voltage rail and the gate of the first FET.

[0119] Aspect 6: The apparatus according to any one of aspects 1-5, wherein the gate voltage boosting circuit further includes a fourth FET, the fourth FET including a source / drain terminal coupled to the upper voltage rail, a gate coupled to the output of the boost voltage generator, and a drain / source terminal coupled to the gate of the first FET.

[0120] Aspect 7: The apparatus according to any one of aspects 1-6, wherein the gate voltage boosting circuit is further configured to: generate the gate voltage at a non-boost level when the discharge signal is deactivated.

[0121] Aspect 8: The apparatus according to any one of aspects 1-7, wherein the gate voltage boosting circuit includes a resistor coupled between the upper voltage rail and the gate of the first FET, wherein the non-boost level is substantially at the voltage at the upper voltage rail.

[0122] Aspect 9: The apparatus according to any one of aspects 1-8, wherein the gate voltage boosting circuit is configured to control the peak of the boosted gate voltage based on the boost voltage.

[0123] Aspect 10: The apparatus according to any one of aspects 1-9, wherein the boosted gate voltage includes a pulse, and wherein the gate voltage boosting circuit is configured to control the width of the pulse based on the boost voltage.

[0124] Aspect 11: The apparatus according to any one of aspects 1 - 10, wherein the gate voltage boost circuit includes: a capacitor including a first terminal configured to receive the discharge signal and a second terminal coupled to the gate of the first FET; and a second FET including a source / drain terminal coupled to an upper voltage rail, a gate coupled to the output of the boost voltage generator, and a drain / source terminal coupled to the gate of the first FET.

[0125] Aspect 12: The apparatus according to any one of aspects 1 - 11, further comprising a current injection circuit configured to inject current into the discharge circuit based on the drain - to - source voltage of the first FET.

[0126] Aspect 13: The apparatus according to any one of aspects 1 - 12, wherein the current injection circuit includes a second FET including a drain / source terminal coupled to an upper voltage rail, a gate coupled to the drain / source terminal of the first FET, and a source / drain terminal coupled to the source / drain terminal of the first FET.

[0127] Aspect 14: The apparatus according to any one of aspects 1 - 13, wherein the boost voltage generator includes a bootstrap switch boost converter.

[0128] Aspect 15: The apparatus according to any one of aspects 1 - 13, wherein the boost voltage generator includes a charge pump boost converter.

[0129] Aspect 16: A method for reducing a boost voltage at an output of a boost voltage generator, comprising: discharging the output of the boost voltage generator via a first field - effect transistor (FET) in response to a discharge signal becoming active; and boosting a gate voltage applied to the gate of the first FET in response to the active discharge signal.

[0130] Aspect 17: The method according to aspect 16, wherein boosting the gate voltage includes routing the active discharge signal to the gate of the first FET through a capacitor.

[0131] Aspect 18: The method according to aspect 16 or 17, wherein a resistor is coupled between an upper voltage rail and the gate of the first FET, and wherein the boosted gate voltage is higher than the voltage at the upper voltage rail.

[0132] Aspect 19: The method according to any one of aspects 16 - 18, further comprising controlling a peak of the boosted gate voltage.

[0133] Aspect 20: The method according to any one of aspects 16 - 19, wherein the boosted gate voltage includes pulses, and further includes controlling the width of the pulses.

[0134] Aspect 21: The method according to any one of aspects 16 - 20, further comprising: discharging the output of the boost voltage generator via a second FET in response to the active discharge signal; generating an injection current; and combining the injection current with the drain - to - source current of the first FET to form a discharge current through the second FET.

[0135] Aspect 22: The method according to aspect 21, wherein generating the injection current includes generating the injection current based on the drain - to - source voltage of the first FET.

[0136] Aspect 23: An apparatus, comprising: a boost voltage generator configured to generate a boosted voltage at an output; a first field - effect transistor (FET) including a drain / source terminal coupled to the output of the boost voltage generator; a discharge circuit coupled to the source / drain terminal of the first FET, wherein the discharge circuit is configured to discharge the output of the boost voltage generator via the first FET in response to a discharge signal becoming active; and a current injection circuit configured to generate a current and inject the current into the discharge circuit.

[0137] Aspect 24: The apparatus according to aspect 23, wherein the current injection circuit is configured to generate the current based on the drain - to - source voltage of the first FET.

[0138] Aspect 25: The apparatus according to aspect 23 or 24, wherein the discharge circuit is configured to generate a discharge current in response to the active discharge signal, and wherein the discharge current includes the sum of the drain - to - source current of the first FET and the current generated by the current injection circuit.

[0139] Aspect 26: The apparatus according to any one of aspects 23 - 25, wherein the current injection circuit includes a third FET, the third FET including a source / drain terminal coupled to an upper voltage rail, a gate coupled to the drain / source terminal of the first FET, and a source / drain terminal coupled to the source / drain terminal of the first FET.

[0140] Aspect 27: The apparatus according to any one of aspects 23 - 26, further comprising a gate voltage boost circuit configured to generate a gate voltage for the gate of the first FET, wherein the gate voltage boost circuit is configured to boost the gate voltage in response to an active discharge signal.

[0141] Aspect 28: A method for reducing the boosted voltage at the output of a boost voltage generator, comprising: discharging the output of the boost voltage generator via a first FET and the second FET in response to an active discharge signal applied to the gate of the second field effect transistor (FET); generating an injection current; and combining the injection current with the drain-to-source current of the first FET to form a discharge current through the second FET.

[0142] Aspect 29: The method according to aspect 28, wherein generating the injection current includes generating the injection current based on the drain-to-source voltage of the first FET.

[0143] Aspect 30: A wireless communication device, comprising: at least one antenna; a transceiver coupled to the at least one antenna, wherein the transceiver includes: a booster, which includes: a boost voltage generator configured to generate a boost voltage at an output, a first field effect transistor (FET) including a drain / source terminal coupled to the output of the boost voltage generator, a discharge circuit coupled to the source / drain terminal of the first FET, wherein the discharge circuit is configured to discharge the output of the boost voltage generator via the first FET in response to the discharge signal becoming active; and a gate voltage boost circuit configured to generate a gate voltage for the gate of the first FET, wherein the gate voltage boost circuit is configured to generate the gate voltage at a boosted level in response to the active discharge signal; and an analog-to-digital converter (ADC) configured to use the boost voltage; and an integrated circuit (IC) including one or more signal processing cores coupled to the transceiver.

[0144] Aspect 31: A wireless communication device, comprising: at least one antenna; a transceiver coupled to the at least one antenna, wherein the transceiver includes: a booster, which includes: a boost voltage generator configured to generate a boost voltage at an output, a first field effect transistor (FET) including a drain / source terminal coupled to the output of the boost voltage generator, a discharge circuit coupled to the source / drain terminal of the first FET, wherein the discharge circuit is configured to discharge the output of the boost voltage generator via the first FET in response to the discharge signal becoming active; and a current injection circuit configured to generate a current and inject the current into the discharge circuit, and an analog-to-digital converter (ADC) configured to use the boost voltage; and an integrated circuit (IC) including one or more signal processing cores coupled to the transceiver.

[0145] The foregoing description of the disclosure is provided to enable a person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the spirit or scope of the disclosure. Thus, the disclosure is not intended to be limited to the examples described herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. An apparatus, comprising: A boost voltage generator configured to generate a boost voltage at an output; A first field effect transistor (FET) including a drain / source terminal coupled to the output of the boost voltage generator; A discharge circuit coupled to the source / drain terminal of the first FET, wherein the discharge circuit is configured to discharge the output of the boost voltage generator via the first FET in response to a discharge signal becoming active; and A gate voltage boost circuit configured to generate a gate voltage for the gate of the first FET, wherein the gate voltage boost circuit is configured to boost the gate voltage in response to an active discharge signal.

2. The device according to claim 1, wherein The gate voltage boost circuit includes a capacitor having a first terminal coupled to the gate of the first FET and a second terminal configured to receive the discharge signal.

3. The device according to claim 2, wherein The discharge circuit includes a second FET having a drain / source terminal coupled to the source / drain terminal of the first FET, a source / drain terminal coupled to a lower voltage rail, and a gate configured to receive the discharge signal.

4. The device according to claim 3, wherein, The discharge circuit further includes a third FET having a source / drain terminal coupled to an upper voltage rail, a gate configured to receive the discharge signal, and a drain / source terminal coupled to the drain / source terminal of the second FET.

5. The device according to claim 2, wherein The gate voltage boost circuit further includes a resistor coupled between the upper voltage rail and the gate of the first FET.

6. The device according to claim 5, wherein, The gate voltage boost circuit further includes a fourth FET having a source / drain terminal coupled to the upper voltage rail, a gate coupled to the output of the boost voltage generator, and a drain / source terminal coupled to the gate of the first FET.

7. The apparatus according to claim 1, wherein The gate voltage boost circuit is further configured to: generate the gate voltage at a non-boost level when the discharge signal is deactivated.

8. The apparatus according to claim 7, wherein The gate voltage boost circuit includes a resistor coupled between the upper voltage rail and the gate of the first FET, wherein the non-boost level is substantially at the voltage at the upper voltage rail.

9. The device according to claim 1, wherein The gate voltage boost circuit is configured to control a peak of the boosted gate voltage based on the boost voltage.

10. The apparatus according to claim 9, wherein, The boosted gate voltage includes a pulse, and wherein the gate voltage boost circuit is configured to control a width of the pulse based on the boost voltage.

11. The device according to claim 9, wherein The gate voltage boost circuit includes: A capacitor having a first terminal configured to receive the discharge signal and a second terminal coupled to the gate of the first FET; and A second FET having a source / drain terminal coupled to the upper voltage rail, a gate coupled to the output of the boost voltage generator, and a drain / source terminal coupled to the gate of the first FET.

12. The apparatus according to claim 1, further comprising a current injection circuit configured to inject current into the discharge circuit based on a drain-to-source voltage of the first FET.

13. The apparatus according to claim 12, wherein, The current injection circuit includes a second FET, the second FET including a drain / source terminal coupled to an upper voltage rail, a gate coupled to the drain / source terminal of the first FET, and a source / drain terminal coupled to the source / drain terminal of the first FET.

14. The device according to claim 1, wherein, The boost voltage generator includes a bootstrap switch booster.

15. The apparatus according to claim 1, wherein the boost voltage generator includes a charge pump booster.

16. A method for reducing a boost voltage at an output of a boost voltage generator, comprising: discharging the output of the boost voltage generator via a first field effect transistor (FET) in response to a discharge signal becoming active; and boosting a gate voltage applied to the gate of the first FET in response to the active discharge signal.

17. The method according to claim 16, wherein Boosting the gate voltage includes routing the active discharge signal to the gate of the first FET through a capacitor.

18. The method according to claim 16, wherein, A resistor is coupled between the upper voltage rail and the gate of the first FET, and wherein the boosted gate voltage is higher than the voltage at the upper voltage rail.

19. The method according to claim 16, further comprising controlling a peak value of the boosted gate voltage.

20. The method according to claim 16, wherein, The boosted gate voltage includes a pulse, and further includes controlling a width of the pulse.

21. The method according to claim 16, further comprising: discharging the output of the boost voltage generator via a second FET in response to the active discharge signal; generating an injection current; and combining the injection current with a drain-to-source current of the first FET to form a discharge current through the second FET.

22. The method according to claim 21, wherein Generating the injection current includes generating the injection current based on a drain-to-source voltage of the first FET.

23. An apparatus, comprising: a boost voltage generator configured to generate a boost voltage at an output; a first field effect transistor (FET) including a drain / source terminal coupled to the output of the boost voltage generator; a discharge circuit coupled to the source / drain terminal of the first FET, wherein the discharge circuit is configured to discharge the output of the boost voltage generator via the first FET in response to a discharge signal becoming active; and a current injection circuit configured to generate a current and inject the current into the discharge circuit.

24. The apparatus according to claim 23, wherein, The current injection circuit is configured to generate the current based on a drain-to-source voltage of the first FET.

25. The device according to claim 23, wherein, The discharge circuit is configured to generate a discharge current in response to an active discharge signal, and wherein the discharge current includes a sum of a drain-to-source current of the first FET and the current generated by the current injection circuit.

26. The apparatus according to claim 23, wherein The current injection circuit includes a third FET, the third FET including a source / drain terminal coupled to an upper voltage rail, a gate coupled to the drain / source terminal of the first FET, and a source / drain terminal coupled to the source / drain terminal of the first FET.

27. The device according to claim 23 further includes a gate voltage boosting circuit configured to generate a gate voltage for the gate of the first FET, wherein, The gate voltage boosting circuit is configured to boost the gate voltage in response to an active discharge signal.

28. A method for reducing the boosted voltage at the output of a boost voltage generator, comprising: Discharging the output of the boost voltage generator via a first FET and the second FET in response to an active discharge signal applied to the gate of the second field effect transistor (FET); Generating an injection current; And Combining the injection current with the drain-to-source current of the first FET to form a discharge current through the second FET.

29. The method according to claim 28, wherein, Generating the injection current includes generating the injection current based on the drain-to-source voltage of the first FET.

30. A wireless communication device, comprising: At least one antenna; A transceiver coupled to the at least one antenna, wherein the transceiver includes: A voltage booster, comprising: A boost voltage generator configured to generate a boost voltage at an output, A first field effect transistor (FET) including a drain / source terminal coupled to the output of the boost voltage generator, A discharge circuit coupled to the source / drain terminal of the first FET, wherein the discharge circuit is configured to discharge the output of the boost voltage generator via the first FET in response to the discharge signal becoming active; and A gate voltage booster circuit configured to generate a gate voltage for the gate of the first FET, wherein The gate voltage booster circuit is configured to generate the gate voltage at a boosted level in response to the active discharge signal; and An analog-to-digital converter (ADC) configured to use the boost voltage; and An integrated circuit (IC) including one or more signal processing cores coupled to the transceiver.

31. A wireless communication device, comprising: At least one antenna ； A transceiver coupled to the at least one antenna, wherein the transceiver includes: A voltage booster, comprising: A boost voltage generator configured to generate a boost voltage at an output terminal, A first field effect transistor (FET) including a drain / source terminal coupled to the output of the boost voltage generator, A discharge circuit coupled to the source / drain terminal of the first FET, wherein the discharge circuit is configured to discharge the output of the boost voltage generator via the first FET in response to the discharge signal becoming active; and A current injection circuit configured to generate a current and inject the current into the discharge circuit, and An analog-to-digital converter (ADC) configured to use the boost voltage; and An integrated circuit (IC) including one or more signal processing cores coupled to the transceiver.

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