Method and device for random analog-to-digital conversion

Abstract

An analog-to-digital converter has an input, a plurality of quantizers, a plurality of feedback loops, and a plurality of filters. The input is configured to receive an input signal. The plurality of quantizers has an Nth quantizer, and the Nth quantizer has an Nth quantizer input and an Nth quantizer output. The input end of the Nth quantizer is connected to the input end. The plurality of feedback loops has an Nth feedback loop, and the Nth feedback loop is formed around the Nth quantizer output and the Nth quantizer input, and is configured to reduce a difference between a signal of the Nth quantizer output and an Nth reference signal at an Nth frequency region. The plurality of filters has an Nth filter. The Nth filter is configured to select an Nth frequency region. The feedback loop provides a method of controlling the influence of some non-ideal factors, such as comparator offset.

Description

Technical Field

[0001] The present invention generally relates to electrical systems and electronic devices, and more particularly to analog-to-digital signal conversion systems and devices. Background Art

[0002] One type of stochastic analog-to-digital converter (ADC) uses the offset of a comparator that acts as a single-bit quantizer as a reference to achieve multi-bit quantization. For example, a comparator-offset-based stochastic ADC is described by T. Sundstrom and A. Alvandpour in the paper "Utilizing Process Variations for Reference Generation in a Flash ADC", which was published in IEEE Transactions on Circuits and Systems II: Express Briefs, Vol. 56, No. 5, pp. 364-368, May 2009, doi: 10.1109 / TCSII.2009.2019165. Using the comparator offset as a reference allows for the use of smaller-sized transistors for the comparator, which is beneficial for increasing the speed of the comparator and reducing its power consumption. At the same time, the mismatch of the comparator offset usually has a Gaussian distribution and is thus determined only in a random manner. Since the references are not linearly spaced, this type of stochastic ADC generally exhibits poor linearity. In addition, since the setting of the comparator offset is determined randomly, the linearity performance is greatly reduced when a set of unfavorable comparator offsets is encountered. A similar type of stochastic ADC can be seen in U.S. Patent No. US2022 / 0140835 A1 (U.S. Patent Application Serial No. 17 / 431,888), where a structure with feedback is employed to reduce the large signal swing at the input of the comparator array. U.S. Patent No. US 7,564,391 B2 discloses an ADC designed to handle large comparator offsets and also uses a feedback loop.

[0003] Another type of stochastic ADC is implemented by introducing a dither signal as the comparator's reference. For example, this type of stochastic ADC was demonstrated by J.L. Ceballos, I. Galton, and G.C. Temes in the paper "Stochastic analog-to-digital conversion", which was published in the 48th Midwest Symposium on Circuits and Systems in 2005, pages 855 - 858, Volume 1, doi: 10.1109 / MWSCAS.2005.1594236. Although its statistical properties are predefined, the dither signal is not constant and is determined only in a random manner. It is well known that linearity can be improved by using dither instead of comparator offset as the reference, as shown by H. Sun, K. Sobue, K. Hamashita, and U.-K. Moon in the paper "An Oversampling Stochastic ADC Using VCO-Based Quantizers", which was published in the IEEE Transactions on Circuits and Systems I: Regular Papers, Volume 65, Issue 12, pages 4037 - 4050, December 2018, doi: 10.1109 / TCSI.2018.2836466. However, when using this type of stochastic ADC, the comparator offset must be small enough not to interfere with the dither. Due to this limitation, it is difficult to obtain the advantages brought by a comparator made of small transistors when using a stochastic ADC that utilizes dither. The US patent with publication number US 7,420,494 B1 also discloses a ΣΔ ADC that uses a stochastic ADC that utilizes a dither signal. Summary of the Invention

[0004] An ADC according to the disclosed technology has an input terminal, a plurality of quantizers, a plurality of feedback loops, and a plurality of filters. The input terminal is configured to receive an input signal. The plurality of quantizers has an Nth quantizer, and the Nth quantizer has an Nth quantizer input terminal and an Nth quantizer output terminal. The Nth quantizer input terminal is connected to the input terminal. N is an integer greater than or equal to 1 and less than or equal to M, and M is an integer greater than or equal to 2. The plurality of feedback loops has an Nth feedback loop, and the Nth feedback loop is formed around the Nth quantizer output terminal and the Nth quantizer input terminal and is configured to reduce the difference between the signal at the Nth quantizer output terminal and the Nth reference signal in the Nth frequency region. The plurality of filters has an Nth filter, and the Nth filter is arranged on the Nth feedback loop but not on any path that forwards the input signal from the input terminal to the Nth quantizer input terminal. The Nth filter is configured to select the Nth frequency region.

[0005] Since the Nth feedback loop is configured to reduce the difference between the signal at the Nth quantizer output terminal and the Nth reference signal in the Nth frequency region, even when the signal at the Nth quantizer output terminal is affected by some non-ideal factors such as comparator offset, the signal at the Nth quantizer output terminal can be controlled by the Nth reference signal and the Nth feedback loop. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 is a schematic diagram of an ADC 1 according to a first embodiment.

[0007] Figure 2 is a flowchart showing a method for analog-to-digital conversion according to a first embodiment.

[0008] Figure 3 is a schematic diagram of an ADC 2 according to a second embodiment.

[0009] Figure 4 is a schematic diagram of an ADC 3 according to a third embodiment.

[0010] Figure 5 is a schematic diagram of a ΣΔ ADC 4 according to a fourth embodiment.

[0011] Figure 6 is a circuit diagram of a global DAC 403 according to a fourth embodiment.

[0012] Figure 7 is a schematic diagram of an ADC 6 according to an embodiment of the disclosed technology.

[0013] Figure 8 is a schematic diagram of a ΣΔ ADC 7 according to an embodiment of the disclosed technology. DETAILED DESCRIPTION

[0014] First Embodiment

[0015] Figure 1 The ADC 1 (an example of an analog-to-digital converter) in [the first embodiment] has an input terminal 10, an output terminal 11, a plurality of quantizers 12, a plurality of feedback loops 13, a plurality of filters 14, a plurality of summing units 15, an output stage 16, a plurality of digital-to-analog converters (DACs) 17, and a plurality of forward paths 18. The number of quantizers 12 is M, and M is an integer greater than or equal to 2. N is an integer greater than or equal to 1 and less than or equal to M. That is, 1 ≤ N ≤ M and 2 ≤ M.

[0016] The input terminal 10 (an example of an input terminal) is configured to receive an analog signal to be converted into a corresponding digital signal. The analog signal may be a continuous or discrete signal. For example, when there is an analog signal that is sampled and held in a certain clock cycle, the sampled and held signal is discrete but still an analog signal. The output terminal 11 is a terminal or a plurality of terminals configured to output a digital signal. The plurality of quantizers 12 (an example of a plurality of quantizers) includes a first to an M-th quantizer. That is, the first quantizer 120b, the N-th quantizer 120a (an example of the N-th quantizer), and the M-th quantizer 120c are all included in the plurality of quantizers 12. In the present embodiment, each quantizer in the plurality of quantizers 12 is a single-bit quantizer. The N-th quantizer 120a has an N-th quantizer input terminal 121a (an example of an N-th quantizer input terminal) and an N-th quantizer output terminal 122a (an example of an N-th quantizer output terminal). The N-th quantizer input terminal 121a is connected to the input terminal 10 via a summing unit 15a. The first quantizer 120b has a first quantizer input terminal 121b and a first quantizer output terminal 122b respectively, and the M-th quantizer 120c has an M-th quantizer input terminal 121c and an M-th quantizer output terminal 122c respectively. The plurality of quantizers 12 quantize the signal at the quantizer input terminal in each clock cycle determined by the clock signal. The output signals of the plurality of quantizers 12 are binary. At the N-th quantizer 120a, if the input signal at the N-th quantizer input terminal 121a is greater than a specific threshold (i.e., a reference), then the signal at the N-th quantizer output terminal 122a is a high value, otherwise the output signal takes a low value. The other quantizers work in the same way. In the present embodiment, the thresholds of the plurality of comparators 12 are nominally zero, but it is assumed that the thresholds are different from each other due to random offsets. The plurality of feedback loops 13 (an example of a plurality of feedback loops) includes a first feedback loop 13b to an M-th feedback loop 13c. The N-th feedback loop 13a (an example of the N-th feedback loop) is formed around the N-th quantizer output terminal 122a and the N-th quantizer input terminal 121a, and is configured to reduce the difference between the signal at the N-th quantizer output terminal 122a and the N-th reference signal 19a (an example of the N-th reference signal) in a low-frequency region (an example of the N-th frequency region). The N-th feedback loop 13a in the present embodiment includes the N-th quantizer 120a, the N-th DAC 17a, the N-th filter 14a, and the N-th summing unit 15a. The first feedback loop 13b to the M-th feedback loop 13c are all formed in substantially the same way as the N-th feedback 13a. The plurality of filters 14 (an example of a plurality of filters) includes a first filter 14b to an M-th filter 14c. The N-th filter 14a (an example of the N-th filter) is arranged on the N-th feedback loop 13a and placed between the N-th quantizer output terminal 122a and the N-th quantizer input terminal 121a.The Nth filter 14a is not on either the forward path 18a or any other path that forwards the input signal from the input terminal 10 to the input terminal 121a of the Nth quantizer. The Nth filter 14a is configured to select the Nth frequency region. More specifically, the Nth filter 14a in this embodiment is a low-pass filter, such that the feedback loop 13a operates to reduce the difference between the single-bit output signal at the output terminal 122a of the Nth quantizer and the Nth reference signal 19a in the low-frequency region. The gain of the Nth filter 14a is high at low frequencies and low in other frequency regions, thereby selecting the low-frequency region. In this embodiment, the first filter 14b to the Mth filter 14c are also low-pass filters and are respectively associated with the first feedback loop 13b to the Mth feedback loop 13c. They are respectively arranged in substantially the same manner as the Nth filter 14a with respect to the first reference signal 19b to the Mth reference signal 19c. The plurality of summing units 15 (an example of a plurality of summing units) includes the first summing unit 15b to the Mth summing unit 15c. The Nth summing unit 15a (an example of the Nth summing unit) is arranged on the Nth feedback loop 13a and is configured to provide the difference between the signal at the input terminal 10 (an example of an input signal and an analog signal) and the signal from the Nth filter 14a to the input terminal 121a of the Nth quantizer. At the Nth summing unit 15a, the signal from the Nth filter 14a is subtracted from the signal at the input terminal 10, and thus the Nth feedback loop 13a is closed here. A summing amplifier or a transconductance stage can be used to implement the Nth summing unit 15a. The Nth summing unit 15a can also be constructed as part of a comparator, as shown in U.S. Patent Publication No. 2022 / 0140835A1. The first summing unit 15b to the Mth summing unit 15c are respectively arranged in substantially the same manner as the Nth summing unit 15a with respect to the signals from the first filter 14b to the Mth filter 14c. The output stage 16 connects the first to the Mth quantizer output terminals and the output terminal 11 and is configured to generate the output signal of the ADC 1. More specifically, the output stage 16 in this embodiment averages the signals at the first to the Mth quantizer output terminals to produce a signal as the output signal at the output terminal 11. In this embodiment, the signals at the first to the Mth quantizer output terminals are single-bit signals, and these signals are averaged in the digital domain. As a result, an output signal as a digital signal is obtained. The plurality of DACs 17 includes the first DAC 17b to the Mth DAC 17c. Each DAC in the plurality of DACs 17 is a single-bit DAC and can be implemented using known topologies, such as a current-steering DAC and a resistor DAC.

[0017] Figure 1The signal flow of the ADC 1 is also shown. The ADC 1 has a plurality of forward paths 18 configured to connect the input terminal 10 and the output terminal 11. The plurality of forward paths 18 includes a first forward path 18b to an Mth forward path 18c. An Nth quantizer 120a is on the Nth forward path 18a (an example of a path that forwards an input signal from the input terminal to the input of the Nth quantizer), a first quantizer 120b is on the first forward path 18b, an Mth quantizer 120c is on the Mth forward path 18c, and so on. The plurality of quantizers 12 are connected in parallel to the input terminal 10 along the plurality of forward paths 18, and the signal at the input terminal 10 is individually quantized by the plurality of quantizers 12. The signal at the output terminal 122a of the Nth quantizer is converted into an analog signal by the Nth DAC 17a, and then the Nth reference signal 19a is subtracted from the output signal of the Nth DAC 17a. The difference signal between the signal at the output terminal 122a of the Nth quantizer and the Nth reference signal 19a is filtered by a filter 14a and processed again by the Nth quantizer 120a. This signal flow around the output terminal 122a and the input terminal 121a of the Nth quantizer constitutes the Nth feedback loop 13a, which operates to reduce the difference between the signal at the output terminal 122a of the Nth quantizer and the Nth reference signal 19a at a frequency region determined by the Nth filter 14a. In the present embodiment, the Nth filter 14a is not on the Nth forward path 18a. The loop gain of the Nth feedback loop 13a is provided by the Nth quantizer 120a and / or the filter 14a.

[0018] Since in the present embodiment, each of the plurality of quantizers 12 is a single-bit quantizer, the plurality of quantizers 12 can be implemented by comparators. Transistors are generally used to construct comparators, and current semiconductor technologies are used to implement transistors and other electronic components. The threshold voltage of a comparator usually has a random offset or displacement relative to a target value, which is caused by process variations due to limitations in the accuracy of semiconductor manufacturing processes. Due to this offset, even if exactly the same input signal is input to the quantizer array, the quantization results among the quantizers may be different from each other. In the ADC 1, the influence of the offset on the quantization at the Nth quantizer 120a is controlled by the feedback loop 13a.

[0019] Figure 2FIG. is a flowchart of a method of converting an analog signal into a digital signal using the techniques disclosed herein. In step S1001, an input terminal 10 receives an analog signal. In step S1002, a plurality of quantizers 12 perform quantization. In step S1003, using an Nth feedback loop 13a formed around an Nth quantizer output terminal 122a and an Nth quantizer input terminal 121a, a difference between a signal at the Nth quantizer output terminal 122a and an Nth reference signal 19a is reduced in an Nth frequency region. In step S1004, an Nth filter 14a disposed on the Nth feedback loop 13a and placed between the Nth quantizer output terminal 122a and the Nth quantizer input terminal 121a selects the Nth frequency region. It should be noted that since the Nth filter 14a is on the Nth feedback loop 13a, S1003 and S1004 are generally completed in one process. In step S1005, a difference between a signal at the input terminal 10, i.e., the analog signal to be converted, and a signal from the Nth filter 14a is provided to the Nth quantizer input terminal 121a via an Nth summing unit 15a disposed on the Nth feedback loop 13a. In step S1001, the Nth quantizer 120a performs quantization on the signal provided via the Nth summing unit 15a.

[0020] Second Embodiment

[0021] Figure 3 FIG. shows an ADC 2 (an example of an analog-to-digital converter) according to the second embodiment. The ADC 2 has an input terminal 20 (an example of an input terminal), an output terminal 21, and the same components as the ADC 1, and these same components are denoted by the same reference numerals as in the ADC 1. Only the parts different from the ADC 1 will be described in detail. The ADC 2 has a DAC 22 (an example of a signal converter), and the DAC 22 is configured to convert signals at first to Mth quantizer output terminals into an analog signal (an example of a conversion signal). The signals at the first to Mth quantizer output terminals are averaged when being converted into an analog signal by the DAC 22. More specifically, the signals at the first quantizer output terminal 122b to the Mth quantizer output terminal 122c are added and divided by M. The averaging process in this embodiment is mainly performed in the analog domain, i.e., after digital-to-analog conversion, but it can be performed in the digital domain or using both the digital domain and the analog domain simultaneously. The analog signal formed by converting the signals at the first to Mth quantizer output terminals is used as the Nth reference signal 29a and all other reference signals. This means that the first reference signal 29b to the Mth reference signal 29c are all common conversion analog signals.

[0022] As described above, due to the offset mismatches of the multiple quantizers 12, the signals at the outputs of the first through M quantizers tend to be different from each other. The first through M feedback loops generate driving forces to reduce the differences between these signals at the outputs of the first through M quantizers. For example, the input offset of the comparator used as the Nth quantizer 120a is quantizer-specific and always provides the same offset to the input signal at the input terminal 121a of the Nth quantizer when the Nth feedback loop 13a is not in use. The Nth feedback loop 13a operates such that the effect of the offset of the Nth quantizer 120a is equalized to the effect of the offsets of the other quantizers at the Nth frequency region selected by the Nth filter 14a. Due to this action, the effect of the offset of the Nth quantizer 120a is distributed to and scrambled by the other quantizers, making the offset look like a random pseudo-dither signal.

[0023] Third Embodiment

[0024] Figure 4 FIG. 7 shows an ADC 3 (an example of an analog-to-digital converter) according to the third embodiment. The ADC 3 has an input terminal 30 (an example of an input terminal), an output terminal 31, and the same components as those of the ADC 1, and these same components are denoted by the same reference numerals as those in the ADC 1. Although the clock signal is omitted in Figure 4 , quantization is regulated by a clock signal as in the previous embodiments. The ADC 3 represents the case where M is 4. In the ADC 3, the reference signal is the signal at one of the output terminals of the other quantizers or a delayed version thereof. More specifically, the Nth reference signal 39a is the signal at the output terminal 122b of the first quantizer. At the same time, the first reference signal 39b is the signal at the output terminal 122c of the Mth quantizer. Similarly, the Mth reference signal 39c is the signal at the output terminal of the adjacent quantizer.

[0025] Since the signals at the quantizer output terminals are used as reference signals for another feedback loop in a cyclic manner, the effects of the offsets of the multiple quantizers 12 are driven to be evenly distributed at the frequency regions selected by the filter 14. As a result, the effects of the offsets originally specific to the quantizers are scrambled, making them look like random pseudo-dither signals in the ADC 2.

[0026] Fourth Embodiment

[0027] Figure 5FIG. 0 shows a ΣΔADC 4 (an example of a ΣΔ analog-to-digital converter) according to a fourth embodiment. The ΣΔ ADC 4 has an ADC 2 according to the second embodiment, a global input terminal 401, a global output terminal 402, a global DAC 403, a global summing unit 404, a loop filter 405, and a fast path 406. The global input terminal 401 (an example of a global input terminal) is configured to receive an analog signal to be converted into a corresponding digital output signal. The global output terminal 402 is connected to the output terminal 21 of the ADC 2 and is configured to output a digital output signal. The global DAC 403 (an example of a global digital-to-analog converter) is configured to generate a feedback signal in response to signals at the output terminals of a plurality of quantizers 12. More specifically, the signals at the first quantizer output terminal 122b to the M-th quantizer output terminal 122c are converted into analog signals and averaged by the global DAC 403. The global DAC 403 may include a signal delay, which accounts for a part of the additional loop delay of the ΣΔADC 4. The additional loop delay includes delays during the quantization process by the plurality of quantizers 12, during signal buffering, and during digital-to-analog conversion, and also includes delays sometimes intentionally added. The fast path 406 is added to compensate for the additional loop delay. The global summing unit 404 (an example of a global summing unit) is connected to the global input terminal 401 and is configured to provide the difference between the signal at the global input terminal 401, i.e., the global input signal, and the feedback signal generated by the global DAC 403. The global summing unit 404 is implemented as, for example, a part of the first integrator in the loop filter 405. The loop filter 405 responds to the global summing unit 404 and is connected between the global summing unit 404 and the input terminal 20 of the ADC 2. The loop filter 405 is used to define the signal frequency band of the ΣΔADC 4. The loop filter 405 is also used to provide the loop gain of the ΣΔADC 4, but alternatively it may be a passive loop filter. The topology of the loop filter 405 is, for example, an integrator cascade feedback / feedforward form, a resonator cascade feedback / feedforward form, or a hybrid thereof.

[0028] A DAC having unary elements can be used to implement as Figure 6The global DAC 403 therein. In this embodiment, the global DAC 403 is a current-steering DAC, where M elements of the same size (i.e., current-steering units) are arranged, and where the on and off states of the elements are controlled by the output signals of a plurality of quantizers 12. The signals from the first quantizer output 122b to the M-th quantizer output 122c are applied to the switches of the corresponding current-steering units of the global DAC 403 without being encoded or decoded. The currents of the elements of the global DAC 403 are collected at the resistors, and the output voltages are obtained as differential signals at the DAC outputs 403a and 403b. The currents of the elements of the global DAC 403 are generally different from each other because the current sources forming each element are not exactly the same due to variations in conditions such as process, bias voltage, and temperature. Variations in the elements of the feedback DAC in the ΣΔ modulator often degrade the linear performance of the DAC. In the ADC 2, the N-th feedback loop 13a is formed around the N-th quantizer output 122a and the N-th quantizer input 121a and is configured to reduce the difference between the signal at the N-th quantizer output 122a and the N-th reference signal 29a at the N-th frequency region selected by the N-th filter 14a. In addition, the ADC 2 has a DAC 22 that is configured to convert the signals at the first to the M-th quantizer outputs into conversion signals, and the N-th reference signal 29a is the conversion signal. This configuration helps the signals from the first quantizer output 122b to the M-th quantizer output 122c to become the same at the frequency regions (low-frequency regions in this embodiment) selected by the plurality of filters 14. This means that the elements of the global DAC 403 are driven by input signals that are similar to each other at the low-frequency regions. Therefore, the variations between the elements of the DAC 403 are averaged according to the frequency characteristics of the N-th filter 14a (1 ≤ N ≤ M), and the degradation of the linearity of the ΣΔ ADC 4 is alleviated. In other words, mismatch shaping is achieved using the ΣΔ ADC 4. Regardless of the type of the DAC 403, the advantages brought by the mismatch shaping of the ADC 4 can be obtained, and other types of DACs (such as resistor DACs and capacitor DACs) can be used for the DAC 403.

[0029] The ADC 2 for the ΣΔADC 4 has an Nth filter 14a. The Nth filter 14a is not connected in series or in cascade with the loop filter 405. In other words, the Nth filter 14a and the loop filter 405 are not on a common forward path starting from the global input terminal 401 and ending at the global output terminal 402. More specifically, the Nth summing section 15a is arranged on the Nth feedback loop 13a and is configured to provide the difference between the signal at the input terminal 20 of the ADC 2 and the signal from the Nth filter 14a to the Nth quantizer input terminal 121a. The Nth summing section 15a is on the forward path, the loop filter 405 is arranged on the forward path, and the Nth filter 14a is on the Nth feedback loop 13a but before the Nth summing section 15a, so the Nth filter 14a is not on the forward path of the ΣΔADC 4. When both the Nth filter 14a and the loop filter 405 are on the same forward path, the influence of the Nth filter 14a on the noise transfer function of the ΣΔADC 4 becomes larger, which in turn tends to reduce the stability of the ΣΔADC 4. However, with the ADC 2, since the Nth filter 14a is not arranged in cascade with the loop filter 405, the reduction in stability is suppressed.

[0030] Other embodiments

[0031] The structure of the present invention is not limited to the previously described embodiments herein, and can be changed as long as the same object expected by the present invention can be achieved. The following are some other possible variations and examples of the embodiments.

[0032] The Nth filter 14a is not limited to a low-pass filter, and it can be other types of filters, such as band-pass and lead-lag filters. In addition, the frequency bands of the first filter 14b to the Mth filter 14c do not necessarily have to be the same, and they can be different from each other. For example, when the plurality of filters 14 are low-pass filters such as single-pole amplifiers, these poles define the first to Mth frequency regions. In this case, the positions of the poles of the first to Mth filters can be the same, but they can also be selected to be different from each other. As in Figure 7In the ADC 6 shown, a replica of the N-th filter 14a can be used for the N-th reference signal 19a. The ADC 6 has a filter 601 that replicates the N-th filter 14a (an example of a unit configured to select the N-th frequency region of the N-th reference signal instead of the N-th filter), which allows the summing point of the signal to be moved to the output of the N-th filter 14a. The filter 601 does not have to exactly match the N-th filter 14a. For example, the filter 601 may have poles and / or zeros different from those of the N-th filter 14a. The N-th quantizer 120a is not limited to a single-bit quantizer, and a multi-bit quantizer may also be used because when the techniques disclosed herein are applied to a ΣΔ ADC having multiple multi-bit quantizers, mismatch shaping also occurs between the multi-bit quantizers, just as it does between single-bit quantizers. Although not explicitly shown in the drawings, the plurality of feedback loops 13 may include signal delays, which are interpreted as delays generated in stages such as the quantization process performed by the plurality of quantizers 12, signal buffering, and digital-to-analog conversion performed by the plurality of DACs 17. In previous embodiments, the offset of the comparator caused by process variations was used to achieve multi-bit analog-to-digital conversion, but an offset may be intentionally added. The effects of these intentionally added offsets are equalized by the N-th feedback loop 13a (1 ≤ N ≤ M) in the same manner as the inherent comparator offset in the previous embodiments, and the intentionally added offsets may cause behavior similar to dithering. In the ADC 2 according to the second embodiment, the averaging process at the DAC 22 is performed using uniform weights, but the averaging process may also be performed using other types of weights (such as non-uniform weights). Here, the concept of averaging includes simple summation. The signals in the foregoing embodiments are not limited to voltages, and may also be other types of signals, such as currents, pulse widths, counts, phases, etc. It is also permissible to use a signal different from the foregoing embodiments as the N-th reference signal 19a. Figure 8 An example of a ΣΔ ADC 7 is shown. The ΣΔ ADC 7 has a global input terminal 701, a global output terminal 702, a sample-and-hold circuit 703, a delay 704, and an ADC 1. Components identical to those of the ΣΔ ADC 4 are denoted by the same reference numerals. The input signal of the global input terminal 701 is sampled and held by the sample-and-hold circuit 703, delayed by one sampling clock period at the delay 704, and then used as the first reference signal 19b to the M-th reference signal 19c.

[0033] Industrial Applicability

[0034] The techniques disclosed herein can be applied to analog-to-digital converters that require high-speed sampling.

Claims

1. An analog-to-digital converter, comprising: An input terminal configured to receive an input signal; A plurality of quantizers, having an Nth quantizer, the Nth quantizer having an Nth quantizer input terminal and an Nth quantizer output terminal, the Nth quantizer input terminal being connected to the input terminal, where N is an integer greater than or equal to 1 and less than or equal to M, and M is an integer greater than or equal to 2; A plurality of feedback loops, having an Nth feedback loop, the Nth feedback loop formed around the Nth quantizer output terminal and the Nth quantizer input terminal, and configured to reduce the difference between the signal at the Nth quantizer output terminal and the Nth reference signal in the Nth frequency region; And A plurality of filters, having an Nth filter, the Nth filter arranged on the Nth feedback loop but not on any path that forwards the input signal from the input terminal to the Nth quantizer input terminal, and the Nth filter being configured to select the Nth frequency region.

2. The analog-to-digital converter according to claim 1, wherein, The analog-to-digital converter further comprises: A signal converter configured to convert the signals at the first to Mth quantizer output terminals into a conversion signal, where the Nth reference signal is at least one of the conversion signal and a delayed version of the conversion signal.

3. The analog-to-digital converter according to claim 1, wherein, The analog-to-digital converter further comprises: A signal converter configured to convert the signals at the first to Mth quantizer output terminals into a conversion signal, where the Nth reference signal is at least one of the conversion signal and a delayed version of the conversion signal, wherein The signals at the first to Mth quantizer output terminals are averaged when being converted by the signal converter.

4. The analog-to-digital converter according to claim 1, wherein The Nth filter is a low-pass filter.

5. The analog-to-digital converter according to claim 1, wherein The Nth quantizer is a single-bit quantizer.

6. The analog-to-digital converter according to claim 1, wherein, The analog-to-digital converter further comprises a unit configured to select the Nth frequency region of the Nth reference signal instead of the Nth filter.

7. A ΣΔ analog-to-digital converter, comprising an analog-to-digital converter, a global input terminal, a global digital-to-analog converter, a global summing unit, and a loop filter, the analog-to-digital converter having: (a) An input terminal configured to receive an input signal; (b) A plurality of quantizers, having an Nth quantizer, the Nth quantizer having an Nth quantizer input terminal and an Nth quantizer output terminal, the Nth quantizer input terminal being connected to the input terminal, where N is an integer greater than or equal to 1 and less than or equal to M, and M is an integer greater than or equal to 2; (c) A plurality of feedback loops, having an Nth feedback loop, the Nth feedback loop formed around the Nth quantizer output terminal and the Nth quantizer input terminal, and configured to reduce the difference between the signal at the Nth quantizer output terminal and the Nth reference signal in the Nth frequency region; And (d) A plurality of filters, having an Nth filter, the Nth filter arranged on the Nth feedback loop, but not on any path that forwards the input signal from the input terminal to the Nth quantizer input terminal, and the Nth filter being configured to select the Nth frequency region, The global input terminal is configured to receive a global input signal, The global digital-to-analog converter is configured to generate a feedback signal in response to signals at the first to M quantizer output terminals, The global summing unit is configured to provide a difference between the global input signal and the feedback signal, The loop filter responds to the global summing unit and is connected between the global summing unit and the input terminal of the analog-to-digital converter.

8. The ΣΔ analog-to-digital converter according to claim 7, wherein, The ΣΔ analog-to-digital converter further includes: A signal converter configured to convert the signals at the first to M quantizer output terminals into converted signals, where the Nth reference signal is at least one of the converted signals and a delayed version of the converted signals.

9. The ΣΔ analog-to-digital converter according to claim 7, wherein, The ΣΔ analog-to-digital converter further includes: A signal converter configured to convert the signals at the first to M quantizer output terminals into converted signals, where the Nth reference signal is at least one of the converted signals and a delayed version of the converted signals, wherein, The signals at the first to M quantizer output terminals are averaged when being converted by the signal converter.

10. The ΣΔ analog-to-digital converter according to claim 7, wherein, The Nth filter is a low-pass filter.

11. The ΣΔ analog-to-digital converter according to claim 7, wherein, The Nth quantizer is a single-bit quantizer.

12. The ΣΔ analog-to-digital converter according to claim 7, wherein, The ΣΔ analog-to-digital converter further includes a unit configured to select the Nth frequency region of the Nth reference signal instead of the Nth filter.

13. A method for converting an analog signal into a digital signal, comprising the following steps: Receiving the analog signal using an input terminal; Performing quantization using a plurality of quantizers having an Nth quantizer, the Nth quantizer having an Nth quantizer input terminal and an Nth quantizer output terminal, the Nth quantizer input terminal being connected to the input terminal, N being an integer greater than or equal to 1 and less than or equal to M, and M being an integer greater than or equal to 2; Using an Nth feedback loop formed around the Nth quantizer output terminal and the Nth quantizer input terminal to reduce the difference between the signal at the Nth quantizer output terminal and the Nth reference signal at an Nth frequency region; And Selecting the Nth frequency region using an Nth filter arranged on the Nth feedback loop but not on any path that forwards the input signal from the input terminal to the Nth quantizer input terminal.

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