Method and device for correcting mask pattern and storage medium

Abstract

The embodiment of the invention provides a method and equipment for correcting a mask pattern and a storage medium. The method comprises the following steps: arranging at least one sub-resolution auxiliary graph (SRAF) adjacent to a target graph in a layout, wherein the target graph comprises at least one graph segment; and performing a first-stage optical proximity correction (OPC) on the target graph, wherein a relative position between a graph segment in the target graph and the one or more SRAFs associated with the graph segment remains unchanged during the first-stage OPC. In this way, the SRAF can be located at a proper position in the layout, so that maximization of a process window is ensured, and the yield of product design is improved.

Description

Technical Field

[0001] Embodiments of the present disclosure mainly relate to the field of semiconductor technology, and more particularly, to methods, devices, and storage media for correcting mask patterns. Background Art

[0002] Lithography is a key process in chip manufacturing. It aims to break through the hardware limitations of exposure size by improving resolution and other technologies under the condition that the existing hardware environment of lithography machines and other equipment remains unchanged, which has greatly promoted the development of semiconductor processes.

[0003] In lithography technology, sub-resolution assist feature (SRAF) is a special technical means. By placing patterns smaller than the minimum design rule around the design layout, the design layout can obtain higher signal contrast, and it itself will not be resolved onto the photoresist by the lithography process, so as to obtain a better process window. Summary of the Invention

[0004] In a first aspect of the present disclosure, a method for correcting a mask pattern is provided. The method includes: arranging at least one sub-resolution assist feature (SRAF) adjacent to a target pattern in a layout, where the target pattern includes at least one pattern segment; and performing a first-stage optical proximity correction (OPC) on the target pattern, wherein the relative positions between the pattern segments in the target pattern and one or more SRAFs associated with the pattern segments remain unchanged during the first-stage OPC correction.

[0005] In a second aspect of the present disclosure, an electronic device is provided. The electronic device includes a processor and a memory coupled to the processor. The memory has instructions stored therein, and when the instructions are executed by the processor, the electronic device is caused to execute the method according to the first aspect of the present disclosure.

[0006] In a third aspect of the present disclosure, a computer-readable storage medium is provided. A computer program is stored on the computer-readable storage medium. When the computer program is executed by a processor, the method according to the first aspect of the present disclosure is implemented.

[0007] It will be understood from the following description that, according to an embodiment of the present disclosure, at least one sub-resolution assist feature (SRAF) is arranged adjacent to a target pattern in a layout, and the target pattern includes at least one pattern segment. Further, a first-stage optical proximity correction (OPC) correction is performed on the target pattern, wherein the relative positions between the pattern segments in the target pattern and one or more SRAFs associated with the pattern segments remain unchanged during the first-stage OPC correction. In this way, the SRAF can be positioned appropriately in the layout, thereby ensuring the maximization of the process window and improving the yield of product design.

[0008] It should be understood that the content described in the present invention content section is not intended to limit the key features or important features of the embodiments of the present disclosure, nor is it used to limit the scope of the present disclosure. Other features of the present disclosure will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] In conjunction with the accompanying drawings and with reference to the following detailed description, the above and other features, advantages, and aspects of the embodiments of the present disclosure will become more apparent. In the drawings, the same or similar reference numerals denote the same or similar elements, where: Figure 1 A schematic diagram showing an example environment in which the embodiments of the present disclosure can be implemented; Figure 2 A flowchart showing a process for correcting a mask pattern according to some embodiments of the present disclosure; Figures 3A to 3G A schematic diagram showing an example layout at different stages in an OPC correction process according to some embodiments of the present disclosure; and Figure 4 A block diagram showing an electronic device in which one or more embodiments of the present disclosure can be implemented. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0010] Embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although some embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Instead, these embodiments are provided to more thoroughly and completely understand the present disclosure. It should be understood that the drawings and embodiments of the present disclosure are for exemplary purposes only and are not used to limit the protection scope of the present disclosure.

[0011] In the description of the embodiments of the present disclosure, the term "including" and its like shall be understood as an open inclusion, that is, "including but not limited to". The term "based on" shall be understood as "at least partially based on". The term "an embodiment" or "the embodiment" shall be understood as "at least one embodiment". The terms "first", "second", etc. may refer to different or the same objects. There may also be other explicit and implicit definitions hereinafter.

[0012] Various exemplary implementations of the solution will be described in detail below with reference to the accompanying drawings.

[0013] First, refer to Figure 1 , which shows a schematic diagram of an exemplary environment 100 in which the embodiments of the present disclosure can be implemented. As Figure 1 shown, the exemplary environment 100 generally may include an electronic device 110.

[0014] In some embodiments, the electronic device 110 may interact with other devices (not shown in the figure). For example, the electronic device 110 may receive input information from other devices and output feedback information to other devices. In some embodiments, the input information from other devices may be design layout data 120. The electronic device 110 may perform corresponding processing on the design layout data and output the corresponding processing result 130 to other devices. In some embodiments, the processing result may be the corrected layout data. In some embodiments, the processing of the layout data 120 may be based on Sub Resolution Assist Feature (SRAF).

[0015] In the exemplary environment 100, the electronic device 110 may be any type of computing device, including a terminal device or a server device. The terminal device may be any type of mobile terminal, fixed terminal or portable terminal, including a mobile phone, a desktop computer, a laptop computer, a notebook computer, a netbook computer, a tablet computer, a media computer, a multimedia tablet, a Personal Communication System (PCS) device, a personal navigation device, a Personal Digital Assistant (PDA), an audio / video player, a digital camera / video camera, a positioning device, a television receiver, a radio broadcast receiver, an e-book device, a gaming device, or any combination of the foregoing, including accessories and peripherals of these devices or any combination thereof. The server device may, for example, include a computing system / server, such as a mainframe, an edge computing node, a computing device in a cloud environment, and so on.

[0016] It should be understood that the structure and function of the environment 100 are described only for exemplary purposes and do not imply any limitation on the scope of the present disclosure. The exemplary embodiments according to the present disclosure will be described in detail below with reference to the accompanying drawings.

[0017] As briefly mentioned above, in lithography technology, by placing SRAFs around the design layout, a higher signal contrast can be obtained for the design layout, and the SRAFs themselves will not be resolved onto the photoresist by the lithography process, thus enabling a better process window. In the computational lithography correction process, before performing Optical Proximity Correction (OPC), SRAFs need to be inserted into the design layout.

[0018] However, during the subsequent OPC correction process, the positions of the SRAFs remain unchanged all the time, which will cause some problems. One problem is that the presence of SRAFs will, to a certain extent, limit the correction space of the design layout. For example, it will limit the correction space of the line segments in the design layout. Another problem is that when inserting SRAFs into the design layout, the rules are determined through simulation. However, after performing OPC correction on the design layout, the positions of the SRAFs determined through simulation will change.

[0019] To this end, embodiments of the present disclosure propose a scheme for correcting mask patterns. According to embodiments of the present disclosure, at least one sub-resolution assist feature (SRAF) is arranged adjacent to a target pattern in a layout, and the target pattern includes at least one pattern segment. Further, a first-stage Optical Proximity Correction (OPC) correction is performed on the target pattern. During the first-stage OPC correction, the relative positions between the pattern segments in the target pattern and one or more SRAFs associated with the pattern segments remain unchanged.

[0020] According to embodiments of the present disclosure, the SRAFs can be placed in appropriate positions in the layout, thereby effectively adjusting the local spatial frequency, compensating for the uneven light intensity distribution caused by diffraction loss, and significantly expanding the tolerance range of the photoresist exposure dose, that is, maximizing the process window. Further, the expansion of the process window directly reduces electrical failures such as short circuits and open circuits caused by lithography process deviations, thereby improving the yield of product design.

[0021] The following further describes various example implementations of this scheme in detail with reference to the accompanying drawings. Figure 2 FIG. 200 shows a flowchart of a process 200 for correcting mask patterns according to some embodiments of the present disclosure. In some embodiments, the process 200 can be executed by an electronic device 110 as shown in Figure 1 FIG. 201. It should be understood that the process 200 may further include additional blocks not shown and / or certain (or some) of the shown blocks may be omitted, and the scope of the present disclosure is not limited in this regard. The following describes the process 200 in detail with reference to Figure 1 FIG. 202, Figure 2 FIG. 203, Figures 3A to 3G and FIG. 204. Figures 3A to 3GFIG. 300 is a schematic diagram showing an example layout at different stages in an OPC correction process according to some embodiments of the present disclosure. It should also be understood that the layouts shown in the drawings are merely examples, and various layout designs may actually exist. Embodiments of the present disclosure are not limited in this regard.

[0022] At block 210, the electronic device 110 arranges at least one sub-resolution assist feature (SRAF) adjacent to a target pattern in the layout. The target pattern includes at least one pattern segment.

[0023] As described above, the electronic device 100 may process the layout. During the processing, the electronic device 110 may arrange at least one SRAF adjacent to the target pattern in the layout. In some embodiments, the process of the electronic device 110 processing the layout may include performing OPC correction on the target pattern. Before performing OPC correction on the layout, the electronic device 110 may arrange at least one SRAF adjacent to the target pattern according to existing rules or simulation results. In some embodiments, the electronic device 110 may determine a distance threshold in the layout according to existing rules or simulation results. Here, the distance threshold may be the distance of a position in the layout relative to the target pattern. Further, the electronic device 110 may determine the arrangement position of at least one SRAF in the layout according to the determined distance threshold. For example, the SRAF may be arranged within a range where the distance between the SRAF and the target pattern is less than or equal to the distance threshold. For another example, there may be multiple determined distance thresholds, and the SRAF may be arranged within a range or region determined by the maximum distance threshold and the minimum distance threshold among the multiple distance thresholds.

[0024] In Figure 3A the example of, the example layout 300 includes a target pattern 310, and the electronic device 110 may arrange SRAFs 321, 322, 323, 324, 325, and 326 adjacent to the target pattern 310. It should be understood that the SRAFs arranged adjacent to the target pattern 310 may include more or fewer SRAFs. Figure 3A The SRAFs shown are for illustrative purposes only and are not intended to limit the embodiments of the present disclosure.

[0025] In some embodiments, the electronic device 110 may segment the target pattern to divide the target image into multiple pattern segments. In Figure 3B the example of, the electronic device 110 may divide the target pattern 310 into pattern segments 311, 312, 313, and 314. It should be understood that the target pattern 310 may also be divided into more or fewer pattern segments. Figure 3B The segmentation results shown are for illustrative purposes only and are not intended to limit the embodiments of the present disclosure.

[0026] In some embodiments, the electronic device 110 may identify the divided graphic segments to distinguish different graphic segments. In Figure 3B the example, the electronic device 110 may use dashed lines to identify the graphic segments. It should be understood that other appropriate ways may also be adopted to identify the graphic segments, such as using different colors to identify different graphic segments. Figure 3B The shown identification method is only for illustrative purposes and is not intended to limit the embodiments of the present disclosure.

[0027] In some embodiments, the electronic device 110 may determine the association relationship between at least one graphic segment and at least one SRAF. Each graphic segment in the at least one graphic segment may be associated with one or more SARFs in the at least one SRAF.

[0028] In some embodiments, the electronic device 110 may associate each graphic segment in the at least one graphic segment with one or more SARFs in the at least one SRAF to determine the above-mentioned association relationship. When associating the graphic segment and the SRAF, the edge of the graphic segment may be associated with the SRAF.

[0029] Taking any edge of any graphic segment in the target graphic as an example. For the purpose of discussion, the any graphic segment and any edge here may be respectively referred to as the "first graphic segment" and the "first edge". For the first edge in the first graphic segment, the electronic device 110 may determine the SRAF adjacent to the first edge among the at least one SRAF and determine the association relationship between the first edge and the SRAF adjacent to the first edge. For example, the electronic device 110 may respectively determine the distances between each SRAF in the at least one SRAF and the first edge, and determine the SRAF with the closest distance as the SRAF adjacent to the first edge. For another example, the electronic device 110 may also sort the at least one SRAF according to the distances between each SRAF in the at least one SRAF and the first edge (for example, sort in ascending order of distance), and determine the SRAF adjacent to the first edge from the sorted at least one SRAF (for example, take multiple SRAFs with higher rankings).

[0030] In some embodiments, when determining the association relationship between the first edge and the SRAF adjacent to the first edge among the at least one SRAF, the electronic device 110 may project the first edge along a predetermined direction onto the SRAF adjacent to the first edge among the at least one SRAF, and determine the SRAF covered by the projection area generated by the association of the first edge to the first edge. The predetermined direction here may be any direction, and the embodiments of the present disclosure are not limited in this regard.

[0031] As an example, when associating the first side with the SRAF covered by the projection area generated by the first side, in response to the projection area covering one or more complete SRAFs, the electronic device 110 determines that the first side is associated with one or more complete SRAFs. In response to the projection area covering an SRAF segment in an SRAF, the electronic device 110 determines that the first side is associated with the SRAF segment.

[0032] In Figure 3C the example of, when the electronic device 110 projects the side of the graphic segment 312 onto the SRAF 324, the projection generated by the side of the graphic segment 312 covers the complete SRAF 324. In this case, the electronic device 110 can determine that the side of the graphic segment 312 is associated with the complete SRAF 324. When the electronic device 110 projects the graphic segment 313 onto the SRAF 322, the projection generated by the side of the graphic segment 313 covers a segment of the SRAF 322. In this case, the electronic device 110 can determine that the side of the graphic segment 313 is associated with the SRAF segment in the SRAF 322 covered by the projection.

[0033] As another example, in the case where the projection area generated by the first side covers one or more complete SRAFs or covers an SRAF segment in an SRAF, the electronic device 110 can determine any point or any points (e.g., the endpoints of the first side or points on the first side other than the endpoints) on the first side are associated with the one or more covered SRAFs or the segment in an SRAF.

[0034] In block 220, the electronic device 110 performs a first-stage OPC correction on the target graphic. During the first-stage OPC correction, the relative positions between the graphic segments in the target graphic and one or more SRAFs associated with the graphic segments remain unchanged. For example, the electronic device 110 can perform the first-stage OPC correction on the target graphic based on the above-mentioned association relationship.

[0035] During the OPC correction of the target graphic, the process of the OPC correction can include multiple OPC corrections. In some embodiments, the multiple OPC corrections can be divided into two-stage OPC corrections, namely the first-stage OPC correction and the second-stage OPC correction. In some embodiments, the accuracy of the first-stage OPC correction is lower than the accuracy of the second-stage OPC correction. In other words, the first-stage OPC correction can also be referred to as "coarse correction", and the second-stage OPC correction can also be referred to as "fine correction".

[0036] For example, the OPC correction process may include N OPC corrections. The first N - 3 OPC corrections are regarded as the first - stage OPC correction (i.e., rough correction), and the (N - 2)th, (N - 1)th, and Nth OPC corrections are regarded as the second - stage OPC correction (i.e., fine correction), where N≥20. It should be understood that the above - mentioned number of OPC corrections, the division method of OPC correction stages, and the number of OPC stages are only for illustrative purposes and are not intended to limit the embodiments of the present disclosure. There can actually be any combination method.

[0037] During the first - stage OPC correction, the relative positions between the graphic segments in the target graphic and one or more SRAFs associated with the graphic segment remain unchanged. In Figure 3C the example of, taking the first - stage OPC correction of graphic segments 312 and 313 as an example. During the first - stage OPC correction, the relative positions between the edge of graphic segment 312 and SRAF 324 and the relative positions between the edge of graphic segment 313 and the SRAF segment covered by the projection of the edge of graphic segment 313 in SRAF 322 are always kept unchanged, that is, the distances d1 and d2 remain unchanged. The corrected target graphic 310 is as Figure 3D shown. In Figure 3D when the electronic device 110 performs the first - stage OPC correction on the target graphic 310, the distances d1, d2, d3, d4, d5, d6, and d7 between each graphic segment and each SRAF in the target graphic 310 all remain unchanged.

[0038] In some embodiments, after the first - stage OPC correction is completed, to ensure compliance with the mask manufacturing rules, the electronic device 110 may process at least a part of at least one SRAF based on the layout of at least one SRAF in the layout. For example, merging and / or cleaning the fragmented SRAFs, so that the processed layout can comply with the mask manufacturing rules.

[0039] The method of processing at least a part of at least one SRAF may include removing the part where two adjacent SRAF points in at least one SRAF are in contact.

[0040] In Figure 3E the example of, the electronic device 110 may remove the contact parts of SRAF 321 and 322, the contact parts of SRAF 323 and 324, and the contact parts of SRAF 324 and 325.

[0041] The method of processing at least a part of at least one SRAF may include expanding the part where two adjacent SRAF points in at least one SRAF are in contact.

[0042] In Figure 3F the example of, the electronic device 110 may connect the point contact portions of SRAF 321 and 322, the point contact portions of SRAF 323 and 324, and the point contact portions of SRAF 324 and 325.

[0043] The manner of processing at least a part of at least one SRAF may include moving a first SRAF in two adjacent SRAFs in at least one SRAF to merge the two adjacent SRAFs, where the length of the first SRAF is less than the length of a second SRAF in the two adjacent SRAFs.

[0044] In Figure 3E the example of, the electronic device 110 may move the shorter one of SRAF 325 and 326, that is, move SRAF 326 to merge SRAF 325 and 326. In Figure 3F the example of, the electronic device 110 may move the shorter one of SRAF 325 and 326, that is, move SRAF 326 to merge SRAF 325 and 326.

[0045] The electronic device 110 may also move the shorter one of SRAF 325 and 326, that is, move SRAF 326 to merge SRAF 325 and 326.

[0046] It should be understood that the above processing of the SRAF is only for illustrative purposes and is not intended to limit the embodiments of the present disclosure. Other appropriate processing manners may actually be adopted.

[0047] In some embodiments, in response to the completion of the processing of at least one SRAF, the electronic device 110 performs a second-stage OPC correction on the target pattern, where the accuracy of the second-stage OPC correction is higher than that of the first-stage OPC correction. When performing the second-stage OPC correction on the target pattern, take any side of any graphic segment in the target pattern as an example. For the purpose of discussion, any graphic segment and any side here may be respectively referred to as the "second graphic segment" and the "second side". The electronic device 110 may determine at least one reference point on the second side and perform a second-stage OPC correction on the second side based on the at least one reference point.

[0048] In Figure 3GIn the example, a reference point 316 is set on an edge 315 of a graphic segment of a target graphic 310. During each OPC correction of the target graphic 310, by comparing the relevant parameter (e.g., light intensity) of the optical signal passing through the reference point 316 with a predetermined value, it is determined whether the correction of the target graphic 310 is completed. For example, if the relevant parameter of the reference point 316 meets the predetermined value, it is determined that the correction of the target graphic 310 is completed; otherwise, it is not completed. It should be understood that Figure 3G The positions and numbers of the reference points in the example are only for illustrative purposes and are not intended to limit the embodiments of the present disclosure. Actually, other numbers of reference points can also be set at other positions.

[0049] In some embodiments, during the OPC correction in the second stage, the relative positions between the graphic segments in the target graphic and the SRAFs associated with the graphic segments can also remain unchanged.

[0050] In summary, by using the above method to correct the mask graphic, the SRAF can be in a suitable position in the layout, thereby ensuring the maximization of the process window and improving the yield of product design.

[0051] Figure 4 The block diagram of an electronic device 400 in which one or more embodiments of the present disclosure can be implemented is shown. The electronic device 400 can be used, for example, to implement the electronic device 110 as shown in Figure 1 It should be understood that Figure 4 The electronic device 400 shown is only exemplary and should not constitute any limitation to the functions and scopes of the embodiments described herein.

[0052] As Figure 4 shown, the electronic device 400 is in the form of a general-purpose electronic device. The components of the electronic device 400 may include, but are not limited to, one or more processors 410 or processing units, a memory 420, a storage device 430, one or more communication units 440, one or more input devices 450, and one or more output devices 460. The processing unit can be an actual or virtual processor and can execute various processes according to the programs stored in the memory 420. In a multi-processor system, multiple processing units execute computer-executable instructions in parallel to improve the parallel processing ability of the electronic device 400.

[0053] The electronic device 400 generally includes multiple computer storage media. Such media can be any available media accessible to the electronic device 400, including but not limited to volatile and non-volatile media, removable and non-removable media. The memory 420 can be volatile memory (such as registers, caches, random access memory (RAM)), non-volatile memory (such as read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory), or some combination thereof. The storage device 430 can be removable or non-removable media and can include machine-readable media, such as a flash drive, a magnetic disk, or any other media that can be capable of storing information and / or data (such as training data for training) and can be accessed within the electronic device 400.

[0054] The electronic device 400 can further include additional removable / non-removable, volatile / non-volatile storage media. Although not shown in Figure 4 it, a disk drive for reading from or writing to a removable, non-volatile magnetic disk (such as a "floppy disk") and an optical disk drive for reading from or writing to a removable, non-volatile optical disk can be provided. In these cases, each drive can be connected to a bus (not shown) by one or more data media interfaces. The memory 420 can include a computer program product 425 having one or more program modules that are configured to execute the various methods or actions of the various embodiments of the present disclosure.

[0055] The communication unit 440 enables communication with other electronic devices via a communication medium. Additionally, the functions of the components of the electronic device 400 can be implemented in a single computing cluster or multiple computer machines that are capable of communicating via a communication connection. Thus, the electronic device 400 can operate in a networked environment using a logical connection with one or more other servers, network personal computers (PCs), or another network node.

[0056] The input device 450 can be one or more input devices, such as a mouse, a keyboard, a trackball, etc. The output device 460 can be one or more output devices, such as a display, a speaker, a printer, etc. The electronic device 400 can also communicate with one or more external devices (not shown) as needed via the communication unit 440, such as storage devices, display devices, etc., communicate with one or more devices that enable a user to interact with the electronic device 400, or communicate with any device that enables the electronic device 400 to communicate with one or more other electronic devices (such as a network card, a modem, etc.). Such communication can be performed via an input / output (I / O) interface (not shown).

[0057] According to an exemplary implementation of the present disclosure, a computer-readable storage medium is provided, on which one or more computer instructions are stored, and when the one or more computer instructions are executed by a processor, the methods described above are implemented.

[0058] Aspects of the present disclosure are described herein with reference to the flowcharts and / or block diagrams of methods, apparatuses (systems), and computer program products according to implementations of the present disclosure. It should be understood that each block of the flowcharts and / or block diagrams, and combinations of blocks in the flowcharts and / or block diagrams, can be implemented by computer-readable program instructions.

[0059] These computer-readable program instructions can be provided to a processing unit of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus to produce a machine, such that when the instructions are executed by the processing unit of the computer or other programmable data processing apparatus, an apparatus is produced that implements the functions / actions specified in one or more blocks of the flowchart and / or block diagram. These computer-readable program instructions can also be stored in a computer-readable storage medium, which causes a computer, a programmable data processing apparatus, and / or other devices to operate in a specific manner, so that the computer-readable medium storing the instructions includes a manufactured article that includes instructions for implementing various aspects of the functions / actions specified in one or more blocks of the flowchart and / or block diagram.

[0060] The computer-readable program instructions can also be loaded onto a computer, other programmable data processing apparatus, or other device, such that a series of operation steps are executed on the computer, other programmable data processing apparatus, or other device to produce a computer-implemented process, so that the instructions executed on the computer, other programmable data processing apparatus, or other device implement the functions / actions specified in one or more blocks of the flowchart and / or block diagram.

[0061] The flowcharts and block diagrams in the accompanying drawings illustrate the possible architectures, functions, and operations of systems, methods, and computer program products according to multiple implementations of the present disclosure. In this regard, each block in the flowchart or block diagram may represent a module, a program segment, or a part of an instruction, and the module, program segment, or part of an instruction includes one or more executable instructions for implementing the specified logical function. In some alternative implementations, the functions noted in the blocks may occur in an order different from that noted in the accompanying drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in the reverse order, depending on the functions involved. It should also be noted that each block in the block diagram and / or flowchart, and combinations of blocks in the block diagram and / or flowchart, can be implemented by a dedicated hardware-based system that performs the specified functions or actions, or can be implemented by a combination of dedicated hardware and computer instructions.

[0062] The various implementations of the present disclosure have been described above. The above description is exemplary, not exhaustive, and is not limited to the disclosed implementations. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described implementations. The choice of terms used herein is intended to best explain the principles of the implementations, practical applications, or improvements to technologies in the marketplace, or to enable other ordinary skill in the art to understand the implementations disclosed herein.

Claims

1. A method for correcting a mask pattern, characterized in that, Comprising: Arranging at least one sub-resolution assist feature (SRAF) adjacent to a target pattern in a layout, where the target pattern includes at least one pattern segment; And Performing a first-stage optical proximity correction (OPC) correction on the target pattern, where during the first-stage OPC correction, the relative positions between the pattern segments in the target pattern and one or more SRAFs associated with the pattern segments remain unchanged.

2. The method for correcting a mask pattern according to claim 1, wherein Before performing the first-stage optical proximity correction (OPC) correction step on the target pattern, the method further includes: Determining an association relationship between the at least one pattern segment and the at least one SRAF, where performing the first-stage OPC correction on the target pattern is based on the association relationship.

3. The method for correcting a mask pattern according to claim 1 or 2, characterized in that Determining the association relationship includes: For a first side of a first pattern segment among the at least one pattern segment, determining the SRAF adjacent to the first side among the at least one SRSF; and Determining the association relationship between the first side and the SRAF adjacent to the first side.

4. The method for correcting a mask pattern according to claim 3, wherein Determining the association relationship between the first side and the SRAF adjacent to the first side includes: Projecting the first side along a predetermined direction onto the SRAF adjacent to the first side; and Determining the SRAF covered by the projection area generated by the first side associated with the first side.

5. The method for correcting a mask pattern according to claim 4, wherein, Determining the SRAF covered by the projection area generated by the first side associated with the first side includes: Responsive to the projection area covering one or more complete SRAFs, determining that the first side is associated with the one or more complete SRAFs; and Responsive to the projection area covering an SRAF segment in an SRAF, determining that the first side is associated with the SRAF segment.

6. The method for correcting a mask pattern according to claim 1 or 2, characterized in that, The method further includes: Based on the layout of the at least one SRAF in the layout, processing at least a part of the at least one SRAF.

7. The method for correcting a mask pattern according to claim 6, wherein Wherein the processing includes: Removing the part where two adjacent SRAF points in the at least one SRAF are in point contact, Expanding the part where two adjacent SRAF points in the at least one SRAF are in point contact, or Moving a first SRAF among two adjacent SRAFs in the at least one SRAF to merge the two adjacent SRAFs, where the length of the first SRAF is less than the length of a second SRAF among the two adjacent SRAFs.

8. The method for correcting a mask pattern according to claim 6, wherein The method further includes: Responsive to completion of the processing of the at least one SRAF, performing a second-stage OPC correction on the target pattern, where the accuracy of the second-stage OPC correction is higher than the accuracy of the first-stage OPC correction.

9. The method for correcting a mask pattern according to claim 8, characterized in that, Performing the second-stage OPC correction on the target pattern includes: For a second side of a second pattern segment in the target pattern, Determining at least one reference point on the second side; and Based on the at least one reference point, performing the second-stage OPC correction on the second side.

10. The method for correcting a mask pattern according to claim 9, wherein, During the second-stage OPC correction, the relative positions between the pattern segments in the target pattern and the SRAFs associated with the pattern segments remain unchanged.

11. An electronic device, characterized in that, Comprising: At least one processing unit; And At least one memory, the at least one memory being coupled to the at least one processing unit and storing instructions for execution by the at least one processing unit, the instructions, when executed by the at least one processing unit, causing the electronic device to perform the method according to any one of claims 1 to 10.

12. A computer-readable storage medium, characterized in that, A computer program is stored thereon, characterized in that the computer program is executable by a processor to implement the method according to any one of claims 1 to 10.

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