Memristor array photoetching error correction method

Abstract

The invention discloses a memristor array photoetching error correction method. The method comprises the following steps: S1, inputting the row and column number of a memristor array, the target cross sectional area of a single memristor unit and the maximum size constraints of a memristor array layout in the transverse direction and the longitudinal direction; s2, generating an initial reference layout; s3, adjusting the number of the auxiliary units to optimize the photoetching consistency; s4, adjusting the size and spacing of the memristor unit to further reduce the photoetching error; and step S5, outputting the optimized memristor array layout. According to the invention, the error of the memristor array in a photoetching process can be reduced, and the accuracy of photoetching exposure is improved, so that the performance and the stability of the memristor array are ensured.

Description

Technical Field

[0001] The present invention relates to the technical field of lithography error correction in semiconductor manufacturing, and particularly to a method for correcting lithography errors of a memristor array. Background Art

[0002] In traditional computer systems, the core processes of data processing include two major links: computing and storage. Data is first processed by computing elements, and then the processing results are transmitted to storage elements for preservation. This transmission process not only takes a long time but also causes significant power consumption problems, becoming a key factor restricting the performance of computer systems. To break this bottleneck, memristors, as an innovative electronic device, have emerged. Memristors can be organized in the form of an array to achieve extremely high integration density, thereby integrating more functional units within a limited chip space.

[0003] The uniqueness of the memristor array lies in its dual functions: on the one hand, it can serve as a storage unit to store a large amount of data information; on the other hand, it can also achieve computing functions through the voltage information at the driving end and the current information flowing through the metal wire. This design ingeniously reduces the transmission requirements between storage and computing units, thereby significantly improving the overall efficiency of the chip. However, with the continuous progress of semiconductor process technology, the process nodes and feature sizes continue to decrease, and the integration density of devices is also constantly increasing, which poses unprecedented challenges to the lithography process.

[0004] The lithography process is one of the key steps in semiconductor manufacturing, and its accuracy directly affects the performance and quality of the chip. However, in the lithography process, due to the inherent limitations of the optical imaging system, the exposure quality of a pattern is often affected by the surrounding patterns. This influence will cause lithography errors in the exposed pattern, resulting in problems such as inconsistent parameters, blurred edges, or even exposure failure in the pattern structure that seemed safe in the layout design stage. For devices such as memristor arrays that have extremely high requirements for integration density and pattern parameter consistency, lithography errors are undoubtedly a serious challenge.

[0005] To reduce the impact of lithography errors on the performance of memristor arrays, researchers have proposed various solutions. Among them, an effective method is to regard the memristor unit as a contact hole or via and apply optical proximity correction technology to it. Traditional optical proximity correction technology mainly makes fine movement adjustments to the patterns on the layout according to the difference between the optical simulation profile and the corresponding target size to minimize lithography errors. However, when this method is applied to contact holes and vias, it mainly focuses on ensuring the electrical connection reliability between different layers of metal or polysilicon.

[0006] In contrast, the performance of the memristor array is more dependent on the consistency of the graphic parameters. Therefore, for the memristor array, the requirements for lithography errors are more stringent. Although the traditional optical proximity correction technology can reduce lithography errors to a certain extent, it cannot meet the high requirements of the memristor array for the consistency of graphic parameters. Therefore, a lithography error correction method specifically for the characteristics of the memristor array is needed to meet its high-precision requirements. Summary of the Invention

[0007] In view of this, the present invention proposes a lithography error correction method for a memristor array to solve the problem in the prior art that the traditional optical correction technology is difficult to meet the lithography requirements of the memristor.

[0008] The specific technical solution of the present invention is as follows:

[0009] A lithography error correction method for a memristor array, comprising:

[0010] Step S1, input the number of rows and columns of the memristor array, the target cross-sectional area of a single memristor unit, and the maximum size constraints in the horizontal and vertical directions of the memristor array layout;

[0011] Step S2, generate an initial reference layout;

[0012] Step S3, adjust the number of auxiliary units to optimize lithography consistency;

[0013] Step S4, adjust the size and spacing of the memristor units to further reduce lithography errors;

[0014] Step S5, output the optimized memristor array layout.

[0015] Further, step S3 includes: selecting a new number of rows of horizontal auxiliary units and a number of columns of vertical auxiliary units; generating the corresponding memristor array layout; performing lithography process simulation; extracting the profiles of the exposed memristor units; calculating the lithography errors between different memristor units, and performing iterative adjustment based on this error.

[0016] Further, the basis for selecting the number of rows of horizontal auxiliary units and the number of columns of vertical auxiliary units is the lithography errors between the graphic profiles of different memristor units, which is determined by using an optimization algorithm, where the number of auxiliary units in the horizontal and vertical directions are represented by dx and dy respectively, and the values of dx and dy are non-negative integers.

[0017] Further, step S4 includes: according to the lithography errors between the current graphic profile of the memristor unit and the design target, selecting a new unit size and unit spacing; generating the corresponding memristor array layout; performing lithography process simulation; extracting the profiles of the exposed memristor units; calculating the lithography errors between the memristor unit and the design target profile, and performing iterative adjustment based on this error.

[0018] Further, the basis for selecting the unit size and unit pitch is the lithography error between the memristor unit graphic contour and the design target contour.

[0019] Further, in step S2, the method for generating the initial reference layout includes: the user inputs a manually drawn layout or randomly generates it according to the input unit size and pitch parameters.

[0020] Further, repeat the operations of adjusting the number of auxiliary units and the size and pitch of the memristor units until the algorithm reaches the maximum number of iteration steps, and output the optimized layout of the memristor array.

[0021] Further, place auxiliary units with the same graphics as the units in the array at equal intervals on the upper side, lower side, left side, and right side of the memristor array to jointly improve the lithography consistency and balance the influence of the optical proximity effect on the units at each position of the memristor array layout.

[0022] The beneficial effects of the present invention are as follows:

[0023] By means of cyclically adjusting the layout parameters of the memristor array and adding auxiliary units, the present invention makes the exposed graphics consistent with the target size of the memristor units, effectively reduces the errors in the lithography process, and ensures that the graphic parameters of the memristor array meet the high-precision requirements. Description of the Drawings

[0024] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0025] Figure 1 It is a schematic diagram of the structural relationship between the auxiliary unit and the memristor unit of the present invention;

[0026] Figure 2 It is a schematic flowchart of the method for correcting the lithography error of the memristor array of the present invention;

[0027] Figure 3 It is a schematic flowchart of the method for adjusting the number of auxiliary units of the present invention;

[0028] Figure 4 It is a schematic flowchart of the method for adjusting the size and pitch of each unit of the memristor unit of the present invention. Detailed Embodiments

[0029] In order to make the technical problems, technical solutions and beneficial effects to be solved by the present invention clearer and more understandable, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0030] The present invention proposes a method for correcting lithography errors of a memristor array. This method involves the insertion of auxiliary units. As Figure 1 shown, auxiliary units with the same pattern as the units in the array are placed at equal intervals on the upper side, lower side, left side and right side of the memristor array. The purpose is to improve the lithography consistency of the memristor array and balance the influence of optical proximity effect on the units at each position of the memristor array layout through the synergistic effect with other operations in the follow-up.

[0031] The method for correcting lithography errors of the memristor array of the present invention, as Figure 2 shown, specifically includes the following steps:

[0032] Step S1, input relevant parameters: According to the requirements of circuit specifications, input the number of rows and columns of the memristor array, the target cross-sectional area of a single memristor unit, and the maximum size constraints in the horizontal and vertical directions of the memristor array layout. These input parameters will serve as the basic basis for generating the memristor array layout and performing lithography error correction in the follow-up. For example, the number of rows and columns of the memristor array determines the basic scale of the array, the target cross-sectional area affects the design goal of a single memristor unit, and the maximum size constraints in the horizontal and vertical directions limit the size range of the entire layout, ensuring that the finally generated layout is within the achievable range of the actual manufacturing process.

[0033] Step S2, generate an initial reference layout: Generate the initial reference layout of the memristor array. The generation method is not limited to manual drawing of the layout by the user or random generation according to the parameters such as the unit size and spacing input in Step S1. This diverse generation method provides flexibility for the creation of the memristor array layout. Whether it is manual drawing or random generation according to parameters, the initial reference layout is the starting point for subsequent lithography error correction.

[0034] Step S3, adjust the number of auxiliary units: Based on the current memristor array layout, combined with optical simulation, adjust the number of auxiliary units in the horizontal and vertical directions to obtain an updated layout. As shown in the appendix Figure 3 shown, the specific steps for adjusting the number of auxiliary units include:

[0035] Step S31, Select the number of auxiliary units: According to the lithography error between the current graphic contours of different memristor units, select a new number of rows of horizontal auxiliary units and columns of vertical auxiliary units. Select a new number of horizontal and vertical auxiliary units, where the number of horizontal and vertical auxiliary units can be represented by dx and dy. dx represents the number of rows of auxiliary units accommodated on the upper and lower sides of the array, and dy represents the number of columns of auxiliary units accommodated on the left and right sides of the array. Their values should be integers not less than zero. The selection of dx and dy is based on the lithography error between the graphic contours of different memristor units, and any optimization algorithm is selected for determination according to the error value. The characterization methods of the lithography error here include but are not limited to edge placement error.

[0036] Step S32, Generate the corresponding layout: Generate the corresponding memristor array layout according to the number of rows and columns of auxiliary units selected in Step S31. This step applies the selected number of auxiliary units to the layout generation to obtain a new memristor array layout structure.

[0037] Step S33, Perform lithography process simulation: Perform lithography process simulation on the layout generated in Step S32. Among them, any simulation method can be selected for the lithography process simulation as long as the graphic contour after lithography can be obtained, and no specific details are given here.

[0038] Step S34, Extract the graphic contour: Extract the graphic contour of the memristor unit obtained by simulation in Step S33. This extraction process is to prepare for calculating the lithography error in the follow-up. By accurately extracting the graphic contour, the actual shape information of the memristor unit after lithography can be obtained.

[0039] Step S35, Calculate the lithography error and iterate: According to the graphic contour in Step S34, calculate the lithography error between different memristor units, and return to Step S31 until the preset number of iterations is reached. Before calculating the lithography error, first calculate the size of the memristor array layout. If the horizontal or vertical size of the array exceeds the preset size constraint, the lithography error is set to a relatively large value. This iterative process can continuously optimize the number of auxiliary units, making the memristor array layout gradually reach a better state considering the lithography error and size constraint.

[0040] Step S4, Adjust the size and spacing of memristor units: Based on the current memristor array layout and combined with optical simulation, adjust the size of the memristor units on the layout and the spacing between each unit to obtain an updated layout. As shown in the appendix Figure 4 The specific steps for adjusting the size of the memristor unit and the spacing between each unit are as follows:

[0041] Step S41, select the unit size and pitch: Based on the lithography error between the current memristor unit pattern profile and the design target, select a new set of unit size and unit pitch. Among them, the unit size can be the side length of the unit, denoted as R; the unit pitch is denoted as Sx and Sy in the horizontal and vertical directions respectively. The selected R, Sx, and Sy should meet the design rules, and the selection basis is the lithography error between the memristor unit pattern profile and the design target profile, and any optimization algorithm is selected for determination according to this error value.

[0042] Step S42, generate the corresponding layout: Generate the corresponding memristor array layout according to the unit size and unit pitch selected in step S41. This step applies the selected unit size and pitch to the layout generation to obtain a new memristor array layout structure.

[0043] Step S43, perform lithography process simulation: Perform lithography process simulation on the layout generated in step S42. Among them, any simulation method can be selected for lithography process simulation as long as the pattern profile after lithography can be obtained, and no specific details are given here.

[0044] Step S44, extract the pattern profile: Extract the memristor unit pattern profile obtained from the simulation in step S43. This operation is similar to step S34, and the purpose is to obtain the actual shape information of the memristor unit after lithography for subsequent calculation of the lithography error.

[0045] Step S45, calculate the lithography error and iterate: Calculate the lithography error between the memristor unit and the design target profile according to the pattern profile in step S44, and return to step S41 until the preset number of iterations is reached. Before calculating the lithography error, first calculate the size of the memristor array layout. If the horizontal or vertical size of the array exceeds the pre-set size constraint, the lithography error is set to a large value. Through this iterative process, the unit size and pitch of the memristor are continuously optimized, so that the memristor array layout is gradually optimized under the dual considerations of lithography error and size constraint.

[0046] Step S5, repeat iteration and output the optimized layout: Repeat steps S3 - S4 until the algorithm reaches the maximum number of iteration steps, and output the optimized memristor array layout. Through multiple repeated operations of adjusting the number of auxiliary units and the size and pitch of the memristor units, a fully optimized memristor array layout is finally obtained. This layout has been effectively corrected in terms of lithography error and can meet the high-precision requirements of the memristor array in the lithography process.

[0047] The beneficial effects of the present invention are as follows:

[0048] 1. Improve lithography consistency: By adding auxiliary unit patterns, the present invention effectively balances the influence of optical proximity effect on units at various positions of the memristor array layout, thus significantly improving the consistency of graphic parameters during lithography and ensuring the performance and stability of the memristor array.

[0049] 2. Enhance design efficiency: In traditional methods, layout design often relies on manual adjustment, which is inefficient and error-prone. By calculating the lithography error based on the graphic contour line, the present invention automatically searches for and optimizes layout parameters, avoiding the inefficiency problem caused by manual layout design and greatly improving the design efficiency and accuracy.

[0050] The above are only the preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent replacements, and improvements made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. A method for correcting lithography errors in a memristor array, characterized in that Including: Step S1: Input the number of rows and columns of the memristor array, the target cross-sectional area of a single memristor cell, and the maximum size constraints in the horizontal and vertical directions of the memristor array layout. Step S2: Generate an initial reference layout. Step S3: Adjust the number of auxiliary cells to optimize lithography consistency. Step S4: Adjust the size and spacing of the memristor cells to further reduce lithography errors. Step S5: Output the optimized memristor array layout.

2. The lithography error correction method for a memristor array according to claim 1, wherein Step S3 includes: Select a new number of rows of horizontal auxiliary cells and a number of columns of vertical auxiliary cells; Generate the corresponding memristor array layout; Perform lithography process simulation; Extract the profiles of the memristor cells after exposure; Calculate the lithography errors between different memristor cells and perform iterative adjustment based on this error.

3. The lithography error correction method for a memristor array according to claim 2, characterized in that, The basis for selecting the number of rows of horizontal auxiliary cells and the number of columns of vertical auxiliary cells is the lithography error between the graphic profiles of different memristor cells, which is determined using an optimization algorithm. The number of auxiliary cells in the horizontal and vertical directions is represented by dx and dy respectively, and the values of dx and dy are non-negative integers.

4. A method for correcting lithography errors of a memristor array according to claim 1, characterized in that, Step S4 includes: According to the lithography error between the current graphic profile of the memristor cell and the design target, select a new cell size and cell spacing; Generate the corresponding memristor array layout; Perform lithography process simulation; Extract the profiles of the memristor cells after exposure; Calculate the lithography error between the memristor cell and the design target profile and perform iterative adjustment based on this error.

5. A method for correcting lithography errors of a memristor array according to claim 4, characterized in that, The basis for selecting the cell size and cell spacing is the lithography error between the graphic profile of the memristor cell and the design target profile.

6. The method for correcting lithography errors of a memristor array according to claim 1, wherein In step S2, the method for generating the initial reference layout includes: The user inputs a manually drawn layout or randomly generates it according to the input cell size and spacing parameters.

7. A lithography error correction method for a memristor array according to claim 1, characterized in that, Repeat the operations of adjusting the number of auxiliary cells and the size and spacing of the memristor cells until the algorithm reaches the maximum number of iteration steps, and output the optimized memristor array layout.

8. A method for correcting lithography errors of a memristor array according to claim 1, characterized in that, Place auxiliary cells with the same graphics as the cells in the array at equal intervals on the upper side, lower side, left side, and right side of the memristor array to jointly improve lithography consistency and balance the influence of optical proximity effects on the cells at various positions of the memristor array layout.

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