Image sonar gain adaptive control method based on FPGA

Abstract

The invention discloses an image sonar gain adaptive control method based on an FPGA. The method comprises the following steps: an upper computer sends a control message carrying a manual gain parameter to a sonar signal processing board based on an Ethernet UDP protocol so as to execute manual gain control; a codeword gain and voltage gain cooperative control architecture is provided; pID closed-loop feedback control is carried out based on beam pattern characteristics, and when a manual gain value changing message issued by the Ethernet is received, the adaptive gain compensation value and the PID historical state are cleared, and the manual gain code is switched to an instruction specified value. According to the invention, conflict-free switching between a self-adaptive mode and a manual mode can be realized, and in addition, the quality of sonar images and the stability of gain regulation and control are improved while large dynamic range and high-precision adjustment of time-varying gain are realized.

Description

Technical Field

[0001] The present invention relates to the technical field of sonar signal processing, and particularly to an image sonar gain adaptive control method based on FPGA. Background Art

[0002] In an image sonar system, time-varying gain control is a key technology for compensating for the attenuation of acoustic wave propagation and improving the target detection ability. Traditional time-varying gain control mostly adopts a single gain adjustment mode. For example:

[0003] Digital gain code control: It realizes segmented adjustment by presetting gain codes (such as 6dB steps). Although it has the advantage of high stability, it has the problem of low adjustment accuracy. Usually, it is also necessary to compensate the AD data collected in the code, which is extremely inconvenient.

[0004] Analog voltage control gain adjustment: It relies on a high-precision digital-to-analog converter to achieve continuous fine-tuning. Although it can improve the adjustment accuracy, it has the problem of limited dynamic range. In addition, the analog voltage control gain adjustment mostly adopts the method of real-time reading of the pre-stored curve and cannot adapt to different hydrological conditions.

[0005] Existing adaptive gain control schemes mostly rely on fixed thresholds or static compensation algorithms. For example, the gain adjustment is triggered by setting a fixed signal strength threshold. Such methods are prone to misadjustment when there are multiple targets or noise interference in the beam pattern, resulting in weak targets being unclear or strong targets being oversaturated. At the same time, the cooperative mechanism between manual gain intervention and adaptive control is missing, and gain oscillation is easily caused by parameter superposition during mode switching, affecting the stability of the system.

[0006] In view of the above problems, there is an urgent need for a sonar gain control scheme that takes into account a large dynamic range, high-precision adjustment, and supports seamless switching between adaptive / manual modes. Summary of the Invention

[0007] Aiming at the problems of low adjustment accuracy or small dynamic range of traditional sonar time-varying gain, unclear weak targets or oversaturated strong targets in sonar images, and easy occurrence of gain oscillation when adjusting the gain value, the present invention provides an image sonar gain adaptive control method based on FPGA. Through the cooperative control architecture of manual gain control and time-varying gain, and the PID closed-loop feedback control based on the characteristics of the beam pattern, while achieving large dynamic range and high-precision adjustment of time-varying gain, the quality of sonar images and the stability of gain regulation are improved.

[0008] To achieve the above technical objectives, the technical solution adopted by the present invention is as follows:

[0009] An image sonar gain adaptive control method based on FPGA, the method comprising the following steps:

[0010] S1: The host computer sends a control message carrying manual gain parameters to the sonar signal processing board based on the Ethernet UDP protocol to perform manual gain control;

[0011] S2: Perform time-varying gain collaborative control, which specifically includes the following sub-steps:

[0012] S2.1: Based on the active sonar equation, combined with the voltage-code value conversion characteristics of the AD5340 chip and the gain-voltage response curve of the VGA810 amplifier, construct a transfer function between the time count value and the gain control code, and generate a time-varying gain code value curve;

[0013] S2.2: Implement piecewise processing on the time-varying gain code value curve, synchronously generate a gain code value curve for the voltage-controlled gain of the VGA810 amplifier and time nodes for the discrete code word switching of the LTC6912-2 chip, and perform time-varying gain collaborative control;

[0014] S3: Perform PID closed-loop feedback control based on the beam pattern characteristics, which specifically includes the following sub-steps:

[0015] S3.1: Obtain the sonar image after conditioning and sonar signal processing, extract the maximum N values of each beam group on the distance axis, and calculate the mean value to generate a brightness feature sequence;

[0016] S3.2: Map the brightness feature sequence to the interval [-1, 1] to generate a mapping curve;

[0017] S3.3: Perform Gaussian smoothing processing on the mapping curve to generate a Gaussian smoothing curve;

[0018] S3.4: Process the Gaussian smoothing curve through the PID algorithm to obtain a gain compensation curve;

[0019] S3.5: After superimposing the gain compensation curve and the time-varying gain code value curve, perform automatic gain control;

[0020] Wherein, when receiving a message for changing the manual gain value sent by Ethernet, clear the adaptive gain compensation value and the PID historical state, and switch the manual gain code to the value specified by the instruction.

[0021] Further, in step S1, the host computer sends a control message carrying manual gain parameters to the sonar signal processing board based on the Ethernet UDP protocol. After parsing the protocol stack to obtain the target gain value, convert it into a control code word based on the register mapping specification of the LTC6912-2 chip.

[0022] Further, in step S2.1, the process of constructing the transfer function between the time count value and the gain control code includes the following sub-steps:

[0023] Call the fixed-point to floating-point function of the Floating-point IP core to convert the time count value from the fixed-point data type to the single-precision floating-point data type;

[0024] Through the mathematical function operation module of the IP core, perform a logarithmic operation on the converted single-precision floating-point time count value;

[0025] Utilize the arithmetic operation module of the IP core to sequentially perform multiplication and addition operations;

[0026] Call the floating-point to fixed-point function module of the IP core to convert the operation result from the single-precision floating-point data type to the fixed-point data type.

[0027] Further, in step S2.1, the time-varying gain code value curve is:

[0028] tvg_code = a·ln(cnt) + b·cnt + c

[0029] where a, b, and c are constants, cnt is the time count value under the processing clock of the FPGA adaptive gain control module; tvg_code is the code value.

[0030] Step S2.2 further includes:

[0031] According to the voltage-code value conversion characteristic of the AD5340 chip and the gain-voltage response curve of the VGA810 amplifier, the transfer characteristic between the AD5340 code value and the gain value is as follows:

[0032]

[0033] where V ref is the reference voltage of the AD5340 chip, tvg_code is the code value, and Gain is the gain value;

[0034] Based on the discrete gain characteristic of the LTC6912-2, calibrate the TVG code value d at the Gain = 6dB operating point, and construct a continuous adjustment curve of the voltage-controlled gain of the VGA810 amplifier by performing piecewise linearization processing on the TVG code value curve:

[0035]

[0036] In the formula, a, b, and c are constants, and cnt is the time count value under the processing clock of the FPGA adaptive gain control module;

[0037] According to the segmentation points of the continuous adjustment curve of the voltage-controlled gain of the VGA810 amplifier, obtain the time nodes for discrete codeword switching of the LTC6912-2 chip, which are used to update the gain codewords of the LTC6912-2 chip at the corresponding time nodes.

[0038] Step S3.1 further includes:

[0039] After filtering and gain adjustment processing on the multi-channel acoustic data collected by the hydrophone array, the sonar signal processing board generates a two-dimensional sonar image through a broadband beamforming algorithm, extracts the maximum N values of each beam group along the distance axis using the statistical method, and generates a brightness feature sequence through mean operation.

[0040] Step S3.2 further includes:

[0041] Set three-level thresholds of m%, l%, and n%, define the interval [0, m%) as the no-target domain, [m%, l%) as the weak-target enhancement domain, [l%, n%] as the ideal neutral domain, and (n%, 100%] as the over-saturation suppression domain. The corresponding mapping piecewise function is:

[0042]

[0043] where x is the brightness feature value and y is the mapping value.

[0044] Step S3.3 further includes:

[0045] Construct a discretized Gaussian kernel with a standard deviation σ of 2 and a kernel length of 6σ + 1. Convolve the generated Gaussian kernel with the original data point by point. The output of each point is the sum of the products of the data points in the neighborhood and the kernel weights, obtaining the Gaussian smoothing curve as follows:

[0046]

[0047] where k is the offset from the center point, k ranges from -M to M, and M = 3σ; y is the mapping value; z(i) is the sum of the products of the i-th data point in the neighborhood and the kernel weights.

[0048] Further, in step S3.4, the Gaussian smoothing curve is processed through a PID algorithm to obtain the following gain compensation curve:

[0049]

[0050] where k p 、k d and k i are the coefficients of the proportional link, differential link, and integral link in the PID algorithm respectively; e(j) is the negation of the Gaussian smoothing curve in the j-th cycle, which is the error of the current cycle; e(j - 1) is the error value obtained in the previous cycle; is the sum of historical error values; K is the conversion ratio between the result calculated by the PID algorithm and the time-varying gain code value curve; u(j) is the gain compensation curve calculated in the j-th cycle.

[0051] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0052] First, the FPGA-based image sonar gain adaptive control method of the present invention, through manual gain control, a collaborative control architecture of time-varying gain, and PID closed-loop feedback control based on beam pattern characteristics, while achieving large dynamic range and high-precision adjustment of time-varying gain, improves the quality of sonar images and the stability of gain regulation. The implementation method of the present invention is simple, the improvement effect is obvious, and it is convenient to be applied to engineering practice.

[0053] Second, the FPGA-based image sonar gain adaptive control method of the present invention supports sending manual gain codes via Ethernet, automatically clears the PID historical state and resets the compensation amount while implementing manual gain, and realizes conflict-free switching between adaptive and manual modes. BRIEF DESCRIPTION OF THE DRAWINGS

[0054] Figure 1 is the flowchart of the FPGA-based image sonar gain adaptive control method of the present invention;

[0055] Figure 2 is a schematic diagram of the gain-voltage response curve of the VGA810 amplifier;

[0056] Figure 3 is the flowchart of the real-time calculation of the TVG code value gain curve by the floating-point IP core;

[0057] Figure 4 is the timing diagram of the register configuration of the AD5340 chip;

[0058] Figure 5 is the timing diagram of the SPI communication protocol of the LTC6912-2 chip;

[0059] Figure 6 is the schematic diagram of the process of FPGA Gaussian smoothing processing;

[0060] Figure 7 is the experimental diagram of adaptive gain control. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0061] The following further describes the embodiments of the present invention in detail with reference to the accompanying drawings.

[0062] The present invention discloses an FPGA-based image sonar gain adaptive control method, which includes the following steps:

[0063] S1: The host computer sends a control message carrying manual gain parameters to the sonar signal processing board based on the Ethernet UDP protocol to perform manual gain control;

[0064] S2: Perform collaborative control of time-varying gain, which specifically includes the following sub-steps:

[0065] S2.1: Based on the active sonar equation, combined with the voltage-code value conversion characteristics of the AD5340 chip and the gain-voltage response curve of the VGA810 amplifier, construct the transfer function between the time count value and the gain control code, and generate the time-varying gain code value curve;

[0066] S2.2: Perform segmentation processing on the time-varying gain code value curve, synchronously generate the gain code value curve for the voltage-controlled gain of the VGA810 amplifier and the time nodes for the discrete codeword switching of the LTC6912-2 chip, and perform time-varying gain collaborative control;

[0067] S3: Perform PID closed-loop feedback control based on the beam pattern characteristics, specifically including the following sub-steps:

[0068] S3.1: Obtain the sonar image after conditioning and sonar signal processing, extract the maximum N values of each beam group on the distance axis, and calculate the mean value to generate the brightness feature sequence;

[0069] S3.2: Map the brightness feature sequence to the interval [-1, 1] to generate the mapping curve;

[0070] S3.3: Perform Gaussian smoothing processing on the mapping curve to generate the Gaussian smoothing curve;

[0071] S3.4: Process the Gaussian smoothing curve through the PID algorithm to obtain the gain compensation curve;

[0072] S3.5: After superimposing the gain compensation curve and the time-varying gain code value curve, perform automatic gain control;

[0073] Among them, when receiving the manual gain value change message sent by Ethernet, clear the adaptive gain compensation value and the PID historical state, and switch the manual gain code to the value specified by the instruction.

[0074] As Figure 1 shown, this embodiment provides an image sonar gain adaptive control method based on FPGA, specifically including the following steps.

[0075] Step 1: The host computer sends a control message carrying the manual gain parameter to the sonar signal processing board based on the Ethernet UDP protocol. After parsing the protocol stack to obtain the target gain value, convert it into a control codeword based on the register mapping specification of the LTC6912-2 chip. The mapping relationship between the gain value and the codeword is shown in Table 1.

[0076] Table 1

[0077]

[0078]

[0079] Step 2: Based on the active sonar equation, combined with the voltage-code value conversion characteristics of the AD5340 chip and the gain-voltage response curve of the VGA810 amplifier, construct the transfer function between the time count value and the gain control code.

[0080] Two parameters related to distance in the active sonar equation: propagation loss and reverberation level; therefore, the total echo reduction formula is as follows:

[0081]

[0082] Among them, EL r is the total attenuation, in dB; TL r is the propagation loss, in dB; RL r is the reverberation level, in dB; r is the propagation distance, in m; α is the attenuation coefficient, in dB / m; τ is the transmit pulse width, in ms; θ H is the transducer horizontal opening angle, in radians; S A is the backscattering intensity, in dB; v c is the sound wave propagation speed in water, usually 1500 m / s.

[0083] In practical applications, what is concerned about is the relative value rather than the absolute value. Therefore, all constants in the formula are ignored, that is: The simplified formula for the total echo attenuation is as follows:

[0084] EL r = 30lg r + 2αr;

[0085] Among them, the relationship between r and the count value cnt in the FPGA code is as follows:

[0086]

[0087] Among them, clk is the processing clock of the time-varying gain code value curve generation module in the FPGA, and cnt is the count value under the processing clock, reflecting the current time;

[0088] The transfer characteristics between the AD5340 code value and the gain value are as follows:

[0089]

[0090] As Figure 2 shown, it is the gain-voltage response curve of the VGA810 amplifier, and the expression is as follows:

[0091] Gain = -40(-V out + 1);

[0092] Combining the above four equations gives the following formula:

[0093]

[0094] Substitute v c , clk, α, and V ref with their specific numerical values into the formula, and after calculation and simplification, the equation for the code value and the time count value is as follows:

[0095] tvg_code = a·ln(cnt) + b·cnt + c;

[0096] where a, b, and c are constants obtained through calculation and simplification after substituting specific numerical values.

[0097] Step 3: As shown in Figure 3 , the flowchart for the FPGA to generate the time-varying gain code value curve in real time is as follows: Call the fixed-point to floating-point function of the Floating-point(7.1) IP core to convert the time count value from the fixed-point data type to the single-precision floating-point data type to achieve data preprocessing; secondly, through the mathematical function operation module of the IP core, perform a logarithmic operation on the converted single-precision floating-point time count value; subsequently, use the arithmetic operation module of the IP core to perform multiplication and addition operations in sequence; finally, call the floating-point to fixed-point function module of the IP core to convert the operation result from the single-precision floating-point data type to the fixed-point data type for subsequent processing.

[0098] Perform segmented processing on the time-varying gain code value curve, synchronously generate the gain code value curve for VGA810 voltage-controlled gain and the time nodes for LTC6912-2 discrete codeword switching, and cooperate to achieve time-varying gain control. The specific process is as follows:

[0099] Based on the voltage-code value conversion characteristic of the AD5340 chip and the gain-voltage response curve of the VGA810 amplifier, the transfer characteristic between the AD5340 code value and the gain value is as follows:

[0100]

[0101] where V ref is the reference voltage of the AD5340 chip.

[0102] Based on the discrete gain characteristic of LTC6912-2 (0 dB to 36 dB, 6 dB step), calibrate the TVG code value d at the Gain = 6 dB operating point, and by performing piecewise linearization processing on the TVG code value curve, construct a continuous adjustment curve for the VGA810 voltage-controlled gain:

[0103]

[0104] According to the segmentation points of the continuous adjustment curve of the VGA810 voltage-controlled gain, the time nodes for the discrete codeword switching of the LTC6912-2 are obtained, which are used to update the gain codeword of the LTC6912-2 at the corresponding time nodes.

[0105] Step 4: Implement gain control according to the register configuration timing in the AD5340 data sheet and the SPI communication protocol timing in the LTC6912-2 data sheet.

[0106] As Figure 4 , the timing diagram of the AD5340 chip register configuration is shown, which is used to implement voltage gain control. When updating the voltage value, dac_cs_n and dac_ldac_n should be set low simultaneously to select the chip and trigger the update of the input register data to the DAC register; pull dac_wr_n low and cooperate with dac_cs_n to write data through the parallel interface, where tvg_db is the parallel data bus for transmitting the tvg_code to be written; set dac_pd_n to high level to prevent the chip from entering the power-down mode; set dac_gain to high level, and at this time, the output range of the DAC is 0 to 2·V ref ; set dac_buf to high level, indicating that the on-chip buffer is used at the reference voltage input terminal; keep dac_clr_n at high level, indicating that the input register and the DAC register are not cleared.

[0107] As Figure 5 , the timing diagram of the SPI communication protocol of the LTC6912-2 chip is shown, which is used to implement codeword gain control. When updating the codeword, spi_clk requires 8 rising edges to implement manual gain codeword control and automatic gain discrete codeword control; during this period, spi_cs needs to be pulled low to select the chip for codeword update; spi_din is the codeword to be input, and its corresponding gain value is shown in Table 1 above.

[0108] Step 5: As Figure 6 , the entire process of calculating the code value compensation curve based on the beam pattern characteristics is as follows:

[0109] First, based on the multi-channel acoustic data collected by the 96-channel hydrophone array, after being filtered and gain-regulated by the signal conditioning board, the sonar signal processing board generates a two-dimensional sonar image (512 beams × distance dimension / 8-bit gray quantization) through the broadband beamforming algorithm, and uses the statistical method to extract the maximum N values of each beam group along the distance axis, and generates a brightness feature sequence through the mean operation.

[0110] Secondly, map the luminance feature sequence generated after the mean operation to the interval [-1, 1]. The following is a schematic diagram of the mapping curve: Set three-level thresholds of m%, l%, and n%. Define the interval [0, m%) as the target-free domain (mapping value is 0), [m%, l%) as the weak target enhancement domain (mapping value range is -1 to 0), [l%, n%] as the ideal neutral domain (mapping value is 0), and (n%, 100%] as the over-saturation suppression domain (mapping value range is 0 to 1). The mapping piecewise function is as follows:

[0111]

[0112] Then, construct a discretized Gaussian kernel. Take the standard deviation σ as 2 and the kernel length as 6σ + 1 to ensure that 99.7% of the energy is covered. Perform a convolution operation between the generated Gaussian kernel and the original data point by point. The output of each point is the sum of the products of the data points in the neighborhood and the kernel weights, and the following Gaussian smoothing curve is obtained:

[0113]

[0114] In the formula, k is the offset from the center point, k ranges from -M to M, and M = 3σ; y is the mapping value; z(i) is the sum of the products of the i-th data point in the neighborhood and the kernel weights.

[0115] As Figure 6 shown, the following is a schematic diagram of implementing Gaussian smoothing processing on FPGA, where

[0116] Finally, process the Gaussian smoothing curve through the PID algorithm to obtain the gain compensation curve as follows:

[0117]

[0118] where k p 、k d and k i are the coefficients of the proportional link, differential link, and integral link in the PID algorithm respectively; e(j) is the result of taking the inverse of the Gaussian smoothing curve in the j-th cycle, which is the error of the current cycle; e(j - 1) is the error value obtained in the previous cycle; is the sum of historical error values; K is the conversion ratio between the result calculated by the PID algorithm and the time-varying gain code value curve; u(j) is the gain compensation curve calculated in the j-th cycle.

[0119] In addition, integral limiting is also required to reduce the overshoot caused by integration.

[0120] Step 6: Superimpose the gain compensation curve and the time-varying gain code value curve to achieve automatic gain control; when receiving a message for changing the manual gain value sent from Ethernet, clear the adaptive gain compensation value and the PID historical status, and switch the SPI gain code to the value specified by the instruction, so as to avoid the out-of-control of the automatic gain control caused by the change of the manual gain value.

[0121] Using the method of this embodiment for experiments, Figure 7 in (a) is the sonar image without automatic gain control. This sonar image shows the imaging effect of an underwater dam. Figure 7 in (b), the maximum N values of each beam group are extracted along the distance axis by the statistical method, and a brightness feature sequence is generated through mean operation. Figure 7 in (c), the brightness feature sequence generated after mean operation is mapped to the range of [-1, 1]. Figure 7 in (d), after Gaussian smoothing processing, it can be seen that the curve becomes smooth. Figure 7 in (e) is the gain compensation curve obtained by processing the Gaussian smooth curve through the PID algorithm. Figure 7 in (f) is the sonar image obtained through multiple loop processes. Compared with Figure 7 in (a), the overall image is brighter and the dam is clearer.

[0122] Although the preferred embodiments of the present application have been described, those skilled in the art can make additional changes and modifications once they know the basic creative concepts. Therefore, the appended claims are intended to be construed to include the preferred embodiments and all changes and modifications falling within the scope of the present application.

[0123] Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalent technologies, the present application also intends to include these changes and modifications.

Claims

1. An image sonar gain adaptive control method based on FPGA, characterized in that, The method includes the following steps: S1: The host computer sends a control message carrying manual gain parameters to the sonar signal processing board based on the Ethernet UDP protocol to perform manual gain control; S2: Perform time-varying gain collaborative control, which specifically includes the following sub-steps: S2.1: Based on the active sonar equation, combined with the voltage-code value conversion characteristics of the AD5340 chip and the gain-voltage response curve of the VGA810 amplifier, construct a transfer function between the time count value and the gain control code, and generate a time-varying gain code value curve; S2.2: Perform segmented processing on the time-varying gain code value curve, synchronously generate a gain code value curve for the voltage-controlled gain of the VGA810 amplifier and time nodes for the discrete code word switching of the LTC6912-2 chip, and perform time-varying gain collaborative control; S3: Perform PID closed-loop feedback control based on the beam pattern characteristics, which specifically includes the following sub-steps: S3.1: Obtain the sonar image after conditioning and sonar signal processing, extract the maximum N values of each beam group on the distance axis, and calculate the average value to generate a brightness feature sequence; S3.2: Map the brightness feature sequence to the interval [-1, 1] to generate a mapping curve; S3.3: Perform Gaussian smoothing processing on the mapping curve to generate a Gaussian smoothing curve; S3.4: Process the Gaussian smoothing curve through the PID algorithm to obtain a gain compensation curve; S3.5: After superimposing the gain compensation curve and the time-varying gain code value curve, perform automatic gain control; Wherein, when receiving a message for changing the manual gain value sent via Ethernet, clear the adaptive gain compensation value and the PID historical state, and switch the manual gain code to the value specified by the instruction.

2. The method for adaptively controlling the gain of an image sonar based on FPGA according to claim 1, wherein In step S1, the host computer sends a control message carrying manual gain parameters to the sonar signal processing board based on the Ethernet UDP protocol. After parsing the protocol stack to obtain the target gain value, convert it into a control code word based on the register mapping specification of the LTC6912-2 chip.

3. The method for adaptively controlling the gain of an image sonar based on FPGA according to claim 1, wherein In step S2.1, the process of constructing the transfer function between the time count value and the gain control code includes the following sub-steps: Call the fixed-point to floating-point function of the Floating-point IP core to convert the time count value from the fixed-point data type to the single-precision floating-point data type; Perform a logarithmic operation on the converted single-precision floating-point time count value through the mathematical function operation module of the IP core; Use the arithmetic operation module of the IP core to perform multiplication and addition operations in sequence; Call the floating-point to fixed-point function module of the IP core to convert the operation result from the single-precision floating-point data type to the fixed-point data type.

4. The method for gain adaptive control of an image sonar based on FPGA according to claim 1, characterized in that In step S2.1, the time-varying gain code value curve is: tvg_code = a·ln(cnt)+b·cnt+c Wherein, a, b, and c are constants, cnt is the time count value under the processing clock of the FPGA adaptive gain control module; tvg_code is the code value.

5. The method for adaptively controlling the gain of an image sonar based on FPGA according to claim 1, characterized in that Step S2.2 further includes: According to the voltage-code value conversion characteristics of the AD5340 chip and the gain-voltage response curve of the VGA810 amplifier, the transfer characteristics between the AD5340 code value and the gain value are as follows: Among them, V ref is the reference voltage of the AD5340 chip, tvg_code is the code value, and Gain is the gain value; Based on the discrete gain characteristics of the LTC6912-2, calibrate the TVG code value d at the operating point of Gain = 6dB. By performing piecewise linearization on the TVG code value curve, construct a continuous adjustment curve for the voltage-controlled gain of the VGA810 amplifier: where a, b, and c are constants, and cnt is the time count value under the processing clock of the FPGA adaptive gain control module; According to the segmentation points of the continuous adjustment curve of the voltage-controlled gain of the VGA810 amplifier, obtain the time nodes for the discrete codeword switching of the LTC6912-2 chip, which are used to update the gain codewords of the LTC6912-2 chip at the corresponding time nodes.

6. The method for adaptively controlling the gain of an image sonar based on FPGA according to claim 1, wherein Step S3.1 further includes: After filtering and gain control processing of the multi-channel acoustic data collected by the hydrophone array, the sonar signal processing board generates a two-dimensional sonar image through the broadband beamforming algorithm, extracts the largest N values of each beam group along the distance axis using the statistical method, and generates a brightness feature sequence through mean operation.

7. The method for gain adaptive control of an image sonar based on an FPGA according to claim 1, wherein Step S3.2 further includes: Set three levels of thresholds of m%, l%, and n%. Define the interval [0, m%) as the no-target domain, [m%, l%) as the weak-target enhancement domain, [l%, n%] as the ideal neutral domain, and (n%, 100%] as the over-saturation suppression domain. The corresponding mapping piecewise function is: where x is the brightness feature value and y is the mapping value.

8. The method for adaptively controlling the gain of an image sonar based on FPGA according to claim 1, characterized in that Step S3.3 further includes: Construct a discretized Gaussian kernel with a standard deviation σ of 2 and a kernel length of 6σ + 1. Perform a convolution operation on the generated Gaussian kernel and the original data point by point. The output of each point is the sum of the products of the data points in the neighborhood and the kernel weights, and obtain the Gaussian smoothing curve as follows: where k is the offset from the center point, k ranges from -M to M, M = 3σ; y is the mapping value; z(i) is the sum of the products of the i-th data point in the neighborhood and the kernel weights.

9. The method for adaptively controlling the gain of an image sonar based on FPGA according to claim 1, wherein In step S3.4, the Gaussian smoothing curve is processed through the PID algorithm to obtain the following gain compensation curve: where k p , k d and k i are the coefficients of the proportional link, the differential link, and the integral link in the PID algorithm respectively; e(j) is obtained by taking the inverse of the Gaussian smoothing curve in the j-th cycle, and is the error of the current cycle; e(j - 1) is the error value obtained in the previous cycle; is the sum of historical error values; K is the conversion ratio between the result calculated by the PID algorithm and the time-varying gain code value curve; u(j) is the gain compensation curve calculated in the j-th cycle.

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