Voltage output circuit, chip and electronic equipment

Abstract

The embodiment of the invention provides a voltage output circuit, a chip and an electronic device, the voltage output circuit comprises an output module, the output module comprises an output transistor and a feedback resistance unit, and the feedback resistance unit is used for outputting a first feedback voltage and a second feedback voltage; the main control module is used for pulling up the control end voltage of the output transistor when the first feedback voltage is smaller than the preset reference voltage and pulling down the control end voltage of the output transistor when the second feedback voltage is larger than the preset reference voltage; the auxiliary control module is used for controlling the change speed of the control end voltage of the output transistor according to the feedback voltage; wherein the magnitude of the feedback voltage is positively correlated with the magnitude of the output voltage provided by the output module, and the change speed of the control end voltage of the output transistor is negatively correlated with the magnitude of the feedback voltage. The starting speed and the transient response capability of the voltage output circuit can be improved.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit technology, and particularly relates to a voltage output circuit, a chip, and an electronic device. Background Art

[0002] At present, a Low Dropout Regulator (LDO) is a DC power supply that can output a stable DC voltage and is widely used in large-scale digital systems such as System on Chip (SoC) to provide a stable DC voltage for each circuit module of the system on chip.

[0003] In the related art, a low dropout linear regulator usually includes a power transistor, a feedback resistor, and an error amplifier, etc. The error amplifier performs feedback control on the gate voltage of the power transistor according to the feedback voltage output by the feedback resistor, so that the power transistor outputs a stable DC voltage. However, the existing low dropout linear regulator needs to supply power to the load. When the current demanded by the load changes suddenly, the feedback loop of the low dropout linear regulator takes a relatively long time to stabilize, which results in the problem of weak transient response ability of the current low dropout linear regulator. Summary of the Invention

[0004] In view of the above problems, embodiments of the present application provide a voltage output circuit, a chip, and an electronic device to solve the above technical problems.

[0005] In a first aspect, an embodiment of the present application provides a voltage output circuit, including:

[0006] The voltage output circuit is characterized by including:

[0007] An output module, the output module includes an output transistor and a feedback resistor unit. The output transistor and the feedback resistor unit are connected in series between a power supply terminal and a ground terminal. The feedback resistor unit is used to output a first feedback voltage and a second feedback voltage, and the first feedback voltage is less than the second feedback voltage;

[0008] A main control module, the main control module is used to pull up the control terminal voltage of the output transistor when the first feedback voltage is less than a preset reference voltage, and pull down the control terminal voltage of the output transistor when the second feedback voltage is greater than the preset reference voltage;

[0009] An auxiliary control module, the auxiliary control module is used to control the change speed of the control terminal voltage of the output transistor according to the feedback voltage;

[0010] Wherein, the magnitude of the feedback voltage is positively correlated with the magnitude of the output voltage provided by the output module, and the change speed of the control terminal voltage of the output transistor is negatively correlated with the magnitude of the feedback voltage.

[0011] In a second aspect, an embodiment of the present application further provides a chip, including the above voltage output circuit.

[0012] In a third aspect, an embodiment of the present application further provides an electronic device, including the above chip or voltage output circuit.

[0013] In the present application, the main control module controls the control terminal voltage of the output transistor according to the first feedback voltage, the second feedback voltage, and a preset reference voltage, so that the output voltage fluctuates between a first set value and a second set value. At the same time, since the auxiliary control module can control the change speed of the control terminal voltage of the output transistor according to the feedback voltage, and the magnitude of the feedback voltage is positively correlated with the magnitude of the output voltage provided by the output module, and the change speed of the control terminal voltage of the output transistor is negatively correlated with the magnitude of the feedback voltage, when the voltage output circuit is started or the output voltage is instantaneously pulled down due to a sudden change in the current demanded by the load, the auxiliary control module can make the output voltage quickly rise to within the range between the first preset value and the second preset value, which is ultimately beneficial to improving the startup speed and transient response ability of the voltage output circuit.

[0014] These aspects or other aspects of the present application will be more clearly understood in the following description of the embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following drawings are only some embodiments of the present application. For those skilled in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0016] Figure 1 Shows a schematic diagram of a low dropout linear regulator in the related art.

[0017] Figure 2 Shows a schematic diagram of a voltage output circuit in an embodiment of the present application.

[0018] Figure 3 Shows another schematic diagram of a voltage output circuit in an embodiment of the present application.

[0019] Figure 4 Shows a schematic diagram of the changes in the first feedback voltage, the second feedback voltage, and the output voltage in an embodiment of the present application.

[0020] Figure 5 Shows a schematic diagram of the changes in the feedback voltage, the first feedback voltage, the second feedback voltage, the output voltage, and the control terminal voltage of the output transistor in an embodiment of the present application.

[0021] Figure 6 Another schematic diagram of the voltage output circuit in the embodiment of the present application is shown.

[0022] Figure 7 Another schematic diagram of the voltage output circuit in the embodiment of the present application is shown.

[0023] Figure 8 Another schematic diagram of the voltage output circuit in the embodiment of the present application is shown.

[0024] Figure 9 A schematic diagram of the charge pump unit in the embodiment of the present application is shown.

[0025] Figure 10 Another schematic diagram of the charge pump unit in the embodiment of the present application is shown.

[0026] Figure 11 Another schematic diagram of the voltage output circuit in the embodiment of the present application is shown.

[0027] Figure 12 Another schematic diagram of the voltage output circuit in the embodiment of the present application is shown.

[0028] Figure 13 Another schematic diagram of the voltage output circuit in the embodiment of the present application is shown.

[0029] Figure 14 A schematic diagram of the auxiliary control module in the embodiment of the present application is shown.

[0030] Figure 15 Another schematic diagram of the auxiliary control module in the embodiment of the present application is shown.

[0031] Figure 16 Another schematic diagram of the auxiliary control module in the embodiment of the present application is shown.

[0032] Figure 17 Another schematic diagram of the auxiliary control module in the embodiment of the present application is shown.

[0033] Figure 18 Another schematic diagram of the auxiliary control module in the embodiment of the present application is shown.

[0034] Wherein, 10 is the output module, 11 is the feedback resistance unit, 20 is the main control module, 21 is the control unit, 22 is the charge pump unit, 23 is the pull-down unit, 30 is the auxiliary control module, 31 is the current control unit, 32 is the oscillation unit, 321 is the charge and discharge sub-unit, 322 is the comparison sub-unit, and 323 is the logic sub-unit;

[0035] Output transistor M0, first resistor R1, second resistor R2, output voltage VOUT, power supply terminal VDD, ground terminal GND, control terminal voltage VCTRL of the output transistor, preset reference voltage VREF, first feedback voltage VFB1, second feedback voltage VFB2, feedback voltage VFB, first setting value Vth1, second setting value Vth2;

[0036] First comparator COMP1, second comparator COMP2, first switch S1, second switch S2, third switch S3, fourth switch S4, fifth switch S5, third capacitor C3, fourth capacitor C4, first clock signal CLK1, second clock signal CLK2, boosting voltage VH, first transistor M1, second transistor M2, third transistor M3, fourth transistor M4;

[0037] First current source I1, second current source I2, first capacitor C1, second capacitor C2, first PMOS transistor MP1, second PMOS transistor MP2, third PMOS transistor MP3, fourth PMOS transistor MP4, fifth PMOS transistor MP5, sixth PMOS transistor MP6, seventh PMOS transistor MP7, eighth PMOS transistor MP8, first NMOS transistor MN1, second NMOS transistor MN2, third NMOS transistor MN3, fourth NMOS transistor MN4, fifth NMOS transistor MN5, sixth NMOS transistor MN6, seventh NMOS transistor MN7, first node m1, second node m2, third node m3, fourth node m4;

[0038] Charging current Iref, clock signal CLK, charge-discharge voltage signal VC, first charge-discharge voltage signal VC1, second charge-discharge voltage signal VC2, bias voltage VB, level signal VHL, first level signal VHL1, second level signal VHL2, first inverter INV1, second inverter INV2, first NAND gate NAND1, second NAND gate NAND2. Detailed implementation manners

[0039] The following details the implementation manners of the present application. The examples of the implementation manners are shown in the drawings, where the same or similar reference numerals represent the same or similar elements or elements with the same or similar functions throughout. The implementation manners described below with reference to the drawings are exemplary and are only used to explain the present application and should not be construed as a limitation to the present application.

[0040] To enable those skilled in the art to better understand the solution of this application, the following will clearly and completely describe the technical solutions in the embodiments of this application with reference to the accompanying drawings in the embodiments of this application. Obviously, the described embodiments are only a part of the embodiments of this application, rather than all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative efforts belong to the scope protected by this application.

[0041] In the embodiments of this application, it should be noted that, in this text, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations.

[0042] Moreover, the term "including", "comprising" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed, or further includes elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "including one..." does not exclude the existence of additional identical elements in the process, method, article or device including the said element.

[0043] In the description of the embodiments of this application, words such as "example" or "for example" are used to represent examples, explanations or descriptions. Any embodiment or design solution described as "for example" or "example" in the embodiments of this application is not construed as being more preferred or having more advantages than another embodiment or design solution. The use of words such as "example" or "for example" is intended to present relative concepts in a clear manner.

[0044] In addition, "a plurality of" in the embodiments of this application means two or more. In view of this, "a plurality of" in the embodiments of this application can also be understood as "at least two". "At least one" can be understood as one or more, for example, understood as one, two or more. For example, including at least one means including one, two or more, and does not limit which ones are included. For example, including at least one of A, B, and C, then what can be included are A, B, C, A and B, A and C, B and C, or A and B and C.

[0045] It should be noted that in the embodiments of this application, "and / or" describes the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist simultaneously, and B exists alone. In addition, the character " / ", unless otherwise specified, generally represents an "or" relationship between the front and rear associated objects.

[0046] It should be noted that in the embodiments of the present application, "connection" can be understood as electrical connection, and the connection of two electrical components can be a direct or indirect connection between the two electrical components. For example, when A is connected to B, it can be a direct connection between A and B, or an indirect connection between A and B through one or more other electrical components.

[0047] In the embodiments of the present application, the control terminal of each transistor is the gate, the first pole / first terminal of each transistor is one of the source and the drain, and the second pole / second terminal of each transistor is the other of the source and the drain. Since the source and drain of a transistor can be symmetric in structure, there may be no difference in their structures. That is to say, there may be no difference in the structures of the first pole / first terminal and the second pole / second terminal of the transistors in the embodiments of the present application. Exemplarily, when the transistor is a P-type transistor, the first pole / first terminal of the transistor is the source, and the second pole / second terminal is the drain; Exemplarily, when the transistor is an N-type transistor, the first pole / first terminal of the transistor is the source, and the second pole / second terminal is the drain.

[0048] In the circuit structure provided by the embodiments of the present application, nodes such as the first node and the second node do not represent actual existing components, but represent the convergence points of relevant couplings in the circuit diagram. That is to say, these nodes are nodes equivalent to the convergence points of relevant couplings in the circuit diagram.

[0049] Currently, a low-dropout linear regulator is a DC power supply that can output a stable DC voltage. Refer to Figure 1 , Figure 1 which shows a schematic diagram of a low-dropout linear regulator in the related art. Among them, the low-dropout linear regulator includes a power transistor MP, a feedback resistor Rf, and an error amplifier OP. The non-inverting input terminal of the error amplifier OP is connected to a reference voltage Vref, the inverting input terminal of the error amplifier OP is connected to the feedback resistor Rf, and the output terminal of the error amplifier is connected to the gate of the power transistor MP.

[0050] It can be seen that the error amplifier OP performs feedback control on the gate voltage of the power transistor MP according to the feedback voltage output by the feedback resistor Rf. When the feedback loop of the error amplifier OP is stable, the output voltage VOUT can be clamped to the reference voltage Vref according to the virtual short and virtual open characteristics of the error amplifier OP, so as to ensure that the power transistor MP outputs a stable DC voltage.

[0051] However, when the low-dropout linear regulator starts up or the output voltage VOUT is instantaneously pulled down due to a sudden change in the current demanded by the load, the feedback loop of the error amplifier OP takes a relatively long time to stabilize, which results in the problems of slow start-up speed and weak transient response ability of the current low-dropout linear regulator.

[0052] To this end, the present application provides a voltage output circuit, a chip, and an electronic device, which will be described in detail below.

[0053] First, refer to Figure 2 , Figure 2 which shows a schematic diagram of a voltage output circuit in an embodiment of the present application. The voltage output circuit includes an output module 10, a main control module 20, and an auxiliary control module 30.

[0054] Specifically, the output module 10 includes an output transistor M0 and a feedback resistance unit 11. The second end of the output transistor M0 is connected to the power supply terminal VDD. The first end of the output transistor M0 is connected to the first end of the feedback resistance unit 11. The second end of the feedback resistance unit 11 is connected to the ground terminal GND. That is, the output transistor M0 and the feedback resistance unit 11 are connected in series between the power supply terminal VDD and the ground terminal GND. During the operation of the voltage output circuit, the output transistor M0 can be regarded as a variable resistor controlled by the main control module 20. The main control module 20 controls the resistance value of the output transistor M0, so that the first end of the output transistor M0 can provide an output voltage VOUT.

[0055] It should be noted that, in the embodiment of the present application, the output transistor M0 is an N-type transistor (such as an NMOS transistor). The feedback resistance unit 11 can output a first feedback voltage VFB1 and a second feedback voltage VFB2, and the first feedback voltage VFB1 is less than the second feedback voltage VFB2, so as to facilitate the main control module 20 to control the control terminal voltage VCTRL of the output transistor M0 according to the first feedback voltage VFB1 and the second feedback voltage VFB2.

[0056] For example, refer to Figure 3 , Figure 3 which shows another schematic diagram of the voltage output circuit in an embodiment of the present application. The feedback resistance unit 11 includes a first resistor R1 and a second resistor R2. The output transistor M0, the first resistor R1, and the second resistor R2 are connected in series in sequence. The node A between the first resistor R1 and the output transistor M0 can provide the second feedback voltage VFB2, and the node B between the second resistor R2 and the first resistor R1 can provide the first feedback voltage VFB1.

[0057] It can be understood that the implementation manner of the feedback resistance unit 11 is not limited to this. For example, the feedback resistance unit 11 can also be provided with more series-connected and / or parallel-connected resistors.

[0058] The main control module 20 can control the control terminal voltage VCTRL of the output transistor M0 according to the first feedback voltage VFB1, the second feedback voltage VFB2, and the preset reference voltage VREF, so as to change the on-resistance of the output transistor M0 and ensure that the magnitude of the output voltage VOUT provided by the output transistor M0 meets the requirements. Specifically, when the first feedback voltage VFB1 is less than the preset reference voltage VREF, the main control module 20 can pull up the control terminal voltage VCTRL of the output transistor M0, and when the second feedback voltage VFB2 is greater than the preset reference voltage VREF, the main control module 20 can pull down the control terminal voltage VCTRL of the output transistor M0.

[0059] For example, referring to Figure 4 , Figure 4 shows a schematic diagram of the changes in the first feedback voltage VFB1, the second feedback voltage VFB2, and the output voltage VOUT in an embodiment of the present application. Since the first feedback voltage VFB1 is less than the second feedback voltage VFB2, when the first feedback voltage VFB1 is less than the preset reference voltage VREF, it indicates that the output voltage VOUT provided by the output transistor M0 is less than the first set value Vth1. At this time, the main control module 20 can raise the control terminal voltage VCTRL of the output transistor M0, so that the on-resistance of the output transistor M0 decreases, and thus the output voltage VOUT can be raised; conversely, when the second feedback voltage VFB2 is greater than the preset reference voltage VREF, it indicates that the output voltage VOUT provided by the output transistor M0 is greater than the second set value Vth2. At this time, the main control module 20 can lower the control terminal voltage VCTRL of the output transistor M0, and the on-resistance of the output transistor M0 increases, so that the output voltage VOUT can be lowered.

[0060] It can be seen that the output voltage VOUT fluctuates between the first set value Vth1 and the second set value Vth2. Therefore, when the first set value Vth1 and the second set value Vth2 are relatively close, it can be considered that the output voltage VOUT provided by the output transistor M0 is a DC voltage.

[0061] The auxiliary control module 30 can control the changing speed of the control terminal voltage VCTRL of the output transistor M0 according to the feedback voltage VFB. Among them, the magnitude of the feedback voltage VFB is positively correlated with the magnitude of the output voltage VOUT provided by the output module 10, and the changing speed of the control terminal voltage VCTRL of the output transistor M0 is negatively correlated with the magnitude of the feedback voltage VFB.

[0062] For example, referring to Figure 5 , Figure 5It shows a schematic diagram of the changes in the feedback voltage VFB, the first feedback voltage VFB1, the second feedback voltage VFB2, the output voltage VOUT, and the control terminal voltage VCTRL of the output transistor M0 in an embodiment of the present application. After the voltage output circuit is started, the feedback voltage VFB, the first feedback voltage VFB1, the second feedback voltage VFB2, and the output voltage VOUT are relatively small. Since the change speed of the control terminal voltage VCTRL of the output transistor M0 is negatively correlated with the magnitude of the feedback voltage VFB, the auxiliary control module 30 can increase the change speed of the control terminal voltage VCTRL of the output transistor M0, so that the control terminal voltage VCTRL of the output transistor M0 is quickly pulled up, thereby enabling the output voltage VOUT to rise rapidly, so as to achieve the purpose of quickly starting the voltage output circuit.

[0063] When the current demanded by the load connected to the voltage output circuit suddenly changes, causing the output voltage VOUT to be instantaneously pulled down, the feedback voltage VFB, the first feedback voltage VFB1, and the second feedback voltage VFB2 are also instantaneously pulled down. Since the change speed of the control terminal voltage VCTRL of the output transistor M0 is negatively correlated with the magnitude of the feedback voltage VFB, the auxiliary control module 30 can also increase the change speed of the control terminal voltage VCTRL of the output transistor M0 at this time, so that the control terminal voltage VCTRL of the output transistor M0 is quickly pulled up, thereby enabling the output voltage VOUT to quickly recover to within the range between the first preset value and the second preset value.

[0064] It can be seen that in the present application, the main control module 20 controls the control terminal voltage VCTRL of the output transistor M0 according to the first feedback voltage VFB1, the second feedback voltage VFB2, and the preset reference voltage VREF, so that the output voltage VOUT fluctuates between the first set value Vth1 and the second set value Vth2. At the same time, since the auxiliary control module 30 can control the change speed of the control terminal voltage VCTRL of the output transistor M0 according to the feedback voltage VFB, and the magnitude of the feedback voltage VFB is positively correlated with the magnitude of the output voltage VOUT provided by the output module 10, and the change speed of the control terminal voltage VCTRL of the output transistor M0 is negatively correlated with the magnitude of the feedback voltage VFB, when the voltage output circuit is started or the output voltage VOUT is instantaneously pulled down due to the sudden change in the current demanded by the load, the output voltage VOUT can be quickly increased to within the range between the first preset value and the second preset value, thereby improving the start-up speed and transient response ability of the voltage output circuit.

[0065] It should be noted that the change rate of the control terminal voltage VCTRL of the output transistor M0 refers to the change value of the control terminal voltage VCTRL per unit time. The larger the change value of the control terminal voltage VCTRL per unit time, the faster the change rate of the control terminal voltage VCTRL of the output transistor M0. Conversely, the slower the change rate of the control terminal voltage VCTRL of the output transistor M0. At the same time, in the embodiments of the present application, the feedback voltage VFB can be a voltage additionally provided by the feedback resistance unit 11 in addition to the first feedback voltage VFB1 and the second feedback voltage VFB2, or it can be one of the first feedback voltage VFB1 or the second feedback voltage VFB2. For example, in Figure 3 it is possible to use the second feedback voltage VFB2 as the voltage of the input auxiliary control module 30.

[0066] In some embodiments of the present application, refer to Figure 6 , Figure 6 which shows another schematic diagram of the voltage output circuit in the embodiments of the present application. Among them, the main control module 20 includes a control unit 21, a charge pump unit 22, and a pull-down unit 23. When the first feedback voltage VFB1 is less than the preset reference voltage VREF, the control unit 21 controls the charge pump unit 22 to pull up the control terminal voltage VCTRL of the output transistor M0; when the second feedback voltage VFB2 is greater than the preset reference voltage VREF, the control unit 21 controls the pull-down unit 23 to pull down the control terminal voltage VCTRL of the output transistor M0.

[0067] It should be noted that the magnitudes of the first feedback voltage VFB1 and the second feedback voltage VFB2 are positively correlated with the output voltage VOUT provided by the output transistor M0. Therefore, when the first feedback voltage VFB1 is less than the preset reference voltage VREF, it indicates that the output voltage VOUT is less than the first set value Vth1. Therefore, the control unit 21 can control the charge pump unit 22 to pull up the control terminal voltage VCTRL of the output transistor M0 when the first feedback voltage VFB1 is less than the preset reference voltage VREF, so that the on-resistance of the output transistor M0 is reduced, thereby raising the output voltage VOUT to the second set value Vth2. When the second feedback voltage VFB2 is greater than the preset reference voltage VREF, it indicates that the output voltage VOUT is greater than the second set value Vth2. Therefore, the control unit 21 can control the pull-down unit 23 to pull down the control terminal voltage VCTRL of the output transistor M0 when the second feedback voltage VFB2 is greater than the preset reference voltage VREF, so that the on-resistance of the output transistor M0 is increased, thereby pulling down the output voltage VOUT to the first set value Vth1.

[0068] It can be seen that the control unit 21 can limit the output voltage VOUT between the first set value Vth1 and the second set value Vth2 by controlling the charge pump unit 22 and the pull-down unit 23. When the first set value Vth1 and the second set value Vth2 are relatively close, it can be considered that the output voltage VOUT provided by the output transistor M0 is a DC voltage.

[0069] In some embodiments of the present application, the auxiliary control module 30 can output a clock signal CLK according to the feedback voltage VFB, and the clock signal CLK is used to control the charge pump unit 22; wherein, the frequency of the clock signal CLK is negatively correlated with the magnitude of the feedback voltage VFB.

[0070] It should be noted that during the rising process of the boosted voltage VH output by the charge pump unit 22, the boosted voltage VH rises gradually, and the rising speed of the boosted voltage VH will be affected by the frequency of the clock signal CLK. The higher the frequency of the clock signal CLK, the faster the rising speed of the boosted voltage VH output by the charge pump unit 22. On the contrary, the smaller the frequency of the clock signal CLK, the slower the rising speed of the boosted voltage VH output by the charge pump unit 22.

[0071] In the above embodiments, since the frequency of the clock signal CLK is negatively correlated with the magnitude of the feedback voltage VFB, when the voltage output circuit is started or the output voltage VOUT drops instantaneously, the feedback voltage VFB is relatively small. At this time, the auxiliary control module 30 can output a clock signal CLK with a higher frequency, so that the charge pump unit 22 can output a rapidly rising boosted voltage VH in response to the clock signal CLK with a higher frequency, thereby using the rapidly rising boosted voltage VH to rapidly raise the control terminal voltage VCTRL of the output transistor M0, and finally improving the startup speed and transient response ability of the voltage output circuit.

[0072] As an exemplary embodiment of the control unit 21, refer to Figure 7 , Figure 7 shows another schematic diagram of the voltage output circuit in the embodiments of the present application. Among them, the control unit 21 includes a first switch S1, a second switch S2, and a first comparator COMP1; the first end of the first switch S1 is used to access the first feedback voltage VFB1, and the second end of the first switch S1 is connected to the inverting input terminal of the first comparator COMP1; the first end of the second switch S2 is used to access the second feedback voltage VFB2, and the second end of the second switch S2 is connected to the inverting input terminal of the first comparator COMP1; the non-inverting input terminal of the first comparator COMP1 is used to access the preset reference voltage VREF.

[0073] It should be noted that the output terminal of the first comparator COMP1 can output an enable signal EN, and the enable signal EN can control the first switch S1, the second switch S2, the charge pump unit 22, and the pull-down unit 23. For example, when the enable signal EN is at a high level, the first switch S1 is closed, the second switch S2 is open, the charge pump unit 22 is turned on, the pull-down unit 23 is turned off, and the charge pump unit 22 pulls up the control terminal voltage VCTRL of the output transistor M0; when the enable signal EN is at a low level, the second switch S2 is closed, the first switch S1 is open, the charge pump unit 22 is turned off, the pull-down unit 23 is turned on, and the pull-down unit 23 pulls down the control terminal voltage VCTRL of the output transistor M0.

[0074] For example, when the voltage output circuit starts, the first feedback voltage VFB1 and the second feedback voltage VFB2 are small, the first comparator COMP1 outputs a high-level signal, the first switch S1 is closed, the second switch S2 is open, the charge pump unit 22 is turned on, the pull-down unit 23 is turned off. At this time, the first comparator COMP1 compares the magnitudes of the first feedback voltage VFB1 and the preset reference voltage VREF, and the charge pump unit 22 pulls up the control terminal voltage VCTRL of the output transistor M0, causing the output voltage VOUT, the first feedback voltage VFB1, and the second feedback voltage VFB2 to rise.

[0075] When the first feedback voltage VFB1 rises to the preset reference voltage VREF, according to the resistor voltage division, the magnitude of the second feedback voltage VFB2 is:

[0076]

[0077] At this time, the first comparator COMP1 outputs a low-level signal, the second switch S2 is closed, the first switch S1 is open, the charge pump unit 22 is turned off, the pull-down unit 23 is turned on. The first comparator COMP1 compares the magnitudes of the second feedback voltage VFB2 and the preset reference voltage VREF, and the pull-down unit 23 pulls down the control terminal voltage VCTRL of the output transistor M0, causing the output voltage VOUT, the first feedback voltage VFB1, and the second feedback voltage VFB2 to decrease.

[0078] When the second feedback voltage VFB2 drops to the preset reference voltage VREF, according to the resistor voltage division, the magnitude of the first feedback voltage VFB1 is:

[0079]

[0080] At this time, the first comparator COMP1 outputs a high-level signal, the first switch S1 is closed, the second switch S2 is opened, the charge pump unit 22 is turned on, the pull-down unit 23 is turned off, the first comparator COMP1 compares the magnitude of the first feedback voltage VFB1 with the preset reference voltage VREF, and the charge pump unit 22 pulls up the control terminal voltage VCTRL of the output transistor M0, so that the output voltage VOUT, the first feedback voltage VFB1, and the second feedback voltage VFB2 increase.

[0081] The above process is repeatedly executed. It can be seen that the variation range of the output voltage VOUT provided by the output transistor M0 is VREF~VREF*(R1+R2) / R1 (that is, the first preset value is VREF, and the second preset value is VREF*(R1+R2) / R1). Therefore, by setting the ratio of the first resistor R1 to the second resistor R2, the output voltage VOUT can be stabilized within a small fluctuation range.

[0082] As another exemplary embodiment of the control unit 21, refer to Figure 8 , Figure 8 shows another schematic diagram of the voltage output circuit in the embodiment of the present application. Among them, the control unit 21 includes a first comparator COMP1 and a second comparator COMP2; the inverting input terminal of the first comparator COMP1 is used to access the first feedback voltage VFB1, the non-inverting input terminal of the first comparator COMP1 is used to access the preset reference voltage VREF, and the output terminal of the first comparator COMP1 is connected to the charge pump unit 22; the non-inverting input terminal of the second comparator COMP2 is used to access the second feedback voltage VFB2, the inverting input terminal of the second comparator COMP2 is used to access the preset reference voltage VREF, and the output terminal of the second comparator COMP2 is connected to the pull-down unit 23.

[0083] For example, when the voltage output circuit is started, the output voltage VOUT, the first feedback voltage VFB1, and the second feedback voltage VFB2 are small. At this time, the first comparator COMP1 outputs a high-level signal, and the second comparator COMP2 outputs a low-level signal. Therefore, the charge pump unit 22 is turned on, the pull-down unit 23 is turned off, and the charge pump unit 22 pulls up the control terminal voltage VCTRL of the output transistor M0, so that the output voltage VOUT, the first feedback voltage VFB1, and the second feedback voltage VFB2 increase.

[0084] When the first feedback voltage VFB1 rises to the preset reference voltage VREF, according to the resistor voltage division, the magnitude of the second feedback voltage VFB2 is:

[0085]

[0086] At this time, the first comparator COMP1 outputs a low-level signal, the second comparator COMP2 outputs a high level, the charge pump unit 22 is turned off, the pull-down unit 23 is turned on, and the pull-down unit 23 pulls down the control terminal voltage VCTRL of the output transistor M0, causing the output voltage VOUT, the first feedback voltage VFB1, and the second feedback voltage VFB2 to decrease.

[0087] When the second feedback voltage VFB2 drops to the preset reference voltage VREF, according to the resistor voltage division, the magnitude of the first feedback voltage VFB1 is:

[0088]

[0089] At this time, the first comparator COMP1 outputs a high-level signal, the second comparator COMP2 outputs a low level, the charge pump unit 22 is turned on, the pull-down unit 23 is turned off, and the charge pump unit 22 pulls up the control terminal voltage VCTRL of the output transistor M0, causing the output voltage VOUT, the first feedback voltage VFB1, and the second feedback voltage VFB2 to increase.

[0090] The above process is repeatedly executed. It can be seen that the output voltage VOUT provided by the output transistor M0 also varies within the range of VREF to VREF*(R1 + R2) / R1.

[0091] It can be understood that the above is only an exemplary embodiment of the control unit 21 of the present application. Those skilled in the art can make equivalent modified designs under the guidance of the present application. For example, for Figure 8 the embodiment, a logic circuit (such as an AND gate, a NOR gate, a NOT gate, etc.) can also be set, and the charge pump unit 22 and / or the pull-down unit 23 are controlled to be turned on or off according to the level signals output by the first comparator COMP1 and the second comparator COMP2 through the logic circuit.

[0092] As an exemplary embodiment of the charge pump unit 22, refer to Figure 9 , Figure 9FIG. 0 shows a schematic diagram of a charge pump unit 22 in an embodiment of the present application. The charge pump unit 22 includes a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a third capacitor C3, a fourth capacitor C4, a third switch S3, and a fourth switch S4. The first end of the first transistor M1 is connected to the power supply terminal VDD, the second end of the first transistor M1 is connected to the first end of the second transistor M2, and the second end of the second transistor M2 is connected to the second end of the fourth transistor M4. The first end of the third transistor M3 is connected to the power supply terminal VDD, and the second end of the third transistor M3 is connected to the first end of the fourth transistor M4. The control terminals of the first transistor M1 and the second transistor M2 are connected to node C. The control terminals of the third transistor M3 and the fourth transistor M4 are connected to node D. The first plate of the third capacitor C3 is connected to node C, and the second plate of the third capacitor C3 receives the first clock signal CLK1. The first plate of the fourth capacitor C4 is connected to node D, and the second plate of the fourth capacitor C4 receives the second clock signal CLK2. A node E between the second transistor M2 and the fourth transistor M4 is used to output a boosted voltage VH. The first end of a fifth switch S5 is connected to node E, and the second end of the fifth switch S5 can output the boosted voltage VH.

[0093] It should be noted that the third switch S3, the fourth switch S4, and the fifth switch S5 can change their switch states in response to an enable signal EN output by the control unit 21. When the enable signal EN output by the control unit 21 controls the third switch S3, the fourth switch S4, and the fifth switch S5 to close, the charge pump unit 22 is turned on. Conversely, when the enable signal EN output by the control unit 21 controls the third switch S3, the fourth switch S4, and the fifth switch S5 to open, the charge pump unit 22 is turned off.

[0094] For example, taking the high-level voltage of the first clock signal CLK1 and the second clock signal CLK2 as the first preset voltage VDD, the first transistor M1 and the third transistor M3 are NMOS transistors, and the second transistor M2 and the fourth transistor M4 are PMOS transistors as an example. When the charge pump unit 22 is turned on, if the first clock signal CLK1 is at a high level and the second clock signal CLK2 is at a low level, the voltage of node C is boosted to: 2VDD, and the voltage of node D changes to: VDD. Therefore, the third transistor M3 is turned on and the fourth transistor M4 is turned off, the first transistor M1 is turned off and the second transistor M2 is turned on. The boosted voltage VH output by the third capacitor C3 at node E through the second transistor M2 is: 2VDD, and the fourth capacitor C4 is charged through the third transistor M3.

[0095] Conversely, when the first clock signal CLK1 is at a low level and the second clock signal CLK2 is at a high level, the voltage of node C changes to: VDD, and the voltage of node D changes to: 2VDD. Therefore, the third transistor M3 is cut off and the fourth transistor M4 is turned on. The first transistor M1 is turned on and the second transistor M2 is cut off. The boosted voltage VH output at node E by the fourth capacitor C4 through the fourth transistor M4 is: 2VDD, and the third capacitor C3 is charged through the first transistor M1.

[0096] It can be seen that since the first clock signal CLK1 and the second clock signal CLK2 are non-overlapping clock signals CLK, the charging and discharging of the third capacitor C3 and the fourth capacitor C4 can be controlled alternately, and finally a boosted voltage VH of 2 times VDD is output at node E, so as to raise the control terminal voltage VCTRL of the output transistor M0 by the boosted voltage VH.

[0097] It can be understood that the implementation manner of the charge pump unit 22 is not limited to, for example, the charge pump unit 22 can also adopt a regulated charge pump; for another example, refer to Figure 10 , Figure 10 shows another schematic diagram of the charge pump unit 22 in the embodiment of the present application. Among them, the charge pump unit 22 includes a switch S01, a switch S02, a switch S03, a switch S04, a capacitor Cf, and a capacitor CL. The charging and discharging of the capacitor Cf and the capacitor CL are alternately controlled by the switches S01 to S04 to output the boosted voltage VH.

[0098] As an exemplary embodiment of the pull-down unit 23, refer to Figure 11 , Figure 11 shows another schematic diagram of the voltage output circuit in the embodiment of the present application. Among them, the pull-down unit 23 includes a resistor R0 and a switch S0. The resistor R0 and the switch S0 are connected in series between the control terminal of the output transistor M0 and the ground terminal GND. When the enable signal EN output by the control unit 21 controls the switch S0 of the pull-down unit 23 to close, the pull-down unit 23 is turned on and can pull down the control terminal voltage VCTRL of the output transistor M0.

[0099] It should be noted that in order to avoid the phenomenon that the control terminal voltage VCTRL of the output transistor M0 is pulled down or raised instantaneously, refer to Figure 12 , Figure 12Another schematic diagram of the voltage output circuit in the embodiment of the present application is shown. Among them, the output module 10 further includes a voltage stabilizing capacitor C0, and the voltage stabilizing capacitor C0 is connected between the control terminal of the output transistor M0 and the ground terminal GND. When the charge pump unit 22 is turned on to output the boosting voltage VH, the boosting voltage VH charges the voltage stabilizing capacitor C0, causing the voltage VCTRL at the control terminal of the output transistor M0 to gradually rise; conversely, when the pulling-down unit 23 is turned on, the pulling-down unit 23 discharges the voltage stabilizing capacitor C0, causing the voltage VCTRL at the control terminal of the output transistor M0 to gradually fall, thereby avoiding the phenomenon of sudden change in the voltage VCTRL at the control terminal of the output transistor M0.

[0100] In some embodiments of the present application, refer to Figure 13 , Figure 13 Another schematic diagram of the voltage output circuit in the embodiment of the present application is shown. Among them, the auxiliary control module 30 includes a current control unit 31 and an oscillation unit 32; the current control unit 31 is used to output a charging current Iref according to the feedback voltage VFB; the oscillation unit 32 is used to output a clock signal CLK according to the charging current Iref; wherein, the magnitude of the charging current Iref is negatively correlated with the magnitude of the feedback voltage VFB, and the magnitude of the charging current Iref is positively correlated with the frequency of the clock signal CLK.

[0101] It should be noted that when the voltage output circuit starts or the output voltage VOUT drops instantaneously, the feedback voltage VFB is small. Since the magnitude of the charging current Iref is negatively correlated with the magnitude of the feedback voltage VFB, at this time, the current control unit 31 can output a larger charging current Iref; at the same time, since the magnitude of the charging current Iref is positively correlated with the frequency of the clock signal CLK, the oscillation unit 32 can output a clock signal CLK with a higher frequency, so that the charge pump unit 22 can output a rapidly rising boosting voltage VH in response to the clock signal CLK with a higher frequency, thereby rapidly raising the voltage VCTRL at the control terminal of the output transistor M0.

[0102] As an exemplary embodiment of the current control unit 31, refer to Figure 14 , Figure 14 A schematic diagram of the auxiliary control module 30 in the embodiment of the present application is shown. Among them, the current control unit 31 includes a first current source I1, a first PMOS transistor MP1, a second PMOS transistor MP2, a first NMOS transistor MN1, a second NMOS transistor MN2, a third NMOS transistor MN3, a third PMOS transistor MP3, and a second current source I2.

[0103] Specifically, the first end of the first current source I1 is connected to the second end of the first PMOS transistor MP1, and the second end of the first current source I1 is connected to the ground terminal GND; the first end of the first PMOS transistor MP1 is connected to the power supply terminal VDD, and the second end of the first PMOS transistor MP1 is connected to the control terminal of the first PMOS transistor MP1; the first end of the second PMOS transistor MP2 is connected to the power supply terminal VDD, and the control terminal of the second PMOS transistor MP2 is connected to the control terminal of the first PMOS transistor MP1; the second end of the first NMOS transistor MN1 is connected to the second end of the second PMOS transistor MP2, the first end of the first NMOS transistor MN1 is connected to the ground terminal GND through a resistor R, and the control terminal of the first NMOS transistor MN1 is used to access the feedback voltage VFB; the second end of the second NMOS transistor MN2 is connected to the second end of the second PMOS transistor MP2, the first end of the second NMOS transistor MN2 is connected to the ground terminal GND, and the control terminal of the second NMOS transistor MN2 is connected to the second end of the second NMOS transistor MN2; the second end of the third NMOS transistor MN3 is connected to the second end of the third PMOS transistor MP3, the first end of the third NMOS transistor MN3 is connected to the ground terminal GND, and the control terminal of the third NMOS transistor MN3 is connected to the control terminal of the second NMOS transistor MN2; the first end of the third PMOS transistor MP3 is connected to the power supply terminal VDD, the second end of the third PMOS transistor MP3 is connected to the first end of the second current source I2, and the second end of the second current source I2 is connected to the ground terminal GND.

[0104] It should be noted that the first PMOS transistor MP1 and the second PMOS transistor MP2 form a current mirror, and the second NMOS transistor MN2 and the third NMOS transistor MN3 form a current mirror. Taking the current mirror ratio of the first PMOS transistor MP1 and the second PMOS transistor MP2 as 1:1 and the current mirror ratio of the second NMOS transistor MN2 and the third NMOS transistor MN3 as 1:1 as an example, it can be known that the magnitudes of the currents flowing through the second NMOS transistor MN2 and the third NMOS transistor MN3 are:

[0105] IN2 = IN3 = I1 - IN1

[0106] Where, IN1 is the current flowing through the first NMOS transistor MN1, IN2 is the current flowing through the second NMOS transistor MN2, IN3 is the current flowing through the third NMOS transistor MN3, and I1 is the magnitude of the current of the first current source I1.

[0107] Therefore, the magnitude of the charging current Iref flowing through the third PMOS transistor MP3 is:

[0108] Iref = I2 + IN3 = I2 + (I1 - IN1)

[0109] Where, I2 is the magnitude of the current of the second current source I2.

[0110] As can be seen from the above formula, since the first NMOS transistor MN1 is a high-level conduction transistor, the current flowing through the first NMOS transistor MN1 is positively correlated with the magnitude of the feedback voltage VFB (the second feedback voltage VFB2). Therefore, the larger the feedback voltage VFB, the larger the current flowing through the first NMOS transistor MN1, and the smaller the charging current Iref; conversely, the smaller the feedback voltage VFB, the smaller the current flowing through the first NMOS transistor MN1, and the larger the charging current Iref.

[0111] Therefore, in the above embodiment, the magnitude of the charging current Iref is negatively correlated with the magnitude of the feedback voltage VFB. Combining the fact that the magnitude of the charging current Iref is positively correlated with the frequency of the clock signal CLK, it can be known that the auxiliary control module 30 can output a clock signal CLK whose frequency is negatively correlated with the magnitude of the feedback voltage VFB.

[0112] In some embodiments of the present application, referring to Figure 15 , Figure 15 shows another schematic diagram of the auxiliary control module 30 in the embodiments of the present application. Among them, the oscillation unit 32 includes a charge and discharge sub-unit 321, a comparison sub-unit 322, and a logic sub-unit 323; the charge and discharge sub-unit 321 charges based on the charging current Iref and outputs a periodically changing charge and discharge voltage signal VC; the comparison sub-unit 322 is used to output a periodically changing level signal VHL according to the periodically changing charge and discharge voltage signal VC; the logic sub-unit 323 is used to output a clock signal CLK according to the periodically changing level signal VHL.

[0113] It should be noted that since the charge and discharge sub-unit 321 charges based on the charging current Iref, the larger the charging current Iref, the shorter the time for the charge and discharge voltage signal VC to reach the set threshold. Therefore, the periods of the periodically changing charge and discharge voltage signal VC and the level signal VHL are shorter, and the frequency of the clock signal CLK output by the logic sub-unit 323 is higher; conversely, the smaller the charging current Iref, the longer the time for the charge and discharge voltage signal VC to reach the set threshold. Therefore, the periods of the periodically changing charge and discharge voltage signal VC and the level signal VHL are longer, and the frequency of the clock signal CLK output by the logic sub-unit 323 is smaller, so that the oscillation unit 32 can output a clock signal CLK whose frequency is positively correlated with the magnitude of the charging current Iref.

[0114] As an exemplary embodiment of the charge and discharge sub-unit 321, referring to Figure 16 , Figure 16Another schematic diagram of the auxiliary control module 30 in the embodiment of the present application is shown, where the charge and discharge sub-unit 321 includes a fourth PMOS transistor MP4, a fifth PMOS transistor MP5, a sixth PMOS transistor MP6, a fourth NMOS transistor MN4, a fifth NMOS transistor MN5, a first capacitor C1, and a second capacitor C2.

[0115] Specifically, the first end of the fourth PMOS transistor MP4 is connected to the power supply terminal VDD, and the control end of the fourth PMOS transistor MP4 is used to access the bias voltage VB, which is generated based on the charging current Iref; the first end of the fifth PMOS transistor MP5 is connected to the second end of the fourth PMOS transistor MP4, the second end of the fifth PMOS transistor MP5 is connected to the second end of the fourth NMOS transistor MN4, and the first end of the fourth NMOS transistor MN4 is connected to the ground terminal GND; the first end of the first capacitor C1 is connected to the first node m1 between the fifth PMOS transistor MP5 and the fourth NMOS transistor MN4, and the second end of the first capacitor C1 is connected to the ground terminal GND; the first end of the sixth PMOS transistor MP6 is connected to the second end of the fourth PMOS transistor MP4, the second end of the sixth PMOS transistor MP6 is connected to the second end of the fifth NMOS transistor MN5, and the first end of the fifth NMOS transistor MN5 is connected to the ground terminal GND; the first end of the second capacitor C2 is connected to the second node m2 between the sixth PMOS transistor MP6 and the fifth NMOS transistor MN5, and the second end of the second capacitor C2 is connected to the ground terminal GND.

[0116] It should be noted that in the above embodiment, the third PMOS transistor MP3 and the fourth PMOS transistor MP4 form a current mirror structure, and the fourth PMOS transistor MP4 can output the charging current Iref in proportion. The logic sub-unit 323 can output non-overlapping first clock signal CLK1 and second clock signal CLK2. The control ends of the fifth PMOS transistor MP5 and the fourth NMOS transistor MN4 are connected to the first clock signal CLK1, and the control ends of the sixth PMOS transistor MP6 and the fifth NMOS transistor MN5 are connected to the second clock signal CLK2.

[0117] For example, when the first clock signal CLK1 is at a high level and the second clock signal CLK2 is at a low level, the fifth PMOS transistor MP5 and the fifth NMMOS transistor are turned off, while the fourth NMOS transistor MN4 and the sixth PMOS transistor MP6 are turned on. The first capacitor C1 discharges, and the second capacitor C2 charges. When the second charge and discharge voltage signal VC2 output by the second capacitor C2 reaches the set threshold, the comparison sub-unit 322 outputs a changed level signal VHL, and the logic sub-unit 323 changes the first clock signal CLK1 to a low level and the second clock signal CLK2 to a high level.

[0118] When the first clock signal CLK1 is at a low level and the second clock signal CLK2 is at a high level, the fifth PMOS transistor MP5 and the fifth NMOS transistor conduct, while the fourth NMOS transistor MN4 and the sixth PMOS transistor MP6 are cut off. The first capacitor C1 is charged and the second capacitor C2 is discharged. When the first charge-discharge voltage signal VC1 output by the first capacitor C1 reaches a set threshold, the output level signal VHL of the comparison sub-unit 322 changes, and the logic sub-unit 323 changes the first clock signal CLK1 to a high level and the second clock signal CLK2 to a low level.

[0119] The above process is repeatedly executed, so that the first capacitor C1 and the second capacitor C2 are alternately charged and discharged based on the charging current Iref. The first clock signal CLK1 and the second clock signal CLK2 can be output through the comparison sub-unit 322 and the logic sub-unit 323. At the same time, the larger the charging current Iref, the shorter the charging time of the first capacitor C1 and the second capacitor C2. Therefore, the frequencies of the first clock signal CLK1 and the second clock signal CLK2 can be increased; conversely, the smaller the charging current Iref, the longer the charging time of the first capacitor C1 and the second capacitor C2. Therefore, the frequencies of the first clock signal CLK1 and the second clock signal CLK2 can be decreased. Considering that the magnitude of the charging current Iref output by the current control unit 31 is negatively correlated with the feedback voltage VFB, it can be known that the auxiliary control module 30 can output a clock signal CLK whose frequency is negatively correlated with the magnitude of the feedback voltage VFB.

[0120] As an exemplary embodiment of the comparison sub-unit 322, refer to Figure 17 , Figure 17Another schematic diagram of the auxiliary control module 30 in the embodiment of the present application is shown. Among them, the comparison sub-unit 322 includes a seventh PMOS transistor MP7, an eighth PMOS transistor MP8, a sixth NMOS transistor MN6, and a seventh NMOS transistor MN7; a first end of the seventh PMOS transistor MP7 is connected to the power supply terminal VDD, and a control end of the seventh PMOS transistor MP7 is used to access a bias voltage VB; a second end of the sixth NMOS transistor MN6 is connected to the second end of the seventh PMOS transistor MP7, a control end of the sixth NMOS transistor MN6 is connected to the first node m1, and a first end of the sixth NMOS transistor MN6 is connected to the ground terminal GND; a first end of the eighth PMOS transistor MP8 is connected to the power supply terminal VDD, and a control end of the eighth PMOS transistor MP8 is used to access a bias voltage VB; a second end of the seventh NMOS transistor MN7 is connected to the second end of the eighth PMOS transistor MP8, a control end of the seventh NMOS transistor MN7 is connected to the second node m2, and a first end of the seventh NMOS transistor MN7 is connected to the ground terminal GND; a third node m3 between the seventh PMOS transistor MP7 and the sixth NMOS transistor MN6 is used to output a first level signal VHL1, a fourth node m4 between the eighth PMOS transistor MP8 and the seventh NMOS transistor MN7 is used to output a second level signal VHL2, and the logic sub-unit 323 is used to output a first clock signal CLK1 and a second clock signal CLK2 according to the first level signal VHL1 and the second level signal VHL2.

[0121] It should be noted that since the control terminal voltages of the seventh PMOS transistor MP7 and the eighth PMOS transistor MP8 are biased by the bias voltage VB, and the sixth NMOS transistor MN6 is connected to the first charge and discharge voltage signal VC1, and the seventh NMOS transistor MN7 is connected to the second charge and discharge voltage signal VC2. When the first capacitor C1 is charged so that the first charge and discharge voltage signal VC1 reaches the threshold voltage of the sixth NMOS transistor MN6, the sixth NMOS transistor MN6 is turned on, the voltage of the third node m3 is pulled down, and the first level signal VHL1 changes from a high level to a low level. Therefore, the logic sub-unit 323 can change the levels of the first clock signal CLK1 and the second clock signal CLK2 in response to the first level signal VHL1.

[0122] Similarly, when the second capacitor C2 is charged so that the second charge and discharge voltage signal VC2 reaches the threshold voltage of the seventh NMOS transistor MN7, the seventh NMOS transistor MN7 is turned on, the voltage of the fourth node m4 is pulled down, and the second level signal VHL2 changes from a high level to a low level. Therefore, the logic sub-unit 323 can change the levels of the first clock signal CLK1 and the second clock signal CLK2 in response to the second level signal VHL2.

[0123] It can be seen that by determining whether the first charge-discharge voltage signal VC1 and the second charge-discharge voltage signal VC2 reach the set threshold, the comparison subunit 322 can change the levels of the first level signal VHL1 and the second level signal VHL2. Finally, the first clock signal CLK1 and the second clock signal CLK2 can be output through the logic subunit 323.

[0124] In some embodiments of the present application, refer to Figure 18 , Figure 18 shows another schematic diagram of the auxiliary control module 30 in the embodiments of the present application. Among them, the logic subunit 323 includes a first inverter INV1, a second inverter INV2, a first NAND gate NAND1, and a second NAND gate NAND2. The first inverter INV1, the second inverter INV2, the first NAND gate NAND1, and the second NAND gate NAND2 form an RS flip-flop. Therefore, non-overlapping clock signals CLK can be output through the RS flip-flop.

[0125] It should be noted that the above embodiments are intended to clearly illustrate the implementation verification process of the voltage output circuit of the present application. Those skilled in the art can make equivalent modified designs under the guidance of the present application. For example, in the above embodiments, the charge pump unit 22 outputs the boosted voltage VH through the first clock signal CLK1 and the second clock signal CLK2, but this is not limited thereto. The oscillation unit 32 can also output a clock signal CLK, and the charge pump unit 22 outputs the boosted voltage VH through a clock signal CLK; for another example, the comparison subunit 322 can also use a comparator to determine whether the first charge-discharge voltage signal VC1 and the second charge-discharge voltage signal VC2 reach the set threshold, and output the first level signal VHL1 and the second level signal VHL2.

[0126] The embodiments of the present application also provide a chip, which includes the above voltage output circuit. A chip (Integrated Circuit, IC) is also called a chip, and this chip can be, but is not limited to, a SOC (System on Chip, chip-level system) chip, a SIP (system in package, system-level package) chip. Since the chip of the present application has the voltage output circuit described in the above embodiments, it has all the beneficial effects of the voltage output circuit in the above embodiments, which will not be elaborated here.

[0127] An embodiment of the present application further provides an electronic device, which includes a device body and the above-mentioned chip disposed in the device body. The electronic device may be, but is not limited to, a weighing scale, a body fat scale, a nutrition scale, an infrared electronic thermometer, a pulse oximeter, a body composition analyzer, a mobile power supply, a wireless charger, a fast charger, a vehicle charger, an adapter, a display, a USB (Universal Serial Bus) expansion dock, a stylus, a true wireless earphone, a car center control screen, a car, a smart wearable device, a mobile terminal, a smart home device. The smart wearable device includes, but is not limited to, a smart watch, a smart bracelet, and a cervical massager. The mobile terminal includes, but is not limited to, a smart phone, a laptop, a tablet computer, and a POS (point of sales terminal) machine. The smart home device includes, but is not limited to, a smart socket, a smart rice cooker, a smart floor sweeper, and a smart lamp.

[0128] The above are only the preferred embodiments of the present application, and do not impose any formal restrictions on the present application. Although the present application has been disclosed above with preferred embodiments, it is not intended to limit the present application. Any person skilled in the art can make some changes or modifications to the equivalent embodiments by using the disclosed technical content within the scope of the technical solution of the present application. However, as long as the content of the technical solution of the present application is not departed from, any brief modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present application still fall within the scope of the technical solution of the present application.

Claims

1. A voltage output circuit, characterized in that Comprising: An output module, the output module includes an output transistor and a feedback resistor unit, the feedback resistor unit is used to output a first feedback voltage and a second feedback voltage, and the first feedback voltage is less than the second feedback voltage; A main control module, the main control module is used to pull up the control terminal voltage of the output transistor when the first feedback voltage is less than a preset reference voltage, and pull down the control terminal voltage of the output transistor when the second feedback voltage is greater than the preset reference voltage; An auxiliary control module, the auxiliary control module is used to control the change speed of the control terminal voltage of the output transistor according to the feedback voltage.

2. The voltage output circuit according to claim 1, wherein The main control module includes a control unit, a charge pump unit, and a pull-down unit; When the first feedback voltage is less than the preset reference voltage, the control unit controls the charge pump unit to pull up the control terminal voltage of the output transistor; When the second feedback voltage is greater than the preset reference voltage, the control unit controls the pull-down unit to pull down the control terminal voltage of the output transistor.

3. The voltage output circuit according to claim 2, wherein The auxiliary control module is used to output a clock signal according to the feedback voltage, and the clock signal is used to control the charge pump unit; Wherein, the frequency of the clock signal is negatively correlated with the magnitude of the feedback voltage.

4. The voltage output circuit according to claim 1, characterized in that, The auxiliary control module includes a current control unit and an oscillation unit; The current control unit is used to output a charging current according to the feedback voltage; The oscillation unit is used to output a clock signal according to the charging current; Wherein, the magnitude of the charging current is negatively correlated with the magnitude of the feedback voltage, and the magnitude of the charging current is positively correlated with the frequency of the clock signal.

5. The voltage output circuit according to claim 4, wherein The current control unit includes a first current source, a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a third PMOS transistor, and a second current source; The first end of the first current source is connected to the second end of the first PMOS transistor, and the second end of the first current source is connected to the ground terminal; The first end of the first PMOS transistor is connected to the power supply terminal, and the second end of the first PMOS transistor is connected to the control terminal of the first PMOS transistor; The first end of the second PMOS transistor is connected to the power supply terminal, and the control terminal of the second PMOS transistor is connected to the control terminal of the first PMOS transistor; The second end of the first NMOS transistor is connected to the second end of the second PMOS transistor, the first end of the first NMOS transistor is connected to the ground terminal, and the control terminal of the first NMOS transistor is used to access the feedback voltage; The second end of the second NMOS transistor is connected to the second end of the second PMOS transistor, the first end of the second NMOS transistor is connected to the ground terminal, and the control terminal of the second NMOS transistor is connected to the second end of the second NMOS transistor; The second end of the third NMOS transistor is connected to the second end of the third PMOS transistor, the first end of the third NMOS transistor is connected to the ground terminal, and the control terminal of the third NMOS transistor is connected to the control terminal of the second NMOS transistor; The first end of the third PMOS transistor is connected to the power supply terminal, the second end of the third PMOS transistor is connected to the first end of the second current source, and the second end of the second current source is connected to the ground terminal.

6. The voltage output circuit according to claim 4, wherein The oscillation unit includes a charge and discharge sub-unit, a comparison sub-unit, and a logic sub-unit; The charge and discharge sub-unit charges based on the charging current and outputs a periodically changing charge and discharge voltage signal; The comparison sub-unit is configured to output a periodically changing level signal according to the periodically changing charge and discharge voltage signal; The logic sub-unit is configured to output the clock signal according to the periodically changing level signal.

7. The voltage output circuit according to claim 6, wherein The charge and discharge sub-unit includes a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a first capacitor, and a second capacitor; The first end of the fourth PMOS transistor is connected to the power supply terminal, and the control end of the fourth PMOS transistor is used to access a bias voltage, and the bias voltage is generated based on the charging current; The first end of the fifth PMOS transistor is connected to the second end of the fourth PMOS transistor, the second end of the fifth PMOS transistor is connected to the second end of the fourth NMOS transistor, and the first end of the fourth NMOS transistor is connected to the ground terminal; The first end of the first capacitor is connected to a first node between the fifth PMOS transistor and the fourth NMOS transistor, and the second end of the first capacitor is connected to the ground terminal; The first end of the sixth PMOS transistor is connected to the second end of the fourth PMOS transistor, the second end of the sixth PMOS transistor is connected to the second end of the fifth NMOS transistor, and the first end of the fifth NMOS transistor is connected to the ground terminal; The first end of the second capacitor is connected to a second node between the sixth PMOS transistor and the fifth NMOS transistor, and the second end of the second capacitor is connected to the ground terminal; Wherein, the logic sub-unit is configured to output non-overlapping first clock signal and second clock signal, the control ends of the fifth PMOS transistor and the fourth NMOS transistor are used to access the first clock signal, and the sixth PMOS transistor and the fifth NMOS transistor are used to access the second clock signal.

8. The voltage output circuit according to claim 7, wherein The comparison sub-unit includes a seventh PMOS transistor, an eighth PMOS transistor, a sixth NMOS transistor, and a seventh NMOS transistor; The first end of the seventh PMOS transistor is connected to the power supply terminal, and the control end of the seventh PMOS transistor is used to access a bias voltage; The second end of the sixth NMOS transistor is connected to the second end of the seventh PMOS transistor, the control end of the sixth NMOS transistor is connected to the first node, and the first end of the sixth NMOS transistor is connected to the ground terminal; The first end of the eighth PMOS transistor is connected to the power supply terminal, and the control end of the eighth PMOS transistor is used to access a bias voltage; The second end of the seventh NMOS transistor is connected to the second end of the eighth PMOS transistor, the control end of the seventh NMOS transistor is connected to the second node, and the first end of the seventh NMOS transistor is connected to the ground terminal; The third node between the seventh PMOS transistor and the sixth NMOS transistor is used to output a first level signal, the fourth node between the eighth PMOS transistor and the seventh NMOS transistor is used to output a second level signal, and the logic sub-unit is used to output the first clock signal and the second clock signal according to the first level signal and the second level signal.

9. The voltage output circuit according to claim 2, wherein The control unit includes a first switch, a second switch, and a first comparator; The first end of the first switch is used to access the first feedback voltage, and the second end of the first switch is connected to the inverting input terminal of the first comparator; The first end of the second switch is used to access the second feedback voltage, and the second end of the second switch is connected to the inverting input terminal of the first comparator; The non-inverting input terminal of the first comparator is used to access the preset reference voltage, and the output terminal of the first comparator is used to output an enable signal; Wherein, when the enable signal is at a high level, the first switch is closed, the second switch is opened, and the charge pump unit pulls up the control terminal voltage of the output transistor; When the enable signal is at a low level, the second switch is closed, the first switch is opened, and the pull-down unit pulls down the control terminal voltage of the output transistor.

10. The voltage output circuit according to claim 2, wherein The control unit includes a first comparator and a second comparator; The inverting input terminal of the first comparator is used to access the first feedback voltage, the non-inverting input terminal of the first comparator is used to access the preset reference voltage, and the output terminal of the first comparator is connected to the charge pump unit; The non-inverting input terminal of the second comparator is used to access the second feedback voltage, the inverting input terminal of the second comparator is used to access the preset reference voltage, and the output terminal of the second comparator is connected to the pull-down unit.

11. A chip, characterized in that, It includes the voltage output circuit according to any one of claims 1 to 10.

12. An electronic device, characterized in that, It includes a device body and the chip according to claim 11 above provided on the device body.

Images