Power consumption control system, power consumption control method, storage medium and image forming device
By selecting the DDR particle state mode by the main controller and using the power consumption adjustment module, the problem of large power consumption and difficult adjustment in the DDR particle design is solved, and adaptive adjustment and reduction of DDR particle power consumption is achieved.
Patent Information
- Application Number
- CN202510295747.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-12
- Publication Date
- 2025-07-18
AI Technical Summary
The existing DDR particle design consumes a lot of power under the fly-by topology and is not easy to adjust the working conditions according to actual needs, which affects the DDR address line signal quality.
The state mode of the DDR particles is selected through the main controller, and the power consumption of the trace is adjusted through the power consumption adjustment module, especially the digital potentiometer and voltage output module, to adapt to different working modes and reduce the power consumption of the DDR particles.
Without affecting the signal quality of the DDR address line, adaptive adjustment of the power consumption of DDR particles is achieved, reducing the power consumption of DDR particles.
Smart Images
Figure CN120335712A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of image formation, and particularly to a power consumption control system, a power consumption control method, a storage medium and an image forming apparatus. Background Art
[0002] A printed circuit board (PCB) is also known as a printed circuit board or printed wiring board, and is an important part of the physical support and signal transmission of electronic products. The traces in the PCB play a role in connecting the pins of different chips. In the widely used DDR (Double Data Rate) chip design, we commonly see two different topologies, the daisy chain topology (also known as the fly-by topology) and the equal-arm branch topology.
[0003] Among them, the fly-by topology is very advantageous in the case of high speed (such as DDR4) and multi-chip loads. For example, in the fly-by topology where the main chip controller drives 5 chip loads, this fly-by topology usually requires the use of a termination resistor R to connect to the VTT voltage (the VTT voltage is half of the power supply voltage of the DDR chip), which can mitigate the reflection of this topology and improve the signal quality. However, since there are multiple signal lines that require additional VTT termination resistors, and each signal line forms a current loop with the termination resistor, the overall DDR current increases and the power consumption becomes larger; and overall, it is not easy to adjust the working conditions according to the actual usage situation, and there are certain limitations. Summary of the Invention
[0004] Aiming at the deficiencies of the prior art, the purpose of the present invention is to provide a power consumption control system, a power consumption control method, a storage medium and an image forming apparatus, which can further adaptively adjust the power consumption of DDR chips on the premise of having less impact on the signal quality of DDR address lines, and can reduce the power consumption of DDR chips according to actual needs to a certain extent.
[0005] According to the first aspect of the present invention, there is provided a power consumption control system, including:
[0006] N DDR chips;
[0007] A main controller, which is used to select the state mode of the N DDR chips and output an adjustment signal;
[0008] Traces, which have trace impedance and are used to connect the main controller to the N DDR chips;
[0009] A power consumption adjustment module, which is used to access the traces and adjust the power consumption input to the traces based on the adjustment signal.
[0010] The power consumption control system of the present invention controls the power consumption input from the power consumption adjustment module to the trace based on the state mode of the DDR particles and the adjustment signal through the main controller, and can further adjust the power consumption of the DDR particles. On the premise of having less impact on the signal quality of the DDR address line, the power consumption of the DDR particles can be adaptively adjusted, and to a certain extent, the power consumption of the DDR particles can be reduced according to actual needs.
[0011] In some embodiments, the power consumption adjustment module includes:
[0012] A digital potentiometer, which is connected to the trace and adjusts the output resistance based on the adjustment signal to adjust the power consumption input to the trace.
[0013] In some embodiments, when the main controller selects the state mode of the DDR particles as the first mode, the main controller outputs the adjustment signal as the first adjustment signal, and the digital potentiometer adjusts the output resistance of the digital potentiometer to be less than or equal to the trace impedance based on the first adjustment signal; and / or
[0014] When the main controller selects the state mode of the DDR particles as the second mode, the main controller outputs the adjustment signal as the second adjustment signal, and the digital potentiometer adjusts the output resistance of the digital potentiometer to be greater than the trace impedance based on the second adjustment signal; and / or
[0015] When the main controller selects the state mode of the DDR particles as the third mode, the main controller outputs the adjustment signal as the third adjustment signal, and the digital potentiometer disconnects the connection with the trace based on the third adjustment signal to adjust the power consumption input to the trace.
[0016] In some embodiments, the power consumption adjustment module further includes: a voltage output module;
[0017] The main controller is further configured to output a voltage control signal based on the selected state mode of the N DDR particles, and the voltage output module is configured to control the input voltage supplied to the power consumption adjustment module based on the voltage control signal.
[0018] In some embodiments, the main controller outputs a voltage control signal based on the selected state mode of the N DDR particles, and the voltage output module is configured to control the input voltage supplied to the power consumption adjustment module based on the voltage control signal, including:
[0019] Based on the state mode of the N DDR particles selected by the master controller being the working mode, the voltage control signal output by the master controller is the first control signal, and based on the first control signal, the voltage output module allows the input voltage to be supplied to the power consumption adjustment module; and / or,
[0020] Based on the state mode of the N DDR particles selected by the master controller being the non-working mode, the voltage control signal output by the master controller is the second control signal, and based on the second control signal, the voltage output module does not allow the input voltage to be supplied to the power consumption adjustment module.
[0021] According to the second aspect of the present invention, a power consumption control method is provided, which is executed in the above power consumption control system, and includes:
[0022] Select the state mode of the N DDR particles and output an adjustment signal;
[0023] The power consumption adjustment module adjusts the power consumption input to the trace based on the adjustment signal.
[0024] In some embodiments, the power consumption adjustment module adjusts the power consumption input to the trace based on the adjustment signal, including:
[0025] The adjustment signal is transmitted to a digital potentiometer, and the digital potentiometer adjusts the output resistance connected to the trace based on the adjustment signal to adjust the power consumption input to the trace.
[0026] In some embodiments, the selecting the state mode of the N DDR particles and outputting an adjustment signal includes:
[0027] When the selected state mode of the DDR particle is the first mode, the output adjustment signal is the first adjustment signal, and the digital potentiometer adjusts the output resistance of the digital potentiometer to be less than or equal to the trace impedance based on the first adjustment signal; and / or
[0028] When the selected state mode of the DDR particle is the second mode, the output adjustment signal is the second adjustment signal, and the digital potentiometer adjusts the output resistance of the digital potentiometer to be greater than the trace impedance based on the second adjustment signal; and / or
[0029] When the selected state mode of the DDR particle is the third mode, the output adjustment signal is the third adjustment signal, and the digital potentiometer disconnects the connection with the trace based on the third adjustment signal to adjust the power consumption input to the trace.
[0030] In some embodiments, it further includes:
[0031] Output a voltage control signal to a voltage output module based on the selected status mode of the N DDR particles, and the voltage output module controls the input voltage supplied to the power consumption adjustment module based on the voltage control signal.
[0032] In some embodiments, outputting a voltage control signal to a voltage output module based on the selected status mode of the N DDR particles, and the voltage output module controls the input voltage supplied to the power consumption adjustment module based on the voltage control signal, includes:
[0033] Based on the selected status mode of the N DDR particles being the working mode, the output voltage control signal is a first control signal, and the voltage output module allows the input voltage to be supplied to the power consumption adjustment module based on the first control signal; and / or,
[0034] Based on the selected status mode of the N DDR particles being the non - working mode, the output voltage control signal is a second control signal, and the voltage output module does not allow the input voltage to be supplied to the power consumption adjustment module based on the second control signal.
[0035] According to the third aspect of the present invention, there is provided an image forming apparatus, including the above - mentioned power consumption control system; or
[0036] At least one processor; and
[0037] A memory communicatively connected to the at least one processor; wherein,
[0038] The memory stores a computer program executable by the at least one processor, and the computer program is executed by the at least one processor so that the at least one processor can execute the above - mentioned power consumption control method.
[0039] According to the fourth aspect of the present invention, there is provided a computer - readable storage medium storing computer instructions for causing a processor to implement the above - mentioned power consumption control method when executed.
[0040] Compared with the prior art, a power consumption control system, a power consumption control method, a storage medium, and an image forming apparatus of the present invention control the power consumption input by the power consumption adjustment module to the trace based on the status mode of the DDR particles and the adjustment signal by the main controller, and thus can further adjust the power consumption of the DDR particles. On the premise of having less impact on the signal quality of the DDR address line, the power consumption of the DDR particles can be adaptively adjusted, and to a certain extent, the power consumption of the DDR particles can be reduced according to actual needs. BRIEF DESCRIPTION OF THE DRAWINGS
[0041] Figure 1Circuit diagram of a power consumption control system according to an embodiment of the present invention;
[0042] Figure 2 Flowchart of a power consumption control method according to an embodiment of the present invention;
[0043] Figure 3 Flowchart of a digital potentiometer adjusting the power consumption input to the trace according to an embodiment of the present invention;
[0044] Figure 4 Flowchart of a voltage output module controlling the input voltage supplied to the power consumption adjustment module according to an embodiment of the present invention;
[0045] Figure 5 Schematic structural diagram of an image forming apparatus according to an embodiment of the present invention. Detailed description of specific embodiments
[0046] The present invention will be further described in detail below with reference to the accompanying drawings.
[0047] An embodiment of the present invention provides a power consumption control system, which is applied to an image forming apparatus. As Figure 1 shown, the power consumption control system includes a main controller 100, a power consumption adjustment module 200, a trace 300, and N DDR chips (Double DataRate SDRAM), where the main controller 100 is a SOC (System on Chip), and the N DDR chips are DDR1, DDR2, DDR3,..., DDRn in sequence.
[0048] The trace 300 has a trace impedance. The trace 300 is used to connect the main controller 100 and the N DDR chips. Specifically, the trace 300 includes M address lines and a clock line. The address lines are used to transmit address information, and the address lines are in a daisy chain structure. The M daisy chain structures are used to connect the main controller 100 and the N DDR chips; the clock line is used to transmit a clock signal, and the clock line is in a daisy chain structure. The clock line is integrated on the address lines, where the daisy chain structure is a FLY-BY structure. In addition, for the clock line, the clock line can also be set separately and no longer integrated on the address lines.
[0049] The number of address lines can be determined according to the number of address lines that the main controller 100 can connect. When the number of address lines that the main controller 100 can connect is one, the main controller 100 and N DDR chips are connected through a single FLY-BY structure. When the number of address lines that the main controller 100 can connect is greater than one, the main controller 100 and N DDR chips can be connected through multiple FLY-BY structures. Therefore, M is an integer greater than or equal to 1. The daisy chain structure (i.e., the FLY-BY structure) generally connects at least two DDR chips, so N is a positive integer greater than or equal to 2.
[0050] The main controller 100 is used to select the state modes of N DDR chips and output adjustment signals. Specifically, the state modes of the DDR chips include a working mode and a non-working mode. When the image forming apparatus is in the working mode, if the image forming apparatus needs to read and write data to / from the DDR chips, the main controller 100 needs to select the state mode of the DDR chips as the working mode. For example, the main controller 100 transmits a clock signal to the corresponding DDR chip through a clock line, and the corresponding DDR chip enters the working mode according to the clock signal when receiving the clock signal. When the image forming apparatus enters the non-working state (such as the sleep state or the low power consumption mode), the image forming apparatus does not need to use the DDR chips to read and write data. To reduce power consumption, the main controller 100 needs to select the state mode of the DDR chips as the non-working mode. For example, the main controller 100 stops outputting the clock signal to the corresponding DDR chip, and the corresponding DDR chip enters the non-working mode (such as the sleep state or the low power consumption mode) when not receiving the clock signal.
[0051] In an alternative embodiment, the operating modes of the DDR particles include a high-rate mode (referred to as the first mode) and a low-rate mode (referred to as the second mode). Correspondingly, the main controller 100 controls the corresponding DDR particles to enter the high-rate mode or the low-rate mode by controlling the frequency of the output clock signal. Specifically, the clock signal can be a first clock signal and a second clock signal, and the frequency of the first clock signal is higher than that of the second clock signal. When the image forming apparatus is in the operating mode, if the image forming apparatus needs to perform fast read and write operations on the DDR particles, the main controller 100 needs to select the state mode of the DDR particles as the first mode. For example, the main controller 100 transmits the first clock signal to the corresponding DDR particles through the clock line, and the corresponding DDR particles enter the high-rate mode according to the first clock signal when receiving the first clock signal. At the same time, the adjustment signal output by the main controller 100 is the first adjustment signal. When the image forming apparatus is in the operating mode, if the image forming apparatus needs to perform low-speed read and write operations on the DDR particles, the main controller 100 needs to select the state mode of the DDR particles as the second mode. For example, the main controller 100 transmits the second clock signal to the corresponding DDR particles through the clock line, and the corresponding DDR particles enter the low-rate mode according to the second clock signal when receiving the second clock signal. At the same time, the adjustment signal output by the main controller 100 is the second adjustment signal.
[0052] In an alternative embodiment, the non-operating mode of the DDR particles includes a sleep mode (referred to as the third mode). Correspondingly, when the image forming apparatus is in the sleep state and does not need to use the DDR particles for read and write operations, the main controller 100 needs to select the state mode of the DDR particles as the third mode. For example, the main controller 100 stops outputting the clock signal to the corresponding DDR particles, and the corresponding DDR particles enter the sleep mode when not receiving the clock signal. The adjustment signal output by the main controller 100 is the third adjustment signal.
[0053] The power consumption adjustment module 200 is used to connect to the trace line 300 and adjust the power consumption input to the trace line 300 based on the adjustment signal. Specifically, the power consumption adjustment module 200 is connected to the address line in the trace line 300, and the power consumption adjustment module 200 is connected to the main controller 100 through the serial clock line SCL and the serial data line SDA in the IIC communication bus. The main controller 100 transmits the adjustment signal to the power consumption adjustment module 200 through the IIC communication bus, so that the power consumption adjustment module 200 adjusts the power consumption input to the trace line 300 based on the adjustment signal.
[0054] In an alternative embodiment, the power consumption adjustment module 200 includes a digital potentiometer 210. The digital potentiometer 210 is connected to the trace 300 and adjusts the output resistance based on the adjustment signal to adjust the power consumption input to the trace 300. Specifically, the first end of the digital potentiometer 210 is connected to the address line in the trace 300, the second end of the digital potentiometer 210 is connected to the first voltage input terminal VTT, and the control end of the digital potentiometer 210 is connected to the main controller 100 through the IIC communication bus. The digital potentiometer 100 receives the adjustment signal output by the main controller 100 through the IIC communication bus and adjusts the output resistance connected to the trace 300 based on the adjustment signal to adjust the power consumption input to the trace 300.
[0055] In an alternative embodiment, when the main controller 100 selects the state mode of the DDR particle as the first mode, the main controller 100 outputs an adjustment signal as the first adjustment signal, and the digital potentiometer 210 adjusts the output resistance of the digital potentiometer 210 to be less than or equal to the trace impedance based on the first adjustment signal. Specifically, the digital potentiometer 100 receives the first adjustment signal output by the main controller 100 through the IIC communication bus, and the digital potentiometer 100 adjusts the output resistance connected to the trace 300 to be less than or equal to the trace impedance based on the first adjustment signal. Exemplarily, the single-ended impedance of the clock / address line signal is 50 ohms, and the impedance after passing through the trace and the capacitor is about 40 ohms. When the state mode of the DDR particle is the first mode, in order to make the clock / address line signal quality better and meet the communication signal quality requirements, the output resistance of the digital potentiometer 100 connected to the trace 300 needs to be less than or equal to the trace impedance. For example, the output resistance of the digital potentiometer 100 connected to the trace 300 is 39 ohms. That is, when the main controller 100 selects the state mode of the DDR particle as the first mode, the main controller 100 outputs the first adjustment signal to the digital potentiometer 210, causing the digital potentiometer 210 to adjust the output resistance connected to the trace 300 to be reduced to 39 ohms. 39 ohms is close to the line-end impedance, making the overall impedance as continuous as possible, reducing signal reflection, and meeting the signal quality requirements. Based on Ohm's law I = U / R, when the voltage at the first voltage input terminal VTT remains unchanged, as the resistance value becomes smaller, the current flowing through it becomes larger. According to the power consumption formula P = I^2 * R, the power consumption will increase at this time. Therefore, after the output resistance of the digital potentiometer 210 becomes smaller to 39 ohms, the power consumption will increase.
[0056] In an alternative embodiment, when the main controller 100 selects the state mode of the DDR particle as the second mode, the main controller 100 outputs an adjustment signal as the second adjustment signal, and the digital potentiometer 210 adjusts the output resistance value of the digital potentiometer 210 to be greater than the trace impedance based on the second adjustment signal; specifically, the digital potentiometer 100 receives the second adjustment signal output by the main controller 100 through the IIC communication bus, and the digital potentiometer 100 adjusts the output resistance value connected to the trace 300 to be greater than the trace impedance based on the second adjustment signal; exemplarily, when the state mode of the DDR particle is the second mode, on the premise of meeting the communication signal quality requirements, the output resistance value of the digital potentiometer 100 connected to the trace 300 needs to be greater than the trace impedance. For example, the output resistance value of the digital potentiometer 100 connected to the trace 300 is 75 ohms. That is, when the main controller 100 selects the state mode of the DDR particle as the second mode, the main controller 100 outputs the second adjustment signal to the digital potentiometer 210, so that the digital potentiometer 210 adjusts the output resistance value connected to the trace 300 to be increased to 75 ohms. Based on Ohm's law I = U / R, when the voltage of the first voltage input terminal VTT remains unchanged, as the resistance value increases, the current flowing through it becomes smaller, and according to the power consumption formula P = I^2 * R, the power consumption will decrease at this time.
[0057] In an alternative embodiment, when the main controller 100 selects the state mode of the DDR particle as the third mode, the main controller 100 outputs an adjustment signal as the third adjustment signal, and the digital potentiometer 210 disconnects from the trace 300 based on the third adjustment signal to adjust the power consumption input to the trace 300; specifically, the control terminal of the digital potentiometer 100 receives the third adjustment signal output by the main controller 100 through the IIC communication bus, and the digital potentiometer 100 disconnects from the trace 300 based on the third adjustment signal. At this time, there is an open circuit state between the first voltage input terminal VTT and the trace 300, and the power consumption input to the trace 300 is regarded as zero.
[0058] This embodiment can adaptively adjust the power consumption according to the working mode of the DDR without affecting the signal quality of the DDR address line. For example, when the main controller 100 selects the state mode of the DDR particle to jump from the first mode to the second mode or the third mode, the main controller 100 controls the power consumption adjustment module 200 to reduce the power consumption input to the trace. On the premise of having a small impact on the signal quality of the DDR address line, the power consumption of the DDR particle can be further reduced; similarly, when the main controller 100 selects the state mode of the DDR particle to jump from the second mode to the third mode, the main controller 100 controls the power consumption adjustment module 200 to reduce the power consumption input to the trace. On the premise of having a small impact on the signal quality of the DDR address line, the power consumption of the DDR particle can be further reduced.
[0059] In an alternative embodiment, the power consumption adjustment module 200 further includes a voltage output module 220. The main controller 100 is further configured to output a voltage control signal based on the status modes of the selected N DDR chips. The voltage output module 220 is configured to control the input voltage supplied to the power consumption adjustment module 200 based on the voltage control signal. Specifically, the voltage output module 220 is a voltage regulator. The voltage input terminal of the voltage output module 220 is connected to the second voltage input terminal VCC-DDR. The voltage output terminal of the voltage output module 220 is connected to the first voltage input terminal VTT. The control terminal VTT-EN of the voltage output module 220 is connected to the output terminal of the main controller 100. The control terminal VTT-EN of the voltage output module 220 is further connected to the third voltage input terminal VCC-3.3V through a resistor R. The main controller 100 outputs a voltage control signal through the output terminal based on the status modes of the selected N DDR chips. The voltage output module 220 receives the voltage control signal output by the main controller 100 through the control terminal VTT-EN and controls the input voltage supplied to the power consumption adjustment module 200 based on the voltage control signal.
[0060] In an alternative embodiment, the main controller 100 outputs a voltage control signal based on the status modes of the selected N DDR chips. The voltage output module 220 is configured to control the input voltage supplied to the power consumption adjustment module 200 based on the voltage control signal, including that when the status modes of the N DDR chips selected by the main controller 100 are in the working mode, the voltage control signal output by the main controller 100 is a first control signal. The voltage output module 220 allows the input voltage to be supplied to the power consumption adjustment module 200 based on the first control signal. That is, when the status modes of the DDR chips are in the working mode, the first voltage input terminal VTT is connected to the trace 300 through the digital potentiometer 210. At this time, the voltage output module 220 needs to supply voltage to the first voltage input terminal VTT. Then, the main controller 100 controls the voltage output module 220 to supply voltage to the first voltage input terminal VTT by outputting the first control signal to the voltage output module 220.
[0061] In an alternative embodiment, the main controller 100 outputs a voltage control signal based on the status modes of the selected N DDR particles. The voltage output module 220 is configured to control the input voltage supplied to the power consumption adjustment module 200 based on the voltage control signal. When the status modes of the N DDR particles selected by the main controller 100 are non-operating modes, the voltage control signal output by the main controller 100 is a second control signal. Based on the second control signal, the voltage output module 220 does not allow the input voltage to be supplied to the power consumption adjustment module 200. That is, when the status modes of the DDR particles are non-operating modes, the digital potentiometer 210 disconnects the first voltage input terminal VTT from the trace 300. At this time, there is no need for the voltage output module 220 to supply voltage to the first voltage input terminal VTT. To reduce power consumption, the main controller 100 controls the voltage output module 220 not to supply voltage to the first voltage input terminal VTT by outputting the second control signal to the voltage output module 220.
[0062] In this embodiment, the main controller 100 controls the power consumption input from the power consumption adjustment module 200 to the trace 300 based on the status modes of the DDR particles and the adjustment signal, and further adjusts the power consumption of the DDR particles, which helps to adaptively adjust the power consumption of the DDR particles to a certain extent while having a relatively small impact on the signal quality of the DDR address lines, and can reduce the power consumption of the DDR particles according to actual requirements.
[0063] An embodiment of the present invention provides a power consumption control method, which is executed in Figure 1 the power consumption control system shown in Figure 2 as shown, and the power consumption control method includes:
[0064] S100: Select the status modes of N DDR particles and output an adjustment signal;
[0065] S200: The power consumption adjustment module 200 adjusts the power consumption input to the trace 300 based on the adjustment signal.
[0066] In an alternative embodiment, as Figure 3 shown, the power consumption adjustment of the N DDR particles in step S200 includes:
[0067] S210: The adjustment signal is transmitted to the digital potentiometer 210, and the digital potentiometer 210 adjusts the output resistance connected to the trace 300 based on the adjustment signal to adjust the power consumption input to the trace 300.
[0068] In an alternative embodiment, selecting the status modes of N DDR particles and outputting an adjustment signal includes:
[0069] When the selected state mode of the DDR particles is the first mode, the output adjustment signal is the first adjustment signal, and the digital potentiometer 210 adjusts the output resistance value of the digital potentiometer 210 to be less than or equal to the trace impedance based on the first adjustment signal; and / or
[0070] When the selected state mode of the DDR particles is the second mode, the output adjustment signal is the second adjustment signal, and the digital potentiometer 210 adjusts the output resistance value of the digital potentiometer 210 to be greater than the trace impedance based on the second adjustment signal; and / or
[0071] When the selected state mode of the DDR particles is the third mode, the output adjustment signal is the third adjustment signal, and the digital potentiometer 210 disconnects the connection with the trace 300 based on the third adjustment signal to adjust the power consumption input to the trace 300.
[0072] In an optional implementation, such as Figure 4 ,the power consumption control method further includes:
[0073] S300: Output a voltage control signal to the voltage output module 220 based on the selected state mode of the N DDR particles, and the voltage output module 220 controls the input voltage supplied to the power consumption adjustment module 200 based on the voltage control signal.
[0074] In an optional implementation, outputting a voltage control signal to the voltage output module 220 based on the selected state mode of the N DDR particles, and the voltage output module 220 controls the input voltage supplied to the power consumption adjustment module 200 based on the voltage control signal, includes:
[0075] Based on the selected state mode of the N DDR particles being the working mode, the output voltage control signal is the first control signal, and the voltage output module 220 allows the input voltage to be supplied to the power consumption adjustment module 200 based on the first control signal; and / or,
[0076] Based on the selected state mode of the N DDR particles being the non-working mode, the output voltage control signal is the second control signal, and the voltage output module 220 does not allow the input voltage to be supplied to the power consumption adjustment module 200 based on the second control signal.
[0077] It should be noted that the steps involved in the power consumption control method have been described in detail in the power consumption control system, so they will not be elaborated here.
[0078] An embodiment of the present invention provides an image forming apparatus, which includes the above-mentioned power consumption control system.
[0079] An embodiment of the present invention provides an image forming apparatus, as Figure 5 shown, Figure 5The displayed image forming apparatus is merely an example and should not impose any limitation on the functions and scope of use of the embodiments of the present invention.
[0080] As Figure 5 shown, the image forming apparatus is presented in the form of a general computing device. The components of the image forming apparatus may include, but are not limited to: one or more processors 510, a memory 530, and a communication bus 540 that connects different system components (including the memory 530 and the processor 510).
[0081] The communication bus 540 represents one or more of several types of bus structures, including a memory bus or memory controller, a peripheral bus, a graphics acceleration port, a processor, or a local bus using any of the various bus structures. By way of example, these architectures include, but are not limited to, Industry Standard Architecture (ISA) bus, Micro Channel Architecture (MAC) bus, Enhanced ISA bus, Video Electronics Standards Association (VESA) local bus, and Peripheral Component Interconnection (PCI) bus.
[0082] The image forming apparatus typically includes a variety of computer system readable media. These media can be any available media that can be accessed by the image forming apparatus, including volatile and non-volatile media, removable and non-removable media.
[0083] The memory 530 may include computer system readable media in the form of volatile memory, such as random access memory (RAM) and / or cache memory. The image forming apparatus may further include other removable / non-removable, volatile / non-volatile computer system storage media. Although Figure 5Not shown in the figure, a disk drive for reading and writing a removable non-volatile disk (such as a "floppy disk") and an optical disk drive for reading and writing a removable non-volatile optical disk (such as a Compact Disc Read Only Memory (hereinafter referred to as: CD-ROM), a Digital Video Disc Read Only Memory (hereinafter referred to as: DVD-ROM) or other optical media) may be provided. In these cases, each drive may be connected to the communication bus 540 through one or more data medium interfaces. The memory 530 may include at least one program product having a set (such as at least one) of program modules configured to perform the functions of the embodiments of the present invention.
[0084] A program / utility having a set (at least one) of program modules may be stored in the memory 530. Such program modules include, but are not limited to, an operating system, one or more application programs, other program modules, and program data. Each or some combination of these examples may include the implementation of a network environment. The program modules generally perform the functions and / or methods in the embodiments described in the present invention.
[0085] The image forming apparatus may also communicate with one or more external devices, and may also communicate with one or more devices that enable a user to interact with the image forming apparatus, or communicate with any device (such as a network card, a modem, etc.) that enables the image forming apparatus to communicate with one or more other computing devices. Such communication may be performed through the communication interface 520. Further, the image forming apparatus may also communicate with one or more networks (such as a Local Area Network (hereinafter referred to as: LAN), a Wide Area Network (hereinafter referred to as: WAN) and / or a public network, such as the Internet) through a network adapter ( Figure 5 not shown in the figure). The above-mentioned network adapter may communicate with other modules of the image forming apparatus through the communication bus 540. It should be understood that although Figure 5 not shown in the figure, other hardware and / or software modules may be used in combination with the image forming apparatus, including but not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, Redundant Arrays of Independent Drives (hereinafter referred to as: RAID) systems, tape drives, and data backup storage systems, etc.
[0086] The processor 510 executes various functional applications and data processing by running the programs stored in the memory 530, such as implementing the power consumption control method provided by the embodiments of the present invention.
[0087] An embodiment of the present invention also provides a computer-readable storage medium. The computer-readable storage medium stores computer instructions, and the computer instructions cause the computer to execute the power consumption control method provided by the embodiment of the present invention.
[0088] The above computer-readable storage medium may be any combination of one or more computer-readable media. The computer-readable medium may be a computer-readable signal medium or a computer-readable storage medium. The computer-readable storage medium may be, for example, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination of the above, but is not limited thereto. More specific examples (non-exhaustive list) of the computer-readable storage medium include: an electrical connection having one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read only memory (ROM), an erasable programmable read only memory (EPROM), or a flash memory, an optical fiber, a portable compact disk read only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In this document, the computer-readable storage medium may be any tangible medium that contains or stores a program that can be used by or in conjunction with an instruction execution system, apparatus, or device.
[0089] The computer-readable signal medium may include a data signal propagated in a baseband or as part of a carrier wave, which carries the computer-readable program code. Such a propagated data signal may take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the above. The computer-readable signal medium may also be any computer-readable medium other than the computer-readable storage medium, which can send, propagate, or transmit a program for use by or in conjunction with an instruction execution system, apparatus, or device.
[0090] The program code contained on the computer-readable medium may be transmitted by any appropriate medium, including but not limited to wireless, wire, optical fiber cable, radio frequency (RF), etc., or any suitable combination of the above.
[0091] The above are only some embodiments of the present invention. For those of ordinary skill in the art, without departing from the inventive concept of the present invention, several modifications and improvements can still be made, and these all belong to the protection scope of the present invention.
Claims
1. A power consumption control system, characterized in that, Comprising: N DDR particles; A main controller for selecting a state mode of the N DDR particles and outputting an adjustment signal; A trace having a trace impedance for connecting the main controller to the N DDR particles; A power consumption adjustment module for accessing the trace and adjusting the power consumption input to the trace based on the adjustment signal.
2. The power consumption control system according to claim 1, wherein The power consumption adjustment module includes: A digital potentiometer accessing the trace and adjusting an output resistance value based on the adjustment signal to adjust the power consumption input to the trace.
3. The power consumption control system according to claim 2, characterized in that, When the main controller selects the state mode of the DDR particle as the first mode, the main controller outputs the adjustment signal as a first adjustment signal, and the digital potentiometer adjusts the output resistance value of the digital potentiometer to be less than or equal to the trace impedance based on the first adjustment signal; and / or When the main controller selects the state mode of the DDR particle as the second mode, the main controller outputs the adjustment signal as a second adjustment signal, and the digital potentiometer adjusts the output resistance value of the digital potentiometer to be greater than the trace impedance based on the second adjustment signal; and / or When the main controller selects the state mode of the DDR particle as the third mode, the main controller outputs the adjustment signal as a third adjustment signal, and the digital potentiometer disconnects from the trace based on the third adjustment signal to adjust the power consumption input to the trace.
4. The power consumption control system according to any one of claims 1-3, characterized in that, The power consumption adjustment module further includes: a voltage output module; The main controller is further configured to output a voltage control signal based on the selected state mode of the N DDR particles, and the voltage output module is configured to control the input voltage supplied to the power consumption adjustment module based on the voltage control signal.
5. The power consumption control system according to claim 4, characterized in that The main controller outputs a voltage control signal based on the selected state mode of the N DDR particles, and the voltage output module controls the input voltage supplied to the power consumption adjustment module based on the voltage control signal, including: Based on the state mode of the N DDR particles selected by the main controller being the working mode, the voltage control signal output by the main controller is a first control signal, and the voltage output module allows the input voltage to be supplied to the power consumption adjustment module based on the first control signal; and / or, Based on the state mode of the N DDR particles selected by the main controller being the non-working mode, the voltage control signal output by the main controller is a second control signal, and the voltage output module does not allow the input voltage to be supplied to the power consumption adjustment module based on the second control signal.
6. A power consumption control method, which is executed in the power consumption control system according to any one of claims 1-6, characterized in that Comprising: Selecting the state mode of the N DDR particles and outputting an adjustment signal; The power consumption adjustment module adjusts the power consumption input to the trace based on the adjustment signal.
7. The power consumption control method according to claim 6, wherein The power consumption adjustment module adjusts the power consumption input to the trace based on the adjustment signal, including: The adjustment signal is transmitted to the digital potentiometer, and the digital potentiometer adjusts the output resistance value connected to the trace based on the adjustment signal to adjust the power consumption input to the trace.
8. The power consumption control method according to claim 7, wherein Selecting a state mode of the N DDR particles and outputting an adjustment signal, including: When the selected state mode of the DDR particles is the first mode, outputting the adjustment signal as a first adjustment signal, and the digital potentiometer adjusts the output resistance value of the digital potentiometer to be less than or equal to the trace impedance based on the first adjustment signal; and / or When the selected state mode of the DDR particles is the second mode, outputting the adjustment signal as a second adjustment signal, and the digital potentiometer adjusts the output resistance value of the digital potentiometer to be greater than the trace impedance based on the second adjustment signal; and / or When the selected state mode of the DDR particles is the third mode, outputting the adjustment signal as a third adjustment signal, and the digital potentiometer disconnects the connection with the trace based on the third adjustment signal to adjust the power consumption input to the trace.
9. The power consumption control method according to any one of claims 6-8, characterized in that, Further including: Outputting a voltage control signal to a voltage output module based on the selected state mode of the N DDR particles, and the voltage output module controls the input voltage supplied to the power consumption adjustment module based on the voltage control signal.
10. The power consumption control method according to claim 9, wherein Outputting a voltage control signal to a voltage output module based on the selected state mode of the N DDR particles, and the voltage output module controls the input voltage supplied to the power consumption adjustment module based on the voltage control signal, including: Based on the selected state mode of the N DDR particles being the working mode, the output voltage control signal is a first control signal, and the voltage output module allows the input voltage to be supplied to the power consumption adjustment module based on the first control signal; and / or, Based on the selected state mode of the N DDR particles being the non-working mode, the output voltage control signal is a second control signal, and the voltage output module does not allow the input voltage to be supplied to the power consumption adjustment module based on the second control signal.
11. An image forming apparatus, characterized in that, Including the power consumption control system according to any one of claims 1-7; or At least one processor; and A memory communicatively connected to the at least one processor; wherein, The memory stores a computer program executable by the at least one processor, and the computer program is executed by the at least one processor so that the at least one processor can execute the power consumption control method according to any one of claims 6-10.
12. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions for causing a processor to execute the power consumption control method according to any one of claims 6-10 when executed.