Implementation method, system and storage medium of vector configuration instruction

Abstract

The application belongs to the technical field of processors, and particularly relates to a vector configuration instruction implementation method, system and storage medium. The implementation system comprises a fetch unit, a decoding unit, a vector configuration instruction execution unit, an execution management unit and a vector execution unit; the vector configuration instruction execution unit is used for obtaining an idle register number, renaming a received vector configuration instruction according to the idle register number, obtaining a renamed vector configuration instruction and renaming information, executing the renamed vector configuration instruction, and generating vector configuration information according to an execution result and sending the vector configuration information to the vector execution unit. Compared with the prior art, the application introduces a register renaming technology to implement a vector configuration instruction, retains the ability of speculative execution, and can simply and quickly recover when the speculative execution is wrong, so that the design complexity can be reduced while the performance is considered, and the execution efficiency of the instruction is improved.

Description

TECHNICAL FIELD

[0001] The present application is suitable for the field of processor technology, and particularly relates to a method and system for implementing a vector configuration instruction, and a storage medium. BACKGROUND

[0002] A processor is the computing and control core of an information processing system. With the continuous improvement of computing power requirements, the performance requirements of the processor are also constantly improving. Traditional processor design methods focus on improving instruction-level parallelism (ILP) to enable the processor to emit and execute as many instructions as possible at a time, thereby improving the performance of the processor. Data-level parallelism (DLP) effectively reduces the number of instruction fetching and instruction emitting by enabling a single instruction to process multiple data, thereby improving the performance of the processor. Currently, there are two main ways to improve the data-level parallelism of a single processor core: single instruction-multiple data (SIMD) instructions and vector instructions. SIMD instructions process fixed-width data, while vector instructions support processing variable-width data, which is more flexible and easier to program. Currently, the main vector instruction sets mainly include two types: ARM's Scalable Vector Extension (SVE) and the Vector Extension of the fifth generation reduced instruction set (RISC-V Vector Extension). The former requires special authorization to develop, while the latter is open source and free. And because the latter was introduced relatively late, it has learned from the historical experience of the development of vector instructions and has many advantages such as more efficient and more compact instructions.

[0003] Before executing the fifth generation reduced instruction set vector instruction, a dedicated vector configuration instruction is needed to set the vector-related control and state registers (CSR), including the vector type register (vtype) and the vector length register (vl). The vector instruction needs to read the values of these two control and state registers before it can start executing, so how to implement the vector configuration instruction and handle the related dependencies has become one of the keys in the implementation of the fifth generation reduced instruction set vector extension.

[0004] There are two main existing implementation manners of the fifth generation RISC vector configuration instruction. One is to implement the vector configuration instruction as a common control and state register instruction. This implementation manner generally needs to wait for all previous instructions to be executed before executing the vector configuration instruction after identifying the vector configuration instruction, and needs to suspend the execution of subsequent instructions during the execution until the instruction is executed. This implementation manner is simple, and can reuse the existing control and state register execution path, thus saving additional area overhead. The other is to directly predict the execution result of the instruction based on the execution history information of the vector configuration instruction, which can support the speculative execution of the vector configuration instruction. This manner can enable the subsequent vector instructions to be executed without blocking, and can greatly improve the efficiency of instruction execution. When the prediction is wrong, the execution state of the processor needs to be restored, and the state of the predictor also needs to be restored and adjusted. This prediction mechanism is usually integrated with the branch predictor, and additional information is added to the existing branch predictor to predict the execution result of the vector configuration instruction.

[0005] The two main existing implementation manners of the fifth generation RISC vector configuration instruction have the following problems. First, for the implementation manner based on the common control and state register instruction, the vector configuration instruction needs to be executed in a blocking manner, which seriously affects the performance of vector instruction execution. Second, for the implementation manner based on prediction, a special prediction mechanism and error recovery mechanism need to be developed, which increases the design complexity.

[0006] Therefore, there is an urgent need for a new implementation method, system and storage medium of a vector configuration instruction to solve the above technical problems. SUMMARY

[0007] The present application provides an implementation method, system and storage medium of a vector configuration instruction. The present application aims to implement the vector configuration instruction by introducing a register renaming technique, which can preserve the ability of speculative execution while enabling simple and fast recovery when the speculative execution is wrong. Therefore, the present application can reduce the design complexity while ensuring performance.

[0008] In a first aspect, the present application provides an implementation system of a vector configuration instruction, which comprises a fetch unit, a decoding unit, a vector configuration instruction execution unit, an execution management unit and a vector execution unit.

[0009] The fetch unit is configured to obtain a to-be-executed instruction from a memory and send the to-be-executed instruction to the decoding unit.

[0010] The decoding unit is configured to identify the received to-be-executed instructions, extract a vector configuration instruction in the to-be-executed instructions, and send the vector configuration instruction to the vector configuration instruction execution unit, and extract a vector instruction in the to-be-executed instructions and send the vector instruction to the vector execution unit.

[0011] The vector configuration instruction execution unit is configured to obtain an idle register number, rename the received vector configuration instruction according to the idle register number, obtain a renamed vector configuration instruction and renaming information, further execute the renamed vector configuration instruction, and obtain an execution result; and further configured to generate vector configuration information according to the execution result, send the vector configuration information to the vector execution unit, and send the renaming information to the execution management unit.

[0012] The execution management unit is configured to manage an execution state of the renamed vector configuration instruction according to the received renaming information, and perform error recovery when the execution of the renamed vector configuration instruction fails.

[0013] The vector execution unit is configured to execute the vector instruction according to the received vector configuration information.

[0014] Preferably, the vector configuration instruction execution unit comprises an idle register list, a speculative register renaming mapping table, an architectural register renaming mapping table, a vector configuration instruction function unit, and a vector configuration register file.

[0015] The idle register list is configured to manage the idle register number.

[0016] The speculative register renaming mapping table is configured to save a mapping relationship between the latest renamed vector configuration instruction and a register in the vector configuration register file.

[0017] The architectural register renaming mapping table is configured to save a mapping relationship between the renamed vector configuration instruction and a register in the vector configuration register file when the submission of the renamed vector configuration instruction succeeds.

[0018] The vector configuration instruction function unit is configured to execute the renamed vector configuration instruction.

[0019] The vector configuration register file is configured to store the execution result and generate the vector configuration information, and send the vector configuration information to the vector execution unit.

[0020] Preferably, when the submission of the renamed vector configuration instruction succeeds, the execution management unit is further configured to return a register number of the renamed vector configuration instruction in a previous mapping to the idle register list.

[0021] Preferably, when the speculative execution of the renaming vector configuration instruction fails, the execution management unit is further configured to restore the free register list to a state before the renaming vector configuration instruction is executed.

[0022] Preferably, when the vector configuration instruction execution unit renames the vector configuration instruction, the speculative register renaming mapping table is further configured to update a mapping relationship between the renaming vector configuration instruction and a corresponding register in the vector configuration register file.

[0023] Preferably, when the speculative execution of the renaming vector configuration instruction fails, the execution management unit is further configured to update the mapping relationship between the renaming vector configuration instruction and the register in the vector configuration register file in the architectural register renaming mapping table.

[0024] Preferably, when the speculative execution of the renaming vector configuration instruction fails, the information in the architectural register renaming mapping table is updated into the speculative register renaming mapping table.

[0025] In a second aspect, the present application further provides an implementation method of a vector configuration instruction, which is based on the implementation system of the vector configuration instruction as described in the above embodiments, and the implementation method comprises the following steps:

[0026] S1, obtaining an instruction to be executed by the instruction fetch unit, and identifying the instruction to be executed by the decoding unit to extract a vector configuration instruction and a vector instruction in the instruction to be executed;

[0027] S2, obtaining a free register number by the free register list of the vector configuration instruction execution unit, renaming the vector configuration instruction according to the free register number, and obtaining a renamed vector configuration instruction and renaming information;

[0028] S3, writing the mapping relationship between the renaming vector configuration instruction and the free register number into the speculative register renaming mapping table;

[0029] S4, executing the renaming vector configuration instruction by the vector configuration instruction functional unit, and obtaining an execution result;

[0030] S5, generating vector configuration information according to the execution result by the vector configuration register file, and executing the vector instruction according to the vector configuration information by the vector execution unit;

[0031] S6, managing execution state of the rename vector configuration instruction according to the rename information by the execution management unit, and performing error recovery when the rename vector configuration instruction fails to execute;

[0032] S7, judging whether the speculative execution succeeds: if yes, proceeding to step S8, and if no, restoring the free register list to a state before the rename vector configuration instruction performs speculative execution by the execution management unit, and updating information in the architectural register rename mapping table to the speculative register rename mapping table;

[0033] S8, when the rename vector configuration instruction is successfully committed, returning register numbers in a previous mapping of the rename vector configuration instruction to the free register list by the execution management unit, and updating register numbers corresponding to the rename vector configuration instruction to the architectural register rename mapping table.

[0034] In a third aspect, the present application also provides a computer device, comprising a memory, a processor, and an implementation program of a vector configuration instruction stored in the memory and executable on the processor, wherein the processor implements steps in the implementation method of the vector configuration instruction as described in the above embodiments when executing the implementation program of the vector configuration instruction.

[0035] In a fourth aspect, the present application also provides a computer readable storage medium, wherein the computer readable storage medium stores an implementation program of a vector configuration instruction, and the implementation program of the vector configuration instruction implements steps in the implementation method of the vector configuration instruction as described in the above embodiments when executed by a processor.

[0036] Compared with the prior art, the present application introduces register renaming technology to implement a vector configuration instruction, which can retain the ability of speculative execution, and can also simply and quickly recover when the speculative execution is wrong, thus reducing the complexity of design while ensuring performance, and improving the execution efficiency of the instruction. BRIEF DESCRIPTION OF DRAWINGS

[0037] The above and other aspects of the present application will become more apparent and more readily appreciated from the following detailed description of the application, taken in conjunction with the accompanying drawings. In the drawings:

[0038] Figure 1 is a structural schematic diagram of an implementation system of a vector configuration instruction provided by an embodiment of the present application;

[0039] Figure 2 is a flowchart of an implementation method of a vector configuration instruction provided by an embodiment of the present application;

[0040] Figure 3is a computer device structure schematic diagram provided by an embodiment of the present application. DETAILED DESCRIPTION

[0041] In order to make the objects, technical solutions and advantages of the present application clearer, the present application is further described in detail below with reference to the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and do not limit the present application.

[0042] Embodiment one

[0043] An implementation system of a vector configuration instruction is provided by an embodiment of the present application. Please refer to Figure 1 , Figure 1 is a structure schematic diagram of the implementation system 100 of the vector configuration instruction provided by an embodiment of the present application, which comprises a fetch unit 1, a decoding unit 2, a vector configuration instruction execution unit 3, an execution management unit 4 and a vector execution unit 5.

[0044] The fetch unit 1 is used to obtain an instruction to be executed from a memory and send the instruction to be executed to the decoding unit 2.

[0045] The decoding unit 2 is used to identify the received instruction to be executed, extract a vector configuration instruction in the instruction to be executed and send the vector configuration instruction to the vector configuration instruction execution unit 3, and extract a vector instruction in the instruction to be executed and send the vector instruction to the vector execution unit 5.

[0046] The vector configuration instruction execution unit 3 is used to obtain an idle register number, rename the received vector configuration instruction according to the idle register number, obtain a renamed vector configuration instruction and renaming information, further execute the renamed vector configuration instruction, and obtain an execution result; and is further used to generate vector configuration information according to the execution result and send the vector configuration information to the vector execution unit 5, and send the renaming information to the execution management unit 4.

[0047] In an embodiment of the present application, the vector configuration instruction execution unit 3 comprises an idle register list 31, a speculative register renaming mapping table 32, an architectural register renaming mapping table 33, a vector configuration instruction function unit 34 and a vector configuration register heap 35.

[0048] The idle register list 31 is used to manage the idle register number.

[0049] The speculative register renaming mapping table 32 is used to save the mapping relationship between the latest renamed vector configuration instruction and the registers in the vector configuration register heap 35.

[0050] The architecture register renaming mapping table 33 is configured to save the mapping relationship between the renaming vector configuration instruction and the register in the vector configuration register file 35 when the submission of the renaming vector configuration instruction is successful.

[0051] The vector configuration instruction function unit 34 is configured to execute the renaming vector configuration instruction, and the execution result is written into the corresponding entry of the vector configuration register file 35.

[0052] The vector configuration register file 35 is configured to store the execution result and generate the vector configuration information, and send the vector configuration information to the vector execution unit 5. Each entry in the vector configuration register file 35 contains two registers of vector length and vector type. Specifically, the vector configuration register file 35 obtains the latest vector configuration register mapping relationship from the speculation register renaming mapping table 32, and obtains the vector configuration information from the corresponding entry to send to the vector execution unit 5 for subsequent execution of the vector instruction.

[0053] The execution management unit 4 is configured to manage the execution state of the renaming vector configuration instruction according to the received renaming information, and perform error recovery when the execution of the renaming vector configuration instruction fails.

[0054] The vector execution unit 5 is configured to execute the vector instruction according to the received vector configuration information. It should be noted that the vector configuration instruction refers to an instruction for setting the execution environment, data layout or hardware parameter of the vector processor, which does not directly participate in data operation. The vector instruction refers to an instruction for simultaneously executing the same operation (such as addition, multiplication) on multiple data elements to realize data-level parallelism.

[0055] In the embodiment of the present application, when the submission of the renaming vector configuration instruction is successful, the execution management unit 4 is further configured to return the register number of the renaming vector configuration instruction in the previous mapping to the idle register list 31 for subsequent renaming of instructions. It should be noted that the submission of the renaming vector configuration instruction refers to that the execution result of the renaming vector configuration instruction is permanently written into a register or memory.

[0056] In the embodiment of the present application, when the speculative execution of the renaming vector configuration instruction fails, the execution management unit 4 is further configured to restore the idle register list 31 to the state before the execution of the renaming vector configuration instruction.

[0057] In an embodiment of the present invention, after the vector configuration instruction execution unit 3 renames the vector configuration instruction, the speculative register renaming mapping table 32 is further used to update the mapping relationship between the renamed vector configuration instruction and the corresponding register in the vector configuration register file 35. Specifically, after the vector configuration instruction is renamed, it is synchronously updated in the speculative register renaming mapping table 32 to indicate which register in the vector configuration register file 35 the vector configuration register of the most recently renamed vector configuration instruction corresponds to.

[0058] In an embodiment of the present invention, when the rename vector configuration instruction is submitted successfully, the execution management unit 4 is also used to update the mapping relationship between the rename vector configuration instruction in the architecture register renaming mapping table 33 and the registers in the vector configuration register stack 35, that is, to update the register number corresponding to the rename vector configuration instruction to be speculatively executed to the architecture register renaming mapping table 33.

[0059] In an embodiment of the present invention, when the execution management unit 4 fails to speculate on the rename vector configuration instruction, the information in the architecture register renaming mapping table 33 is updated to the speculative register renaming mapping table 32 so as to restore the speculative register renaming mapping table 32 to the state before the execution of the rename vector configuration instruction.

[0060] Compared with the existing technology, the present invention implements vector configuration instructions by introducing register renaming technology. While retaining the ability of speculative execution, it can also perform simple and rapid recovery when speculative execution errors occur. Therefore, it can reduce the complexity of the design while taking into account performance and improve the execution efficiency of instructions.

[0061] Example 2

[0062] Please refer to Figure 2 The present invention also provides a method for implementing a vector configuration instruction, the method comprising the following steps:

[0063] S1, obtaining instructions to be executed by the instruction fetch unit 1, and identifying the instructions to be executed by the decoding unit 2, and extracting vector configuration instructions and vector instructions from the instructions to be executed;

[0064] S2, obtaining a free register number through the free register list 31 of the vector configuration instruction execution unit 3, and renaming the vector configuration instruction according to the free register number to obtain a renamed vector configuration instruction and renaming information;

[0065] S3, write the mapping relationship between the renaming vector configuration instruction and the idle register number corresponding to the mapping relationship into the speculative register renaming mapping table 32;

[0066] S4, execute the renaming vector configuration instruction by the vector configuration instruction functional unit 34 to obtain an execution result;

[0067] S5, generate vector configuration information according to the execution result by the vector configuration register heap 35, and execute the vector instruction according to the vector configuration information by the vector execution unit 5;

[0068] S6, manage the execution state of the renaming vector configuration instruction according to the renaming information by the execution management unit 4, and perform error recovery when the renaming vector configuration instruction fails to execute;

[0069] S7, determine whether the speculative execution is successful: if yes, proceed to step S8, and if no, restore the idle register list 31 to the state before the speculative execution of the renaming vector configuration instruction by the execution management unit 4, and update the information in the architecture register renaming mapping table 33 to the speculative register renaming mapping table 32;

[0070] S8, when the renaming vector configuration instruction is successfully submitted, return the register number of the renaming vector configuration instruction in the last mapping to the idle register list 31 by the execution management unit 4, and update the register number corresponding to the renaming vector configuration instruction to the architecture register renaming mapping table 33.

[0071] The implementation method is based on the vector configuration instruction implementation system 100 as described in the above embodiment, and can achieve the same technical effects. Please refer to the description in the above embodiment, which will not be repeated here.

[0072] Embodiment three

[0073] The embodiment of the present application also provides a computer device, please refer to Figure 3 , Figure 3 is a structural schematic diagram of the computer device provided by the embodiment of the present application, the computer device 300 comprises a memory 302, a processor 301 and an implementation program of a vector configuration instruction stored in the memory 302 and capable of running on the processor 301.

[0074] The processor 301 invokes the implementation program of the vector configuration instruction stored in the memory 302, and executes the steps in the implementation method of the vector configuration instruction provided by the embodiment of the present application. Please combine Figure 1 , specifically comprising the following steps:

[0075] S1, obtaining an instruction to be executed by the instruction fetch unit 1, and identifying the instruction to be executed by the decode unit 2, and extracting a vector configuration instruction in the instruction to be executed;

[0076] S2, obtaining an idle register number in the idle register list 31 of the vector configuration instruction execution unit 3, and renaming the vector configuration instruction according to the idle register number, to obtain a renamed vector configuration instruction and renaming information;

[0077] S3, writing the mapping relationship between the renamed vector configuration instruction and the idle register number into the speculative register renaming mapping table 32;

[0078] S4, executing the renamed vector configuration instruction by the vector configuration instruction function unit 34 to obtain an execution result;

[0079] S5, generating vector configuration information according to the execution result by the vector configuration register stack 35, and executing a vector instruction according to the vector configuration information by the vector execution unit 5;

[0080] S6, managing the execution state of the renamed vector configuration instruction according to the renaming information by the execution management unit 4, and performing error recovery when the renamed vector configuration instruction fails to execute;

[0081] S7, determining whether the speculative execution is successful: if yes, performing step S8, and if no, restoring the idle register list 31 to the state before the speculative execution of the renamed vector configuration instruction by the execution management unit 4, and updating the information in the architectural register renaming mapping table 33 to the speculative register renaming mapping table 32;

[0082] S8, when the renamed vector configuration instruction is successfully submitted, returning the register number of the renamed vector configuration instruction in the last mapping to the idle register list 31 by the execution management unit 4, and updating the register number corresponding to the renamed vector configuration instruction to the architectural register renaming mapping table 33.

[0083] The computer device 300 provided by the embodiment of the present application can realize the steps in the implementation method of the vector configuration instruction in the above-described embodiment, and can realize the same technical effects, and the description in the above-described embodiment is referred to, and will not be repeated here.

[0084] Embodiment four

[0085] The embodiment of the present application further provides a computer readable storage medium, which stores an implementation program of a vector configuration instruction, the implementation program of the vector configuration instruction is executed by a processor to implement each process and step in the implementation method of the vector configuration instruction provided by the embodiment of the present application, and the same technical effects can be achieved. To avoid repetition, details are not described herein.

[0086] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by a computer program instructing related hardware, and the program can be stored in a computer readable storage medium. When the program is executed, the processes of the above-mentioned embodiment methods can be included. The storage medium can be a magnetic disc, an optical disc, a read-only memory (ROM) or a random access memory (RAM).

[0087] It should be noted that in this document, the terms "comprising", "containing", or any other variant thereof are intended to cover non-exclusive inclusion, so that processes, methods, articles or devices that include a series of elements not only include those elements, but also include other elements not explicitly listed or inherent to such processes, methods, articles or devices. Without more limitations, the element defined by the statement "comprising a" does not exclude the presence of additional identical elements in the process, method, article or device that includes the element.

[0088] From the above description of the embodiments, those skilled in the art can clearly understand that the above-mentioned embodiment methods can be realized by means of software and a general hardware platform, of course, they can also be realized by hardware, but in many cases the former is a better embodiment. Based on such understanding, the technical solutions of the present application can be embodied in the form of a software product, which is stored in a storage medium (such as ROM / RAM, magnetic disc, optical disc) and includes a plurality of instructions for making a terminal (which can be a mobile phone, computer, server, air conditioner or network device, etc.) execute the methods described in the embodiments of the present application.

[0089] The embodiments of the present application are described above in combination with the drawings, and the disclosed are only the preferred embodiments of the present application, but the present application is not limited to the above-mentioned specific embodiments, which are only illustrative and not restrictive. Those skilled in the art can make many equivalent changes under the guidance of the present application without departing from the scope of the present application and the protection scope of the claims, which are all within the protection scope of the present application.

Claims

1. An implementation method of a vector configuration instruction, characterized in that, The implementation method comprises the following steps: S1, obtaining an instruction to be executed by a fetch unit, and identifying the instruction to be executed by a decoding unit to extract a vector configuration instruction and a vector instruction in the instruction to be executed; S2, obtaining an idle register number by an idle register list of a vector configuration instruction execution unit, renaming the vector configuration instruction according to the idle register number to obtain a renamed vector configuration instruction and renaming information; S3, writing a mapping relationship between the renamed vector configuration instruction and the idle register number corresponding to the idle register number into a speculative register renaming mapping table; S4, executing the renamed vector configuration instruction by a vector configuration instruction function unit to obtain an execution result; S5, generating vector configuration information according to the execution result by a vector configuration register stack, and executing the vector instruction according to the vector configuration information by a vector execution unit; S6, managing an execution state of the renamed vector configuration instruction according to the renaming information by an execution management unit, and performing error recovery when the execution of the renamed vector configuration instruction fails; S7, judging whether the speculative execution is successful: if yes, performing step S8, and if no, restoring the idle register list to a state before the speculative execution of the renamed vector configuration instruction by the execution management unit, and updating information in an architecture register renaming mapping table into the speculative register renaming mapping table; S8, when the submission of the renamed vector configuration instruction is successful, returning the register number in the last mapping of the renamed vector configuration instruction to the idle register list by the execution management unit, and updating the register number corresponding to the renamed vector configuration instruction to the architecture register renaming mapping table.

2. An implementation system of a vector configuration instruction, characterized by, The implementation system of the vector configuration instruction is based on the implementation method of the vector configuration instruction according to claim 1, and the implementation system comprises a fetch unit, a decoding unit, a vector configuration instruction execution unit, an execution management unit and a vector execution unit; The fetch unit is used to obtain an instruction to be executed from a memory, and send the instruction to be executed to the decoding unit; The decoding unit is used to identify the received instruction to be executed, and send a vector configuration instruction in the instruction to be executed to the vector configuration instruction execution unit and a vector instruction in the instruction to be executed to the vector execution unit; The vector configuration instruction execution unit is used to obtain an idle register number, rename the received vector configuration instruction according to the idle register number to obtain a renamed vector configuration instruction and renaming information, further execute the renamed vector configuration instruction to obtain an execution result, and send the vector configuration information generated according to the execution result to the vector execution unit, and send the renaming information to the execution management unit; The vector execution unit is used to execute the vector instruction according to the vector configuration information, and generate an execution result; The execution management unit is configured to manage execution states of the renaming vector configuration instruction according to the received renaming information, and perform error recovery when the renaming vector configuration instruction fails to execute. The vector execution unit is configured to execute the vector instruction according to the received vector configuration information.

3. The implementation system of vector configuration instructions of claim 2, wherein, The vector configuration instruction execution unit comprises an idle register list, a speculative register renaming mapping table, an architectural register renaming mapping table, a vector configuration instruction function unit, and a vector configuration register file. The idle register list is configured to manage the idle register numbers. The speculative register renaming mapping table is configured to save a mapping relationship between the latest renaming vector configuration instruction and a register in the vector configuration register file. The architectural register renaming mapping table is configured to save a mapping relationship between the renaming vector configuration instruction and a register in the vector configuration register file when the renaming vector configuration instruction is successfully committed. The vector configuration instruction function unit is configured to execute the renaming vector configuration instruction. The vector configuration register file is configured to store the execution result and generate the vector configuration information, and send the vector configuration information to the vector execution unit.

4. The implementation system of vector configuration instructions of claim 3, wherein, When the renaming vector configuration instruction is successfully committed, the execution management unit is further configured to return a register number of the renaming vector configuration instruction in a previous mapping to the idle register list.

5. The implementation system of vector configuration instructions of claim 3, wherein, When the speculative execution of the renaming vector configuration instruction fails, the execution management unit is further configured to restore the idle register list to a state before the renaming vector configuration instruction is executed.

6. The implementation system of vector configuration instructions of claim 3, wherein, When the vector configuration instruction execution unit renames the vector configuration instruction, the speculative register renaming mapping table is further configured to update a mapping relationship between the renaming vector configuration instruction and a corresponding register in the vector configuration register file.

7. The implementation system of vector configuration instructions of claim 3, wherein, When the renaming vector configuration instruction is successfully committed, the execution management unit is further configured to update a mapping relationship between the renaming vector configuration instruction in the architectural register renaming mapping table and a register in the vector configuration register file.

8. The implementation system of vector configuration instructions of claim 3, wherein, When the speculative execution of the renaming vector configuration instruction by the execution management unit fails, information in the architectural register renaming mapping table is updated to the speculative register renaming mapping table.

9. A computer device, comprising: The computer readable storage medium stores a vector configuration instruction implementation program, and the vector configuration instruction implementation program is executed by a processor to implement the steps in the vector configuration instruction implementation method in claim 1. The computer readable storage medium stores a vector configuration instruction implementation program, and the vector configuration instruction implementation program is executed by a processor to implement the steps in the vector configuration instruction implementation method in claim 1.

10. A computer-readable storage medium, characterized in that, ​

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