CPU (Central Processing Unit) capable of realizing accurate delay control and accurate delay control method

Abstract

The invention discloses a CPU capable of accurate delay control and an accurate delay control method, and the CPU comprises an instruction decoder which is used for decoding an effective delay instruction and outputting a delay request and instruction information; the input end of the summator inputs the first delay number and the second delay number, and the output end of the summator is connected with the counter; the counter is used for reloading the output value of the adder when receiving the delay request, counting and outputting a counting result to the delay controller; the delay monitor is used for receiving the instruction matching information, performing matching according to the detected assembly line instruction and transmitting a matching result to the delay controller; and the delay controller is used for receiving the delay request and the instruction matching information output by the instruction decoder, the counting result output by the counter and the matching result output by the delay monitor, and generating a pause request or cancelling the pause request to the CPU pipeline controller. The method is high in delay accuracy, determinable in result, high in processor utilization rate and low in power consumption.

Description

Technical Field

[0001] The present invention belongs to the field of processor design, and particularly relates to a CPU capable of precise delay control and a precise delay control method. Background Art

[0002] Delay functions are almost indispensable in the programming process and are commonly used in scenarios such as embedded systems, real-time control, communication protocols, and user interfaces. There are mainly two implementation methods in the prior art: implementation by loop body and implementation by hardware timer, and these two implementation methods have the following defects respectively: 1. Defects of implementing delay functions by loop body: (1) High processor occupancy rate. Using a loop body (such as an empty loop) to implement delay, the CPU is in a busy waiting state, resulting in resource waste, being unable to execute other tasks, and reducing the system response and throughput.

[0003] (2) Increased power consumption. Continuous repeated instruction fetching and execution lead to increased power consumption, which is particularly obvious in power-sensitive devices (such as battery-powered embedded systems), and may lead to shortened battery life.

[0004] (3) Uncertainty of delay results. The delay effect is affected by various factors such as the processor instruction fetching speed, pipeline length, and branch prediction, resulting in large differences in delay results under different conditions and affecting the predictability of the program.

[0005] (4) Unable to meet high-precision requirements. For applications that require precise control, an empty loop is difficult to provide sufficient delay accuracy, which may lead to system instability or functional failure.

[0006] 2. Defects of implementing delay functions by hardware timer: (1) High implementation complexity. Hardware timers require register configuration and management of interrupt service programs, increasing the development complexity and the risk of errors.

[0007] (2) Occupying hardware resources. Systems with limited resources may not have enough hardware resources for timer configuration and use, restricting its scope of application.

[0008] (3) Uncertainty of delay results. Hardware timers rely on the execution speed of the processor during configuration, flag query, or interrupt processing, including instruction fetching speed, compilation conditions, and interrupt response time, which may lead to unreliable delay results.

[0009] (4) Strong hardware dependence. The implementation of hardware timers depends on the specific hardware platform, and differences in timer configuration between different platforms may cause the code to be unable to be directly migrated.

[0010] (5) Resource competition problem. In a multi-task environment, the same timer resource may be competed for, resulting in uncertainty and uncontrollability of the delay. Summary of the Invention

[0011] Invention Objective: To solve the uncertainty of the delay control result in the prior art and improve the accuracy of delay control, the present invention provides a CPU capable of precise delay control and a precise delay control method.

[0012] Technical Solution: A CPU capable of precise delay control includes: An instruction decoder, which is used to decode valid delay instructions, obtain instruction information and output a delay request. The instruction information includes a first delay number, a second delay number, and instruction matching information; An adder, with the first delay number and the second delay number input at the input end, and the output end connected to a counter; A counter, which is used to reload the output value of the adder when receiving a delay request, decrement the count, and output the count result to a delay controller; A delay monitor, which is used to detect the pipeline, receive instruction matching information, match the detected pipeline instructions according to the instruction matching information, match the detected pipeline privileges according to preset privilege information, and transmit the matching result to the delay controller; A delay controller, which is used to receive the delay request and instruction matching information output by the instruction decoder, store the instruction matching information in a register and output it to the delay monitor, receive the count result output by the counter, receive the matching result output by the delay monitor, switch the delay working state, and output a pause request or cancel a pause request to the CPU pipeline controller.

[0013] Further, the counter includes a delay counter and a frequency division counter; the instruction information further includes frequency division count enable open and frequency division count enable close. Both the delay counter and the frequency division counter are connected to the delay controller. The input end of the delay counter is connected to the output end of the adder, and the input end of the frequency division counter is connected to a control register, which is used to store a pre-divided value. The delay counter reloads to the output value of the adder when receiving a delay request; In the state where the frequency division count enable is closed, the delay counter works and the frequency division counter does not work, and the delay counter decrements by 1 per cycle; in the state where the frequency division count enable is open, both the delay counter and the frequency division counter work. The frequency division counter reloads to the pre-divided value when receiving a delay request or decrementing to 0, and the frequency division counter decrements by 1 per cycle. Whenever the frequency division counter decrements to 0, the delay counter decrements by 1.

[0014] Further, the instruction matching information includes one or more of a read instruction, a write instruction, an arbitrary instruction, a delay instruction, and a preset instruction.

[0015] Further, the first delay number and the second delay number are operand or delay immediate number; a general register is further included, and the general register is used to pre-store the operand. The instruction decoder decodes the operand register label, and then obtains the operand through the register.

[0016] Further, a selector is further included. The first input end of the selector is connected to the register, the second input end is connected to the decoder, and it is controlled by the selection of the instruction decoder, and the output end is connected to the adder.

[0017] An accurate delay control method for a CPU capable of accurate delay control, including the following steps: Step 1: Assume that in the t-th clock cycle, where t is a positive integer greater than 0, the CPU executes a valid delay instruction, decodes the delay instruction, obtains instruction information and outputs a delay request. The instruction information includes a first delay number, a second delay number, and instruction matching information. At the same time, the following operations are performed: The adder adds the first delay number and the second delay number, and provides the output value to the counter; The counter receives the delay request and reloads the output value of the adder; The delay controller receives the delay request and the instruction matching information, switches the delay working state to the busy state, saves the instruction matching information in the register and outputs it to the delay monitor; Step 2: Starting from the (t + 1)-th clock cycle, the CPU continues to execute the subsequent instructions, and at the same time, the following operations are performed: The counter performs a decrement count and outputs the count result to the delay controller; The delay monitor detects the pipeline in real time, matches the detected pipeline instructions according to the received instruction matching information, matches the pipeline privilege according to the preset privilege matching information, and transmits the matching result to the delay controller. When both the pipeline instruction and the pipeline privilege are successfully matched, the matching result is valid; When the delay controller is in the busy state and the matching result is valid, it sends a pause request to the CPU pipeline controller; when the count result reaches zero, the delay controller switches the delay working state to the idle state and cancels the pause request to the CPU pipeline controller, and the delay ends.

[0018] Further, in Step 1, the instruction information further includes enable opening of frequency division counting and enable closing of frequency division counting; the counter includes a delay counter and a frequency division counter, and the delay counter reloads to the output value of the adder when receiving the delay request; When the frequency division count enable is in the off state, the delay counter works and the frequency division counter does not work. The delay counter decrements by 1 every cycle. When the frequency division count enable is in the on state, both the delay counter and the frequency division counter work. The frequency division counter reloads to the pre - division value when it receives a delay request or decrements to 0, and the frequency division counter decrements by 1 every cycle. Whenever the frequency division counter decrements to 0, the delay counter decrements by 1.

[0019] Further, in step two, when the counting result of the delay controller reaches zero, it switches to the idle state, which specifically includes: when the frequency division count enable is off, when the counting result of the delay counter is 0, the delay working state switches to the idle state; when the frequency division count enable is on, when the counting results of both the delay counter and the frequency division counter are 0, the delay working state switches to the idle state.

[0020] Further, in step two, the instruction matching information includes one or more of a read instruction, a write instruction, all instructions, a delay instruction, and a preset instruction.

[0021] Further, in step one, the first delay number and the second delay number are delay immediate numbers or operands stored in general - purpose registers. If they are operands, the instruction decoder decodes the operand register label, and then obtains the operand through the register.

[0022] Compared with the prior art, a CPU capable of precise delay control and a precise delay control method provided by the present invention have the following beneficial effects: (1) It does not need to execute a loop body, nor does it need to perform flag - bit and interrupt - response processes. Therefore, its delay effect is not dependent on factors such as instruction fetch speed, instruction execution speed, and interrupt response speed, with high delay precision and determinable results; (2) The actual delay time mainly depends on the main frequency. Therefore, when executing this delay instruction at the same frequency on chips of different systems with the same core, the delayed time is almost the same, which maximally avoids the influence of factors such as system bus structure, bus delay, and timer configuration differences on the delay, and has good portability; (3) Only one instruction is required to complete various delays, with low complexity, an intuitive user interface, reducing the development complexity and the risk of errors; (4) The processor utilization rate is high, the power consumption is low, and the power consumption will not increase due to repeated instruction fetching and execution; (5) For the prior art, whether it is the loop body or the delay scheme of the hardware timer, the instruction fetch speed and execution speed will have a great impact on the actual delay time. The loop body needs to calculate the average time of each instruction accordingly, and the hardware timer needs to balance the interrupt response speed and flag bit query speed. In contrast, the delay control of this solution is executed synchronously and in parallel with the operation of the CPU. Once a matching instruction (this instruction is often set as the first instruction after the expected delay ends) is detected, a pause request is immediately sent to the pipeline, and steps such as interrupt response are not required. Therefore, it has a higher tolerance for instruction fetching and execution delays. Description of the Drawings

[0023] Figure 1 Partial structural block diagram of a CPU capable of precise delay control; Figure 2 Partial structural block diagram of an extended CPU capable of precise delay control. Specific Embodiments

[0024] The present invention will be further explained below with reference to the drawings and specific embodiments.

[0025] A CPU capable of precise delay control, as Figure 1 shown, includes: An instruction decoder, configured to decode valid delay instructions, obtain instruction information, and output a delay request. The instruction information includes a first delay number, a second delay number, and instruction matching information; An adder, with the first delay number and the second delay number input to the input end, and the output end connected to a counter; A counter, configured to reload the output value of the adder when receiving a delay request, decrement the count, and output the count result to a delay controller; A delay monitor, configured to detect the pipeline, receive instruction matching information, match the detected pipeline instructions according to the instruction matching information, match the detected pipeline privileges according to preset privilege information, and transmit the matching result to the delay controller. The instruction matching information may be one or more of a read instruction, a write instruction, an arbitrary instruction, a delay instruction, and a preset instruction. When the detected pipeline instruction can match the instruction matching information, it is considered that the instruction matching is valid. The pipeline privilege matching is used to match privilege modes, such as machine mode, supervisor mode, and user mode. When the detected pipeline privilege matches the preset privilege mode, it is considered that the privilege matching is valid.

[0026] A delay controller is used to receive a delay request and instruction matching information output by an instruction decoder, store the instruction matching information in a register and output it to a delay monitor, receive a counting result output by a counter, receive a matching result output by the delay monitor, switch the delay working state, and output a pause request or cancel a pause request to a CPU pipeline controller.

[0027] To further improve the delay accuracy, a frequency division timing function can be added on this basis, that is, the timing is divided into two gears, such as Figure 2 , the counter includes a delay counter and a frequency division counter, and the frequency division counter is used for prescaling counting; the instruction information also includes a frequency division counting enable open and a frequency division counting enable close. Both the delay counter and the frequency division counter are connected to the delay controller. The input end of the delay counter is connected to the output end of an adder, and the input end of the frequency division counter is connected to a control register, as Figure 2 shown. The control register is used to store the prescaling value, and the delay counter is reloaded with the output value of the adder when receiving a delay request.

[0028] In the state where the frequency division counting enable is closed, the delay counter works and the frequency division counter does not work. The delay counter decrements by 1 per cycle; in the state where the frequency division counting enable is open, both the delay counter and the frequency division counter work. The frequency division counter is reloaded with the prescaling value when receiving a delay request or when it decrements to 0. The frequency division counter decrements by 1 per cycle, and whenever the frequency division counter decrements to 0, the delay counter decrements by 1.

[0029] The first delay number and the second delay number can be operands stored in a register or can directly be immediate numbers; it also includes a general register. The operands are pre-stored in the register. The instruction decoder first decodes the operand register label and then obtains the operands from the register through the operand register label.

[0030] If the first delay number needs to support both operands and immediate numbers, a selector should also be included. The first input end of the selector is connected to the register, the second input end is connected to the decoder, and it is controlled by the selection of the instruction decoder, and the output end is connected to the adder.

[0031] Such as Figure 1 and Figure 2 The register in can be further divided into a general register, a control register, etc. The general register stores the delay number (operand). The control register stores preset control words, including a preset frequency division coefficient, a preset matching data, a preset matching mask, a preset machine privilege, etc.

[0032] An accurate delay control method for a CPU capable of accurate delay control includes the following steps: Step 1. Assume that in the t-th clock cycle, where t is a positive integer greater than 0, the CPU executes a valid delay instruction, decodes the delay instruction to obtain instruction information and outputs a delay request. The instruction information includes a first delay number, a second delay number, and instruction matching information. At the same time, the following operations are performed: The adder adds the first delay number and the second delay number and provides the output value to the counter. The counter receives the delay request and reloads the output value of the adder. The delay controller receives the delay request and the instruction matching information, switches the delay working state to the busy state, saves the instruction matching information in the register and outputs it to the delay monitor. Step 2. Starting from the (t + 1)-th clock cycle, the CPU continues to execute subsequent instructions. At the same time, the following operations are performed: The counter performs a decrement count and outputs the count result to the delay controller. The delay monitor continuously detects the pipeline, matches the detected pipeline instructions according to the received instruction matching information, matches the pipeline privileges according to the preset privilege matching information, and transmits the matching result to the delay controller. When both the pipeline instructions and the pipeline privileges are successfully matched, the matching result is considered valid. When the delay controller is in the busy state and the matching result is valid, it sends a pause request to the CPU pipeline controller; when the count result reaches zero, the delay controller switches the delay working state to the idle state and cancels the pause request to the CPU pipeline controller, and the delay ends.

[0033] To further improve the delay accuracy, the counter can be set to two gears. In Step 1, the instruction information also includes enable frequency division count open and enable frequency division count close; the counter includes a delay counter and a frequency division counter, and the delay counter reloads to the output value of the adder when it receives the delay request.

[0034] In the enable frequency division count close state, the delay counter works and the frequency division counter does not work, and the delay counter decrements by 1 per cycle; in the enable frequency division count open state, both the delay counter and the frequency division counter work. The frequency division counter reloads to the pre-frequency division value when it receives the delay request or decrements to 0, and the frequency division counter decrements by 1 per cycle; whenever the frequency division counter decrements to 0, the delay counter decrements by 1.

[0035] In Step 2, when the count result reaches zero, the delay controller switches to the idle state. Depending on whether the enable frequency division count is open, there are two cases: in the enable frequency division count close case, when the count result of the delay counter is 0, the delay working state switches to the idle state; in the enable frequency division count open case, when the count results of both the delay counter and the frequency division counter are 0, the delay working state switches to the idle state.

[0036] Example of using this method: Assume that the instruction stream is I1, I2, I3, and a 1us delay needs to be inserted between I1 and I2. Configure the control register CSR_DIV_VAL to the current main frequency (for example, if it is 144Mhz, write 144). Insert a delay instruction (delay) between I1 and I2, where the first delay number is the operand, and the register label of the first delay number is encoded as 5'b00000 (x0 register, RISCV specification defines x0 register as hardware connection 0); the second delay number is an immediate number, and the immediate number is encoded as 1; the frequency division count function is turned on, and the frequency division count enable (DIV_EN) is 1; the instruction matching information is all instructions, and the delay matching enable (DLY_MODE) turns on all instruction matching (AM). The instruction stream after the delay is I1, DLY, I2, I3.

[0037] To further verify the effect of this method, the prior art method and this method are used to insert a delay of 5 main frequency cycles between IO flip codes: PA = 0<<24; PA = 1<<24; The above is a simple IO (PA) flip c code, which inserts 5 main frequency cycle delays between flips. The existing technology is as follows: PA = 0<<24; __NOP__; __NOP__; __NOP__; __NOP__; __NOP__; PA = 1<<24; That is, between the IO flip codes, empty instructions are inserted to achieve the purpose of delay. As mentioned in the background technology, the execution of empty instructions depends on instruction fetch and execution delay, and the delay result is uncertain, which cannot meet high-precision requirements; PA = 1<<24, whether the C code is a single instruction or multiple instructions after compilation depends on the compilation options and additional factors such as the instruction encoding format. A single instruction can often be completed in a single cycle, while multiple instructions mean that more cycles are required to complete. Therefore, during the debugging stage, it is necessary to reduce or increase the number of __NOP__ according to the actual situation. At the same time, executing these empty instructions temporarily uses system resources and wastes power consumption.

[0038] This method only requires inserting a delay instruction between two instructions, such as: PA = 0<<24; asm("dly.i x0, 5, SM"); / / Disable frequency division, match STORE, delay number 5.

[0039] PA = 1 << 24; After the processing of this method, asm("dly.i x0, 5, SM") has a higher tolerance for instruction fetching and execution delays, and at the same time has better adaptability to the delay end point (PA = 1 << 24;).

Claims

1. A CPU capable of precise delay control, characterized in that, Including: An instruction decoder, which is used to decode a valid delay instruction, obtain instruction information and output a delay request. The instruction information includes a first delay number, a second delay number, and instruction matching information; An adder, with the first delay number and the second delay number input at the input end, and the output end connected to a counter; A counter, which is used to reload the output value of the adder when receiving a delay request, decrement the count, and output the count result to a delay controller; A delay monitor, which is used to detect a pipeline, receive instruction matching information, match the detected pipeline instructions according to the instruction matching information, match the detected pipeline privileges according to preset privilege information, and transmit the matching result to the delay controller; A delay controller, which is used to receive the delay request and instruction matching information output by the instruction decoder, store the instruction matching information in a register and output it to the delay monitor, receive the count result output by the counter, receive the matching result output by the delay monitor, switch the delay working state, and output a pause request or cancel a pause request to the CPU pipeline controller.

2. The CPU capable of precise delay control according to claim 1, wherein, The counter includes a delay counter and a frequency division counter; the instruction information further includes enabling frequency division count to open and enabling frequency division count to close. Both the delay counter and the frequency division counter are connected to the delay controller. The input end of the delay counter is connected to the output end of the adder, and the input end of the frequency division counter is connected to a control register, which is used to store a pre-frequency division value. The delay counter reloads to the output value of the adder when receiving a delay request; In the state where enabling frequency division count is closed, the delay counter works and the frequency division counter does not work. The delay counter decrements by 1 per cycle; in the state where enabling frequency division count is open, both the delay counter and the frequency division counter work. The frequency division counter reloads to the pre-frequency division value when receiving a delay request or decrementing to 0. The frequency division counter decrements by 1 per cycle. Whenever the frequency division counter decrements to 0, the delay counter decrements by 1.

3. The CPU capable of precise delay control according to claim 1 or 2, characterized in that The instruction matching information includes one or more of a read instruction, a write instruction, an arbitrary instruction, a delay instruction, and a preset instruction.

4. The CPU capable of precise delay control according to claim 1 or 2, characterized in that, The first delay number and the second delay number are operands or delay immediate numbers; a general register is further included, and the general register is used to pre-store operands. The instruction decoder decodes the operand register label, and then obtains the operands through the register.

5. The CPU capable of precise delay control according to claim 4, wherein A selector is further included. The first input end of the selector is connected to the register, the second input end is connected to the decoder, and it is controlled by the selection of the instruction decoder, and the output end is connected to the adder.

6. A precise delay control method for a CPU capable of precise delay control, characterized in that, Including the following steps: Step 1: Assume that in the t-th clock cycle, where t is a positive integer greater than 0, the CPU executes a valid delay instruction, decodes the delay instruction, obtains instruction information and outputs a delay request. The instruction information includes a first delay number, a second delay number, and instruction matching information. At the same time, the following operations are performed: The adder adds the first delay number and the second delay number, and provides the output value to the counter; The counter receives the delay request and reloads the output value of the adder; The delay controller receives the delay request and instruction matching information, switches the delay working state to the busy state, saves the instruction matching information in the register and outputs it to the delay monitor; Step 2: Starting from the (t + 1)-th clock cycle, the CPU continues to execute subsequent instructions and simultaneously performs the following operations: The counter performs a decrement count and outputs the count result to the delay controller; The delay monitor continuously detects the pipeline, matches the detected pipeline instructions according to the received instruction matching information, matches the pipeline privileges according to the preset privilege matching information, and transmits the matching result to the delay controller. When both the pipeline instructions and the pipeline privileges are successfully matched, the matching result is valid; When in the busy state and the matching result is valid, the delay controller sends a pause request to the CPU pipeline controller; when the count result reaches zero, the delay controller switches the delay working state to the idle state and cancels the pause request sent to the CPU pipeline controller, and the delay ends.

7. The precise delay control method of the CPU capable of precise delay control according to claim 6, characterized in that, In Step 1, the instruction information further includes enabling and disabling of the divided-frequency count; the counter includes a delay counter and a divided-frequency counter. The delay counter reloads to the output value of the adder when receiving a delay request; In the state where the divided-frequency count is disabled, the delay counter works and the divided-frequency counter does not work, and the delay counter decrements by 1 per cycle; in the state where the divided-frequency count is enabled, both the delay counter and the divided-frequency counter work. The divided-frequency counter reloads to the pre-divided frequency value when receiving a delay request or when it decrements to 0, and the divided-frequency counter decrements by 1 per cycle; whenever the divided-frequency counter decrements to 0, the delay counter decrements by 1.

8. The precise delay control method of the CPU capable of precise delay control according to claim 7, characterized in that, In Step 2, when the count result reaches zero, the delay controller switches to the idle state, specifically including: when the divided-frequency count is disabled, when the count result of the delay counter is 0, the delay working state switches to the idle state; when the divided-frequency count is enabled, when the count results of both the delay counter and the divided-frequency counter are 0, the delay working state switches to the idle state.

9. The precise delay control method of a CPU capable of precise delay control according to any one of claims 6-8, characterized in that, In Step 2, the instruction matching information includes one or more of a read instruction, a write instruction, all instructions, a delay instruction, and a preset instruction.

10. The precise delay control method of a CPU capable of precise delay control according to any one of claims 6-8, characterized in that, In Step 1, the first delay number and the second delay number are delay immediate numbers or operands stored in a general register. If they are operands, the instruction decoder decodes the operand register label, and then the operand is obtained through the register.

Images