Memory testing method and device based on AI technology and medium

Abstract

The invention discloses a memory test method and device based on an AI technology and a medium, and the method comprises the following steps: 1) obtaining structure analysis data and memory type description information of a to-be-tested memory, and generating a test intention vector used for expressing a test target; 2) taking the test intention vector as an input to generate a test excitation sequence; 3) executing the test excitation sequence, and performing multi-cycle test on the storage array to form a multi-modal response feature set; 4) inputting the multi-modal response feature set into a graph neural network, performing fault type identification and causal path reasoning, and generating a fault tag sequence and a reasoning path graph; 5) based on the characteristic difference between the inference path diagram and the test excitation sequence, weight parameter updating of the depth generation model is carried out; and 6) generating a test excitation sequence based on the updated depth generation model to test the memory. The intelligent level and the test coverage rate of the memory test can be effectively improved.

Description

Technical Field

[0001] The present invention relates to integrated circuit testing technology, and in particular to a memory testing method, device and medium based on AI technology. Background Art

[0002] With the development of memory chips towards high capacity, high speed and high integration, the structural complexity and manufacturing process precision have been continuously improved. Traditional rule-driven and static excitation-based testing methods have difficulty in comprehensively covering potential failure risks. Especially in the high-speed memory testing process for heterogeneous structures such as SRAM, DRAM, and MRAM, the following key challenges exist: First, the current testing methods lack in-depth analysis of the chip structure-level information, making it difficult to identify structure-sensitive areas such as bit crossing, edge effect, and process anomalies, resulting in insufficient fault excitation coverage. Second, the testing strategies generally rely on manual experience configuration, and cannot generate expressive excitation sequences with fault driving ability according to the target structure, making it difficult to achieve targeted fault triggering and behavior coverage. Third, the response data collection mostly exists in a single-modal form, and fails to fully integrate multi-source information such as operation behavior, electrical response, and environmental disturbance, restricting the accuracy of fault classification and the integrity of the inference path. Fourth, the current system model lacks a dynamic feedback mechanism and adaptive ability, cannot automatically optimize the testing strategy according to the test results, and is also difficult to achieve efficient migration and deployment of the model between different hardware platforms.

[0003] Therefore, there is an urgent need for a fast testing method that integrates structure analysis, semantic modeling, multi-modal response fusion, and feedback optimization mechanism, and constructs an AI testing system with intelligent generation, accurate discrimination, and cross-platform self-evolution capabilities to improve the testing efficiency, accuracy, and deployment flexibility of modern memory products. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide a memory testing method, device and medium based on AI technology in view of the defects in the prior art.

[0005] The technical solution adopted by the present invention to solve its technical problems is: A fast memory testing method based on AI, comprising the following steps: 1) Obtain the structure analysis data and memory type description information of the memory to be tested, and generate a test intention vector for expressing the test target according to the structure analysis data and memory type description information of the memory to be tested; Wherein, the structure analysis data includes the storage unit arrangement matrix, bit line word line structure, and redundancy mapping relationship of the memory to be tested; 2) Using the test intention vector as the input, combined with the memory target fault mode database, input it into a preset deep generation model to construct a fault coverage semantic representation and generate a test excitation sequence; 3) Execute the test excitation sequence to perform multi - cycle testing on the storage array, collect the electrical signal data, operation timing traces, and operating environment parameters during the testing process to form a multi - modal response feature set; 4) Input the multi - modal response feature set into a graph neural network for fault type identification and causal path reasoning to generate a fault label sequence and an inference path graph; 5) Based on the feature differences between the inference path graph and the test excitation sequence, calculate the deviation vector and back - propagate to obtain the feedback gradient for weight update of the deep generation model; 6) Generate a test excitation sequence based on the updated deep generation model for memory testing.

[0006] According to the above - mentioned solution, the structure analysis data hierarchically unfolds the physical structure information of the memory to be tested. Through layout structure analysis, a storage cell arrangement matrix, bit - line word - line structure, and redundancy mapping relationship are constructed to obtain the structure analysis data; Among them, the physical structure information includes layout netlist, physical address mapping diagram, redundancy structure configuration table, bit - line layout file, and word - line group structure information.

[0007] According to the above - mentioned solution, the type description information is attribute information including memory type, process technology node, number of stacked layers, dielectric type, transistor type, etc.

[0008] According to the above - mentioned solution, generating a test intention vector for expressing the test target based on the structure analysis data and memory type description information of the memory to be tested; specifically as follows: Based on the structure analysis data, extract the key structure - sensitive area features to form a structure sensitivity feature vector; based on the structure sensitivity feature vector and the memory type description information, construct a test construction objective function to generate a test intention vector for expressing the test target.

[0009] According to the above - mentioned solution, based on the structure analysis data, extracting the key structure - sensitive area features to form a structure sensitivity feature vector specifically includes: Process weakness bit identification: Identify the areas that are prone to unstable behavior during the manufacturing process, including high - density bit - crossing areas, critical dimension error sections, PMOS - NMOS boundary transition areas, etc. Use the lithography model combined with the residual mapping technology to extract the coordinate points of the corresponding logic units to form a set of process anomaly positions; Edge cell area extraction: Locate the groups of memory cells at the boundaries of the row-column matrix, record their redundant mapping counts and failure history statistics values, and form an edge cell feature set; Bit-crossing dense area extraction: Statistically analyze the integration density of bit lines and word lines in the crossing area, and mark the error-prone nodes in combination with the coupling capacitance threshold to form a cross-interference area set; Based on the above three sets, construct a unified structural sensitive area feature representation tensor, and encode the tensor into a structural sensitivity feature vector , and the structural sensitivity feature vector includes the following fields: node density statistics value, structural type identifier, failure history weight, and process anomaly probability estimate.

[0010] According to the above scheme, test the intent vector The fields included are: target access area index , address jump frequency control item , potential failure induction score , concurrent conflict warning weight .

[0011] According to the above scheme, construct a failure coverage semantic representation and generate a test excitation sequence; specifically as follows: Based on the structural intent vector Precisely drive the depth generation model, perform semantic-level modeling and access path construction on the target failure coverage pattern, and finally generate a test excitation sequence with accurate coverage, controllable path, and traceable index ; Perform position embedding on to obtain a structural semantic representation sequence , where represents the embedding result of the corresponding dimension; Subsequently, the structural semantic representation sequence is combined with the failure coverage task label vector to generate a structure-failure correlation vector map for capturing the prior features of the structural area and historical failure mapping.

[0012] Input the structural semantic representation sequence and the structure-failure correlation vector map into the multi-layer Transformer encoder of the depth generation model for vector parsing, and the output vector parsing result is a set of semantic attention values and a position weight distribution vector ; Based on the vector parsing result and the target failure type sample features, construct an access path logic diagram for triggering the target sensitive area; Unfold the structure of the access path logic diagram to generate a test excitation sequence corresponding to the test intent vector ​ 。

[0013] According to the above scheme, the logic diagram for constructing the access path to trigger the target sensitive area is as follows: Obtain the semantic attention value and the position weight distribution , and combine the structural excitation paradigm vectors in the fault type sample library to construct the logic diagram of the structural access path.

[0014] Specifically, extract the target fault type feature subset that matches the current from the fault type sample library, where the features include typical access order, fan-out path, register perturbation sequence, and interleaved address mapping rule; Combine the semantic attention value , and perform the extraction of the initial topological structure of the access path, mapping the access method in it to the physical location pointed to by the target structure area coordinates . On this basis, use the position weight distribution to control the segment depth, number of concurrent nodes, and address jump amplitude of the access path, and construct the access path logic diagram ; The access path logic diagram is a directed graph structure, where nodes represent access actions, edges represent timing and control dependencies, and edge weights include indicators such as access delay, coupling interference, and logic coverage.

[0015] According to the above scheme, perform structural expansion on the access path logic diagram to generate a test stimulus sequence corresponding to the test intention vector ; specifically as follows: First, based on the timing dependency constraints and access instruction classification in it, perform a depth-first traversal of the graph structure, linearly sort the access nodes in the graph according to the control dependency order, and obtain the access path sequence ; For each path segment in the access path sequence , the system combines the original structure sensitive area indicators and the jump control parameters to generate an access control block , and the content of the access control block includes address jump mode, word line selection identifier, read / write control bit, and precharge cycle mask; Sequentially splice all the access control blocks, and finally combine them to form a test stimulus sequence: ; Among them, each element in the set represents a structural intention vector Mapped control, target fault type feature subset Adapted and distributed by the position vector The test control instruction group generated by the constraint.

[0016] According to the above scheme, the multi-modal response feature set is as follows:

[0017] Among them: Is the Electrical response feature in the i-th cycle; among them, Represents the Voltage in the i-th cycle, Represents the Current in the i-th cycle Represents the Capacitance in the i-th cycle; Is the operation timing field of the i-th excitation instruction; among them, Is the timestamp, Is the operation type, Is the row and column address; among them, the i-th excitation instruction corresponds to the Excitation instruction in the i-th cycle; Is the environmental state variable in the i-th cycle; among them, Is the chip surface temperature sequence; Is the power supply voltage fluctuation sequence; Is the spatial electromagnetic interference index sequence; Is the Fusion response feature unit generated in the cycle.

[0018] According to the above scheme, input the multi-modal response feature set into the graph neural network model to perform graph structure feature encoding and generate a fault feature graph vector; Perform fault classification processing on the fault feature graph vector to obtain the corresponding fault type label sequence; Based on the fault feature graph vector and node nested path information, generate an inference path graph for representing the causal path of test excitation triggering a fault.

[0019] According to the above scheme, input the multi-modal response feature set into the graph neural network to perform fault type recognition and causal path reasoning, generating a fault label sequence and an inference path graph; Perform causal path analysis on the graph structure to construct an inference path graph during the test trigger process .

[0020] The system first extracts all node pairs from the graph structure , and the node pairs satisfy the following conditions: The time order holds: ; Spatial adjacency: with the difference being less than a preset threshold ; The possibility of a fault impact exists: belongs to the set of possible triggering consequences (based on historical path statistics).

[0021] For the node pairs that meet the above conditions, construct a set of path edges , and define the inference path graph as follows: Inference path graph generation:

[0022] where: is the set of subgraph nodes containing the predicted fault nodes; represents the th feature vector of the th node in the th layer; is the set of directed edges that satisfy the time - space - causality inference conditions; is the causality verification function used to determine whether node

[0023] is likely to affect node According to the above scheme, based on the feature differences between the inference path graph and the test excitation sequence, calculate the deviation vector and backpropagate it to obtain the feedback gradient for updating the weights of the deep generation model; Among them, the following method is used to calculate the deviation vector: Measure the path similarity and trigger correlation between the fault node in the inference path graph and the excitation instruction of the test excitation sequence through feature matching; the features include address overlap degree, time alignment, and operation type consistency; Calculate the matching deviation vector through feature difference accumulation, where each in the matching deviation vector represents the magnitude of the matching error between the

[0024] According to the above solution, the memory test is to construct a model adaptation vector and generate a platform-customized model based on the updated depth generation model and the current test platform parameter configuration; Deploy the platform-customized model to the target test platform or edge node, complete the configuration of the model execution engine, and realize the adaptive execution of a new round of test tasks.

[0025] The present invention also provides an electronic device, including: One or more processors; And A storage device for storing one or more programs, wherein, when the one or more programs are executed by the one or more processors, the one or more processors are caused to execute the method described in any one of the above solutions.

[0026] The present invention also provides a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the method described in any one of the above solutions is realized.

[0027] The beneficial effects produced by the present invention are: 1. By constructing a structure sensitivity feature vector and generating a test intention vector based on the test to construct an objective function, the present invention realizes the matching between the test and the target memory structure, thereby accurately identifying potential fault areas before the test sequence is generated. Compared with traditional experience-driven or general test vector construction methods, the present invention significantly improves the pertinence and coverage efficiency of test stimulus generation, and is particularly suitable for detecting tiny faults in complex heterogeneous memory structures.

[0028] 2. By inputting multi-modal response features (including electrical signals, timing trajectories, and environmental parameters) into a graph neural network, the present invention completes the generation of fault labels and causal path reasoning. This method can realize the visualization of the structural-level causal chain and interpretable fault analysis, solves the problem that existing methods are difficult to locate the root cause of faults in complex interaction scenarios, and improves the cognitive ability of complex fault modes.

[0029] 3. Realize the adaptive optimization of the test strategy and platform migration and deployment. The weight of the depth generation model is updated through a feedback gradient mechanism, and a model adaptation vector is constructed based on platform parameters to complete model customization and deployment, enabling the test system to have the ability of continuous evolution and wide platform adaptability. Compared with the static model test method, the present invention has stronger versatility and deployment flexibility, and is suitable for distributed automatic test requirements under multi-process and multi-chip platforms. Description of the Drawings

[0030] The present invention will be further described below in conjunction with the drawings and embodiments. In the drawings: Figure 1It is the flowchart of the method according to the embodiments of the present invention. Detailed implementation manners

[0031] In order to make the objectives, technical solutions and advantages of the present invention clearer and more understandable, the present invention will be further described in detail below with reference to embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0032] As Figure 1 shown, an embodiment of the present invention provides a fast memory test method based on AI technology, and the method includes the following steps: S100. Based on the structure analysis data and type description information of the memory to be tested of the memory under test, extract the structure-sensitive area features of the memory, and generate a test intent vector TIV for test construction; S110. Obtain the physical structure information and type description information of the memory under test; In this step, first, extract the underlying structure information and process description data related to the target test chip from the memory design data and process database. The structure information includes layout netlist, physical address mapping diagram, redundant structure configuration table, bit line layout file, word line group structure information; the type description information is the classification label to which the memory belongs and its process node parameters, and specifically may include basic attributes such as memory type (such as SRAM, DRAM, MRAM, ReRAM, etc.), process node (such as 28nm, 14nm, 7nm, etc.), number of stacked layers, medium type, and transistor type.

[0033] S120. Hierarchically expand the physical structure information, perform layout structure analysis, obtain a storage unit arrangement matrix, a bit line and word line structure, and a redundant bit mapping relationship, obtain structure analysis data, and convert it into a readable matrix format; the specific steps are as follows: Generate a storage unit arrangement matrix, which is used to express the relative spatial positions and logical associations of each storage unit in a two-dimensional layout; Extract the bit line and word line structure information, and identify the actually connected control signal paths in each row and column; Construct a redundant bit mapping relationship graph, which is used to record the jump logic between the standard address space and the redundant address space; The structure analysis data obtained in this step will be used as the input data set for subsequent sensitive area extraction, named the structure analysis data set which contains multi-dimensional feature structures such as physical location information, redundant compensation relationship, and address mapping rules. As the basic data for extracting feature vectors in the subsequent S130 stage.

[0034] S130. Extract key sensitive area features from the memory structure information, including process weakness bits, edge cell area extraction, and bit-crossing dense area extraction, to generate a structure sensitivity feature vector ; After obtaining the structure analysis data set in step S130, analyze the physical areas that may cause test blind spots or easily trigger hidden faults, and extract structure sensitive parameters strongly correlated with test defect triggering. Specifically, it includes feature extraction in the following three dimensions: Process weakness bit identification: Identify the areas prone to unstable behavior during the manufacturing process, including high-density bit-crossing areas, critical dimension error sections, PMOS and NMOS boundary transition areas, etc. Use the lithography model combined with the residual mapping technology to extract the coordinate points of the corresponding logic units to form a set of process anomaly positions ; Edge cell area extraction: Locate the storage cell groups at the row and column matrix boundaries, record their redundant mapping quantities and fault history statistical values, and form an edge cell feature set ; Bit-crossing dense area extraction: Statistically analyze the integration density of bit lines and word lines in the crossing area, and mark the error-prone nodes in combination with the coupling capacitance threshold to form a set of cross-interference areas ; Based on the above three sets, the system constructs a unified structure sensitive area feature representation tensor .

[0035] Compress and encode the tensor into a structure sensitivity feature vector , which is a one-dimensional representation and contains the following field contents: node density statistical value, structure type identifier, fault history weight, process anomaly probability estimate, etc. The vector will be directly used as the core input parameter in step S140 to participate in the modeling of the objective function and the construction of the expression vector

[0036] S140. Based on the structure sensitivity feature vector and the memory type description information, construct a test construction objective function, perform preliminary expression encoding on the objective function, and generate a test intention vector .

[0037] In this step, on the basis of completing the construction of the feature vector, input the structure sensitivity vector and the previously obtained memory type description information into the test construction objective function together to generate an expressive vector that can be recognized by the deep model, that is, the test intention vector .

[0038] Specifically, first construct a test construction objective function , the function is defined to fuse, transform, and compress the structure vector with type description information to express intention information such as the coverage area expectation of the current test target, the characteristics of the excitation sequence, and the structure form of the trigger circuit. The function adopts a structure composed of an embedding layer, a convolutional layer, and an attention module to perform a deep mapping between the structure features and semantic labels.

[0039] During the expression process, the function outputs an intermediate expression tensor, and further performs linear stretching and normalization processing on this tensor to finally form a test intention vector . The test intention vector can be set to a fixed length in dimension (such as 128 dimensions, 256 dimensions, etc.), and each dimension corresponds to a type of structure-sensitive trigger path, fault mode matching category, or excitation strategy classification.

[0040] This test intention vector will be directly used as the input of the subsequent deep generation model to generate the target test excitation sequence .

[0041] Through the complete execution of S100, in the initialization stage of the test task, a deep analysis of the structure of the memory under test, the process weaknesses, and the fault trigger characteristics is completed, and a unified structure sensitivity feature vector is constructed, and further a test intention vector with semantic expression ability is constructed. This vector not only accurately reflects the current structure state of the memory and the potential fault risk area, but also provides basic structural semantic support for test excitation generation, multi-modal data acquisition, fault path inference, and model feedback optimization in the subsequent steps, ensuring the continuity, intelligence, and closed-loop collaboration of the test process.

[0042] S200. Input the test intention vector TIV into a preset deep generation model to perform adaptive modeling on the target fault coverage mode and generate a test excitation sequence TES.

[0043] The AI technology applied in this embodiment includes deep generation models in the field of deep learning; Step S200 includes the following steps: S210. Input the test intention vector into a preset deep generation model constructed based on the Transformer structure for vector parsing.

[0044] Specifically, after completing the feature encoding in S130, a structure-driven test intention vector is obtained, and the fields it contains include: the target access area index and the address jump frequency control item , Fault-induced potential score , Concurrent conflict warning weight . This vector is used as a key input feature and input into a deep generative model constructed based on the Transformer network structure.

[0045] The deep generative model consists of a multi-head attention mechanism, a multi-layer encoder structure, and a positional encoding sub-module, and has the capabilities of context feature memory and temporal structure learning. Its parsing process is as follows: Call the pre-trained model weights in the deep generative model and load the initial state parameters , and execute the vector parsing process.

[0046] During the vector parsing process, first perform positional embedding to obtain a sequence of structural semantic representations , where represents the embedding result of the th dimension; subsequently, the sequence of structural semantic representations is combined with the fault coverage task label vector to generate a structural-fault association vector graph , which is used to capture the prior features of the mapping between structural regions and historical faults.

[0047] Furthermore, the sequence of structural semantic representations and the structural-fault association vector graph are input into a multi-layer Transformer encoder for vector parsing. After completing the vector parsing, the deep generative model outputs a set of semantic attention values and a positional weight distribution vector , which are used to guide the construction of the access path logic graph in the next stage.

[0048] S220. Construct an access path logic graph for triggering the target sensitive area based on the vector parsing result and the target fault type sample features.

[0049] After completing the vector parsing, obtain the semantic attention value and the positional weight distribution , and further combine the structural excitation paradigm vector in the fault type sample library to execute the construction of the logic graph of the structural access path.

[0050] Specifically, extract a subset of target fault type features and matching the current from the fault type sample library, and the features include typical access order, fan-out path, register perturbation sequence, interleaved address mapping rule, etc.

[0051] Combined with the semantic attention value obtained from S210 , perform the extraction of the initial topological structure of the access path, and map the access method in it to the physical location pointed to by the target structure area coordinates . On this basis, use the position weight distribution to control the segmentation depth, number of concurrent nodes, and address jump amplitude of the access path, and construct an access path logic graph .

[0052] This access path logic graph is a directed graph structure, where nodes represent access actions (such as write 0, write 1, read, precharge, reserve, etc.), edges represent timing and control dependencies, and edge weights represent indicators such as access latency, coupling interference, and logical coverage. The system introduces an address sequence constraint and a bit line conflict detection module during the graph construction process to ensure the executability of the path logic and the effectiveness of target fault induction.

[0053] The output of this step is the direct input object for the subsequent generation of the test stimulus sequence.

[0054] S230. Expand the structure of the access path logic graph to generate a test stimulus sequence corresponding to the test intent vector .

[0055] After the access path logic graph is constructed , further execute the path expansion and test sequence generation process. Specifically, first, based on the timing dependency constraints and access instruction classification in it, perform a depth-first traversal of the graph structure, linearly sort the access nodes in the graph according to the control dependency order, and obtain an access path sequence .

[0056] For each path segment in the access path sequence , the system combines the original structure sensitive area indicators and the jump control parameters to generate an access control block .

[0057] Sequentially splice all access control blocks, and introduce a timing boundary interpolation factor and an address perturbation weight , and finally combine them to form a test stimulus sequence:

[0058] Among them, each represents an access controlled by a structure intent vector Mapping control, fault-induced template Adapted and by the position distribution vector The control instruction group generated by the constraint.

[0059] In this embodiment, to meet the test execution and response acquisition requirements in the subsequent step S300, the system Embeds an index identification bit and a path traceability label at the end of each control block to assist in the subsequent one-to-one mapping of response data and excitation instructions, ensuring the traceability of the test execution path.

[0060] This sequence Will be used as the input data for the excitation process in S300 and is used to call the actual test task.

[0061] Through the implementation manner of the above S200, it is possible to accurately drive the deep generation model based on the structure intention vector To semantically model the target fault coverage pattern and construct the access path, and finally generate a test excitation sequence with accurate coverage, controllable path, and traceable index , providing high-adaptability test input support for subsequent rapid testing, fault collection, and intelligent discrimination, and constituting a key feedforward information flow element in the AI-driven closed-loop system.

[0062] S300. Execute the test excitation sequence TES, collect the response data in the corresponding test cycle, including electrical signal data, operation timing data, and operating environment parameters, and construct a multimodal response feature set MRF.

[0063] S310. Execute the test excitation sequence In the memory array, collect the voltage, current, and capacitance change values in each cycle during the test process to generate an electrical signal sequence .

[0064] In this step, after receiving the test excitation sequence generated in S230 , the sequence is gradually applied to the target memory array through the test control engine. Is an operation instruction sequence expanded by time steps, including an operation type identifier , access address information , write / read flag And control timing parameters , where Represents the timing cycle where the current instruction is located.

[0065] During the test execution process, the system synchronously collects the electrical parameters of the target unit in each excitation cycle , including the voltage value , current value With local capacitance fluctuations , a corresponding signal observation vector is generated .

[0066] The system splices the signal vectors collected in consecutive excitation cycles to generate an electrical signal sequence , which is used to reflect the dynamic electrical response characteristics in the storage array under the action of the excitation.

[0067] Electrical signal acquisition construction method:

[0068] Wherein: represents the voltage measurement value of the target storage unit in the th cycle; represents the current change value on the bit line in the corresponding cycle; represents the capacitance perturbation data of the measurement point; represents the total number of execution cycles of the test excitation sequence.

[0069] This formula ensures that the collected electrical response signals have time continuity and physical meaning, provides a basis for constructing high-dimensional dynamic response features, enables subsequent models to learn abnormal behavior patterns from the change trends, and is applicable to dealing with soft errors and occasional breakdown defects.

[0070] S320. Extract the access operation trajectory from the process of executing the test excitation, including the access timestamp, operation type, row and column addresses, and construct an operation timing sequence ; In this step, while the system is executing , it parses the operation trajectory of the instruction execution flow, extracts the timing control information and the spatial access path, and generates a timing operation sequence . This sequence is used to express the timing characteristics and access logic order of the excitation sequence at the execution level, and is the key intermediate data for constructing the subsequent timing-response fusion model.

[0071] Specifically, the system extracts the following information fields: Access timestamp vector : Records the physical time (or system clock cycle) when each operation instruction is executed; Operation type identification vector : Indicates that each instruction is read (R), write (W), erase (E), etc.; Access address vector : Includes the row address , column address , which is used to indicate the spatial position of the operating unit.

[0072] After combining the above three vectors, the system constructs an operation timing sequence : Operation timing sequence construction method:

[0073] Where: is the execution timestamp of the th excitation instruction; is the instruction type, and the value range includes R, W, E, etc.; and are the target row and column addresses respectively.

[0074] Technical effect: This formula establishes the mapping between the excitation flow in the physical address space and the execution time axis, provides strong timing constraints for multimodal fusion modeling, and supports path backtracking and time synchronization mapping in the subsequent graph model.

[0075] S330. Based on the electrical signal sequence and the operation timing sequence , combined with operating state variables such as real-time temperature, voltage, and electromagnetic interference parameters, generate a multimodal response feature set .

[0076] After completing the acquisition of electrical response data and operation behavior trajectories , the system further fuses real-time operating state variables to generate a high-dimensional feature set. The operating state variables are collected by the environmental perception unit and include: Chip surface temperature sequence ; Power supply voltage fluctuation sequence ; Spatial electromagnetic interference index sequence .

[0077] The system uniformly models the above operating state variables as an environmental state vector set , and combines it with and to form a multimodal response feature set with a unified structure .

[0078] Multimodal response feature set fusion method:

[0079] Where: is the electrical response characteristic within the th cycle; where represents the voltage within the th cycle, represents the current within the th cycle represents the capacitance within the th cycle; is the operation timing field of the th excitation instruction; where is the timestamp, is the operation type, is the row and column address; where the th excitation instruction corresponds to the excitation instruction of the th cycle; is the chip surface temperature sequence; is the power supply voltage fluctuation sequence; is the spatial electromagnetic interference index sequence; is the fused response feature unit generated in the th cycle.

[0080] Technical effect: This formula realizes cross-domain data synchronization mapping, fuses electrical signals, operation behaviors, and environmental variables into a unified data structure, improves the consistency, timing resolution, and input feature density of the data space, and enables subsequent graph neural network processing to have context awareness capabilities.

[0081] When traditional methods collect test responses, they mostly store them in the form of single signals, ignoring the coupling effect between the operation sequence and environmental factors, resulting in a weak generalization ability of the fault discrimination model and a low soft error recognition rate. By introducing the above fusion model, the system has the following advantages: Supports the construction of graph modeling structures; explicitly retains access semantics; accurately maps the influence of the process environment on fault behaviors.

[0082] Through the execution of S300, the system realizes the full-link test data acquisition process from physical excitation application to multi-modal response expression, and the generated feature set has high time resolution, high-dimensional multi-channel, and cross-domain fusion characteristics, which not only improves the perception depth of the fault detection model but also enhances the system's ability to identify complex coupled faults. The constructed data structure has good structural scalability while maintaining timing consistency, is suitable for various AI discrimination architectures such as graph neural networks, causal graph modeling, and structural variation reasoning, and ensures data compatibility and feature integrity in the subsequent processing stage of the system.

[0083] S400. Input the multi-modal response feature set (MRF) into the graph neural network model for fault type identification and root cause reasoning, and output the fault discrimination label and the reasoning path graph (RPG). S410. Input the said multi-modal response feature set into the graph neural network model for graph structure feature encoding to generate the fault feature graph vector .

[0084] In this step, the system receives the multi-modal response feature set output by S330 , and constructs the input graph structure of the graph neural network in the form of node features, and performs node feature encoding and relationship construction. Each record in contains the following fields: voltage , current , capacitance perturbation , timestamp , operation type , row and column address .

[0085] First, the system constructs the input graph with as the node features, where the node set , and the edge set is established according to the time sequence and the degree of spatial address overlap.

[0086] Furthermore, a multi-head graph attention network (GAT) is used to perform fusion calculation on the embedded features of each node. The formula is as follows: Graph node feature encoding formula:

[0087] Where: represents the feature vector of the th node in the th layer; represents the set of all nodes adjacent to the th node; is the attention weight of node and in the th layer; is the weight matrix of the th layer; is the activation function, such as ReLU or GELU.

[0088] After the above-mentioned feature propagation process is executed After the layer, the system obtains the set of feature vectors of the full-image encoding , which is used for subsequent fault discrimination and causal graph construction.

[0089] In this embodiment, the graph attention mechanism can effectively mine multiple semantic relationships between nodes based on time order, spatial overlap, signal similarity, etc., form graph-level fault coding features with high expression ability, and enhance the model's perception of abnormal response patterns.

[0090] S420. Perform fault classification processing on the fault feature graph vector to obtain the corresponding fault type label sequence .

[0091] After completing the encoding of the graph node feature representation , this step uses a fault discrimination classifier to perform label inference on each node representation vector to obtain the corresponding fault type prediction label sequence .

[0092] First, define the fault classification label set , where each represents a fault type, such as transient interference, stable breakdown, data retention anomaly, soft error, coupling interference, etc.

[0093] Specifically, a multi-layer perceptron (MLP) with attention enhancement is used to perform multi-class discrimination on each node embedding vector, and the formula is as follows: Fault label prediction formula:

[0094] Where: is the classification weight matrix; is the bias vector; is the node final graph embedding vector; represents the node corresponding fault type label; represents selecting the class index with the highest probability.

[0095] Output the above label sequence to the user visible layer and the model feedback layer as the fault discrimination result, which is used for root cause tracing analysis and the error backpropagation optimization module in S500.

[0096] In S430, it serves as the node identification field in the path graph and also as the differential calculation reference vector in S500, constituting the model error objective function.

[0097] The fault label prediction formula maps the high-dimensional graph embedding vector to the category space, and on the basis of maintaining the semantic continuity of the space, realizes the automatic recognition and quantitative classification of multi-class memory fault phenomena.

[0098] S430. Based on the fault feature map vector and the node nested path information, generate an inference path graph , which is used to represent the causal path of the test stimulus triggering the fault.

[0099] In this step, after obtaining the complete graph node encoding and the corresponding label , further perform causal path analysis on the graph structure to construct an inference path graph during the test trigger process .

[0100] First, extract all node pairs from the graph structure that satisfy the following conditions: The time sequence holds: ; Spatial adjacency: The difference between is less than the threshold ; The possibility of fault influence exists: belongs to the possible trigger consequence set of

[0101] Based on the historical path statistics). For the node pairs that meet the above conditions, construct an edge set of the path and define the inference path graph as follows:

[0102] Where: is the sub-graph node set containing the predicted fault nodes; is the directed edge set that meets the time-space-causal inference conditions; is the causal verification function, which is used to judge whether the node may affect the node .

[0103] This graph structure captures the spatio-temporal causal relationship between the test stimulus and the fault manifestation, supports the practical storage fault logic simulation of multi-path concurrency and multi-cause multi-effect, and is the key intermediate representation for system feedback learning and path closed-loop.

[0104] In step S400, by introducing a graph neural network structure and a graph inference algorithm, the complete structural mapping from multi-modal response data to fault type labels and inference path graphs is achieved, with the following technical features and effects: The multi-head graph attention mechanism is adopted to extract local anomaly features, realizing the joint fault characterization in multiple dimensions such as time, space, and signal strength; The graph classification mechanism is used to classify complex fault phenomena, realizing the automatic recognition of multiple types of faults; The inference path graph structure is constructed to model the implicit causal chain of "test excitation - response behavior - fault type", supporting subsequent optimization and deployment migration; The perception and response capabilities of the system to sporadic faults, complex soft errors, and coupling phenomena are improved; The above steps S100 to S400 realize a closed-loop process from structure-sensitive parsing, excitation generation, response acquisition, to fault inference, providing causal evidence support for the model self-evolution optimization in subsequent step S500.

[0105] S500. Calculate the feedback gradient based on the difference vector between the inference path graph RPG and the test excitation sequence TES, and update the weight parameters of the deep generation model.

[0106] S510. Obtain the feature matching deviation between the inference path graph and the test excitation sequence , and calculate the deviation vector .

[0107] In this step, after obtaining the inference path graph output from S400 , extract the node sequence, causal edge weight relationship, and corresponding fault label sequence included in the graph . The path graph reflects the causal triggering path of the test excitation on the fault behavior and can be regarded as a causal chain representation of "response - inference".

[0108] Meanwhile, call the test excitation sequence generated in step S230 , obtain the operation type identifier , access address vector and execution timestamp contained therein, and construct an excitation behavior vector sequence , where each corresponds to a behavior description of an excitation instruction in it.

[0109] To characterize the difference between the actual test path (defined by ) and the system-identified path (defined by ), a feature matching function is constructed to measure the path similarity and trigger correlation between the fault node and the excitation instruction . The features include address overlap, time alignment, and operation type consistency.

[0110] Furthermore, through the cumulative calculation of feature differences, a matching deviation vector is obtained, where each represents the magnitude of the matching error between the th instruction in and the relevant nodes in the inference path graph. This deviation vector will be used as the target input for subsequent gradient calculations.

[0111] What is required in this step is the output result of S430, and the output result of S230, both of which are the outputs of the key system structures; They will be introduced into the gradient propagation process as the building blocks of the loss function in S520.

[0112] S520. Based on the deviation vector , backpropagate to a specific parameter layer in the deep generation model to calculate the feedback gradient vector .

[0113] In this step, after obtaining the deviation vector , further calculate its propagation path in the deep generation model, and construct a gradient backpropagation framework based on this path to obtain the feedback gradient vector .

[0114] Specifically, first trace back to the deep generation model architecture adopted in S200. This model consists of multiple embedding layers, a Transformer attention mechanism layer, and a semantic reconstruction decoder. For the output vector of each layer, the system constructs a hierarchical residual term based on to calculate the local partial derivative.

[0115] On this basis, through the chain rule of partial derivatives, layer by layer, the error signal is backpropagated, and the system obtains the corresponding feedback gradient components on each parameter layer. All components are aggregated to form the gradient vector , where each represents the feedback correction value on the th layer parameter .

[0116] To improve stability and convergence rate, the system introduces the mean of historical gradients and the exponentially weighted momentum coefficient , fusing the historical update trend with the current feedback to control the range of single-step gradient changes. Example values for relevant parameters are as follows: , , , and the data can be sourced from the backtracking experience of existing test models or the statistics of the training set.

[0117] S530. Weightedly fuse the feedback gradient vector to update the weight parameters in the deep generation model, generating an optimized test generation model .

[0118] After calculating the feedback gradient vector , the system updates the parameter weights of the original test generation model to form an optimized version . To ensure the robustness and generalization ability of the update process, the system performs weighted fusion processing on the feedback gradient, adopting the following strategy: Introduce a learning rate vector , where each dimension is used to control the update rate of the th layer of the model; Combine the structure sensitivity vector (output of S120) as the structure-sensitive factor to weight the response of different structural layers; Introduce a target coverage vector (output of S220) as the semantic attention weight to ensure that the optimized model maintains semantic consistency.

[0119] Finally, synthesize all parameters and iteratively update the corresponding parameters in the original model to generate an optimized model . This model will be further deployed to edge nodes or heterogeneous test platforms in S600 to support the next round of adaptive test tasks.

[0120] By executing step S500, based on the structural deviation between the inference graph structure ( ) and the incentive strategy ( ), an error vector ( ) is formed, and a feedback gradient ( ) is generated through the backpropagation mechanism. Finally, the policy iteration of the deep generation model ( ) to the optimized version ( ) is completed, providing high-quality and dynamically adjustable model parameter support for subsequent cross-platform deployment, and improving the robustness and generalization ability of the overall system.

[0121] S600. Based on the updated deep generation model and the current test platform configuration parameters, construct a test deployment configuration plan, and perform cross-platform migration and deployment on the deep generation model.

[0122] S610. Based on the optimized test generation model and the hardware parameter configuration of the test platform, construct a model adaptation configuration vector .

[0123] In this step, the system first obtains the optimized test generation model updated in step S530 , which has incorporated the feedback gradient vector in S500 and the historical structure sensitivity , target fault coverage semantics and other key feature parameters, and has the optimal test strategy generation ability under the current task.

[0124] Specifically, the system reads the software and hardware configurations of the target deployment platform, including the following parameter information: Processor architecture information (such as x86, ARM, RISC-V); Memory capacity and cache level distribution; Instruction set support (such as SIMD / NEON / AVX); Supported number of parallel threads and maximum model loading volume; Network connection bandwidth and edge node communication protocol stack.

[0125] Further, the above information is constructed into a platform parameter representation in a dimensionalized vector manner . Subsequently, according to the network structure configuration in (including number of layers, number of attention heads, input and output dimensions, parameter occupancy space), perform static graph analysis to construct an internal model structure representation .

[0126] Through a fusion function, and are adaptively modeled to generate a model adaptation configuration vector , which represents strategies such as resource mapping, precision adjustment, computing power allocation, and channel pruning during model deployment. It will be used as the input to the subsequent platform migration module to guide the efficient adaptation of the model in heterogeneous environments.

[0127] Output by S530, is the structural abstraction of, and will be used as the input configuration vector for S620; parameter and It is also introduced as a reference basis for model behavior during the fusion process.

[0128] S620. Input the model adaptation configuration vector and the model into the platform migration scheduling module to complete model migration adaptation and generate a migrated model instance .

[0129] After the construction of the model adaptation configuration vector , in this step, the system calls the platform migration scheduling module to perform structural adjustment and computational graph optimization on the deep generation model to generate a migrated model instance executable on the target test platform .

[0130] The platform migration scheduling module includes the following core sub-functions: Structure pruning: Based on the specified acceptable parameter scale, latency budget, and computational resource ratio, perform channel pruning and structural quantization on each Transformer sub-layer, attention head, fully connected channel, etc. in .

[0131] Weight reconstruction: For low-capacity platforms, approximate the reconstruction of some sparse structures with low-rank matrices to ensure the stability of the basic functions of the model under volume compression.

[0132] Graph operator replacement: According to the operator types supported by the target platform, convert some special activation functions and tensor operations in the original model into equivalent operators that can run on the target platform.

[0133] Finally, output the adapted and translated model instance , which has the complete functions of generating test excitation sequences, scheduling test strategies, and calling feedback data in the specified platform, and maintains semantic equivalence with the original model.

[0134] and are jointly provided by S610, which is the output of this step and will be loaded as a deployment entity into the edge node or the scheduling manager in S630.

[0135] S630. Deploy the migrated model instance to the specified test platform or edge node to complete the test system configuration and prepare for the execution of a new round of test tasks.

[0136] After the completion of the model instance After the migration and construction, the system deploys the model instance to the target test node according to the test task scheduling plan and the platform deployment strategy, and completes the final encapsulation of the system configuration. The types of deployment platforms include: Embedded hardware test terminals (supporting MCU / FPGA); High-performance computing platforms (CPU / GPU clusters); Cloud task centers and edge collaboration nodes.

[0137] During the deployment process, the system will Load it into the local model execution engine and complete the following key initialization steps: Register the interfaces of the incentive generation sub-module and the response collection module; Load the historical test intent vector library for constructing a new round of task seeds; Establish a test status feedback channel with the main control scheduling platform to support the monitoring of the closed-loop feedback path; Initialize the output buffer for receiving the sequences and corresponding response data ; Check the model version compatibility to ensure that the test strategy generation module can be supported by the current node.

[0138] After the above steps are completed, the deployment node enters the standby state, waiting for the scheduling module to initiate a new round of test task instructions. After the model is deployed, it will take as the core to participate in the next round of "structure - incentive - response - reasoning - feedback" AI test closed-loop process, realizing the systematic upgrade of the continuous test strategy.

[0139] By executing step S600, the feedback-optimized test generation model is constructed into a platform-customized version after parameter structure adaptation, migration scheduling, and platform mapping and deployed to the specified edge node. It has the following technical effects: Realize the seamless migration of the model between heterogeneous test platforms and improve the flexibility of system deployment; Support automatic adaptation of platform parameters based on vectors to reduce manual intervention; Ensure the semantic consistency of test strategies, suitable for test migration tasks of cross-generation products, different processes, or package versions; Have the ability to quickly switch test tasks and local execution feedback ability, realizing the closed-loop deployment of test strategies; The above steps S100 to S600 construct a full-link intelligent testing framework from structural modeling, strategy generation, response collection, discriminative reasoning, feedback optimization to migration and deployment, improving the overall automation level and migrability of the system.

[0140] In an embodiment of the present application, there is also provided a computer-readable storage medium storing computer instructions. When the computer instructions stored in the computer-readable storage medium are executed by a computer device, the computer device is caused to execute the above-provided fast memory testing method based on AI technology.

[0141] In an embodiment of the present application, there is also provided an electronic device, including: one or more processors; and a storage device for storing a computer program product of one or more instructions, which when running on the computer device, causes the computer device to execute the above-provided fast memory testing method based on AI technology.

[0142] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the processes or functions according to the present application are generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The computer instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center by wire (such as coaxial cable, optical fiber, digital subscriber line) or wireless (such as infrared, wireless, microwave, etc.). The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device such as a server, data center, etc. that integrates one or more available media. The available media can be magnetic media (such as floppy disks, hard disks, magnetic tapes), optical media (such as DVDs), or semiconductor media (such as solid state disks).

[0143] It should be understood that those of ordinary skill in the art can make improvements or transformations according to the above description, and all such improvements and transformations should fall within the protection scope of the appended claims of the present invention.

Claims

1. A memory testing method based on AI technology, characterized in that, It includes the following steps: 1) Obtain the structural analysis data and memory type description information of the memory to be tested, and generate a test intention vector for expressing the test target according to the structural analysis data and memory type description information of the memory to be tested; Among them, the structural analysis data includes the storage cell arrangement matrix, bit line word line structure and redundancy mapping relationship of the memory to be tested; 2) Use the test intention vector as the input, combine with the memory target fault mode database, and input it into a preset deep generation model to construct a fault coverage semantic representation and generate a test excitation sequence; 3) Execute the test excitation sequence, perform multi-cycle testing on the storage array, collect the electrical signal data, operation timing trajectory and operating environment parameters during the testing process, and form a multi-modal response feature set; 4) Input the multi-modal response feature set into a graph neural network for fault type identification and causal path reasoning, and generate a fault label sequence and an inference path graph; 5) Update the weight parameters of the deep generation model based on the feature differences between the inference path graph and the test excitation sequence; 6) Generate a test excitation sequence based on the updated deep generation model for memory testing.

2. The memory test method based on AI technology according to claim 1, wherein The structural analysis data is to hierarchically expand the physical structure information of the memory to be tested, and through layout structure analysis, construct a storage cell arrangement matrix, a bit line word line structure and a redundancy mapping relationship to obtain the structural analysis data; Among them, the physical structure information includes a layout netlist, a physical address mapping diagram, a redundancy structure configuration table, a bit line layout file, and word line group structure information.

3. The memory test method based on AI technology according to claim 1, wherein The type description information is attribute information including memory type, process manufacturing node, stacking layer number, dielectric type, transistor type, etc.

4. The memory test method based on AI technology according to claim 1, wherein The generation of a test intention vector for expressing the test target according to the structural analysis data and memory type description information of the memory to be tested is as follows: Based on the structural analysis data, extract the key structure sensitive area features to form a structure sensitivity feature vector; based on the structure sensitivity feature vector and the memory type description information, construct a test construction objective function to generate a test intention vector for expressing the test target.

5. The memory test method based on AI technology according to claim 4, wherein The extraction of the key structure sensitive area features based on the structural analysis data to form a structure sensitivity feature vector specifically includes: Process weakness bit identification: Identify the areas that are prone to unstable behavior during the manufacturing process, including high-density bit crossover areas, critical dimension error sections, PMOS and NMOS boundary transition areas, and use the lithography model combined with residual mapping technology to extract the coordinate points of the corresponding logic units to form a process anomaly position set; Edge unit area extraction: Locate the storage cell groups at the boundaries of the row and column matrices, record their redundancy mapping quantities and fault history statistical values, and form an edge unit feature set; Bit crossover dense area extraction: Statistically analyze the integration density of bit lines and word lines in the crossover area, and mark the error-prone nodes in combination with the coupling capacitance threshold to form a cross-interference area set; Based on the three sets of process anomaly location sets, edge unit feature sets, and cross-interference region sets, a unified structural sensitive region feature representation tensor is constructed, and the tensor is encoded into a structural sensitivity feature vector , and the structural sensitivity feature vector includes the following fields: node density statistical value, structure type identifier, fault history weight, and process anomaly probability estimate.

6. The memory test method based on AI technology according to claim 1, wherein Test intention vector The included fields are: target access area index , address jump frequency control item , fault induction potential score , concurrent conflict warning weight .

7. The memory testing method based on AI technology according to claim 1, wherein Construct a fault coverage semantic representation and generate a test excitation sequence; specifically as follows: Drive a deep generation model based on the test intention vector to perform semantic-level modeling and access path construction on the target fault coverage pattern, and generate a test excitation sequence ; Perform positional embedding on the test intention vector to obtain a sequence of structural semantic representations, The sequence of structural semantic representations Combine with the fault coverage task label vector to generate a structural-fault association vector map for capturing the prior features of the mapping between the structural region and historical faults; Input the sequence of structural semantic representations and the structure-fault association vector atlas into the deep generation model for vector parsing, and the output of the vector parsing result is a set of semantic attention values and the position weight distribution vector ; Based on the vector analysis result and the target fault type sample features, construct an access path logic diagram for triggering the target sensitive area; Structurally expand the access path logic diagram to generate a test stimulus sequence corresponding to the test intention vector .

8. The memory testing method based on AI technology according to claim 1, wherein, The construction of the access path logic diagram for triggering the target sensitive area is as follows: Obtain semantic attention value and position weight distribution , combine with the structure excitation paradigm vector in the fault type sample library , and perform the construction of the logic diagram of the structure access path; Extract from the fault type sample library the target fault type feature subset that matches the current and , where the features include typical access order, fan-out path, register perturbation sequence, and interleaved address mapping rule; ​ Combined with semantic attention value , perform the extraction of the initial topological structure of the access path, and map the access method in to the coordinates of the target structure area pointed to by the physical location. On this basis, use the position weight distribution to control the segmentation depth, the number of concurrent nodes and the address jump amplitude of the access path, and construct the access path logic diagram ; Access path logic diagram It is a directed graph structure, where nodes represent access actions, edges represent temporal and control dependencies, and edge weights include metrics such as access latency, coupling interference, and logical coverage.

9. The memory testing method based on AI technology according to claim 7, wherein, Performing structural expansion on the access path logic diagram to generate a test stimulus sequence corresponding to the test intention vector ; specifically as follows: First, based on the temporal dependence constraints and access instruction classifications in ; perform a depth-first traversal on the graph structure, linearly sort the access nodes in the graph according to the control dependence order, and obtain the access path sequence For each path segment in the access path sequence , the system combines the original structure-sensitive region metrics and the jump control parameter to generate an access control block . The content of the access control block includes an address jump pattern, a word line selection identifier, a read / write control bit, and a precharge cycle mask; Sequentially splice all access control blocks, and finally combine them to form a test stimulus sequence: 。 10. The memory testing method based on AI technology according to claim 1, wherein The multi-modal response feature set is as follows: Wherein: is the electrical response characteristic within the th cycle; wherein, represents the voltage within the th cycle, represents the current within the th cycle represents the capacitance within the th cycle; is the operation timing field of the i-th excitation instruction; wherein, is the timestamp, is the operation type, is the row and column address; wherein, the i-th excitation instruction corresponds to the excitation instruction of the th cycle; is the environmental state variable for the i-th cycle; wherein, is the chip surface temperature sequence; is the power supply voltage fluctuation sequence; is the spatial electromagnetic interference index sequence; The fusion response feature unit generated in the cycle.

11. The memory testing method based on AI technology according to claim 1, wherein Input the multi-modal response feature set into the graph neural network model for graph structure feature encoding to generate a fault feature map vector; Perform fault classification processing on the fault feature map vector to obtain the corresponding fault type label sequence ; Based on the fault feature map vector and the node nested path information, an inference path graph is generated to represent the causal path of the test stimulus triggering the fault.

12. The memory test method based on AI technology according to claim 11, wherein, Based on the fault feature map vector and the node nested path information, an inference path graph is generated as follows: First, extract all node pairs from the graph structure , where the node pairs satisfy the following conditions: Temporal order holds: ; Spatially adjacent: and the difference is less than a preset threshold ; There is a possibility of failure impact: Belonging to The set of possible triggering consequences, where the set of possible triggering consequences is obtained based on historical path statistics; Construct a set of path edges for node pairs that meet the above conditions , and define the inference path graph as follows: Inference path graph generation: Wherein: is a set of subgraph nodes containing predicted faulty nodes; Set of directed edges that satisfy the inference conditions; is a causality verification function used to determine whether a node is likely to affect a node .

13. The memory testing method based on AI technology according to claim 1, wherein Based on the feature differences between the inference path graph and the test stimulus sequence, calculate the deviation vector and backpropagate to obtain the feedback gradient for weight update of the deep generation model; Among them, the following method is used to calculate the deviation vector: Fault Nodes Based on Inference Path Graph by Feature Matching Metric With the excitation instructions of the test excitation sequence The path similarity and trigger correlation between them; the features include address overlap, time alignment, and operation type consistency; By accumulating the feature differences, a matching deviation vector is obtained , where each in the matching deviation vector represents the magnitude of the matching error between the th instruction in and the relevant nodes in the inference path diagram 14. The memory testing method based on AI technology according to claim 1, wherein Performing memory testing is to construct a model adaptation vector and generate a platform-customized model based on the updated deep generation model and the current test platform parameter configuration; Deploy the platform-customized model to the target test platform or edge node, complete the configuration of the model execution engine, and realize the adaptive execution of a new round of test tasks.

15. An electronic device, characterized in that Comprising: One or more processors; And A storage device for storing one or more programs, Wherein, when the one or more programs are executed by the one or more processors, the one or more processors are caused to execute the method according to any one of claims 1 to 14.

16. A computer-readable storage medium having a computer program stored thereon, characterized in that, The computer program, when executed by a processor, implements the method according to any one of claims 1 to 14.

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