Verification system and method for multi-data-stream direct memory access based on UVM

Abstract

The invention discloses a verification system and method for multi-data-stream direct memory access based on a UVM. The verification system comprises an excitation generation module, a configuration module, an excitation transmission module, an interface monitoring module, an adapter module, a result comparison module and a coverage rate detection module. Wherein the configuration module is used for performing function configuration on the tested DMA, and the function configuration at least comprises defining a function parameter of a data stream, defining an enabling working mode of the data stream and defining a request generation mode of the data stream. Test vectors are made according to different angles and different directional constraint modes, in any test vector, any data packet randomly calls a function parameter configuration mode, an enabling working mode and a request generation mode of any data stream, and the function parameter configuration mode, the enabling working mode and the request generation mode of any data stream are used as a test vector; and large-scale traversal testing including simultaneous working of various combinations of a plurality of data streams is carried out on the tested DMA, so that the correctness and functional integrity of data transmission of the tested DMA are ensured.

Description

Technical Field

[0001] The present invention relates to a verification method for multi-data-stream direct memory access based on UVM, and also relates to a verification system for multi-data-stream direct memory access based on UVM, belonging to the technical field of chip verification. Background Art

[0002] Direct Memory Access (DMA for short) is an access function possessed by certain computer bus architectures. It enables high-speed data transfer directly between peripherals and memories, or between memories, without the participation of the CPU, thereby saving CPU resources. In a System on Chip (SOC for short), each DMA controller is used to manage the memory access requests of one or more peripherals, usually having multiple data streams, and each data stream has multiple channels. At the same time, an arbiter is provided inside each DMA controller to handle the priorities among multiple DMA requests to achieve correct data transfer.

[0003] In the prior art, when the SOC chip is working properly, the DMA controller usually enables multiple data streams and can process multiple requests simultaneously. However, in the system design verification phase, that is, by building a UVM (Universal Verification Methodology) verification environment, driving and controlling the DMA to transfer data and simultaneously monitoring the data transfer results to verify the correctness and functional integrity of data transfer. The existing verification methods usually can only verify the working conditions of a single data stream. To meet the complex combination of all possible multiple data streams working simultaneously, the exhaustive workload is huge and the reusability is relatively low. Therefore, how to automatically verify the complex combination of multiple data streams directly accessing memory simultaneously, and ensure that the DMA can reasonably allocate priorities and correctly process all access requests is a very important technical research topic in this field.

[0004] In the Chinese invention patent with the patent number ZL 202111293414.4, a verification method for multi-data paths based on a UVM verification platform is disclosed. The method includes the following steps: building a UVM verification platform according to the function of the module to be tested, and obtaining the data packet to be tested and the output result of the module to be tested through the monitoring module; sending the configuration information parsed by the data parsing module and the data information carried by the data packet to be tested to the reference model, and storing the reference result according to the DMA id; comparing the output result of the module to be tested with the reference result of the first DMA to complete the data comparison of this burst transfer. Summary of the Invention

[0005] The primary technical problem to be solved by the present invention is to provide a verification system for multi-data-stream direct memory access based on UVM.

[0006] Another technical problem to be solved by the present invention is to provide a verification method for multi-data-stream direct memory access based on UVM.

[0007] To achieve the above object, the present invention adopts the following technical solutions:

[0008] According to the first aspect of the embodiments of the present invention, there is provided a verification system for multi-data-stream direct memory access based on UVM, including an incentive generation module, a configuration module, an incentive transmission module, an interface monitoring module, an adapter module, a result comparison module, and a coverage detection module; wherein,

[0009] The incentive generation module is used to generate a data stream switch control signal, a random incentive signal, and their control signals;

[0010] The configuration module is used to perform functional configuration on the Device Under Test (DUT), and the functional configuration items at least include defining functional parameters of the data stream, defining the enabling working mode of the data stream, and defining the request generation mode of the data stream. Each functional configuration defines multiple different configuration methods, including a configuration method for multiple data streams to work simultaneously; wherein, the DUT is a DMA controller to be tested and verified.

[0011] The incentive transmission module is used to transmit the random incentive signal to the DUT and the reference model;

[0012] The interface monitoring module is used to sample and collect the actual test data of the input and output of the DUT, and after processing, send it to the result comparison module in the form of a transaction-level data packet;

[0013] The result comparison module is used to compare the actual test data with the expected data output by the reference model and output a verification comparison result;

[0014] The coverage detection module is used to check and count the coverage according to the verification comparison result to evaluate the integrity of the verification;

[0015] Test vectors are made in accordance with different angles and different orientation constraints. And, in any one of the test vectors, any data packet randomly calls any one of the functional parameter configuration methods, enabling working modes, and request generation methods of any data stream to perform a large-scale traversal test on the DUT, including various combinations of multiple data streams working simultaneously.

[0016] Preferably, the function parameters at least include the data width of the mem end, the data width of the peri end, the length of continuously transmitted data at the mem end, the length of continuously transmitted data at the peri end, the increment mode at the mem end, the increment mode at the peri end, the data flow priority, and the data transmission direction.

[0017] Preferably, the configuration methods of the function parameters include:

[0018] The first method: The function parameters of all data flows are configured the same;

[0019] The second method: The function parameters of two or more data flows are configured differently, and the function parameters of the remaining data flows are configured the same;

[0020] The third method: The function parameters of all data flows are configured with arbitrary values.

[0021] Preferably, the configuration methods of the enabling working mode include:

[0022] The first method: The enables of all data flows are simultaneously valid, and become invalid after transmitting the same number of data;

[0023] The second method: The enables of one or more data flows are simultaneously valid, and the enables of the remaining data flows are invalid;

[0024] The third method: The valid or invalid time of the enables of all data flows is a random time.

[0025] Preferably, the configuration methods of the request generation method include:

[0026] The first method: Only one request is generated each time;

[0027] The second method: Multiple requests are generated simultaneously each time;

[0028] The third method: The number of requests generated simultaneously is a random number.

[0029] Preferably, the second method of configuring the function parameters traverses the combination cases where two data flows are configured differently, including the following sub-steps:

[0030] Define a loop body. In the first loop, the function parameters of data flow 0 and data flow 1 are configured differently, and the function parameters of the remaining data flows are configured the same; in the second loop, the function parameters of data flow 0 and data flow 2 are configured differently, and the function parameters of the remaining data flows are configured the same; in the third loop, the function parameters of data flow 0 and data flow 3 are configured differently, and the function parameters of the remaining data flows are configured the same; until in the last loop, the function parameters of the last two data flows are configured differently, and the function parameters of the remaining data flows are configured the same, and then the loop is exited.

[0031] Preferably, the second method for configuring the enabling working mode traverses the case where the enabling of 1 data stream is effective, including the following sub-steps:

[0032] Define a loop body. In the first loop, the enabling of data stream 0 is effective, and the enabling of the remaining data streams is ineffective; in the second loop, the enabling of data stream 1 is effective, and the enabling of the remaining data streams is ineffective; in the third loop, the enabling of data stream 2 is effective, and the enabling of the remaining data streams is ineffective; until in the last loop, the enabling of the last data stream is effective, and the enabling of the remaining data streams is ineffective, and then jump out of the loop.

[0033] Preferably, the first method and the second method for configuring the request generation method include the following sub-steps:

[0034] The first method traverses each request of all data streams in sequence: Define a loop body. In the first loop, generate the 1st request of data stream 0; after the fourth time, in the second loop, generate the 2nd request of data stream 0; after another fourth time, in the third loop, generate the 3rd request of data stream 0; until in the last loop, generate the last request of the last data stream, and then jump out of the loop;

[0035] The second method traverses multiple requests that increase sequentially: Define a loop body, and use the first method of the request generation method as a sub-loop body. The number of requests generated by the loop factor increases by one each time; in the first loop, the sub-loop body generates 2 requests simultaneously; after the fourth time, in the second loop, the sub-loop body generates 3 requests simultaneously; after another fourth time, in the third loop, the sub-loop body generates 4 requests simultaneously; until in the last loop, the sub-loop body generates all requests of all data streams simultaneously, and then jump out of the loop.

[0036] Preferably, when the DUT under test has 8 data streams and each data stream has 8 requests, configure the third method of the request generation method, including the following sub-steps:

[0037] Define a total of 64 requests of 8 data streams as a 64-bit random variable R[63:0]. Among them, each request corresponds to one bit in the 64 bits of the random variable in sequence; each time, generate a random number of requests according to the random value of the random variable.

[0038] Preferably, when generating the test vectors, the data stream function configuration, the data stream enabling configuration, and the stimuli generated by the UVM environment are randomized. The randomization process generates specific random values or data packets with a relatively large proportion of boundary values through directional constraints.

[0039] According to a second aspect of the embodiments of the present invention, a verification method for multi-data stream direct memory access based on UVM is provided. The method is implemented based on the above-mentioned verification system for multi-data stream direct memory access based on UVM, and includes the following steps:

[0040] (1) Build a UVM verification platform according to the function of the Device Under Test (DUT), define the input and output environment interfaces, and connect the top-level interface of the DUT to the top-level UVM environment interface;

[0041] (2) Build the UVM verification environment components, and configure the function of the DUT through the configuration module. The function configuration items at least include defining the function parameters of the data stream, defining the enabling working mode of the data stream, and defining the request generation mode of the data stream. Each function configuration defines multiple different configuration methods, including a configuration method for multiple data streams to work simultaneously;

[0042] (3) Generate test vectors and generate corresponding stimuli to be provided to the DUT and the reference model; the generation of the test vectors includes the following sub-steps:

[0043] (31) Generate the test vectors in different angles and different directional constraint manners;

[0044] (32) In any one of the test vectors, any data packet randomly calls any one of the function parameter configuration methods, enabling working modes, and request generation methods of the data stream in step (2);

[0045] (4) Compare the actual test data output by the DUT with the expected data output by the reference model and output the verification comparison result;

[0046] (5) Statistically calculate the coverage rate according to the verification comparison result and judge the coverage rate; if the coverage rate reaches 100%, go to step (7); if the coverage rate does not reach 100%, go to step (6);

[0047] (6) Make corresponding design modifications to the DUT, and then go back to step (3) to continue the verification;

[0048] (7) The verification is passed and ended.

[0049] Compared with the prior art, the verification system for multi-data-stream direct memory access based on UVM provided by the present invention can ensure the characteristics of directional constraints while the generated stimuli are highly randomized. By writing corresponding vectors to operate different stimulus generation methods, including complex combination situations of simultaneous transmission of multi-data-streams, the data transmission and functional verification of the DUT (Device Under Test) can be realized. At the same time, the verification system has high reusability and is applicable to any multi-data-stream DMA verification. Therefore, the verification system for multi-data-stream direct memory access based on UVM provided by the present invention has beneficial effects such as flexible adjustment of packet directional randomness, convenient control of large-scale random stimulus transmission, automatic inspection and statistics of output results, time cost savings, and high reusability. Description of the Drawings

[0050] Figure 1 It is a schematic diagram of the structure of the DMA controller and related signals for simultaneous processing of multi-data-streams in the prior art.

[0051] Figure 2 It is a block diagram of the structure of a verification system for multi-data-stream direct memory access based on UVM provided by the present invention;

[0052] Figure 3 It is a schematic diagram in an embodiment of the present invention where both the enabling effective time and the enabling invalid time of the data stream are random times;

[0053] Figure 4 It is a schematic diagram of the data transmission process of a DMA request in an embodiment of the present invention;

[0054] Figure 5 It is a flowchart of a verification method for multi-data-stream direct memory access based on UVM provided by the present invention. Detailed Embodiments

[0055] The technical content of the present invention will be described in detail below with reference to the drawings and specific embodiments.

[0056] For the convenience of understanding and description, the structure of the DUT (Design Under Test), namely the DMA controller, and related signals for simultaneous processing of multi-data-streams to be verified and tested are first briefly introduced in the embodiments of the present invention. As Figure 1As shown in the figure, a typical DMA controller in the prior art includes a data processing and control module, a request processing and control module, a register configuration module, and other related modules. DMA includes 8 data streams, namely data stream 0 to data stream 7. Each data stream contains 8 channels corresponding to different DMA requests. Among them, the related signals for multi-data stream simultaneous processing include: the clock signal hclk, which specifies that the current DMA clock is named hclk, with a frequency of 48 MHz and a period of approximately 21 nanoseconds; 8 request signals req_str0 to req_str7 for each data stream; 8 response signals ack_str0 to ack_str7 for each data stream, used for handshaking with the request signals of each channel; the data bus hbus_mem at the mem (Memory) end, connected to the external bus matrix, for receiving and sending data from the mem end; the data bus hbus_peri at the peri (Peripheral) end, connected to the external bus matrix, for receiving and sending data from the peri end. It should be noted that Figure 1 other input and output signals of the DMA controller are not shown in the figure.

[0057] A verification system for multi-data stream direct memory access based on UVM provided by an embodiment of the present invention includes an excitation generation module, a configuration module, an excitation transmission module, an interface monitoring module, an adapter module, a result comparison module, and a coverage detection module.

[0058] The excitation generation module is used to generate a data stream switch control signal, a random excitation signal, and their control signals.

[0059] The configuration module is used to perform functional configuration on the register configuration module of the DUT to be tested. The functional configuration items at least include defining the functional parameters of the data stream, defining the enable working mode of the data stream, and defining the request generation mode of the data stream. Each functional configuration defines multiple different configuration methods, including a configuration method for multiple data streams to work simultaneously. Among them, the DUT to be tested is the DMA controller to be tested and verified.

[0060] The excitation transmission module is used to transmit the excitation to the DUT to be tested and the reference model. The excitation transmission module includes a connector and an excitation transmitter; among them, the connector sends the excitation generated in the verification vector case to the excitation transmitter, and the excitation transmitter is responsible for sending the excitation to the DUT to be tested and the reference model respectively.

[0061] The interface monitoring module is used to sample and collect the actual test data of the input and output of the DUT to be tested, and after processing, send the actual test data to the result comparison module in the form of a transaction-level data packet.

[0062] The result comparison module is used to compare the actual test data output by the Device Under Test (DUT) with the expected data output by the reference model and output the verification comparison result. The result comparison module includes a reference model and a scoreboard. Among them, the designed function of the reference model is the same as that of the DUT under test. After receiving the same stimuli as the DUT under test, it automatically generates ideal expected data to verify the correctness of the DUT under test. The scoreboard is used to compare the expected data output by the reference model with the actual test data output by the DUT under test and obtain the verification comparison result.

[0063] The adapter module is used to convert the register read and write operations of the DUT under test into UVM bus transactions and perform data conversion between transactions in UVM.

[0064] The coverage detection module is used to check and statistically analyze the coverage according to the verification comparison result to evaluate the integrity of the verification.

[0065] Test vectors are generated in accordance with different angles and different orientation constraints. Moreover, in any test vector, any data packet randomly calls any function parameter configuration method, enabling working method, and request generation method of any data stream to perform a large-scale traversal test on the DUT under test, including various combinations of multiple data streams working simultaneously, to ensure the correctness of data transmission and the functional integrity of the DUT under test.

[0066] In an embodiment of the present invention, for the DUT under test, this verification system is implemented by writing SystemVerilog language code using the vcs (Version Control System) software tool in the Linux system. The verification environment that needs to be built for the verification system is as Figure 2 shown. The case is the verification vector, which includes a stimulus generation module and a configuration module; the sequencer is a connector, the driver is a stimulus sender, the monitoro is an interface monitoring module, the adapter is an adapter module, the reference_model is a reference model, the scoreboard is a scoreboard, and the coverage collection represents the coverage detection module.

[0067] First, build a UVM verification platform according to the function of the DUT under test, including defining the input and output environment interfaces and connecting the top-level interface of the DUT under test to the top-level UVM environment interface. The following specifically describes the construction of the verification environment and the functional configuration of the corresponding modules.

[0068] The excitation generation module, also known as the random excitation generator, is used to generate data stream switch control signals, random excitation signals, and their control signals. Among them, the random excitation signal is provided to the DUT under test as an input signal, and the control signal is used to control the data transmission process, including the generation, holding, and reset of the request signal, etc., to perform operations such as data stream enabling, data stream disabling, and request initiation at corresponding times.

[0069] When building the excitation generation module, multiple data streams need to be defined for the random excitation generator. Each data stream includes multiple channels, and each channel corresponds to a different DMA request and is responsible for the generation, holding, and reset of the request signal. The generation of the request signal has a high degree of randomness and can be generated at any constrained time. The holding time of the request signal is also a constrained random time. In addition, multiple data stream switch signals of the DUT under test are defined, and after the excitation is generated, the environment can control the start or end of a certain data stream of the DUT under test. In this embodiment, the random excitation generator defines 8 data streams, and each data stream includes 8 channels.

[0070] The configuration module is used to perform functional configuration on the register configuration module of the DUT under test, including the function control register and data type control register of the DUT under test. Performing functional configuration on the DUT under test includes defining the functional parameters of the data stream, defining the enabling working mode of the data stream, and defining the request generation mode of the data stream. The following specifically describes the methods for each functional configuration.

[0071] I. Define the functional parameters of the data stream.

[0072] In any data stream, the functional parameters include but are not limited to the data width at the mem end, the data width at the peri end, the length of continuous data transmission at the mem end, the length of continuous data transmission at the peri end, the increment mode at the mem end, the increment mode at the peri end, the data stream priority, and the data transmission direction. The specific configurations of these functional parameters in any test package can be the same or different. In this embodiment, the following three data stream parameter configuration methods are defined:

[0073] 1. The functional parameter configurations of all data streams are the same.

[0074] 2. The functional parameter configurations of two or more data streams are different, and the functional parameter configurations of the remaining data streams are the same.

[0075] For example, define a loop body. In the first loop, the functional parameter configurations of data stream 0 and data stream 1 are different, while the functional parameter configurations of the remaining data streams are the same; in the second loop, the functional parameter configurations of data stream 0 and data stream 2 are different, while the functional parameter configurations of the remaining data streams are the same; in the third loop, the functional parameter configurations of data stream 0 and data stream 3 are different, while the functional parameter configurations of the remaining data streams are the same; and so on, until in the last loop, the functional parameter configurations of data stream 6 and data stream 7 are different, while the functional parameter configurations of the remaining data streams are the same, and then the loop exits. Thus, it is verified that all combinations of pairwise different data stream configurations are traversed. It should be understood that in other embodiments, combinations of three or four different data stream configurations can also be selected.

[0076] 3. The functional parameter configurations of all data streams are arbitrary values.

[0077] Write the above three configuration methods into three data stream parameter configuration programs respectively for convenient invocation during the verification process.

[0078] II. Define the enabling working mode of the data stream.

[0079] After any data stream enabling of the DUT under test becomes effective, the data stream starts to transmit data, and the number of transmitted data is configurable. When the amount of transmitted data reaches the configured number, the enabling of this data stream automatically becomes ineffective. The specific configurations of the enabling working modes of multiple data streams in any test packet can be the same or different. In this embodiment, the following three data stream enabling configuration methods are defined:

[0080] 1. The enabling of all data streams becomes effective simultaneously, and all become ineffective after transmitting the same number of data, for example, becoming ineffective after transmitting 100 data.

[0081] 2. The enabling of one or more data streams becomes effective simultaneously, while the enabling of the remaining data streams is ineffective.

[0082] For example, define a loop body. In the first loop, the enabling of data stream 0 becomes effective, while the enabling of the remaining data streams is ineffective; in the second loop, the enabling of data stream 1 becomes effective, while the enabling of the remaining data streams is ineffective; in the third loop, the enabling of data stream 2 becomes effective, while the enabling of the remaining data streams is ineffective; and so on, until in the eighth loop, the enabling of data stream 7 becomes effective, while the enabling of the remaining data streams is ineffective, and then the loop exits. During the above loop process, the data stream with effective enabling transmits a specified number of data and then the enabling becomes ineffective, for example, becoming ineffective after transmitting 100 data. Thus, it is verified that all combinations of 1 data stream with effective enabling are traversed. It should be understood that in other embodiments, combinations of two or three data streams with simultaneous effective enabling can also be selected.

[0083] 3. The enabling or disabling time of all data streams is random time.

[0084] As Figure 3 shown, in a possible configuration, the enabling effective times of data stream 0, data stream 3, and data stream 7 are all different. In the data stream enabling signal, high level represents that the data stream is working, and low level represents that the data stream stops working. Other data streams such as data stream 2 and data stream 4 ( Figure 3 not shown in the figure) are disabled and not working.

[0085] Write the above three configuration methods into three data stream enabling configuration programs respectively for convenient calling during the verification process.

[0086] III. Define the request generation method of the data stream

[0087] In this embodiment, it is defined that the DUT under test has 8 data streams, each data stream includes 8 channels, and a total of 64 DMA requests are connected to the UVM environment. Among them, the data transmission process of one DMA request is as Figure 4 shown. After the request signal req becomes valid, after the first time ta, the DMA generates an acknowledgement signal ack. After the second time tb, the environment controls the request signal to be invalid. After the third time tc, the acknowledgement signal ack is controlled by the DMA to be invalid. At the same time, the DMA will drive the bus to generate a data transmission, read data from the source address and then write it to the destination address. Each request signal must correspond to a data transmission, but the data transmission time is randomly controlled, which is jointly determined by the UVM environment control and the DMA design nature.

[0088] The DMA controller can only process one DMA request at the same time. When multiple DMA requests are valid at the same time, the DMA internal arbiter decides the processing order of multiple requests, but ultimately there cannot be a situation where a request is not correctly processed. In order to test the combined situation where multiple requests are valid at the same time, it is necessary to configure the generation method of multiple DMA requests. In this embodiment, the following three data stream request generation methods are defined:

[0089] 1. Only generate one request each time.

[0090] For example, define a loop body. In the first loop, the 1st request req_str0 of data stream 0 is generated; after the fourth time, in the second loop, the 2nd request req_str1 of data stream 0 is generated; after another fourth time, in the third loop, the 3rd request req_str2 of data stream 0 is generated; and so on, until in the last loop, the 8th request req_str7 of data stream 7 is generated; thus, each request of the data stream is traversed in sequence, and then the loop is exited. Among them, the fourth time can be defined as any time between the rising edge of the request signal and the end of data transmission.

[0091] 2. Generate multiple requests simultaneously each time.

[0092] For example, to traverse multiple requests that increase sequentially, define a loop body, and take all the contents in the 1st request configuration method as a loop factor, i.e., a sub-loop body, and the number of requests generated by the loop factor increases by one each time in the loop. Mark the 64 DMA requests with serial numbers 0 to 63 in sequence, i.e., the 1st request req_str0 of data stream 0 is marked as 0; the 2nd request req_str1 of data stream 0 is marked as 1, the 3rd request req_str2 of data stream 0 is marked as 2, and so on for sequential marking.

[0093] In the first loop, the sub-loop body generates 2 requests simultaneously, i.e., request 0 and request 1; after the fourth time, in the second loop, the sub-loop body generates 3 requests simultaneously, i.e., request 0, request 1, and request 2; after another fourth time, in the third loop, the sub-loop body generates 4 requests simultaneously, i.e., request 0, request 1, request 2, and request 3; and so on, until in the last loop, the sub-loop body generates all the requests of all data streams, i.e., 64 requests, and then the loop is exited.

[0094] 3. The number of requests generated simultaneously is a random number.

[0095] In this embodiment, a total of 64 requests of 8 data streams are defined as a 64-bit random variable R[63:0], and each request corresponds to one bit in the 64 bits of this random variable in sequence. Each time, a random number of requests are generated simultaneously according to the random value of this random variable. For example, when the random variable R = 3 at a certain time, it means that the 1st request req_str0 and the 2nd request req_str1 of data stream 0 are both valid. It should be understood that in other possible embodiments, the random number can also be generated by other methods, and the present invention does not impose any restrictions on this.

[0096] Write the above three request generation methods into three data stream request configuration programs respectively for convenient invocation during the verification process.

[0097] The excitation transmission module includes a connector and an excitation transmitter; among them, the connector sends the excitation generated in the verification vector case to the excitation transmitter, and the excitation transmitter is responsible for sending the excitation to the Device Under Test (DUT) and the reference model respectively. When initializing the DMA source address data, the excitation generation module generates randomized data and writes it into the DMA source address. A data stream enabling randomization program is called to enable or disable any data stream at any time. A program for requesting events is called to transmit the excitation to the DUT and the reference model through the excitation transmitter.

[0098] The interface monitoring module is used to sample and collect the actual test data of the input and output of the DUT. An interface monitoring module is built to monitor the generation of the acknowledgment signal (ack) and the transfer of the DMA destination address in each data stream, sample and collect the actual test data of the input and output of the DUT, and after processing, send the actual test data to the scoreboard in the result comparison module in the form of transaction-level data packets.

[0099] A set of transaction-level data packet collections sent by the interface monitoring module includes:

[0100] 1. When a response signal ack is detected, whether the corresponding request signal req is valid, and these data are defined as data packet A.

[0101] 2. Monitor the generation time of the flag bits of each data stream of the measured DMA, and these data are defined as data packet B.

[0102] 3. Monitor the number of data finally transmitted in each data stream, and these data are defined as data packet C.

[0103] 4. Monitor the data of all destination addresses of the measured DMA, and these data are defined as data packet D.

[0104] All the above monitoring data are carried out simultaneously and independently at the beginning of the verification. Each time a data packet is generated, it will be immediately transmitted to the scoreboard until the verification is completed.

[0105] The result comparison module is used to compare the actual test data output by the DUT with the expected data output by the reference model and output the verification comparison result. The result comparison module includes a reference model and a scoreboard; among them, the designed function of the reference model is the same as that of the DUT. After receiving the same excitation as the DUT, it automatically generates ideal expected data for verifying the correctness of the DUT. The scoreboard is used to compare the expected data output by the reference model with the actual test data output by the DUT and obtain the verification comparison result.

[0106] When building a reference model, the logic in the reference model can be written in SystemVerilog language. Theoretically, the logic is the same as that of the DUT under test. During the verification process, the reference model processes the input stimuli and generates ideal expected data and outputs it. This expected data is also transmitted to the scoreboard in the form of transaction-level data packets. Similarly, a set of expected transaction-level data packet collections output by the reference model also includes data packet A`, data packet B`, data packet C`, and data packet D`.

[0107] In the scoreboard, the actual data packet collection transmitted by the DUT under test after being processed by the interface monitoring module is compared one by one with the expected data packet collection transmitted by the reference model. As shown in Table 1, if a comparison between an actual data packet and an expected data packet is inconsistent, the verification environment will use the output statement in SystemVerilog to print the comparison result to the verification report and mark an error "xx ERROR"; otherwise, it is considered that the verification comparison result is consistent.

[0108] Table 1 Comparison Table of Data Packet Collections

[0109]

[0110] When an error occurs in the data packet comparison result, the designer of the DUT under test can make corresponding design modifications according to the prompt information and then re-perform functional verification until the verification is error-free. It should be noted that when the data packet comparison result is consistent, the comparison result will not be output immediately. If all data packet comparison results are consistent, at the end of the verification, the environment will use the output statement in SystemVerilog to print it to the verification report and mark "OK".

[0111] The adapter module is used to convert the register read and write operations of the DUT under test into UVM bus transactions and perform data conversion between the transactions in UVM.

[0112] The coverage detection module performs line coverage check, toggle coverage check, state machine coverage check, condition coverage check, and branch coverage check on the simulation verification results, then writes corresponding functional coverage checkpoints for the concerned points, and finally calculates all coverages. If the coverage reaches 100%, it is considered that the verification passes. If the coverage does not reach 100%, further verification is required. For example, continue to add corresponding vectors, modify the configuration method, or increase the simulation time to continue verifying the DUT under test.

[0113] A verification system for multi-data-stream direct memory access based on UVM provided by an embodiment of the present invention, after setting up the above verification environment and related configurations, during the verification process, the DUT under test is tested from different angles and test vectors with directional constraints are produced. In any one test vector, up to ten thousand data packets can be tested. In any one data packet, it includes but is not limited to calling any one of the function parameter configuration methods, enabling working methods, and request generation methods of data streams. Each data packet can randomly switch the combination of these methods, including various combinations of multiple data streams working simultaneously. Moreover, the data stream function configuration, data stream enabling configuration, and stimuli generated by the UVM environment can all be randomized in different test vectors. Randomization can produce data packets with specific random values or a relatively large proportion of boundary values through directional constraints. After the verification is completed, all verification results are output. By large-scale random testing, the coverage rate is further improved to ensure the correctness and functional integrity of the data transmission of the DUT under test.

[0114] Based on the above verification system for multi-data-stream direct memory access, an embodiment of the present invention further provides a verification method for multi-data-stream direct memory access based on UVM. As Figure 5 shown, the verification method includes the following steps:

[0115] S1: Build a UVM verification platform according to the function of the DUT under test, define the input and output environment interfaces, and connect the top-level interface of the DUT under test to the top-level environment interface of UVM.

[0116] S2: Build the components of the UVM verification environment and configure the function of the DUT under test through the configuration module.

[0117] The components of the verification environment include an excitation generation module, a configuration module, an excitation transmission module, an interface monitoring module, an adapter module, a result comparison module, and a coverage detection module. Configuring the function of the DUT under test includes defining the function parameters of the data stream, defining the enabling working method of the data stream, and defining the request generation method of the data stream. Among them, in any one data stream, the function parameters include but are not limited to the data width of the mem side, the data width of the peri side, the length of continuous data transmission on the mem side, the length of continuous data transmission on the peri side, the increment mode on the mem side, the increment mode on the peri side, the data stream priority, and the data transmission direction.

[0118] Configuring the function of the DUT under test specifically includes the following sub-steps:

[0119] S21: Select one of the following three methods to configure the function parameters of the data stream.

[0120] The first method: The function parameter configurations of all data streams are the same.

[0121] The second method: The functional parameters of two or more data streams are configured differently, and the functional parameters of the remaining data streams are configured identically.

[0122] The third method: The functional parameters of all data streams are configured with arbitrary values.

[0123] S22: Select one of the following three methods to configure the enable working mode of the data stream.

[0124] The first method: The enables of all data streams are simultaneously effective, and become ineffective after transmitting the same number of data.

[0125] The second method: The enables of one or more data streams are simultaneously effective, and the enables of the remaining data streams are ineffective.

[0126] The third method: The effective or ineffective time of the enables of all data streams is a random time.

[0127] S23: Select one of the following three methods to configure the request generation method of the data stream.

[0128] The first method: Only one request is generated each time.

[0129] The second method: Multiple requests are generated simultaneously each time.

[0130] The third method: The number of requests generated simultaneously is a random number.

[0131] S3: Produce test vectors, generate corresponding stimuli and provide them to the DUT under test and the reference model. The method for producing test vectors includes the following sub-steps:

[0132] S31: Produce test vectors in a manner of different angles and different orientation constraints.

[0133] S32: In any one test vector, any one data packet randomly calls any one of the functional parameter configuration methods, enable working methods, and request generation methods of the data stream in step S2.

[0134] Optionally, the data stream function configuration, the data stream enable configuration, and the stimuli generated by the UVM environment can also be randomized in different test vectors. The randomization process can generate data packets with specific random values or a relatively large proportion of boundary values through directional constraints.

[0135] S4: Compare the actual test data output by the DUT under test with the expected data output by the reference model and output the verification and comparison results.

[0136] S5: Statistically calculate the coverage based on the verification and comparison result, and judge the coverage rate; if the coverage rate reaches 100%, go to step S7; if the coverage rate does not reach 100%, go to step S6.

[0137] S6: Make corresponding design modifications to the DUT under test, and then go back to step S3 to continue the verification.

[0138] S7: The verification is passed and ended.

[0139] Through the above verification method, the DUT under test is tested with different angles and different directional constraints. And in any one test vector, up to ten thousand data packets can be tested. In any one data packet, any functional parameter configuration method, enabling working method, and request generation method of any data stream can be called, including various combination situations of multiple data streams working simultaneously. Through large-scale random testing, verify the correctness of data transmission and the functional integrity of the DUT under test when multiple data streams perform direct memory access simultaneously.

[0140] In summary, compared with the prior art, the verification system for multi-data-stream direct memory access based on UVM provided by the present invention has highly randomized generated stimuli while ensuring the characteristics of directional constraints. By writing corresponding vectors to operate different stimulus generation methods, including complex combination situations of multiple data streams transmitting simultaneously, the data transmission and functional verification of the DUT under test are realized. At the same time, the verification system has high reusability and is applicable to any multi-data-stream DMA verification. Different DMA controllers may have different numbers of data streams and different transmission methods, but the stimulus configuration method and output type of each data stream can be included in the present invention. When in use, only some connection codes need to be simply adjusted or modified to achieve. Therefore, the verification system for multi-data-stream direct memory access based on UVM provided by the present invention has beneficial effects such as flexible adjustment of data packets in a directed and random manner, convenient control of large-scale random stimulus sending, automatic inspection and statistics of output results, time cost savings, and high reusability.

[0141] It should be noted that the above-mentioned multiple embodiments are only examples. The technical solutions of each embodiment can be combined and are all within the protection scope of the present invention.

[0142] In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the present invention, "a plurality of" means two or more unless otherwise specifically defined.

[0143] The above has provided a detailed description of the verification system and method for multi-data stream direct memory access based on UVM. For those of ordinary skill in the art, any obvious changes made to it without departing from the essence of the present invention will constitute an infringement of the patent right of the present invention and will bear corresponding legal responsibilities.

Claims

1. A verification system for multi-data-stream direct memory access based on UVM, characterized in that It includes an excitation generation module, a configuration module, an excitation transmission module, an interface monitoring module, an adapter module, a result comparison module, and a coverage detection module; among them, The excitation generation module is used to generate a data stream switch control signal, a random excitation signal, and their control signals; The configuration module is used to perform functional configuration on the DUT under test. The functional configuration items at least include defining the functional parameters of the data stream, defining the enabling working mode of the data stream, and defining the request generation mode of the data stream. Each functional configuration defines multiple different configuration methods, including a configuration method in which multiple data streams work simultaneously; among them, the DUT under test is a DMA controller to be tested and verified; The excitation transmission module is used to transmit the random excitation signal to the DUT under test and the reference model; The interface monitoring module is used to sample and collect the actual test data of the input and output of the DUT under test, and after processing, send it to the result comparison module in the form of a transaction-level data packet; The result comparison module is used to compare the actual test data with the expected data output by the reference model and output the verification comparison result; The coverage detection module is used to check and count the coverage according to the verification comparison result to evaluate the integrity of the verification; Test vectors are made in accordance with different angles and different orientation constraints. And, in any one of the test vectors, any data packet randomly calls any one of the functional parameter configuration methods, enabling working modes, and request generation methods of any data stream to perform a large-scale traversal test on the DUT under test, including various combinations of multiple data streams working simultaneously.

2. The verification system for multi-data-stream direct memory access based on UVM according to claim 1, characterized in that: The functional parameters at least include the data width of the mem end, the data width of the peri end, the length of continuous data transmission at the mem end, the length of continuous data transmission at the peri end, the increment mode at the mem end, the increment mode at the peri end, the data stream priority, and the data transmission direction.

3. The verification system for multi-data-stream direct memory access based on UVM according to claim 1, characterized in that The configuration methods of the functional parameters include: The first method: The functional parameter configurations of all data streams are the same; The second method: The functional parameter configurations of two or more data streams are different, and the functional parameter configurations of the remaining data streams are the same; The third method: The functional parameter configurations of all data streams are arbitrary values.

4. The verification system for multi-data stream direct memory access based on UVM according to claim 1, wherein The configuration methods of the enabling working mode include: The first method: The enables of all data streams are simultaneously valid, and after transmitting the same number of data, the enables become invalid; The second method: The enables of one or more data streams are simultaneously valid, and the enables of the remaining data streams are invalid; The third method: The valid time or invalid time of the enables of all data streams is a random time.

5. The verification system for direct memory access of multiple data streams based on UVM according to claim 1, characterized in that The configuration methods of the request generation mode include: The first method: Only one request is generated each time; The second method: Multiple requests are generated simultaneously each time; The third method: The number of requests generated simultaneously is a random number.

6. The verification system for direct memory access of multiple data streams based on UVM according to claim 3, wherein The second method of configuring the functional parameters adopts a traversal of the combination cases where the configurations of two data streams are different, including the following sub-steps: Define a loop body. In the first loop, the functional parameter configurations of data stream 0 and data stream 1 are different, while the functional parameter configurations of the remaining data streams are the same; in the second loop, the functional parameter configurations of data stream 0 and data stream 2 are different, while the functional parameter configurations of the remaining data streams are the same; in the third loop, the functional parameter configurations of data stream 0 and data stream 3 are different, while the functional parameter configurations of the remaining data streams are the same; until in the last loop, the functional parameter configurations of the last two data streams are different, while the functional parameter configurations of the remaining data streams are the same, and then break out of the loop.

7. The verification system for direct memory access of multiple data streams based on UVM according to claim 4, wherein The second method for configuring the enabling working mode is to traverse the situation where the enabling of 1 data stream is effective, including the following sub-steps: Define a loop body. In the first loop, the enabling of data stream 0 is effective, while the enabling of the remaining data streams is ineffective; in the second loop, the enabling of data stream 1 is effective, while the enabling of the remaining data streams is ineffective; in the third loop, the enabling of data stream 2 is effective, while the enabling of the remaining data streams is ineffective; until in the last loop, the enabling of the last data stream is effective, while the enabling of the remaining data streams is ineffective, and then break out of the loop.

8. The verification system for direct memory access of multiple data streams based on UVM according to claim 5, characterized in that Configure the first method and the second method of the request generation method, including the following sub-steps: The first method is to sequentially traverse each request of all data streams: Define a loop body. In the first loop, generate the 1st request of data stream 0; after the fourth time, in the second loop, generate the 2nd request of data stream 0; after another fourth time, in the third loop, generate the 3rd request of data stream 0; until in the last loop, generate the last request of the last data stream, and then break out of the loop; The second method is to traverse multiple requests that increase sequentially: Define a loop body, and use the first method of the request generation method as a sub-loop body. The number of requests generated by the loop factor increases by one each time; in the first loop, the sub-loop body generates 2 requests simultaneously; after the fourth time, in the second loop, the sub-loop body generates 3 requests simultaneously; after another fourth time, in the third loop, the sub-loop body generates 4 requests simultaneously; until in the last loop, the sub-loop body generates all requests of all data streams simultaneously, and then break out of the loop.

9. The verification system for multi-data stream direct memory access based on UVM according to claim 5, characterized in that When the DUT under test has 8 data streams and each data stream has 8 requests, configuring the third method of the request generation method includes the following sub-steps: Define a 64-bit random variable R[63:0] for a total of 64 requests of 8 data streams, where each request corresponds to one bit in the 64 bits of the random variable in sequence; each time, generate a random number of requests according to the random value of the random variable.

10. A verification method for direct memory access of multiple data streams based on UVM, implemented based on the verification system for direct memory access of multiple data streams based on UVM described in any one of claims 1 to 9, characterized in that Include the following steps: (1) Build a UVM verification platform according to the function of the DUT under test, define the input and output environment interfaces, and connect the top-level interface of the DUT under test to the top-level environment interface of UVM; (2) Build UVM verification environment components, and configure the functions of the DUT under test through the configuration module. The function configuration items shall at least include function parameters for defining data streams, enable working modes for defining data streams, and request generation modes for defining data streams. Each function configuration defines multiple different configuration methods, including a configuration method for multiple data streams to work simultaneously. (3) Produce test vectors and generate corresponding stimuli to be provided to the DUT under test and the reference model. The production of the test vectors includes the following sub-steps: (31) Produce the test vectors in a manner of different angle and different orientation constraints. (32) In any one of the test vectors, any data packet randomly calls any one of the function parameter configuration methods, enable working modes, and request generation modes of the data streams in step (2). (4) Compare the actual test data output by the DUT under test with the expected data output by the reference model and output the verification comparison result. (5) Statistically calculate the coverage rate according to the verification comparison result and judge the coverage rate. If the coverage rate reaches 100%, go to step (7); if the coverage rate does not reach 100%, go to step (6). (6) Make corresponding design modifications to the DUT under test, and then go back to step (3) for continued verification. (7) The verification is passed and ended.

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