A bandwidth management system

Abstract

The present application relates to the field of data transmission, and in particular to a bandwidth management system. The system determines an average transmission rate based on a clock frequency ratio, a first address channel data read bandwidth, a second address channel data read bandwidth, a first read bandwidth, a second read bandwidth, a bus width ratio, and a clock frequency ratio. The average transmission rate can ideally ensure stable usage of a cache area. However, due to physical distance limitations, resource conflicts, and the like, data or commands may be delayed during transmission, thereby affecting cache usage. Therefore, a target transmission rate of a target read command set is determined based on the average transmission rate and real-time usage, thereby effectively increasing bandwidth utilization, avoiding data congestion, and improving data transmission efficiency.

Description

Technical Field

[0001] The present invention relates to the field of data transmission, and in particular to a bandwidth management system. Background Art

[0002] In the data reading scenario, the chip usually includes an engine, a system bus and its corresponding cache area and memory. The engine sends a read command to the system bus through the address channel. The system bus reads the data corresponding to the read command from the memory and then returns the data to the engine through the data return channel.

[0003] However, because the bandwidth of the address channel and the data return channel may be different, and the clock frequencies of the engine and system bus may be different, when the engine continuously sends read commands, the data read from the system bus may take multiple clock cycles to be returned to the engine. Therefore, existing methods usually use a cache to temporarily store the read data. However, when the cache depth is insufficient, it will cause data congestion on the system bus, resulting in poor data transmission efficiency.

[0004] To address the above problems, the method of expanding the cache capacity can be used to alleviate them, but this method will increase additional costs. Therefore, how to improve data transmission efficiency without increasing costs as much as possible has become an urgent problem to be solved. Summary of the Invention

[0005] In view of the above technical problems, the technical solution adopted by the present invention is:

[0006] A bandwidth management system includes: a system bus and its corresponding cache area, an engine, and a memory. A first channel and a second channel exist between the system bus and the engine. The first channel is used by the engine to send a read command to the system bus, and the second channel is used by the system bus to send data corresponding to the read command to the engine. A third channel exists between the system bus and the memory. The system bus corresponds to a first clock frequency, the engine corresponds to a second clock frequency, the third channel corresponds to a first bus width, and the second channel corresponds to a second bus width.

[0007] The engine is also used to obtain real-time usage of the cache area when sending a target read command set to the system bus through the first channel, the target read command set including target read commands corresponding to several cycles respectively, and the target read command set corresponding to the average access length.

[0008] The engine is further configured to determine a first read bandwidth based on the first bus width and the first clock frequency, and to determine a second read bandwidth based on the second bus width and the second clock frequency.

[0009] The engine is further configured to determine a first address channel data read bandwidth according to the average access length and the first clock frequency, and to determine a second address channel data read bandwidth according to the average access length and the second clock frequency.

[0010] The engine is further configured to determine a bus width ratio based on the first bus width and the second bus width, and to determine a clock frequency ratio based on the first clock frequency and the second clock frequency.

[0011] The engine is further configured to determine an average transmission rate according to the clock frequency ratio, the first address channel data read bandwidth, the second address channel data read bandwidth, the first read bandwidth, the second read bandwidth, and the bus width ratio.

[0012] The engine is further configured to determine a target emission rate of the target read command set according to the average emission rate and a real-time usage of the cache area.

[0013] Compared with the prior art, the present invention has significant benefits. By utilizing the above technical solution, the bandwidth management system provided by the present invention can achieve considerable technological advancement and practicality, and has wide industrial application value. It has at least the following beneficial effects:

[0014] The present invention provides a bandwidth management system, which includes: a system bus and its corresponding cache area, an engine and a memory, wherein a first channel and a second channel are located between the system bus and the engine, the first channel is used by the engine to send a read command to the system bus, and the second channel is used by the system bus to send data corresponding to the read command to the engine, a third channel is located between the system bus and the memory, the system bus corresponds to a first clock frequency, the engine corresponds to a second clock frequency, the third channel corresponds to a first bus width, and the second channel corresponds to a second bus width, the engine is further used to obtain real-time usage of the cache area when sending a target read command set to the system bus through the first channel, the target read command set including target read commands corresponding to several cycles respectively, the target read command set corresponding to an average access length, and the engine is further used to obtain real-time usage of the cache area when sending a target read command set to the system bus through the first channel, the target read command set including target read commands corresponding to several cycles respectively, the target read command set corresponding to an average access length, and the engine is further used to obtain real-time usage of the cache area when sending a target read command set to the system bus through the first channel The engine is further configured to determine a first read bandwidth according to the average access length and the first clock frequency, and to determine a second read bandwidth according to the second bus width and the second clock frequency. The engine is further configured to determine a first address channel data read bandwidth according to the average access length and the first clock frequency, and to determine a second address channel data read bandwidth according to the average access length and the second clock frequency. The engine is further configured to determine a bus width ratio according to the first bus width and the second bus width, and a clock frequency ratio according to the first clock frequency and the second clock frequency. The engine is further configured to determine an average emission rate according to the clock frequency ratio, the first address channel data read bandwidth, the second address channel data read bandwidth, the first read bandwidth, the second read bandwidth, and the bus width ratio. The engine is further configured to determine a target emission rate of the target read command set according to the average emission rate and the real-time usage of the cache area.

[0015] It can be seen that the average transmission rate is determined according to the clock frequency ratio, the first address channel data read bandwidth, the second address channel data read bandwidth, the first read bandwidth, the second read bandwidth, the bus width ratio and the clock frequency ratio. Under ideal circumstances, the average transmission rate can ensure the stable usage of the cache area. However, due to physical distance limitations, resource conflicts, etc., there will be delays in the transmission of data or commands, which will affect the usage of the cache area. Therefore, according to the average transmission rate and real-time usage, the target transmission rate of the target read command set is determined, which can effectively increase the bandwidth utilization and avoid data congestion, thereby improving data transmission efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0017] Figure 1 A schematic diagram of the structure of a bandwidth management system provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0018] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without making any creative efforts shall fall within the scope of protection of the present invention.

[0019] This embodiment provides a bandwidth management system. Figure 1 , is a schematic structural diagram of a bandwidth management system provided by an embodiment of the present invention. The system includes: a system bus and its corresponding cache area, an engine, and a memory. A first channel and a second channel exist between the system bus and the engine. The first channel is used by the engine to send a read command to the system bus, and the second channel is used by the system bus to send data corresponding to the read command to the engine. A third channel exists between the system bus and the memory. The system bus corresponds to a first clock frequency, the engine corresponds to a second clock frequency, the third channel corresponds to a first bus width, and the second channel corresponds to a second bus width.

[0020] The engine is further configured to obtain real-time usage of the cache area when sending a target read command set to the system bus through the first channel, the target read command set including target read commands corresponding to a plurality of cycles, the target read command set corresponding to an average access length;

[0021] The engine is further configured to determine a first read bandwidth based on the first bus width and the first clock frequency, and to determine a second read bandwidth based on the second bus width and the second clock frequency;

[0022] The engine is further configured to determine a first address channel data read bandwidth based on the average access length and the first clock frequency, and to determine a second address channel data read bandwidth based on the average access length and the second clock frequency;

[0023] The engine is further configured to determine a bus width ratio based on the first bus width and the second bus width, and to determine a clock frequency ratio based on the first clock frequency and the second clock frequency;

[0024] The engine is further configured to determine an average transmit rate based on the clock frequency ratio, the first address channel data read bandwidth, the second address channel data read bandwidth, the first read bandwidth, the second read bandwidth, and the bus width ratio;

[0025] The engine is further configured to determine a target emission rate of the target read command set according to the average emission rate and a real-time usage of the cache area.

[0026] Among them, the system bus can refer to a public signal line that supports functions such as data transmission, address addressing and control signal transmission. The cache area can be used to temporarily store data read from the memory by the system bus. The memory can refer to a static random access memory, etc. In this embodiment, the system can include multiple memories, but all of them read data through the system bus.

[0027] The first channel may be used for transmitting a read command from the engine to the system bus, the third channel may be used for reading data from the memory via the system bus, and the second channel may be used for returning the read data from the system bus to the engine.

[0028] Specifically, the real-time usage may refer to the utilization rate of the cache area, and its value range may be [0, 1]. The closer the real-time usage is to 0, the smaller the utilization rate of the cache area and the emptier the cache area. The closer the real-time usage is to 1, the greater the utilization rate of the cache area and the fuller the cache area.

[0029] The engine determines the intervals at which each target read command is issued to the system bus based on the target issuance rate.

[0030] This embodiment takes the burst transmission mode of the read command as a priori condition, that is, the engine sends a target read command to the system bus in one clock cycle. The engine sending a target read command set to the system bus through the first channel can mean that the engine will continuously send multiple target read commands to the system bus through the first channel.

[0031] In a specific embodiment, the target read command corresponds to a first access length, and the average access length is calculated as the average of the first access lengths of the target read commands corresponding to all cycles, wherein if there is no target read command in any cycle, the first access length corresponding to the cycle is zero.

[0032] Among them, the first access length can refer to the amount of data required to be read for the corresponding target read command. The amount of data required to be read for different target read commands may be different, for example, it can be 256 bytes, 128 bytes, 64 bytes, etc. The average access length can refer to the average amount of data required to be read for each target read command.

[0033] In a specific embodiment, determining a first read bandwidth according to the first bus width and the first clock frequency, and determining a second read bandwidth according to the second bus width and the second clock frequency, includes:

[0034] multiplying the first bus width and the first clock frequency to obtain a first multiplication result, and using the first multiplication result as the first read bandwidth;

[0035] The second bus width and the second clock frequency are multiplied to obtain a second multiplication result, and the second multiplication result is used as the second read bandwidth.

[0036] The first read bandwidth may refer to the amount of data that can be read by the system bus per unit time, and the second read bandwidth may refer to the amount of data that can be returned to the engine by the system bus per unit time.

[0037] In a specific embodiment, determining the first address channel data read bandwidth according to the average access length and the first clock frequency, and determining the second address channel data read bandwidth according to the average access length and the second clock frequency, includes:

[0038] multiplying the average access length and the first clock frequency to obtain a third multiplication result, and using the third multiplication result as the first address channel data read bandwidth;

[0039] The average access length and the second clock frequency are multiplied to obtain a fourth multiplication result, and the fourth multiplication result is used as the second address channel data read bandwidth.

[0040] The first address channel data read bandwidth may refer to the amount of data that the system bus needs to read per unit time, and the second address channel data read bandwidth may refer to the amount of data that the system bus needs to return to the engine per unit time.

[0041] In a specific embodiment, determining the bus width ratio according to the first bus width and the second bus width, and determining the clock frequency ratio according to the first clock frequency and the second clock frequency, includes:

[0042] Dividing the second bus width by the first bus width to obtain a first division result, and using the first division result as the bus width ratio;

[0043] The second clock frequency is divided by the first clock frequency to obtain a second division result, and the second division result is used as the clock frequency ratio.

[0044] In a specific embodiment, determining the average transmission rate according to the clock frequency ratio, the first address channel data read bandwidth, the second address channel data read bandwidth, the first read bandwidth, the second read bandwidth, and the bus width ratio includes:

[0045] taking a ratio of the first address channel data read bandwidth to the first read bandwidth as a first reference rate;

[0046] using a ratio of the second address channel data read bandwidth to the second read bandwidth as a second reference rate;

[0047] If the clock frequency ratio is greater than a first preset value, determining the average transmission rate according to the first reference rate, the bus width ratio, and the clock frequency ratio;

[0048] Otherwise, the second reference rate is used as the average transmission rate.

[0049] Among them, the first reference rate may refer to the transmission rate corresponding to when the system bus reads data and can meet the data reading bandwidth of the first address channel; the second reference rate may refer to the transmission rate corresponding to when the system bus returns data and can meet the data reading bandwidth of the second address channel; the transmission rate may refer to the period between two consecutive target read commands transmitted by the engine; and the first preset value may be set to 1.

[0050] In a specific implementation, determining the average transmission rate according to the first reference rate, the bus width ratio, and the clock frequency ratio includes:

[0051] Multiplying the bus width ratio and the clock frequency ratio to obtain a fifth multiplication result:

[0052] dividing the first reference rate and the fifth multiplication result to obtain a third division result;

[0053] If the third division result is greater than a second preset value, determining the first reference rate as the average transmission rate;

[0054] Otherwise, the preset rate is used as the average transmission rate.

[0055] Among them, the second preset value can be set to 1, and the preset rate can be 1.

[0056] Specifically, taking the first clock frequency of 2 GHz, the first bus width of 64B, the second clock frequency of 1 GHz, the first bus width of 32B, and the average access length of 128B as an example, the first read bandwidth is 128 GB / s, the second read bandwidth is 32 GB / s, the first address channel data read bandwidth is 256 GB / s, the second address channel data read bandwidth is 128 GB / s, the bus width ratio is 0.5, the clock frequency ratio is 0.5, then the first reference rate is 2, the second reference rate is 4, since the clock frequency ratio is less than the first preset value, the second reference rate 4 is used as the average transmission rate;

[0057] Taking the first clock frequency of 1 GHz, the first bus width of 64B, the second clock frequency of 2 GHz, the first bus width of 32B, and the average access length of 128B as an example, the first read bandwidth is 64 GB / s, the second read bandwidth is 64 GB / s, the first address channel data read bandwidth is 128 GB / s, the second address channel data read bandwidth is 256 GB / s, the bus width ratio is 0.5, the clock frequency ratio is 0.5, then the first reference rate is 2, the second reference rate is 4, since the clock frequency ratio is greater than the first preset value, the fifth multiplication result is 1, the third division result is 2, the third division result 2 is greater than the second preset value 1, then the first reference rate 2 is used as the average transmission rate;

[0058] Taking the first clock frequency of 1GHz, the first bus width of 64B, the second clock frequency of 2GHz, the first bus width of 256B, and the average access length of 128B as an example, the first read bandwidth is 64GB / s, the second read bandwidth is 512GB / s, the first address channel data read bandwidth is 128GB / s, the second address channel data read bandwidth is 256GB / s, the bus width ratio is 4, and the clock frequency ratio is 2. Then the first reference rate is 2, and the second reference rate is 0.5. Since the clock frequency ratio is greater than the first preset value, the fifth multiplication result is 8, and the third division result is 0.25. The third division result 0.25 is less than the second preset value 1, so the preset rate 1 is used as the average transmission rate.

[0059] In a specific implementation, determining the target transmission rate of the target read command set according to the average transmission rate and the real-time usage includes:

[0060] If the real-time usage is less than a preset first threshold, the target transmission rate is greater than the average transmission rate;

[0061] If the real-time usage is greater than a preset second threshold, the target transmission rate is less than the average transmission rate, wherein the second preset threshold is greater than the preset first threshold;

[0062] Otherwise, the target transmission rate is equal to the average transmission rate.

[0063] Among them, data reading will be delayed due to the physical distance between the system bus and the memory, resource conflicts caused by the system bus processing read and write commands of multiple engines, etc. Therefore, when the real-time usage is less than the preset first threshold, in order to improve bandwidth utilization, the target transmission rate can be greater than the average transmission rate. At this time, even if there is a delay in the data arriving at the cache area, it will basically not exceed the cache capacity of the cache area.

[0064] When the target emission rate is equal to the average emission rate, the depth of the cache area can theoretically remain stable. However, there is still data that arrives at the cache area with delay. Therefore, when the real-time usage is greater than the preset second threshold, the target emission rate should be lower than the average emission rate to avoid as much as possible that the cache capacity of the cache area is exceeded when the data arrives at the cache area with delay.

[0065] Specifically, the preset first threshold value may be set to 0.5, and the preset second threshold value may be set to 0.8. The implementer may adjust the values of the preset first threshold value and the preset second threshold value according to actual conditions.

[0066] The target transmission rate can be determined by function mapping, preconfigured rate, etc. For example, when using function mapping, the function y=2×V×(1-x) can be set, where x represents the real-time usage, V represents the average transmission rate, and y represents the target transmission rate. When the real-time usage is less than the preset first threshold or the real-time usage is greater than the preset second threshold, the function is used to determine the target transmission rate. In one embodiment, the implementer can directly determine the target transmission rate based on the function, the average transmission rate and the real-time usage. It should be noted that this function is only an example and the implementer can adjust the mapping function according to actual conditions.

[0067] It can be seen that this embodiment determines the average transmission rate based on the clock frequency ratio, the first address channel data read bandwidth, the second address channel data read bandwidth, the first read bandwidth, the second read bandwidth, the bus width ratio and the clock frequency ratio. The average transmission rate can ensure the stable usage of the cache area under ideal circumstances. However, due to physical distance limitations, resource conflicts, etc., there will be delays in the transmission of data or commands, which will affect the usage of the cache area. Therefore, based on the average transmission rate and real-time usage, the target transmission rate of the target read command set is determined, which can effectively increase bandwidth utilization and avoid data congestion, thereby improving data transmission efficiency.

[0068] Although some specific embodiments of the present invention have been described in detail by way of example, it should be understood by those skilled in the art that the above examples are for illustration only and are not intended to limit the scope of the present invention. It should also be understood by those skilled in the art that various modifications may be made to the embodiments without departing from the scope and spirit of the present invention. The scope of the present invention is defined by the appended claims.

Claims

1. A bandwidth management system, characterized in that: The system includes: a system bus and its corresponding cache area, an engine, and a memory, wherein a first channel and a second channel exist between the system bus and the engine, the first channel is used by the engine to send a read command to the system bus, and the second channel is used by the system bus to send data corresponding to the read command to the engine, and a third channel exists between the system bus and the memory, the system bus corresponds to a first clock frequency, the engine corresponds to a second clock frequency, the third channel corresponds to a first bus width, and the second channel corresponds to a second bus width: The engine is further configured to obtain real-time usage of the cache area when sending a target read command set to the system bus through the first channel, the target read command set including target read commands corresponding to a plurality of cycles, the target read command set corresponding to an average access length; The engine is further configured to determine a first read bandwidth based on the first bus width and the first clock frequency, and to determine a second read bandwidth based on the second bus width and the second clock frequency; The engine is further configured to determine a first address channel data read bandwidth based on the average access length and the first clock frequency, and to determine a second address channel data read bandwidth based on the average access length and the second clock frequency; The engine is further configured to determine a bus width ratio based on the first bus width and the second bus width, and to determine a clock frequency ratio based on the first clock frequency and the second clock frequency; The engine is further configured to determine an average transmit rate based on the clock frequency ratio, the first address channel data read bandwidth, the second address channel data read bandwidth, the first read bandwidth, the second read bandwidth, and the bus width ratio; The engine is further configured to determine a target emission rate of the target read command set according to the average emission rate and a real-time usage of the cache area.

2. The bandwidth management system according to claim 1, wherein: The target read command corresponds to a first access length, and the average access length is calculated as the average of the first access lengths of the target read commands corresponding to all cycles. If there is no target read command in any cycle, the first access length corresponding to the cycle is zero.

3. The bandwidth management system according to claim 1, wherein: Determining a first read bandwidth according to the first bus width and the first clock frequency, and determining a second read bandwidth according to the second bus width and the second clock frequency, includes: multiplying the first bus width and the first clock frequency to obtain a first multiplication result, and using the first multiplication result as the first read bandwidth; The second bus width and the second clock frequency are multiplied to obtain a second multiplication result, and the second multiplication result is used as the second read bandwidth.

4. The bandwidth management system according to claim 1, wherein: The determining of a first address channel data read bandwidth according to the average access length and the first clock frequency, and the determining of a second address channel data read bandwidth according to the average access length and the second clock frequency, comprises: multiplying the average access length and the first clock frequency to obtain a third multiplication result, and using the third multiplication result as the first address channel data read bandwidth; The average access length and the second clock frequency are multiplied to obtain a fourth multiplication result, and the fourth multiplication result is used as the second address channel data read bandwidth.

5. The bandwidth management system according to claim 1, wherein: Determining a bus width ratio according to the first bus width and the second bus width, and determining a clock frequency ratio according to the first clock frequency and the second clock frequency, includes: Dividing the second bus width by the first bus width to obtain a first division result, and using the first division result as the bus width ratio; The second clock frequency is divided by the first clock frequency to obtain a second division result, and the second division result is used as the clock frequency ratio.

6. The bandwidth management system according to claim 1, wherein: The determining the average transmission rate according to the clock frequency ratio, the first address channel data read bandwidth, the second address channel data read bandwidth, the first read bandwidth, the second read bandwidth, and the bus width ratio includes: taking a ratio of the first address channel data read bandwidth to the first read bandwidth as a first reference rate; using a ratio of the second address channel data read bandwidth to the second read bandwidth as a second reference rate; If the clock frequency ratio is greater than a first preset value, determining the average transmission rate according to the first reference rate, the bus width ratio, and the clock frequency ratio; Otherwise, the second reference rate is used as the average transmission rate.

7. The bandwidth management system according to claim 6, characterized in that: The determining the average transmission rate according to the first reference rate, the bus width ratio, and the clock frequency ratio includes: Multiplying the bus width ratio and the clock frequency ratio to obtain a fifth multiplication result: dividing the first reference rate and the fifth multiplication result to obtain a third division result; If the third division result is greater than a second preset value, determining the first reference rate as the average transmission rate; Otherwise, the preset rate is used as the average transmission rate.

8. The bandwidth management system according to claim 1, wherein: The determining, according to the average transmission rate and the real-time usage, a target transmission rate of the target read command set includes: If the real-time usage is less than a preset first threshold, the target transmission rate is greater than the average transmission rate; If the real-time usage is greater than a preset second threshold, the target transmission rate is less than the average transmission rate, wherein the preset second threshold is greater than the preset first threshold; Otherwise, the target transmission rate is equal to the average transmission rate.

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