Dynamic time sequence rapid analysis method based on graph neural network

Abstract

The invention discloses a dynamic time sequence rapid analysis method based on a graph neural network. The method comprises the following steps: modeling a topological structure and working load characteristics of a target circuit; constructing a pre-training graph representation learning model based on GAE, capturing static topological information of the circuit in an unsupervised mode, and learning a dynamic input state and pin overturning information in a supervised mode; extracting circuit structure characteristics by utilizing the trained GNN, and performing representation learning on an input node state in combination with dynamic working load information to generate a uniform circuit embedding vector; constructing a dynamic time sequence prediction model based on GAT, and predicting dynamic signal arrival time under different loads through regression learning in combination with pre-trained graph embedding information; and S5, verifying the trained model on a test data set, and carrying out dynamic time sequence prediction by utilizing an optimized model framework, so that compared with a traditional method, the prediction precision is improved, and calculation acceleration is realized. The method is suitable for the field of chip design and optimization, and can be used for dynamic time sequence analysis of an advanced process.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit design and optimization, particularly to timing analysis technology in electronic design automation (EDA). Specifically, it relates to a dynamic timing analysis method based on a graph neural network (Graph Neural Network, GNN). This method is applicable to artificial intelligence (AI) accelerators, high-performance computing (HPC) chips, and other compute-intensive circuits, and can effectively predict the dynamic signal arrival time of the circuit under different workloads, improving the accuracy of timing analysis and optimizing the computing efficiency.

Background Art

[0002] In the process of chip design and optimization, timing analysis is a crucial step to ensure the correct operation of the chip. Currently, the mainstream timing analysis methods mainly include static timing analysis (STA) and dynamic timing analysis (DTA).

[0003] Static timing analysis (STA) is a widely adopted analysis method that calculates the operating frequency of the chip by evaluating the worst-case signal propagation delay. However, STA has the following main problems: overly conservative estimation, STA is based on the worst-case assumption, resulting in a lower frequency setting for the chip and affecting the overall performance; it does not consider the impact of workload, STA ignores the dynamic changes of input signals and cannot accurately predict the timing behavior in the actual operating environment; large consumption of computing resources: as the chip scale increases, the computational complexity of STA rises rapidly, making it difficult to meet the optimization requirements of large-scale AI accelerators.

[0004] Compared with STA, dynamic timing analysis (DTA) performs timing evaluation under the actual workload of the chip and can provide more accurate timing information. More accurate prediction of signal arrival time: DTA can capture the behavior of the circuit under real loads, reduce the over-design problem caused by STA, and improve chip utilization; support for dynamic voltage and frequency scaling (DVFS): DTA can combine dynamic voltage and frequency scaling (DVFS) strategies to achieve chip energy consumption optimization; applicable to compute-intensive applications: DTA has broad application prospects in compute-intensive applications such as AI accelerators and deep learning inference hardware.

[0005] However, the main challenges of DTA are as follows: the computational overhead is huge. Traditional DTA relies on Gate-Level Simulation and requires a large number of SPICE simulations to be executed, resulting in long calculation time and high storage requirements; it is difficult to efficiently model dynamic load information: DTA needs to consider complex information such as input signal flips and timing arc constraints, and traditional methods are difficult to ensure computational efficiency while achieving high-precision prediction.

[0006] In recent years, machine learning methods have been applied to solve many challenging problems in the field of design automation, such as logic probability prediction, netlist classification, static timing prediction, etc. However, the existing machine learning methods still have the following problems in dynamic timing analysis tasks: lack of modeling of dynamic loads, most studies only focus on static circuit structures and ignore the flips of input signals and changes in workloads; the model generalization ability is limited, and existing methods need to train models separately for different process nodes, resulting in insufficient model migration ability; the computational cost is still relatively high: although deep learning methods can improve computational efficiency, traditional machine learning methods are still difficult to efficiently process large-scale circuits.

[0007] Graph neural network is a powerful machine learning model that is good at processing data with graph structures. Graph neural network realizes deep learning of complex data by representing data as graphs (data structures composed of nodes and edges) and using neural networks for processing.

[0008] In a graph neural network, each node can be understood as an element or entity in the data, and the edges represent the associations between these elements or entities. By passing the entire graph data through the neural network, the graph neural network can capture complex patterns and structures in the data.

[0009] In practical applications, graph neural networks can be applied to various data with graph structures, such as social networks, protein interaction networks, knowledge graphs, etc. Transforming these problems into graph problems helps to better understand and solve these problems.

[0010] Precisely because graph neural networks have special advantages compared to other machine learning methods in processing data structures like graphs, and circuit structures can be very conveniently abstracted into graph data structures, graph neural networks have received extensive attention in the field of design automation. However, currently, the methods using graph neural networks for timing prediction are still mainly limited to static timing information and do not fully integrate the dynamic changes of circuit workloads.

[0011] In view of the technical problem of chip performance waste caused by the existing static timing analysis (STA), the present invention proposes a dynamic timing analysis method based on a graph neural network (Graph Neural Network, GNN).

Summary of the Invention

[0012] The objective of the present invention is to provide a dynamic timing analysis method based on a Graph Neural Network (GNN), which is used to improve the prediction accuracy of the dynamic signal arrival time of a circuit under different process nodes (such as 45nm, 7nm, etc.), optimize the power consumption and performance of a chip, and significantly improve the computing efficiency.

[0013] The present invention realizes fast timing analysis of AI accelerators, compute-intensive chips, and other digital circuits by constructing a hierarchical two-stage framework and combining graph representation learning and dynamic timing prediction, including the following steps:

[0014] S1. Circuit diagram modeling: Represent the topological structure and workload characteristics of the target circuit as a graph data structure with nodes and edges; among them, the nodes represent the input / output pins (I / O Pins) and standard cell logic gates (Standard Cells) of the circuit; the edges represent the connection relationship and timing arc information (Timing Arcs) of the circuit, including timing parameters such as minimum / maximum rise delay, minimum / maximum fall delay, etc.

[0015] S2. Pretrain the graph representation learning model: Use a Graph Auto Encoder (GAE) for unsupervised learning of the circuit topological structure to learn the structural features of the circuit; combine the supervised learning task to predict the pin flip states of the circuit input pins to improve the adaptability of the GNN model to dynamic timing changes; after training is completed, obtain the global circuit embedding vector of the circuit as the input of the timing prediction model.

[0016] S3. Dynamic timing prediction based on a graph neural network (GNN): Construct a timing prediction model based on a Graph Attention Network (GAT); combine the pre-trained circuit embedding information and dynamic load characteristics to predict the signal arrival time under different workloads through regression learning; adopt an edge feature enhancement strategy and combine the constraint information of the timing arcs to optimize the circuit timing modeling ability of the GNN model.

[0017] S4. Joint fine-tuning optimization, adopting the multi-task learning strategy, jointly optimizes the pre-trained GNN model and the time series prediction model; uses the mean squared error (MSE) loss function to optimize the dynamic time series prediction task and improve the prediction accuracy; combines adaptive learning rate decay to improve the convergence speed of the model.

[0018] S5. Test the trained machine learning model based on the graph neural network on different test data sets, and use the machine learning model based on the graph neural network to quickly predict the dynamic delay under different scale circuits and different load conditions.

[0019] Preferably, the circuit diagram data structure further includes node weights and edge weights, where: the node weights include the logic type, input / output characteristics, etc. of the circuit pins; the edge weights include timing parameters such as minimum / maximum rise delay, minimum / maximum fall delay, etc., to enhance the expression ability of circuit topology information.

[0020] Preferably, the pre-trained graph representation learning model combines the graph autoencoder (GAE) with multi-task learning, where: uses unsupervised learning to reconstruct the circuit topology structure to improve the generalization ability of the GNN model; uses supervised classification tasks to predict the flip state of the input pins to enhance the dynamic time series prediction accuracy.

[0021] Preferably, the dynamic time series prediction model adopts a structure based on the graph attention network (GAT) and combines the following optimization strategies: Edge Feature Enhancement: Utilizes timing constraint information to optimize the modeling ability of signal propagation; Global Circuit Embedding: Combines the global features output by the pre-trained GNN model to improve the prediction stability.

[0022] Preferably, the dynamic time series prediction task adopts the adaptive learning rate decay (Adaptive Learning Rate Decay) strategy, where: uses a larger learning rate in the initial stage of training to accelerate the convergence speed; adopts an exponential decay strategy in the later stage of training to improve the final prediction accuracy and reduce the risk of overfitting.

[0023] Preferably, the method is applicable to different process nodes, including but not limited to: 45nm process: applicable to chip optimization of mature process nodes; 7nm process: applicable to AI accelerator optimization of advanced processes; other advanced processes: applicable to timing optimization of future high-performance computing chips.

[0024] Preferably, the method can be applied to a variety of computationally intensive functional units, including but not limited to: Multiplier units (MULs): used for digital signal processing and AI accelerator computing; Multiply-accumulate units (MACs): suitable for deep learning computations such as convolutional neural networks (CNNs); Matrix multiplication units (MMUs): applied to large neural networks and high-performance computing tasks.

[0025] Preferably, the method can be further combined with a dynamic voltage and frequency scaling (DVFS) strategy to optimize the power consumption and computing performance of the chip, where: Combining dynamic timing prediction, automatically adjust the circuit operating frequency to improve the energy efficiency ratio; Reduce the voltage and frequency under low load conditions to reduce power consumption and increase the chip lifespan.

[0026] Preferably, the method supports parallel inference optimization to improve computing efficiency, where: Adopt batch inference to process multiple workloads simultaneously to improve the timing prediction throughput; Combine GPU acceleration to achieve fast dynamic timing analysis for large-scale circuits.

[0027] The present invention provides an efficient and accurate dynamic timing analysis method, which has important value in computationally intensive applications such as AI accelerators and high-performance computing chips. The main technical advantages are as follows: 1. Improve the timing prediction accuracy. By combining graph neural networks (GNNs), it can capture the structural information and dynamic load changes of the circuit. Compared with traditional static timing analysis (STA), it can improve the prediction accuracy and reduce the over-design problem; 2. Support different process nodes, applicable to 45nm, 7nm and more advanced semiconductor process nodes, improving the cross-process migration ability; 3. Significantly reduce the computing cost. Compared with the traditional method of obtaining dynamic delays through gate-level simulation, this method achieves a 50-fold computing acceleration on AI accelerator circuits, meeting the optimization requirements of large-scale circuits; 4. Enhance the model generalization ability. Adopt an unsupervised + supervised multi-task learning strategy to improve the adaptability of the model to different circuit topologies and load conditions, reducing the risk of overfitting; 5. Optimize the chip power consumption and performance. By combining dynamic timing prediction, it can be further applied to the dynamic voltage and frequency scaling (DVFS) strategy to optimize the chip power consumption and improve the computing efficiency. The present invention combines graph representation learning and dynamic timing analysis to provide an efficient and accurate timing prediction method, which has broad application prospects in future high-performance chip design and optimization.

Description of the Drawings

[0028] Figure 1 is a flowchart of a dynamic timing fast analysis method based on graph neural networks.

[0029] Figure 2 is an instance structure diagram of an embodiment based on a graph neural network machine learning model.

Detailed Implementation Modes

[0030] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0031] Embodiment

[0032] This embodiment implements a dynamic timing fast analysis method based on a graph neural network for timing analysis of functional units in an AI accelerator. Through graph representation learning and dynamic timing prediction, the prediction accuracy of signal arrival time is improved and the computational overhead is optimized.

[0033] Figure 1 It is a flow chart of a dynamic timing fast analysis method based on a graph neural network. As Figure 1 shown, the implementation process includes: generating training and test data sets, constructing a graph data structure, pre-training the model, jointly fine-tuning, and validating the model; specifically including the following steps:

[0034] S1. Generation of the data set:

[0035] S1.1 Selection of functional units: Select typical functional units in the AI accelerator (such as multipliers MULs, multiply-accumulate units MACs, matrix multiplication units MMUs).

[0036] S1.2 Process node coverage: Use standard cell libraries with 45nm and 7nm process nodes to represent mature and advanced processes respectively, ensuring that the model can adapt to the timing characteristic differences of different process nodes (such as delay, power consumption, noise tolerance) 。

[0037] S1.3 Logic synthesis (Cadence Genus) and placement and routing (Cadence Innovus):

[0038] Logic synthesis: Convert the high-level description of the circuit (such as Verilog code) into a gate-level netlist to determine the connection relationship between logic gates;

[0039] Placement and routing: According to physical design rules, determine the physical positions of logic gates on the chip and the metal connection paths to generate real timing path information (such as interconnect delay);

[0040] S1.4 Generation of the standard delay format (SDF):

[0041] Extract timing parameters through static timing analysis (STA) and generate a Standard Delay Format (SDF) file, which contains key information such as the minimum / maximum rise delay and minimum / maximum fall delay of each timing path in the circuit.

[0042] S1.5 Gate-level simulation (Synopsys VCS):

[0043] Input randomly generated workload signals (such as the input pin level flip sequence) to simulate the actual operation scenario of the circuit;

[0044] Obtain dynamic delay data through simulation, that is, the actual time for the signal to propagate from the input pin to the output pin (related to the load and input state).

[0045] S1.6 Dataset construction:

[0046] Cover the input pin flip information and the corresponding circuit dynamic delay random generated input signals in different load scenario datasets for subsequent model training.

[0047] S2. Graph data structure construction: The node information of the graph structure includes input / output pins (I / O Pins) and standard cell logic gates (Gates), and encodes the gate type and its functional attributes; the edge information includes extracting the minimum / maximum rise delay and minimum / maximum fall delay according to the SDF file and forming directed timing arc (Timing Arcs) information; in addition, record the input signal status and internal pin flip information of different workloads at time steps t and t - 1.

[0048] S3. Pre-train the graph representation learning model: First, construct a graph representation learning model based on GAE, and use unsupervised learning to reconstruct the circuit topology structure to improve the generalization ability of the model. Next, use supervised learning to predict the input pin flip state to enhance the adaptability to dynamic load changes. Finally, after the training is completed, generate a global circuit embedding vector (Global CircuitEmbedding) for the timing prediction task. When establishing the model, we use a graph convolutional neural network (GCN) as the encoder for graph embedding calculation. During the entire pre-training process, we use a weighted method of three loss functions, namely the topology reconstruction loss L adj , calculate the circuit structure reconstruction error based on binary cross-entropy; the pin flip classification loss L pin , use cross-entropy loss to improve the accuracy of flip state classification; the workload reconstruction loss L workload , use binary cross-entropy loss to optimize the input state reconstruction effect; the loss function for the entire pre-training stage is L pretrained = L adj + L pin + λL workload where Lpretrained Denote the overall loss of the pre-trained model as \(L\). adj Represent the topology reconstruction loss as \(L_{topo}\). pin Represent the pin flip classification loss as \(L_{flip}\). workload is the workload reconstruction loss, and \(\lambda\) is a hyperparameter used to adjust the weight of the workload reconstruction loss in the entire loss function.

[0049] S4. Training of the dynamic timing prediction model based on graph neural network: First, we use the graph attention network (GAT) for feature extraction, adopt the edge feature enhancement strategy, combine circuit topology and timing constraint information, and optimize the signal propagation modeling ability. At the same time, calculate the attention coefficients of the adjacency matrix for weighted aggregation of node information. When performing dynamic timing prediction, the input is the combination of the global circuit embedding obtained from the pre-trained model and the workload features. The output is the predicted value of the signal arrival time. To improve the overall prediction accuracy of the model, as an auxiliary prediction task, we simultaneously predict the pin flip conditions inside the circuit network and calculate the loss function for this part. Finally, add a certain weight multiplied by the loss function of the pre-trained model in the joint debugging session. The loss function in the entire joint fine-tuning process is \(L\). total = \(L\). arrival +\(L\). inc_pin +\(\beta L\). pretrained , where \(L\). total Denote the loss function in the entire joint fine-tuning process as \(L\). arrival Represent the prediction loss for the signal arrival time under dynamic excitation as \(L_{arrival}\). inc_pin Represent the loss for predicting the pin flips inside the circuit as \(L_{flip}\). pretrained is the loss of the pre-trained model, and \(\beta\) is a hyperparameter used to adjust the weight of the loss of the pre-trained model in the entire loss.

[0050] S5. After complete pre-training and joint fine-tuning, test and use the trained model on the test dataset.

[0051] Specifically, during the construction of the graph data structure in S2, to ensure the accuracy of the circuit topology, the present invention further refines the features of nodes and edges when constructing the graph data structure:

[0052] S21. The node features include input / output pins (I / O Pins) and standard cells. Each standard cell contains information such as logic gate type, input driving ability, load capacity, etc., and the cell type is represented in a 9-bit binary encoding manner. The edge features include the timing constraint relationships representing the circuit, including information such as the minimum / maximum rising delay and minimum / maximum falling delay extracted from the Standard Delay Format (SDF) file. The dynamic load feature includes, for the input pins, recording the load status at time t and time t - 1, and using 0 or 1 to represent the current workload status. The feature of non-input nodes is set to -1 to ensure the rationality of the dynamic features.

[0053] Specifically, during the pre-training of the graph representation learning model in S3, when constructing the pre-training model based on the Graph Autoencoder (GAE), the present invention further optimizes the learning objective and loss function of the model:

[0054] S31. Optimization of the topology reconstruction task: On the basis of GAE, an edge prediction task is introduced to enhance the model's understanding ability of the circuit topology relationship. When calculating the reconstruction error L of the adjacency matrix adj of the binary cross-entropy loss is used to make the model more accurately recover the circuit structure; Optimization of the pin flip classification: A three-classification supervised task is adopted to identify three situations: 0→1 flip, 1→0 flip, and no flip. When calculating the loss L pin a weighted cross-entropy strategy is used to solve the problem of class imbalance in the training data; Optimization of the input load reconstruction task: For the workload reconstruction of the input pins, a masking mechanism is introduced, and the binary cross-entropy loss L is calculated only for the actual input nodes workload to prevent the features of non-input nodes from affecting the model learning.

[0055] Specifically, during the training of the dynamic timing prediction model based on the graph neural network in S4, in order to improve the prediction accuracy of the signal arrival time, the present invention makes specific optimizations to the Graph Attention Network (GAT):

[0056] S41. Introduction of the edge feature enhancement mechanism (Edge Feature Enhancement): When calculating the attention coefficient, not only node features are used, but also the timing constraint information of the edges is combined. The edge-enhanced GAT (Edge-Enhanced GAT, EGAT) is used to calculate the attention weights, so that the model can better capture the circuit timing characteristics; Multi-scale graph feature fusion: By stacking multiple GAT layers, the model learns the circuit topology structure at different scales, and finally obtains the global circuit embedding vector (Global Circuit Embedding). Combining the timing constraint information improves the stability of the timing prediction.

[0057] Specifically, during the training process of the dynamic time-series prediction model based on the graph neural network in S4, the present invention adopts a multi-task learning strategy to achieve joint optimization of the pre-trained model and downstream tasks:

[0058] S42. Joint optimization strategy: When optimizing the downstream dynamic time-series prediction task, the pre-trained graph representation learning model is fine-tuned simultaneously to make full use of the circuit embedding features and improve the accuracy of signal arrival time prediction. Incremental pin flip classification task: On the basis of the original pre-trained pin flip prediction, an incremental correction task is introduced, that is, the flip state classification is re-optimized by combining real workload data in the fine-tuning stage, so that the model can adapt to the actual circuit application environment. Adaptive learning rate adjustment (Adaptive Learning Rate Decay): In order to improve the training stability, an exponential decay strategy is adopted to gradually reduce the learning rate in the later stage of training, prevent overfitting and improve the generalization ability of the model.

[0059] Model training: The dynamic time-series analysis method based on the graph neural network proposed by the present invention adopts a phased training method, including a pre-training stage and a joint fine-tuning stage.

[0060] 1) Pre-training stage: In order to improve the learning ability of circuit topology features, the present invention uses a graph autoencoder (GAE) for pre-training, enabling the model to learn circuit structure information unsupervised. At the same time, supervised learning is used to optimize the pin flip state prediction to improve the generalization ability of the model. First, 10 AI accelerator benchmark circuits (MULs, MACs, MMUs) with 45nm GPDK045 and 7nm ASAP7 process nodes are used; then logic synthesis (Cadence Genus), placement and routing (Cadence Innovus), static timing analysis (Synopsys PrimeTime), SDF annotation, and gate-level simulation (Synopsys VCS) are carried out; finally, 100,000 random input signals (Workloads) with different loads are generated, the input pin flip information is extracted, and it is converted into a graph data structure.

[0061] For the pre-trained network structure, for the encoder, a 7-layer graph convolutional neural network (GCN) is adopted, and the hidden layer dimensions are [256, 128, 128, 64, 64, 64, 32] in sequence. Finally, the circuit is mapped to a 32-dimensional latent space. For the decoder part, the topology reconstruction decoder calculates the binary cross-entropy loss of the circuit adjacency matrix; for the pin flip classification decoder, a 3-layer MLP is used for flip classification and the weighted cross-entropy loss is calculated; for the input load reconstruction decoder, a single-layer MLP is used for input signal state reconstruction and the loss is calculated. For the pre-trained joint loss function, the hyperparameter λ is set to 0.1.

[0062] In the pre-training stage, the Adam optimizer is adopted. The initial learning rate is set to 0.001, the batch size is set to 32, and 200 Epochs of training are carried out. And exponential learning rate decay is used, and the learning rate decays by 0.1 times every 50 Epochs.

[0063] 2) Joint fine-tuning stage: After the pre-training stage is completed, the present invention further combines the pre-trained graph embedding vector (Global Circuit Embedding) with the dynamic timing prediction task to improve the prediction accuracy of the model through joint fine-tuning.

[0064] First, data preparation for the downstream task is carried out. The graph data structure is extended, and timing arcs features are added, including edge features: minimum / maximum rise delay, minimum / maximum fall delay, and input node dynamic load information, to enhance the adaptability of the model to different workloads.

[0065] Next, when carrying out joint fine-tuning training, for the feature extractor: a 4-layer edge-enhanced graph attention network (Edge-enhanced GAT, EGAT) is adopted for feature extraction to improve the model's ability to model dynamic load changes. For the regression prediction of dynamic timing, a single-layer MLP regression is used to calculate the signal arrival time, and the mean square error (MSE) loss function is used for training optimization.

[0066] Finally, for the entire joint fine-tuning, the weight hyperparameter β of the loss function of the pre-trained model is set to 0.1. The entire fine-tuning process still uses the Adam optimizer, the initial learning rate is set to 0.001, the batch size is 32, and a total of 200 Epochs of training are carried out. And exponential learning rate decay is adopted, with a period of 50 Epochs, and the learning rate is reduced by 0.1 times.

[0067] Model Testing: The present invention was tested on 10 benchmark circuits at the 7nm and 45nm process nodes to evaluate the generalization ability of the present invention. The test data includes circuit structures of different sizes, from 4-bit MAC to 32-bit MMU and 10K unseen random input loads, ensuring the generalization ability of the model under different workloads.

[0068] Under the 45nm process, the mean squared error (MSE) of the dynamic delay predicted by the present invention is reduced by 25.49% compared with the multi-layer perceptron method (MLP) and by 23.37% compared with the random forest method (RF); under the 7nm process, the mean squared error (MSE) of the dynamic delay predicted by the present invention is reduced by 31.92% compared with the multi-layer perceptron method (MLP) and by 13.57% compared with the random forest method (RF). Under the gate-level simulation, the analysis of the computing time of a circuit is about 560.37 seconds.

[0069] Under the same conditions, the present invention only requires 11.24 seconds, achieving a 50-fold acceleration and being able to meet the timing analysis requirements of large-scale circuits.

[0070] Those of ordinary skill in the art can understand that all or part of the steps to implement the above embodiments can be completed by hardware or by a program instructing relevant hardware. The program can be stored in a computer-readable storage medium, where the storage medium can be a magnetic disk, an optical disk, a read-only memory (ROM), or a random access memory (RAM), etc.

[0071] The above are only the preferred embodiments of the present invention. It should be noted that for those of ordinary skill in the art, without departing from the principle of the present invention, several improvements and supplements can still be made, and these improvements and supplements should also be regarded as the protection scope of the present invention.

Claims

1. A dynamic time series analysis method based on graph neural network, characterized in that It includes the following steps: S1. Obtain dynamic timing data covering different processes and load scenarios; S2. Circuit diagram modeling: Model the topological structure and workload characteristics of the target circuit, and represent it as a graph data structure with nodes and edges, where nodes represent the functional units and input / output pins of the circuit, edges represent the circuit connection relationships and timing arc information, and combine dynamic load information; S3. Graph representation learning: Perform unsupervised learning on the static circuit topology through a pre-trained model based on a graph autoencoder (GAE), and combine supervised learning of dynamic loads to generate a global circuit embedding vector; S4. Use the trained graph neural network (GNN) to extract circuit structure features, and combine dynamic workload information to generate a unified global circuit embedding vector; S4. Training and fine-tuning of the dynamic timing prediction model: Use a graph attention network with edge feature enhancement (EGAT) to combine the pre-trained global circuit embedding vector and timing arc constraint information, and predict the dynamic signal arrival time through regression learning, and adopt a multi-task learning strategy to jointly optimize the pre-trained model and downstream tasks; S5: Model optimization and application: Input the dynamic timing data into the trained model, perform dynamic timing analysis using the optimized graph neural network (GNN), and optimize the training process through an adaptive learning rate decay strategy to achieve dynamic timing analysis across process nodes.

2. The method according to claim 1, wherein The node types of the circuit diagram data structure include: input / output pins (I / O Pins), which are used to represent circuit input and output signals; standard cell logic gates, which represent different types of logic units through multi-bit encoding; signal flip status, which is used to indicate the change in signal status at a specific time step.

3. The method according to claim 2, wherein The circuit connection relationship is used to define the circuit topology; the timing arc information includes the minimum rise delay, maximum rise delay, minimum fall delay, and maximum fall delay; the signal propagation direction is used to represent the direction in which the signal propagates along the timing arc.

4. The method according to claim 1, characterized in that The pre-trained graph representation learning model includes: a topology reconstruction task, which reconstructs the circuit topology based on a graph autoencoder (GAE); a pin flip classification task, which predicts the flip status of the input pins through supervised learning, including rising flip (0→1), falling flip (1→0), and no flip; an input signal reconstruction task, which uses a binary cross-entropy loss function to reconstruct the input load to improve the feature expression ability.

5. The method according to claim 1, wherein The dynamic timing prediction model is based on a graph attention network (GAT) and combines the following optimization strategies: edge feature enhancement, which improves the prediction ability of signal arrival time by performing feature fusion on the timing constraint information of the edges; global embedding combination, which embeds the global circuit representation of the pre-trained model into the timing prediction model to improve the generalization ability; supervised learning optimization, which uses a mean squared error loss function (MSE) for regression learning to optimize the prediction accuracy of signal arrival time.

6. The method according to claim 1, wherein The dynamic timing prediction task is a regression problem, and its goal is to predict the signal arrival time in the worst case on the critical path of the circuit.

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