Analog integrated circuit routing methods, systems, electronic devices and storage media

Abstract

This application discloses a method, system, electronic device, and storage medium for analog integrated circuit routing. The method includes: acquiring a preset net to generate a minimum spanning tree based on the preset net; wherein the minimum spanning tree includes several preset pin regions; determining pin priority data corresponding to the preset pin regions according to a preset sorting mechanism; wherein the preset sorting mechanism is determined using a Manhattan distance algorithm; performing routing planning based on the pin priority data and the minimum spanning tree using a pattern routing algorithm to obtain preset routing data; performing design rule checks on the preset routing data to obtain a check result; and when the check result is determined to be a pass, generating a target routing file based on the preset routing data. The embodiments of this application can effectively improve the efficiency and quality of analog integrated circuit routing, thereby improving the performance and reliability of analog integrated circuits. This application can be widely applied in the field of integrated circuit technology.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to an analog integrated circuit wiring method, system, electronic device and storage medium. Background Technology

[0002] With the rapid development of integrated circuit manufacturing processes, the integration and complexity of chips have significantly increased, leading to a substantial increase in the difficulty of routing in VLSI (Very Large Scale Integration) circuits. The number and density of signal nets in chip design continue to rise, causing traditional routing algorithms, such as maze routing algorithms, to face severe performance bottlenecks in high-complexity scenarios. In analog circuit layout design, due to the special characteristics of analog signals, routing needs to address even more complex issues. Analog circuit signals are extremely sensitive to path length, impedance matching, and signal interference; even a small deviation can significantly affect signal integrity. In this case, routing must not only consider reducing signal delay and phase distortion but also focus on addressing the impact of parasitic capacitance and inductance on high-frequency signal transmission to optimize the overall circuit performance. In related technologies, traditional routing algorithms, such as maze routing algorithms, can find the global optimum through depth-first search, but they are inefficient for large-scale pin routing, and the layout path quality is generally poor. This can easily lead to increased signal propagation delay, decreased electromagnetic interference characteristics, and localized heat concentration, negatively impacting circuit thermal management and reducing circuit performance and reliability.

[0003] In summary, the technical problems existing in the relevant technologies need to be improved. Summary of the Invention

[0004] The main objective of this application is to provide a method, system, electronic device, and storage medium for analog integrated circuit wiring, which can effectively improve the efficiency and quality of analog integrated circuit wiring, thereby improving the performance and reliability of analog integrated circuits.

[0005] To achieve the above objectives, one aspect of this application proposes a method for wiring analog integrated circuits, the method comprising the following steps:

[0006] Obtain a preset net to generate a minimum spanning tree based on the preset net; wherein the minimum spanning tree includes several preset pin regions;

[0007] The pin priority data corresponding to the preset pin region is determined according to a preset sorting mechanism; wherein, the preset sorting mechanism is determined by the Manhattan distance algorithm;

[0008] Based on the pin priority data and the minimum spanning tree, a routing algorithm is used to plan the routing data to obtain preset routing data.

[0009] The preset wiring data is subjected to design rule checks to obtain the check results;

[0010] Once the inspection result is determined to be a pass, a target wiring file is generated based on the preset wiring data.

[0011] In some embodiments, before performing the generation of the target wiring file based on preset wiring data, the method further includes:

[0012] The preset wiring data is optimized and trimmed using a preset trimming algorithm to obtain optimized wiring data.

[0013] In some embodiments, determining the pin priority data corresponding to the preset pin region according to a preset sorting mechanism includes:

[0014] Determine the boundary point distribution data based on the preset pin region;

[0015] Based on the boundary point distribution data, the distance data between the device pins corresponding to the preset pin area and the target area is calculated using the Manhattan distance algorithm;

[0016] The pin priority data is determined based on the distance data and the preset signal threshold.

[0017] In some embodiments, the step of performing routing planning based on the pin priority data and the minimum spanning tree using a pattern routing algorithm to obtain preset routing data includes:

[0018] The preset feature value of the corresponding wiring edge is determined based on the pin coordinate data of the minimum spanning tree;

[0019] The pin region to be routed is determined based on the pin priority data;

[0020] The desired routing pattern is determined based on the preset feature value and the area of ​​the pin to be routed, and routing planning is performed through the desired routing pattern to obtain the preset routing data.

[0021] In some embodiments, determining the desired routing pattern based on the preset feature value and the pin area to be routed, and then performing routing planning based on the desired routing pattern to obtain the preset routing data, includes:

[0022] When it is determined that the pin regions to be routed are in the same routing layer, a corresponding first feature value is determined based on the pin regions to be routed and the preset feature value, and a first routing planning process is performed on the pin regions to be routed based on the first feature value to obtain a first planning result; when it is determined that the first planning result is that the routing is incomplete, a second routing planning process is performed on the pin regions to be routed based on the first planning result to obtain the preset routing data; wherein, the first routing planning process includes a two-dimensional single L-shaped routing mode or a straight-line routing mode, and the second routing planning process includes a two-dimensional double L-shaped routing mode or a two-dimensional Z-shaped routing mode;

[0023] Alternatively, when it is determined that the pin region to be routed is in a different routing layer, a corresponding second feature value is determined based on the pin region to be routed and the preset feature value, so as to perform a third routing planning process on the pin region to be routed based on the second feature value to obtain a second planning result; when it is determined that the second planning result is that the routing is incomplete, a fourth routing planning process is performed on the pin region to be routed based on the second planning result to obtain the preset routing data; wherein, the third routing planning process includes a three-dimensional single L-shaped routing mode, a three-dimensional double L-shaped routing mode, or a three-dimensional Z-shaped routing mode, and the fourth routing planning process includes a multi-source multi-sink routing mode.

[0024] In some embodiments, after performing the step of determining the pin priority data corresponding to the preset pin region according to a preset sorting mechanism, the method further includes:

[0025] A first pin region is determined based on the pin priority data; wherein, the first pin region includes the preset pin regions with the same priority;

[0026] The pin priority data is adjusted using a preset activation function based on the obstacle distribution density data of the first pin region within a preset area.

[0027] In some embodiments, performing design rule checks on the preset wiring data to obtain check results includes:

[0028] Generate a through-hole expansion rectangle based on the through-hole data in the preset wiring data;

[0029] The wiring edges in the preset wiring data are split to obtain preset split edges; wherein, the preset split edges include vertical edges and horizontal edges;

[0030] The preset disassembly edge is expanded according to the preset expansion parameters to generate a disassembly edge expansion rectangle;

[0031] The overlap of the disassembly edge extension rectangle and the via extension rectangle is determined based on the historical wiring rectangle area to obtain the inspection result; wherein, the historical wiring rectangle area includes the extension rectangle area where wiring has been completed.

[0032] To achieve the above objectives, another aspect of this application provides an analog integrated circuit routing system, the system comprising:

[0033] The first module is used to obtain a preset net to generate a minimum spanning tree based on the preset net; wherein the minimum spanning tree includes several preset pin regions;

[0034] The second module is used to determine the pin priority data corresponding to the preset pin region according to a preset sorting mechanism; wherein, the preset sorting mechanism is determined by the Manhattan distance algorithm;

[0035] The third module is used to perform routing planning based on the pin priority data and the minimum spanning tree using a pattern routing algorithm to obtain preset routing data.

[0036] The fourth module is used to perform design rule checks on the preset wiring data and obtain the check results;

[0037] The fifth module is used to generate a target wiring file based on preset wiring data when the inspection result is determined to be a pass.

[0038] To achieve the above objectives, another aspect of this application provides an electronic device, the electronic device comprising:

[0039] At least one processor;

[0040] At least one memory for storing at least one program;

[0041] When the at least one program is executed by the at least one processor, the at least one processor performs the method described above.

[0042] To achieve the above objectives, another aspect of the embodiments of this application proposes a computer-readable storage medium storing a computer program that, when executed by a processor, implements the above-described method.

[0043] The embodiments of this application include at least the following beneficial effects: This application provides a method, system, electronic device, and storage medium for analog integrated circuit routing. This scheme obtains a preset net and generates a minimum spanning tree including several preset pin regions based on the preset net. Next, the embodiments of this invention determine the pin priority data corresponding to the preset pin regions according to a preset sorting mechanism determined by the Manhattan distance algorithm. Further, the embodiments of this invention perform routing planning using a pattern routing algorithm based on the pin priority data and the minimum spanning tree to obtain preset routing data, and then perform design planning checks on the preset routing data to obtain check results. Accordingly, when the check result is determined to be passed, the embodiments of this invention generate a target routing file based on the preset routing data, completing the analog integrated circuit routing. It is easily understood that the embodiments of this invention determine the pin priority data of the preset pin regions through a preset sorting mechanism determined by the Manhattan distance algorithm, thereby making routing more efficient. Simultaneously, the embodiments of this invention effectively improve the efficiency and quality of analog integrated circuit routing through routing planning using a pattern routing algorithm, and improve the reliability of analog integrated circuit routing by performing design rule checks on the preset routing data, thereby effectively improving the performance and reliability of the generated analog integrated circuit. Attached Figure Description

[0044] Figure 1 This is a flowchart of the analog integrated circuit wiring method provided in the embodiments of the present invention;

[0045] Figure 2 This is a schematic diagram of the minimum spanning tree provided in an embodiment of the present invention;

[0046] Figure 3 This is a schematic diagram of pin rectangular region overlap determination provided in an embodiment of the present invention;

[0047] Figure 4 This is a schematic diagram of feature-based pattern routing provided in an embodiment of the present invention;

[0048] Figure 5 This is a schematic diagram of same-layer mode routing provided in an embodiment of the present invention;

[0049] Figure 6 These are schematic diagrams of different layer modes provided in embodiments of the present invention;

[0050] Figure 7 This is a schematic diagram of multi-source, multi-sink cabling provided in an embodiment of the present invention;

[0051] Figure 8 This is a schematic diagram of DRC discrimination provided in an embodiment of the present invention;

[0052] Figure 9 This is a schematic diagram of the overall process of the analog integrated circuit routing method provided in the embodiment of the present invention;

[0053] Figure 10 This is a schematic diagram of the structure of the analog integrated circuit wiring system provided in an embodiment of the present invention;

[0054] Figure 11 This is a schematic diagram of the hardware structure of the electronic device provided in an embodiment of the present invention. Detailed Implementation

[0055] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of this application and are not intended to limit it. In the following description, when referring to the accompanying drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with those of this application; they are merely examples of apparatuses and methods consistent with some aspects of the embodiments of this application as detailed in the appended claims.

[0056] It is understood that the terms “first,” “second,” etc., used in this application may be used herein to describe various concepts, but unless otherwise stated, these concepts are not limited by these terms. These terms are only used to distinguish one concept from another. For example, without departing from the scope of the embodiments of this application, first information may also be referred to as second information, and similarly, second information may also be referred to as first information. Depending on the context, the words “if,” “when,” or “in response to a determination” as used herein may be interpreted as “when…” or “when…” or “in response to a determination.”

[0057] As used in this application, the terms "at least one", "multiple", "each", "any", etc., "at least one" includes one, two or more, "multiple" includes two or more, "each" refers to each of the corresponding multiples, and "any" refers to any one of the multiples.

[0058] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing embodiments of this application only and is not intended to limit this application.

[0059] Before providing a detailed description of the embodiments of this application, some of the nouns and terms involved in the embodiments of this application will be explained first. The nouns and terms involved in the embodiments of this application are subject to the following interpretations.

[0060] Manhattan distance is a geometric metric used to measure the sum of the absolute axial distances between two points in a standard coordinate system. It only considers the distance on the standard coordinate axes and does not consider the distance in the diagonal direction.

[0061] R-tree spatial indexing algorithm: A data structure for efficiently querying spatial data. It is a self-balancing tree-like data structure that organizes spatial data into multiple levels of nodes based on a tree structure for quick data location and access. Accordingly, the R-tree spatial indexing algorithm builds a spatial index using the bounding rectangle of the spatial entity.

[0062] Design Rule Checking (DRC) is a physical design process designed to determine whether a design conforms to a set of rules defined by the semiconductor manufacturer or designer, such as line width, line spacing, component spacing, power and ground layout, thereby ensuring the manufacturability and electrical performance of the design.

[0063] With the rapid development of integrated circuit manufacturing processes, the integration and complexity of chips have significantly increased, leading to a substantial increase in the difficulty of routing in VLSI (Very Large Scale Integration) circuits. The number and density of signal nets in chip design continue to rise, causing traditional routing algorithms, such as maze routing algorithms, to face severe performance bottlenecks in high-complexity scenarios. In analog circuit layout design, due to the special characteristics of analog signals, routing needs to address even more complex issues. Analog circuit signals are extremely sensitive to path length, impedance matching, and signal interference; even a small deviation can significantly affect signal integrity. In this case, routing must not only consider reducing signal delay and phase distortion but also focus on addressing the impact of parasitic capacitance and inductance on high-frequency signal transmission to optimize the overall circuit performance. In related technologies, traditional routing algorithms, such as maze routing algorithms, can find the global optimum through depth-first search, but they are inefficient for large-scale pin routing, and the layout path quality is generally poor. This can easily lead to negative impacts on circuit thermal management, such as increased signal propagation delay, decreased electromagnetic interference characteristics, and localized heat concentration, resulting in reduced circuit performance and reliability.

[0064] For example, while traditional maze routing algorithms can find the global optimum through depth-first search, their path curvature and inefficiency in routing large numbers of pins are clearly unsuitable for the demands of modern integrated circuits. Furthermore, in analog circuit layouts, the horizontal and vertical coordinates of device pins can reach hundreds of thousands, leading to a dramatic increase in the number of grid points. In such cases, the runtime and resource consumption of maze algorithms grow exponentially. Additionally, the path curvature of maze algorithms brings a series of negative impacts, including increased signal propagation delay, decreased electromagnetic interference characteristics, and negative impacts on circuit thermal management due to localized heat concentration.

[0065] In view of this, this application provides an analog integrated circuit routing method, system, electronic device, and storage medium. This scheme obtains a preset net and generates a minimum spanning tree including several preset pin regions based on the preset net. Next, this embodiment determines the pin priority data corresponding to the preset pin regions according to a preset sorting mechanism determined by the Manhattan distance algorithm. Further, this embodiment performs routing planning based on the pin priority data and the minimum spanning tree using a pattern routing algorithm to obtain preset routing data, and then performs a design planning check on the preset routing data to obtain a check result. Accordingly, when the check result is determined to be a pass, this embodiment generates a target routing file based on the preset routing data to complete the analog integrated circuit routing, effectively improving the efficiency and quality of analog integrated circuit routing, thereby improving the performance and reliability of analog circuits.

[0066] The analog integrated circuit routing method provided in this application relates to the field of integrated circuit technology. This method can be applied to terminals, servers, or software running on either a terminal or server. In some embodiments, the terminal may be a smartphone, tablet, laptop, desktop computer, smart speaker, smartwatch, or in-vehicle terminal, but is not limited thereto. The server may be configured as an independent physical server, a server cluster or distributed system composed of multiple physical servers, or a cloud server providing basic cloud computing services such as cloud services, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communication, middleware services, domain name services, security services, CDN, and big data and artificial intelligence platforms. The software may be an application implementing the analog integrated circuit routing method, but is not limited to the above forms.

[0067] This application can be used in a wide variety of general-purpose or special-purpose computer system environments or configurations. Examples include: personal computers, server computers, handheld or portable devices, tablet devices, multiprocessor systems, microprocessor-based systems, set-top boxes, programmable consumer electronics, network PCs, minicomputers, mainframe computers, and distributed computing environments including any of the above systems or devices. This application can be described in the general context of computer-executable instructions executed by a computer, such as program modules. Generally, program modules include routines, programs, objects, components, data structures, etc., that perform specific tasks or implement specific abstract data types. This application can also be practiced in distributed computing environments where tasks are performed by remote processing devices connected via a communication network. In distributed computing environments, program modules can reside in local and remote computer storage media, including storage devices.

[0068] Figure 1 This is an optional flowchart of the analog integrated circuit routing method provided in the embodiments of this application. Figure 1 The method may include, but is not limited to, steps S110 to S150.

[0069] Step S110: Obtain a preset net to generate a minimum spanning tree based on the preset net. The minimum spanning tree includes several preset pin regions.

[0070] Step S120: Determine the pin priority data corresponding to the preset pin region according to the preset sorting mechanism. The preset sorting mechanism is determined by the Manhattan distance algorithm.

[0071] Step S130: Based on the pin priority data and the minimum spanning tree, perform routing planning using the pattern routing algorithm to obtain preset routing data.

[0072] Step S140: Perform a design rule check on the preset wiring data and obtain the check results.

[0073] Step S150: When the inspection result is determined to be a pass, generate the target wiring file according to the preset wiring data.

[0074] In the operation of this specific embodiment, the present invention first obtains a preset net to generate a minimum spanning tree based on the preset net. Specifically, the minimum spanning tree in this embodiment includes several preset pin regions. Specifically, in this embodiment, a preset net is first input, and the preset net is divided into multiple pairs of minimum spanning tree edges for rectangular regions. Routing is then performed on each pin region (e.g., a two-pin region) to generate the minimum spanning tree. For example, before routing, this embodiment first generates multiple pairs of pin routing edges based on the specific distribution of the pins, thereby constructing the minimum spanning tree for the preset pin regions, such as... Figure 2 As shown. Furthermore, in the process of generating the minimum spanning tree, this embodiment of the invention optimizes the connection path and reduces the total wiring length by calculating the shortest Manhattan distance between the pin rectangular regions as weights. Next, this embodiment of the invention determines the pin priority data corresponding to the preset pin regions according to a preset sorting mechanism. Specifically, the preset sorting mechanism in this embodiment refers to a mechanism for prioritizing each preset pin region, which is determined by the Manhattan distance algorithm; that is, the preset sorting mechanism is constructed based on the Manhattan distance algorithm. In this embodiment, the pin priority data refers to the current wiring priority of each preset pin region. Accordingly, before wiring, this embodiment of the invention first sorts each preset pin region to obtain the corresponding pin priority, and then performs subsequent wiring according to the pin priority. For example, preset pin regions with higher priority are wired first, thereby effectively improving wiring efficiency.

[0075] Furthermore, in this embodiment of the invention, routing planning is performed using a pattern routing algorithm based on pin priority data and the minimum spanning tree to obtain preset routing data. Specifically, after determining the pin priority data for each preset pin region, this embodiment of the invention performs individual routing for each preset pin region according to the pin priority based on the routing edges of the minimum spanning tree. Simultaneously, during the routing process, the optimal solution is selected for routing by comprehensively considering factors such as routing length, number of vias, and path curvature. Correspondingly, when routing preset pin regions (such as dual-pin regions), in order to limit the routing shape to a fixed form as early as possible in the initial routing stage, this embodiment of the invention uses a pattern routing algorithm to obtain preset routing data. For example, in this embodiment of the invention, pattern routing includes L-shaped, U-shaped, and Z-shaped pattern routing. L-shaped and Z-shaped routing only search within the rectangular search box enclosed by the dual pins, while U-shaped routing exceeds this rectangular box, thus interfering with the routing space of other nets and resulting in a higher obstacle density. Next, this embodiment of the invention performs Design Rule Check (DRC) on the preset routing data to obtain the check result. When the check result is determined to be passed, the target routing file is generated based on the preset routing data. Specifically, this embodiment of the invention checks the preset routing data against design rules to determine whether the routing results in the preset routing data violate relevant design rules, including line width, line spacing, and via size. Accordingly, if the check result is deemed satisfactory, meaning the preset routing data does not violate relevant design rules, the routing is completed, the preset routing data is used as the final routing data, and a corresponding target routing file is generated. For example, this embodiment of the invention generates a GDS file based on the preset routing data. During the GDS file generation process, key parameters of the routing and vias are first read, path coordinates are dynamically adjusted, different layer paths are stored as independent FlexPath objects, and finally all data is written to the GDS file. Furthermore, if the check result is deemed unsatisfactory, the process returns to the pattern routing step to re-route the routing areas that do not conform to the design rules.

[0076] It should be noted that the wiring capacity is recorded on each side of the entire wiring diagram. ),use( ) and overflow value ( (information). Representing an edge The maximum number of nets that can be passed through, Representing an edge The actual number of wires passing through, ,if Then the edge is called Overflow edges are considered. To minimize overflow edges and optimize routing path length, pattern routing algorithms are superior to traditional routing algorithms, such as maze routing algorithms.

[0077] In some embodiments of the present invention, before generating the target routing file based on preset routing data, the analog integrated circuit routing method provided by the embodiments of the present invention further includes, but is not limited to, the following steps:

[0078] The preset wiring data is optimized and trimmed using a preset trimming algorithm to obtain optimized wiring data.

[0079] In this specific embodiment, after the routing is completed, the preset routing data is optimized and trimmed using a preset trimming algorithm to obtain optimized routing data. Specifically, the preset trimming algorithm in this embodiment refers to a line segment trimming algorithm, such as the Liang-Barsky trimming algorithm, the Cohen-Sutherland trimming algorithm, or the Cyrus-Beck trimming algorithm. Correspondingly, after routing, the present invention uses an optimization algorithm based on line segment overlap detection to remove redundant paths using the preset trimming algorithm to ensure the global connectivity and shortest path characteristics of the path. For example, the present invention trims the overlapping area of ​​the starting path and the ending path using the Liang-Barsky trimming algorithm. This algorithm trims line segments that overlap with obstacles, removes the overlapping portion, and splices the remaining line segments to generate the optimized path, thus obtaining the optimized routing data. For example, when the starting point of the line segment is... The destination is It can be represented by a parameterized line segment, as shown in equation (1) below:

[0080] (1)

[0081] Where, in the formula Represents the parameterized scaling factor, and Between 0 and 1, the boundary of the clipping region can be defined by four parameters, as shown in equation (2) below:

[0082] (2)

[0083] Accordingly, the coordinates of the trimmed line segment in this embodiment of the invention are shown in equation (3) below:

[0084] (3)

[0085] It is easy to understand that, by optimizing and trimming the preset wiring data using a preset trimming algorithm after the design rule check has passed, the embodiments of the present invention can effectively trim overlapping line segments, optimize the wiring path, and thus ensure the efficiency and reliability of the circuit design.

[0086] In some embodiments of the present invention, pin priority data corresponding to a preset pin region is determined according to a preset sorting mechanism, including but not limited to the following steps:

[0087] The boundary point distribution data is determined based on the preset pin area.

[0088] Based on the boundary point distribution data, the distance between the device pins corresponding to the preset pin area and the target area is calculated using the Manhattan distance algorithm.

[0089] Pin priority data is determined based on distance data and preset signal thresholds.

[0090] In this specific embodiment, the present invention first determines boundary point distribution data based on a preset pin region. Then, using the Manhattan distance algorithm, it calculates the distance between the device pins corresponding to the preset pin region and the target region. Finally, it determines pin priority data based on the distance data and a preset signal threshold. Specifically, the present invention dynamically evaluates the pin geometry, connection requirements, and routing environment to prioritize the optimal pins for routing. Accordingly, the present invention first performs geometric analysis on the device pin region to establish the boundary point distribution of the rectangular region where the pins are located, ensuring that pins with a good positional relationship to the target region are prioritized during routing. Secondly, the present invention sorts the pins based on the Manhattan distance and signal requirements. By calculating the Manhattan distance between each pin and the target region, pin selection is performed based on the corresponding distance data and a preset signal threshold, thus prioritizing the pins from both distance and signal dimensions to obtain priority data. For example, the present invention prioritizes pins with shorter distances to reduce signal path length and decrease latency and loss.

[0091] Furthermore, for routing requirements in a two-pin rectangular region, this embodiment of the invention first detects whether the pin regions are located on the same layer. The algorithm sorts the rectangular pins according to priority, routing the pins with higher priority first. Specifically, this embodiment of the invention detects whether the X or Y coordinates of the rectangular regions coincide. Figure 3As shown, the left side indicates that Pin a and Pin b have overlapping areas. In this case, the algorithm prioritizes extracting a series of point pairs in the format [((x1,y1),(x2,y2)),((x3,y3),(x4,y4)),...]. These point pairs represent the boundary points of the two rectangular areas in the overlapping part. Accordingly, the routing algorithm in this embodiment of the invention will prioritize routing in these overlapping areas because the routing paths in these areas are shorter and the routing complexity is lower. At the same time, if the routing in the overlapping areas cannot meet all requirements, the algorithm will prioritize the remaining points. The sorting criteria include the density of obstacle blocks and the bus length, prioritizing point pairs that pass through the lower density of obstacles and the shorter bus length. Each pair of points ((x1,y1),(x2,y2)) represents the points that satisfy the shortest Manhattan distance, and (x1,y1) is located on the starting rectangle, and (x2,y2) is located on the ending rectangle. If there is no overlap, such as Figure 3 As shown in Pin a and Pin c on the right, only a pair of points that satisfy the shortest Manhattan distance can be selected first. If the routing is not completed, the priority of the remaining points is sorted by the density of the obstacle blocks that the points pass through and the bus length.

[0092] In some embodiments of the present invention, routing planning is performed based on pin priority data and minimum spanning tree using a pattern routing algorithm to obtain preset routing data, including but not limited to the following steps:

[0093] The preset feature value of the corresponding wiring edge is determined based on the pin coordinate data of the minimum spanning tree.

[0094] The pin area to be routed is determined based on the pin priority data.

[0095] The desired routing pattern is determined based on preset feature values ​​and the area of ​​pins to be routed, and routing planning is performed using the desired routing pattern to obtain preset routing data.

[0096] In this specific embodiment, the present invention first determines the preset feature values ​​of the corresponding routing edges based on the pin coordinate data of the minimum spanning tree. Specifically, in this embodiment, the pin coordinate data refers to the horizontal and vertical coordinates corresponding to the routing edges generated by the minimum spanning tree. For example, as... Figure 4As shown, in this embodiment of the invention, the input is a routing edge generated by the minimum spanning tree. First, routing edges with unequal x and y coordinates for two pin points are identified and randomly assigned 0 or 1 as feature values. Simultaneously, routing edges with equal x or y coordinates for two pin points are assigned feature values ​​of 2 or 3. Next, this embodiment of the invention determines the pin region to be routed based on pin priority data. Specifically, to improve routing efficiency, this embodiment of the invention manages the priority sorting of pins through a priority queue. All candidate pins are dynamically sorted according to their comprehensive priority and added to the priority queue. During the routing process, pins are selected sequentially from high to low priority to determine the pin region to be routed. The priority queue is updated in real time to adapt to changes in the routing environment, thereby ensuring that high-priority pins are used first, reducing the complexity of the routing path, and improving routing speed and quality.

[0097] Further, in this embodiment of the invention, a desired routing pattern is determined based on preset feature values ​​and the area of ​​the pin to be routed, so as to perform routing planning through the desired routing pattern and obtain preset routing data. Specifically, in this embodiment of the invention, the desired routing pattern refers to a routing pattern determined based on corresponding feature values, such as straight-line routing, U-shaped routing, single L-shaped routing, and double L-shaped routing. Accordingly, this embodiment of the invention first determines the corresponding routing edge based on the area of ​​the pin to be routed, and then obtains the corresponding feature value of the routing edge. In this embodiment of the invention, each routing edge is matched with a corresponding routing pattern according to its corresponding feature value. For example, for routing edges with feature values ​​of 2 or 3, this embodiment of the invention prioritizes straight-line routing. If straight-line routing cannot meet the requirements (e.g., encountering obstacles), this embodiment of the invention uses U-shaped routing. U-shaped routing ensures the integrity of the connection and the stability of signal transmission by circling around the obstacle. Meanwhile, for routing edges with feature values ​​of 0 or 1, this embodiment of the invention uses single L-shaped routing or double L-shaped routing. In this invention, single L-shaped routing is suitable for simple corner connections, while double L-shaped routing is suitable for more complex path planning, especially when it is necessary to bypass multiple obstacles or specific areas. It is easy to understand that this embodiment first calculates the feature values ​​corresponding to each routing edge based on the geometry of each routing edge, connection requirements, and the complexity of the surrounding environment. Then, based on the classification of the feature values, a corresponding routing pattern (desired routing pattern) is matched to each routing edge. Accordingly, this embodiment performs routing planning based on the determined desired routing pattern, generates an initial routing scheme, and obtains preset routing data.

[0098] In some embodiments of the present invention, a desired routing pattern is determined based on preset feature values ​​and the area of ​​the pins to be routed, so as to perform routing planning through the desired routing pattern and obtain preset routing data, including but not limited to the following steps:

[0099] When it is determined that the pin regions to be routed are within the same routing layer, a corresponding first feature value is determined based on the pin regions to be routed and preset feature values. A first routing planning process is then performed on the pin regions to be routed according to the first feature value to obtain a first planning result. If the first planning result indicates that routing is incomplete, a second routing planning process is performed on the pin regions to be routed according to the first planning result to obtain preset routing data. The first routing planning process includes a two-dimensional single L-shaped routing mode or a straight-line routing mode, and the second routing planning process includes a two-dimensional double L-shaped routing mode or a two-dimensional Z-shaped routing mode.

[0100] Alternatively, when it is determined that the pin area to be routed is located in a different routing layer, a corresponding second feature value is determined based on the pin area to be routed and a preset feature value. A third routing planning process is then performed on the pin area to be routed based on the second feature value to obtain a second planning result. If the second planning result indicates that routing is incomplete, a fourth routing planning process is performed on the pin area to be routed based on the second planning result to obtain preset routing data. The third routing planning process includes a three-dimensional single L-shaped routing mode, a three-dimensional double L-shaped routing mode, or a three-dimensional Z-shaped routing mode. The fourth routing planning process includes a multi-source, multi-sink routing mode.

[0101] In this specific embodiment, during routing, the present invention determines whether the read pin rectangular area, i.e., the pin to be routed, is located on the same layer. Specifically, when it is determined that the pin area to be routed is on the same routing layer, the present invention determines a first feature value based on the pin area to be routed and a preset feature value, and performs a first routing rule processing on the pin area to be routed according to the first feature value to obtain a first planning result. The first routing rule processing in this embodiment includes a two-dimensional single L-shaped routing mode or a straight-line routing mode. Correspondingly, the first feature value refers to the feature value of the routing edge corresponding to the pin in the pin area to be routed. Furthermore, after completing the first routing planning processing, the present invention determines whether routing is complete based on the first planning result. When it is determined that routing is not complete, the present invention performs a second routing planning processing on the pin area to be routed according to the first planning result to obtain preset routing data. The second routing planning processing in this embodiment includes a two-dimensional double L-shaped routing mode or a two-dimensional Z-shaped routing mode. For example, as... Figure 5 As shown, when the pin areas are read to be on the same layer, this embodiment of the invention performs corresponding routing patterns based on the characteristic values ​​of the routing. First, a two-dimensional single L-shaped routing pattern is adopted, with paths divided into horizontal priority and vertical priority strategies. Then, by detecting obstacles between the start and end points, the algorithm dynamically adjusts the path and determines whether vias need to be drilled in the pin area based on the obstacle density. If the obstacle density is too high, the L-shaped path may not be able to find a valid path. In this case, the incomplete routing will be split and converted to a straight-line double-via routing pattern, such as... Figure 5The linear routing section is shown in the diagram. During this process, the embodiment of the invention searches based on the priority of point pairs in the overlapping area. The linear routing mode will find two points p and q in the point pair. If the Y coordinates of the point pair are equal, then p is (inter_x, y), where inter_x is within the X coordinate range of this pair of points, and q is (inter_x1, y), where inter_x1 is within the range of inter_x to the maximum X coordinate of the point pair. Through-holes are then drilled at points p and q. The algorithm pre-determines whether the expanded frame overlaps with the previous routing shape. Correspondingly, if routing cannot be completed after the first routing planning process, the embodiment of the invention adopts a bidirectional Z-shaped routing mode (i.e., a two-dimensional Z-shaped routing mode) based on the points within the pin area. Where the x or y coordinates of the points on the boundaries of the two pin rectangles do not coincide, the same-layer L-shaped routing mode is also preferentially used. Then, the shortest Manhattan distance point pair is extracted for double L-shaped double-through-hole routing (i.e., a two-dimensional double L-shaped routing mode). Finally, the remaining two pins are routed using a two-dimensional Z-shaped routing mode to ensure the completion of the routing.

[0102] Furthermore, when it is determined that the pin region to be routed is located in different routing layers, this embodiment of the invention determines a second feature value based on the pin region to be routed and a preset feature value, and then performs a third routing planning process on the pin region to be routed according to the second feature value to obtain a second planning result. Specifically, the third routing planning process in this embodiment of the invention includes a three-dimensional single L-shaped routing mode, a three-dimensional double L-shaped routing mode, or a three-dimensional Z-shaped routing mode. For example, as shown... Figure 6 As shown, when the pin areas are not on the same layer, this embodiment of the invention also performs a first-stage pattern routing. The desired routing pattern is determined based on the second feature value, such as 3D L-shaped, Z-shaped, and double L-shaped routing patterns (i.e., three-dimensional single L-shaped routing pattern, three-dimensional double L-shaped routing pattern, or three-dimensional Z-shaped routing pattern) to meet cross-layer routing requirements. The three-dimensional single L-shaped routing pattern is used for simple inter-layer connections. When there are few obstacles between the start and end points, horizontal or vertical paths are preferred, and cross-layer connections are achieved by adding vias. The vias are operated using continuous vias, such as... Figure 6As shown in the continuous via strategy section, the geometric center points of continuous vias must coincide. Secondly, the routing path consists of multiple line segments (such as start point, inflection point, and end point) to ensure the shortest overall path length. Correspondingly, three-dimensional double L-shaped routing patterns or three-dimensional Z-shaped routing patterns are used for more complex routing scenarios, such as those with multiple obstacles or interlayer barriers. In this mode, the path is adjusted using a path cost function and combined with via position optimization to reduce the number of vias. Secondly, when the first stage of routing is not completed, this embodiment of the invention performs a second-stage routing pattern for different layers. First, the edges to be routed are migrated, and then a multi-source, multi-sink routing pattern is implemented. Using a single pin area routing pattern may result in excessively long traces, adversely affecting subsequent edge routing. For example, as... Figure 7 As shown, Pin a and Pin b use an L-shaped routing pattern. However, when connecting Pin c and Pin a, since they are not on the same layer, a cross-layer L-shaped connection is required. This connection method obviously leads to insufficient line length optimization. To solve this problem, this embodiment of the invention considers the routing edge connected to Pin a and Pin a as a new pin area, denoted as Pina'. During routing, only Pin b needs to be connected to Pin a', as shown. Figure 7 As shown. In this way, embodiments of the present invention introduce Steiner points on the wiring edge, thereby effectively shortening the line length, optimizing the signal transmission path, and significantly reducing signal loss.

[0103] In some embodiments of the present invention, after determining the pin priority data corresponding to the preset pin region according to a preset sorting mechanism, the analog integrated circuit routing method provided by the embodiments of the present invention further includes, but is not limited to, the following steps:

[0104] The first pin region is determined based on pin priority data. This first pin region includes preset pin regions with the same priority.

[0105] The pin priority data is adjusted by a preset activation function based on the obstacle distribution density data of the first pin area within a preset area.

[0106] In this specific embodiment, the priority of each preset pin region may be the same. In this case, the embodiment first determines the preset pin regions with the same priority, namely the first pin region, based on the pin priority data. Then, the pin priority data is adjusted by a preset activation function based on the obstacle distribution density data of the first pin region within the preset region. Specifically, in this embodiment, the preset pin regions with the same priority are first selected based on the priority data. Then, the embodiment introduces the influence factors of obstacle density and dynamic environmental interference. By statistically analyzing the obstacle distribution density around each pin, the priority data of the device pins is adjusted by combining a preset activation function (such as the Sigmoid function). In this embodiment, the Sigmoid function is represented as shown in the following formula (4):

[0107] (4)

[0108] Where, in the formula Usually, it is taken as 2. Usually, it is taken as 5. This indicates the wiring capacity at the current pin point. This indicates the congestion level of the network.

[0109] Accordingly, this embodiment of the invention adjusts the pin priority data by introducing the influence factors of obstacle density and dynamic environmental interference, so that the routing process tends to select pins located in low-density areas, thereby reducing the risk of signal interference caused by obstacles during the routing process.

[0110] In some embodiments of the present invention, before performing routing planning based on pin priority data and minimum spanning tree using a pattern routing algorithm to obtain preset routing data, the analog integrated circuit routing method provided by the embodiments of the present invention further includes, but is not limited to, the following steps:

[0111] The expected wiring step size is calculated based on obstacle density data, path complexity data, and target area distance data.

[0112] The step size is dynamically adjusted according to the desired routing step size.

[0113] In this specific embodiment, before performing pattern routing, the present invention first determines the routing compensation based on the layout size of the analog circuit. Accordingly, the present invention calculates the desired routing step size based on obstacle density data, path complexity data, and target area distance data, and then dynamically adjusts the step size accordingly. Specifically, for shorter distances or areas with dense obstacles, the present invention reduces the step size to improve search accuracy. Conversely, for longer distances or areas with sparse obstacles, the present invention increases the step size to accelerate the search speed. Furthermore, before performing pattern routing, the present invention also prioritizes obstacles based on their size and distribution. Accordingly, the present invention prioritizes avoiding larger obstacles while tolerating slight path deviations.

[0114] In some embodiments of the present invention, design rule checks are performed on preset wiring data to obtain check results, including but not limited to the following steps:

[0115] Generate via expansion rectangles based on via data in the preset wiring data.

[0116] The wiring edges in the preset wiring data are split to obtain preset split edges. The preset split edges include vertical edges and horizontal edges.

[0117] The preset disassembly edges are expanded according to the preset expansion parameters to generate a disassembly edge expansion rectangle.

[0118] The overlap of the disassembly edge expansion rectangle and the via expansion rectangle is determined based on the historical wiring rectangle area to obtain the inspection results. The historical wiring rectangle area includes the expansion rectangle area where wiring has already been completed.

[0119] In this specific embodiment, the present invention generates via expansion rectangles based on via data in preset wiring data. Specifically, the present invention first processes the vias of the corresponding wiring edges in the preset wiring data. For example, Figure 8As shown, if the pin point is not a Steiner point, the expanded rectangular area is as shown by the black dashed line in the figure. The via point expands outward into a rectangle with a length and width of 1 / 2 * (via_length + spacing), generating the via expansion rectangle. Alternatively, if the pin point is a Steiner point, the expanded rectangular area will be larger to include possible multiple connection points. Then, in this embodiment, the routing edges in the preset routing data are split to obtain preset split edges, and then the preset split edges are expanded according to preset expansion parameters to generate a split edge expansion rectangle. Specifically, in this embodiment, the preset split edges include vertical edges and horizontal edges. Correspondingly, in this embodiment, the preset expansion parameters refer to the spacing parameters for the outward expansion of different split edges. For example, for the processing of routing edges, from pin point b to pin point a, the routing edge is first split into horizontal edges and vertical edges. Then, in this embodiment, the spacing is expanded outward by 1 / 2 * (minWidth + spacing) on ​​each type of edge, and the expanded rectangle, i.e., the split edge expansion rectangle, is returned. Furthermore, in this embodiment of the invention, overlap judgment is performed on the dismantling edge expansion rectangle and the via expansion rectangle based on the historical routing rectangle area to obtain the inspection result. Specifically, in this embodiment of the invention, the historical rectangle area includes the expansion rectangle area corresponding to the routing edge that has been completed. Accordingly, this embodiment of the invention achieves DRC discrimination through overlap judgment and processing, and compares all returned rectangle areas (dismantling edge expansion rectangle and via expansion rectangle) with the previously completed rectangle area class (historical routing rectangle area) to determine whether they overlap. If there is an overlap, the DRC constraint is violated, and the routing edge is marked for dismantling and rerouting. Conversely, if there is no overlap, it is added to the rectangle area class, and the pattern routing of the next edge continues. Through the above method, this embodiment of the invention can quickly complete pattern routing while satisfying the DRC constraint.

[0120] It should be noted that, to improve real-time performance and efficiency, this embodiment of the invention uses R-tree indexing technology to spatially index and store the completed wiring shapes. Spatial queries quickly filter obstacle areas that may overlap with the expansion box, avoiding the performance overhead of global computation. Correspondingly, in this embodiment, the generation of the expansion box dynamically adjusts the protection distance based on the cross-layer wiring situation. For cross-layer via areas, the protection ranges of the expansion boxes on the upper and lower layers are superimposed to ensure that inter-layer isolation requirements are met. Simultaneously, this embodiment of the invention performs conflict determination on overlapping areas between upper and lower layers of vias, with vias at different levels having different spacing constraints.

[0121] It should be noted that, in the embodiments of the present invention, when performing iterative routing, the objectives such as path length, number of inflection points, and number of vias are integrated into a single optimization objective through a cost function, as shown in the following equation (5):

[0122] (5)

[0123] Where, in the formula Indicates the path length. Indicates the number of corners. Indicates the number of through holes. , as well as This represents the weighting coefficient.

[0124] Furthermore, the optimal cabling pattern is dynamically selected based on the distribution of obstacles around the path and the location of the terminal equipment. L-shaped, Z-shaped, or double L-shaped cabling patterns can be flexibly switched at different stages to meet diverse cabling needs. Near the endpoint, path points with sparse obstacles are prioritized to reduce the number of final adjustments.

[0125] In some embodiments of the present invention, after routing is completed, a 3D visualization of routing paths, vias, obstacles, start points, and end points is achieved using the Plotly library. Exemplarily, the embodiments of the present invention first define input parameters, including rectangles for the start and end points, a list of start-level paths, a list of end-level paths, a list of cross-level paths, and via information for multiple levels. Next, the embodiments of the present invention create a 3D graphic object to facilitate the addition of subsequent elements. Then, the embodiments of the present invention define all relevant layers to ensure that the layers containing the start and end points are correctly included and ordered. Accordingly, during visualization, the system draws a rectangle for each pin, defining the coordinates of the four corners and using the Mesh3d method to render it as a red rectangle to visually represent the start and end points. Subsequently, the embodiments of the present invention generate rectangles of different colors to represent different paths. For example, the system traverses the list of start-level paths, generating blue rectangles to represent the path and adding them to the graphic. Similarly, the path of the end-level layer is drawn by traversing the list of end-level paths and represented by green rectangles. Furthermore, the system can also visualize cross-level paths, traversing the list of cross-level paths and displaying them using purple rectangles. Meanwhile, for drawing vias, the system uses the Scatter3d method to draw the lines of the vias based on their coordinates and layer information, and generates rectangular frames for the vias using the Mesh3d method, distinguishing them with different colors for easy identification. Finally, this embodiment of the invention ensures the accuracy and aesthetics of the visualization by setting the scale, coordinate axis labels, and range of the graphics. This system can effectively display the layout of 3D wiring, providing an intuitive view that facilitates analysis and optimization by designers, and has significant application value and technical advantages.

[0126] The following section provides a detailed description and explanation of the solutions in this embodiment of the invention, using specific analog integrated circuit wiring scenarios as examples:

[0127] For example, such as Figure 9As shown, this embodiment of the invention first obtains a netlist and process documents to simulate a schematic diagram using the netlist, determine which pins should be connected, and obtain different line widths and design rule requirements through different process documents. Then, after obtaining the pin connection relationships, routing layers, and routing-related dimensions (such as via rectangles, line widths, and line spacing), this embodiment of the invention splits the net based on the minimum spanning tree edges, thereby dividing the net into multiple pairs of minimum spanning tree edges for rectangular regions, and then routing each two-pin rectangular region. Accordingly, this embodiment of the invention uses priority-oriented minimum spanning tree splitting and point selection for pin rectangular regions. Accordingly, this embodiment of the invention determines corresponding feature values ​​based on the horizontal and vertical coordinates of the two pin points on the routing edge, and then determines the corresponding desired routing pattern based on the feature values. During the routing process, this embodiment of the invention first detects whether the pin regions are on the same layer. When it is determined that the pin regions are on the same layer, this embodiment of the invention sorts the rectangular pins according to their respective priorities, routing the pins with higher priorities first. In the same-layer routing process, this embodiment of the invention performs pattern routing based on the desired routing pattern determined by feature values, such as L-shaped and straight-line routing patterns, and uses a virtual expansion frame to determine whether DRC rules are violated. Correspondingly, when pin areas are detected to be not on the same layer, this embodiment of the invention also performs pattern routing based on the desired routing pattern determined by feature values, such as L-shaped, double L-shaped, and Z-shaped routing patterns, and uses a virtual expansion frame to determine whether DRC rules are violated. After the design rule check is passed, this embodiment of the invention uses the Liang-Barsky trimming algorithm to trim overlapping parts in the routing data, thereby optimizing the routing segments, obtaining the final routing data, and generating the corresponding routing GDS file.

[0128] It should be noted that this embodiment of the invention takes into account the special characteristics of analog circuit pins, using a three-dimensional mesh model to represent routing resources, and optimizing same-layer and cross-layer routing through pattern routing strategies (such as L-shaped, Z-shaped, double L-shaped, etc.). During the routing process, this embodiment of the invention can dynamically evaluate pin priorities and adjust paths by combining obstacle density and dynamic environmental factors. This dynamic adjustment capability makes routing more efficient, especially when the number of signal lines is large or the pin area distribution is complex, significantly reducing the number of vias, path length, and the risk of signal interference. Simultaneously, to meet the requirements of analog signals for path consistency during routing, this embodiment of the invention manages the priority ordering of pins through a priority queue mechanism, comprehensively considering Manhattan distance, geometric position, and signal requirements, prioritizing the pin with the shortest path and least interference at each step. Furthermore, this embodiment of the invention uses R-tree spatial indexing technology to quickly query the spatial relationship between paths and obstacles, thereby significantly reducing the overhead of global computation and improving routing speed and resource utilization. In cross-layer routing scenarios, this embodiment of the invention adopts a continuous via topology and combines a path cost function and a dynamic step size adjustment strategy to prioritize the layer with the lowest obstacle density for path planning, thereby effectively improving the efficiency and success rate of cross-layer routing, while reducing the number of cross-layer vias and optimizing the path length.

[0129] Please see Figure 10 This application also provides an analog integrated circuit routing system that can implement the above-described analog integrated circuit routing method. The system includes:

[0130] The first module 210 is used to obtain a preset net to generate a minimum spanning tree based on the preset net. The minimum spanning tree includes several preset pin regions.

[0131] The second module 220 is used to determine the pin priority data corresponding to the preset pin area according to the preset sorting mechanism. The preset sorting mechanism is determined by the Manhattan distance algorithm.

[0132] The third module 230 is used to perform routing planning based on pin priority data and minimum spanning tree using a pattern routing algorithm to obtain preset routing data.

[0133] The fourth module 240 is used to perform design rule checks on the preset wiring data and obtain the check results.

[0134] The fifth module 250 is used to generate a target wiring file based on preset wiring data when the inspection result is determined to be a pass.

[0135] It is understood that the content of the above method embodiments is applicable to this system embodiment. The specific functions implemented in this system embodiment are the same as those in the above method embodiments, and the beneficial effects achieved are also the same as those achieved in the above method embodiments.

[0136] This application also provides an electronic device, which includes a memory and a processor. The memory stores a computer program, and the processor executes the computer program to implement the above-described analog integrated circuit wiring method. This electronic device can be any smart terminal, including tablet computers, in-vehicle computers, etc.

[0137] It is understood that the content of the above method embodiments is applicable to this device embodiment. The specific functions implemented by this device embodiment are the same as those of the above method embodiments, and the beneficial effects achieved are also the same as those achieved by the above method embodiments.

[0138] Please see Figure 11 , Figure 11 The hardware structure of an electronic device according to another embodiment is illustrated. The electronic device includes:

[0139] The processor 310 can be implemented using a general-purpose CPU (Central Processing Unit), microprocessor, application-specific integrated circuit (ASIC), or one or more integrated circuits, and is used to execute relevant programs to implement the technical solutions provided in the embodiments of this application.

[0140] The memory 320 can be implemented as a read-only memory (ROM), static storage device, dynamic storage device, or random access memory (RAM). The memory 320 can store the operating system and other applications. When the technical solutions provided in the embodiments of this specification are implemented through software or firmware, the relevant program code is stored in the memory 320 and called and executed by the processor 310 using the analog integrated circuit wiring method of the embodiments of this application.

[0141] Input / output interface 330 is used to realize information input and output;

[0142] The communication interface 340 is used to enable communication and interaction between this device and other devices. Communication can be achieved through wired means (such as USB, network cable, etc.) or wireless means (such as mobile network, WIFI, Bluetooth, etc.).

[0143] Bus 350 transmits information between various components of the device (e.g., processor 310, memory 320, input / output interface 330, and communication interface 340);

[0144] The processor 310, memory 320, input / output interface 330 and communication interface 340 are connected to each other within the device via bus 350.

[0145] This application also provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the above-described analog integrated circuit wiring method.

[0146] It is understood that the content of the above method embodiments is applicable to this storage medium embodiment. The specific functions implemented in this storage medium embodiment are the same as those in the above method embodiments, and the beneficial effects achieved are also the same as those achieved in the above method embodiments.

[0147] Memory, as a non-transitory computer-readable storage medium, can be used to store non-transitory software programs and non-transitory computer-executable programs. Furthermore, memory may include high-speed random access memory, and may also include non-transitory memory, such as at least one disk storage device, flash memory device, or other non-transitory solid-state storage device. In some embodiments, memory may optionally include memory remotely located relative to the processor, and these remote memories can be connected to the processor via a network. Examples of such networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof.

[0148] The embodiments described in this application are for the purpose of more clearly illustrating the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions provided by the embodiments of this application. As those skilled in the art will know, with the evolution of technology and the emergence of new application scenarios, the technical solutions provided by the embodiments of this application are also applicable to similar technical problems.

[0149] Those skilled in the art will understand that the technical solutions shown in the figures do not constitute a limitation on the embodiments of this application, and may include more or fewer steps than shown, or combine certain steps, or different steps.

[0150] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.

[0151] Those skilled in the art will understand that all or some of the steps in the methods disclosed above, as well as the functional modules / units in the systems and devices, can be implemented as software, firmware, hardware, or appropriate combinations thereof.

[0152] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in the specification and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0153] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of the units described above is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0154] The units described above as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0155] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0156] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes multiple instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of this application. The aforementioned storage medium includes various media capable of storing programs, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0157] The preferred embodiments of the present application have been described above with reference to the accompanying drawings, but this does not limit the scope of the claims of the present application. Any modifications, equivalent substitutions, and improvements made by those skilled in the art without departing from the scope and substance of the embodiments of the present application shall be within the scope of the claims of the present application.

Claims

1. A wiring method for analog integrated circuits, characterized in that, The method includes the following steps: Obtain a preset net to generate a minimum spanning tree based on the preset net; wherein the minimum spanning tree includes several preset pin regions; The pin priority data corresponding to the preset pin region is determined according to a preset sorting mechanism; wherein, the preset sorting mechanism is determined by the Manhattan distance algorithm; Based on the pin priority data and the minimum spanning tree, a routing algorithm is used to plan the routing data to obtain preset routing data. The preset wiring data is subjected to design rule checks to obtain the check results; Once the inspection result is determined to be a pass, a target wiring file is generated based on the preset wiring data; The method further includes, after performing the step of determining the pin priority data corresponding to the preset pin region according to the preset sorting mechanism: A first pin region is determined based on the pin priority data; wherein, the first pin region includes the preset pin regions with the same priority; The pin priority data is adjusted using a preset activation function based on the obstacle distribution density data of the first pin region within a preset area.

2. The method according to claim 1, characterized in that, Before generating the target wiring file based on the preset wiring data, the method further includes: The preset wiring data is optimized and trimmed using a preset trimming algorithm to obtain optimized wiring data.

3. The method according to claim 1, characterized in that, The step of determining the pin priority data corresponding to the preset pin region according to the preset sorting mechanism includes: Determine the boundary point distribution data based on the preset pin region; Based on the boundary point distribution data, the distance data between the device pins corresponding to the preset pin area and the target area is calculated using the Manhattan distance algorithm; The pin priority data is determined based on the distance data and the preset signal threshold.

4. The method according to claim 1, characterized in that, The step of performing routing planning based on the pin priority data and the minimum spanning tree using a pattern routing algorithm to obtain preset routing data includes: The preset feature value of the corresponding wiring edge is determined based on the pin coordinate data of the minimum spanning tree; The pin region to be routed is determined based on the pin priority data; The desired routing pattern is determined based on the preset feature value and the area of ​​the pin to be routed, and routing planning is performed through the desired routing pattern to obtain the preset routing data.

5. The method according to claim 4, characterized in that, The step of determining the desired routing pattern based on the preset feature value and the pin area to be routed, and then performing routing planning based on the desired routing pattern to obtain the preset routing data, includes: When it is determined that the pin regions to be routed are in the same routing layer, a corresponding first feature value is determined based on the pin regions to be routed and the preset feature value, and a first routing planning process is performed on the pin regions to be routed based on the first feature value to obtain a first planning result; when it is determined that the first planning result is that the routing is incomplete, a second routing planning process is performed on the pin regions to be routed based on the first planning result to obtain the preset routing data; wherein, the first routing planning process includes a two-dimensional single L-shaped routing mode or a straight-line routing mode, and the second routing planning process includes a two-dimensional double L-shaped routing mode or a two-dimensional Z-shaped routing mode; Alternatively, when it is determined that the pin region to be routed is in a different routing layer, a corresponding second feature value is determined based on the pin region to be routed and the preset feature value, so as to perform a third routing planning process on the pin region to be routed based on the second feature value to obtain a second planning result; when it is determined that the second planning result is that the routing is incomplete, a fourth routing planning process is performed on the pin region to be routed based on the second planning result to obtain the preset routing data; wherein, the third routing planning process includes a three-dimensional single L-shaped routing mode, a three-dimensional double L-shaped routing mode, or a three-dimensional Z-shaped routing mode, and the fourth routing planning process includes a multi-source multi-sink routing mode.

6. The method according to claim 1, characterized in that, The step of performing a design rule check on the preset wiring data to obtain the check results includes: Generate a through-hole expansion rectangle based on the through-hole data in the preset wiring data; The wiring edges in the preset wiring data are split to obtain preset split edges; wherein, the preset split edges include vertical edges and horizontal edges; The preset disassembly edge is expanded according to the preset expansion parameters to generate a disassembly edge expansion rectangle; The overlap of the disassembly edge extension rectangle and the via extension rectangle is determined based on the historical wiring rectangle area to obtain the inspection result; wherein, the historical wiring rectangle area includes the extension rectangle area where wiring has been completed.

7. A wiring system for analog integrated circuits, characterized in that, The system includes: The first module is used to obtain a preset net to generate a minimum spanning tree based on the preset net; wherein the minimum spanning tree includes several preset pin regions; The second module is used to determine the pin priority data corresponding to the preset pin region according to a preset sorting mechanism; wherein, the preset sorting mechanism is determined by the Manhattan distance algorithm; The third module is used to perform routing planning based on the pin priority data and the minimum spanning tree using a pattern routing algorithm to obtain preset routing data. The fourth module is used to perform design rule checks on the preset wiring data and obtain the check results; The fifth module is used to generate a target wiring file based on preset wiring data when the inspection result is determined to be a pass. After executing the step of determining the pin priority data corresponding to the preset pin region according to the preset sorting mechanism, the method further includes: A first pin region is determined based on the pin priority data; wherein, the first pin region includes the preset pin regions with the same priority; The pin priority data is adjusted using a preset activation function based on the obstacle distribution density data of the first pin region within a preset area.

8. An electronic device, characterized in that, include: At least one processor; At least one memory for storing at least one program; When the at least one program is executed by the at least one processor, the at least one processor implements the method as described in any one of claims 1-6.

9. A computer-readable storage medium storing a computer program, characterized in that, When the computer program is executed by a processor, it implements the method of any one of claims 1 to 6.

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